diff --git a/CPLD/MAXII/RAM2GS.mif b/CPLD/MAXII/RAM2GS.mif index 3382c37..4b2ca5a 100644 --- a/CPLD/MAXII/RAM2GS.mif +++ b/CPLD/MAXII/RAM2GS.mif @@ -23,6 +23,6 @@ DATA_RADIX=HEX; CONTENT BEGIN [000..0FD] : 0000; - 0FE : 5FFF; + 0FE : 7FFF; [0FF..1FF] : FFFF; END; diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index 5479d55..c95d0a6 100644 Binary files a/CPLD/MAXII/RAM2GS.qws and b/CPLD/MAXII/RAM2GS.qws differ diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb index aca770c..7b5cb95 100644 Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb index 25c2cf9..b2231d6 100644 Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAXII/db/RAM2GS.asm.qmsg index 148265f..9f4d03d 100644 --- a/CPLD/MAXII/db/RAM2GS.asm.qmsg +++ b/CPLD/MAXII/db/RAM2GS.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903574998 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903575014 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:54 2023 " "Processing started: Sun Aug 13 01:12:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903575014 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903575014 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903575014 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903575264 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903575279 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903575279 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:55 2023 " "Processing ended: Sun Aug 13 01:12:55 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903575389 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914219957 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914219957 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:19 2023 " "Processing started: Sun Aug 13 04:10:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914219957 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691914219957 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691914219957 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691914220207 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691914220223 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691914220223 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:20 2023 " "Processing ended: Sun Aug 13 04:10:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691914220363 ""} diff --git a/CPLD/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAXII/db/RAM2GS.asm.rdb index 5113c0c..e450378 100644 Binary files a/CPLD/MAXII/db/RAM2GS.asm.rdb and b/CPLD/MAXII/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb index 8be3571..100838c 100644 Binary files a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAXII/db/RAM2GS.cmp.cdb index fd4e838..374000a 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.cdb and b/CPLD/MAXII/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.hdb b/CPLD/MAXII/db/RAM2GS.cmp.hdb index 731d24c..6b03a94 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.hdb and b/CPLD/MAXII/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.idb b/CPLD/MAXII/db/RAM2GS.cmp.idb index 556ea78..2369090 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.idb and b/CPLD/MAXII/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAXII/db/RAM2GS.cmp.rdb index 47adcb3..e0bda02 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.rdb and b/CPLD/MAXII/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAXII/db/RAM2GS.cmp0.ddb index e321716..c2b7154 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp0.ddb and b/CPLD/MAXII/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info index 844e3c3..fc87f9b 100644 --- a/CPLD/MAXII/db/RAM2GS.db_info +++ b/CPLD/MAXII/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sun Aug 13 01:07:41 2023 +Creation_Time = Sun Aug 13 04:09:48 2023 diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg index 9c62ca4..98c68b9 100644 --- a/CPLD/MAXII/db/RAM2GS.fit.qmsg +++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg @@ -1,45 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903572781 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903572781 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903572781 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903572812 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903572812 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903572827 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903572843 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903572952 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903572999 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903572999 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903572999 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903572999 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903572999 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903572999 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903572999 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903572999 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903573015 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903573031 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903573046 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903573046 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903573046 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903573046 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573077 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903573093 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903573171 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573265 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903573265 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903573588 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573588 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903573603 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903573713 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903573713 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903573873 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903573873 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573873 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903573873 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573889 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903573904 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903573935 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5346 " "Peak virtual memory: 5346 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:53 2023 " "Processing ended: Sun Aug 13 01:12:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903573967 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691914217113 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691914217113 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691914217113 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691914217144 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691914217144 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691914217176 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691914217176 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691914217347 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691914217473 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691914217473 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691914217488 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691914217488 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691914217488 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691914217504 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691914217504 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691914217504 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691914217520 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691914217551 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691914217582 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691914217582 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691914217582 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691914217582 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914217613 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691914217644 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691914217785 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914217926 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691914217941 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691914218301 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218301 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691914218332 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691914218488 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691914218488 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691914218629 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691914218629 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218629 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691914218660 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218660 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691914218691 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691914218754 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:18 2023 " "Processing ended: Sun Aug 13 04:10:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691914218785 ""} diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info index df04f0e..11d3420 100644 --- a/CPLD/MAXII/db/RAM2GS.hier_info +++ b/CPLD/MAXII/db/RAM2GS.hier_info @@ -69,19 +69,19 @@ MAin[9] => RowA.DATAB MAin[9] => RDQML.DATAA CROW[0] => RBA.DATAB CROW[1] => RBA.DATAB +Din[0] => XOR8MEG.IN1 Din[0] => CmdDRDIn.DATAB -Din[0] => XOR8MEG.DATAB Din[0] => WRD[0].DATAIN Din[0] => Bank[0].DATAIN Din[0] => Equal14.IN2 Din[0] => Equal15.IN4 Din[0] => Cmdn8MEGEN.DATAB +Din[1] => XOR8MEG.IN1 Din[1] => CmdDRCLK.DATAB Din[1] => WRD[1].DATAIN Din[1] => Bank[1].DATAIN Din[1] => Equal14.IN7 Din[1] => Equal15.IN7 -Din[1] => Equal17.IN2 Din[1] => CmdLEDEN.DATAB Din[2] => CmdUFMPrgm.DATAB Din[2] => WRD[2].DATAIN @@ -124,14 +124,14 @@ Din[7] => Equal15.IN0 Din[7] => Equal16.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 -Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE -Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE -Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE -Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE -Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE -Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE -Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE -Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE +Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE nCCAS => WRD[0].CLK nCCAS => WRD[1].CLK nCCAS => WRD[2].CLK @@ -164,21 +164,21 @@ nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN -LED << LED.DB_MAX_OUTPUT_PORT_TYPE -RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE -RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE -RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE +LED <= LED.DB_MAX_OUTPUT_PORT_TYPE +RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE RD[0] <> RD[0] RD[1] <> RD[1] RD[2] <> RD[2] @@ -187,7 +187,7 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] -nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK @@ -243,12 +243,12 @@ RCLK => RASr.CLK RCLK => PHI2r3.CLK RCLK => PHI2r2.CLK RCLK => PHI2r.CLK -RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE -RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE +RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE +RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE |RAM2GS|UFM:UFM_inst diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif index 392ade2..1ad5e65 100644 Binary files a/CPLD/MAXII/db/RAM2GS.hif and b/CPLD/MAXII/db/RAM2GS.hif differ diff --git a/CPLD/MAXII/db/RAM2GS.map.cdb b/CPLD/MAXII/db/RAM2GS.map.cdb index b684441..467e095 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.cdb and b/CPLD/MAXII/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.map.hdb b/CPLD/MAXII/db/RAM2GS.map.hdb index 7bf8462..7dc3b49 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.hdb and b/CPLD/MAXII/db/RAM2GS.map.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.map.qmsg b/CPLD/MAXII/db/RAM2GS.map.qmsg index 09dc277..f9a0462 100644 --- a/CPLD/MAXII/db/RAM2GS.map.qmsg +++ b/CPLD/MAXII/db/RAM2GS.map.qmsg @@ -1,27 +1,27 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903562627 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903562643 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:42 2023 " "Processing started: Sun Aug 13 01:12:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903562643 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903562643 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903562643 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903562971 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903562971 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903570984 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903570984 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903570984 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903571015 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903571015 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903571015 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903571015 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571015 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903571343 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903571343 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571374 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:51 2023 " "Processing ended: Sun Aug 13 01:12:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571406 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914206145 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914206145 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:06 2023 " "Processing started: Sun Aug 13 04:10:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914206145 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914206145 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914206145 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691914206473 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691914206473 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691914214816 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214832 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914214832 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691914214879 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691914214879 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214879 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214879 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914214879 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691914214926 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691914214988 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691914215035 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691914215473 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691914215473 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914215582 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:15 2023 " "Processing ended: Sun Aug 13 04:10:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914215598 ""} diff --git a/CPLD/MAXII/db/RAM2GS.map.rdb b/CPLD/MAXII/db/RAM2GS.map.rdb index d8031a0..c870412 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.rdb and b/CPLD/MAXII/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAXII/db/RAM2GS.pre_map.hdb index a4242b2..e7a5a58 100644 Binary files a/CPLD/MAXII/db/RAM2GS.pre_map.hdb and b/CPLD/MAXII/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAXII/db/RAM2GS.routing.rdb index 88e339e..a6f4920 100644 Binary files a/CPLD/MAXII/db/RAM2GS.routing.rdb and b/CPLD/MAXII/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAXII/db/RAM2GS.rtlv.hdb index 1a398d0..fc64e7e 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv.hdb and b/CPLD/MAXII/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb index 1613756..082701c 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb index e90dd16..14786fa 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAXII/db/RAM2GS.sta.qmsg index d0a14a4..9c2c87d 100644 --- a/CPLD/MAXII/db/RAM2GS.sta.qmsg +++ b/CPLD/MAXII/db/RAM2GS.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903576561 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903576561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:56 2023 " "Processing started: Sun Aug 13 01:12:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903576561 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903576561 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903576561 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903576670 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903576795 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903576795 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903576826 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903576826 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903576857 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903576998 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903577029 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577029 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903577029 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903577045 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903577045 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903577045 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.970 -99.540 PHI2 " " -8.970 -99.540 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.571 -261.130 RCLK " " -7.571 -261.130 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.200 -7.385 nCRAS " " -1.200 -7.385 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.289 " "Worst-case hold slack is -16.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.289 -16.289 ARCLK " " -16.289 -16.289 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.153 -1.956 PHI2 " " -1.153 -1.956 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.098 0.000 nCRAS " " 0.098 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.148 0.000 RCLK " " 1.148 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903577076 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577092 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903577154 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903577185 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903577185 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:57 2023 " "Processing ended: Sun Aug 13 01:12:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903577232 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914221676 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914221676 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:21 2023 " "Processing started: Sun Aug 13 04:10:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914221676 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691914221676 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691914221676 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691914221785 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691914221926 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691914221926 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914221957 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914221957 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691914222004 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691914222144 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691914222196 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222197 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691914222198 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691914222202 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691914222205 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691914222220 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.193 -97.128 PHI2 " " -9.193 -97.128 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.818 -246.083 RCLK " " -8.818 -246.083 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.245 -5.591 nCRAS " " -1.245 -5.591 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222223 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.888 " "Worst-case hold slack is -16.888" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.888 -16.888 DRCLK " " -16.888 -16.888 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.289 -16.289 ARCLK " " -16.289 -16.289 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.679 -2.377 PHI2 " " -0.679 -2.377 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.104 -0.104 nCRAS " " -0.104 -0.104 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.157 0.000 RCLK " " 1.157 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222254 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691914222332 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691914222348 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691914222348 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:22 2023 " "Processing ended: Sun Aug 13 04:10:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691914222410 ""} diff --git a/CPLD/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAXII/db/RAM2GS.sta.rdb index cc4283f..4c614d7 100644 Binary files a/CPLD/MAXII/db/RAM2GS.sta.rdb and b/CPLD/MAXII/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb index 0559858..dc3d958 100644 Binary files a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb and b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb differ diff --git a/CPLD/MAXII/db/RAM2GS.tmw_info b/CPLD/MAXII/db/RAM2GS.tmw_info index 610074f..1935e4e 100644 --- a/CPLD/MAXII/db/RAM2GS.tmw_info +++ b/CPLD/MAXII/db/RAM2GS.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:15 -start_analysis_synthesis:s:00:00:09-start_full_compilation +start_full_compilation:s:00:00:18 +start_analysis_synthesis:s:00:00:11-start_full_compilation start_analysis_elaboration:s-start_full_compilation start_fitter:s:00:00:03-start_full_compilation start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation diff --git a/CPLD/MAXII/db/RAM2GS.vpr.ammdb b/CPLD/MAXII/db/RAM2GS.vpr.ammdb index 64c0be8..04358f8 100644 Binary files a/CPLD/MAXII/db/RAM2GS.vpr.ammdb and b/CPLD/MAXII/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt index dbc6b27..f87d6bd 100644 Binary files a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt index a80e1b1..dbc10d4 100644 --- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 01:12:55 2023 +Sun Aug 13 04:10:20 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 01:12:55 2023 ; +; Assembler Status ; Successful - Sun Aug 13 04:10:20 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+---------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+---------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00172FC9 ; -; Checksum ; 0x001732B9 ; +; JTAG usercode ; 0x001743AE ; +; Checksum ; 0x0017462E ; +----------------+---------------------------------------------------------------------------------+ @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:12:54 2023 + Info: Processing started: Sun Aug 13 04:10:19 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 4662 megabytes - Info: Processing ended: Sun Aug 13 01:12:55 2023 + Info: Processing ended: Sun Aug 13 04:10:20 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done index 406fd9f..61604a9 100644 --- a/CPLD/MAXII/output_files/RAM2GS.done +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 01:12:57 2023 +Sun Aug 13 04:10:23 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt index aef6950..c8fd28c 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 01:12:53 2023 +Sun Aug 13 04:10:18 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,14 +59,14 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 01:12:53 2023 ; +; Fitter Status ; Successful - Sun Aug 13 04:10:18 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 174 / 240 ( 73 % ) ; +; Total logic elements ; 175 / 240 ( 73 % ) ; ; Total pins ; 63 / 80 ( 79 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -135,8 +135,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.5% ; -; Processors 3-4 ; 1.4% ; +; Processor 2 ; 1.7% ; +; Processors 3-4 ; 1.2% ; +----------------------------+-------------+ @@ -151,28 +151,28 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ +---------------------------------------------+-----------------------+ ; Resource ; Usage ; +---------------------------------------------+-----------------------+ -; Total logic elements ; 174 / 240 ( 73 % ) ; -; -- Combinational with no register ; 76 ; +; Total logic elements ; 175 / 240 ( 73 % ) ; +; -- Combinational with no register ; 77 ; ; -- Register only ; 21 ; ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 47 ; -; -- 2 input functions ; 40 ; +; -- 4 input functions ; 56 ; +; -- 3 input functions ; 48 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 158 ; +; -- normal mode ; 159 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 23 ; +; -- synchronous clear/load mode ; 29 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 23 / 24 ( 96 % ) ; +; Total LABs ; 22 / 24 ( 92 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 80 ( 79 % ) ; @@ -186,11 +186,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 22.7% / 24.7% / 20.6% ; -; Peak interconnect usage (total/H/V) ; 22.7% / 24.7% / 20.6% ; +; Average interconnect usage (total/H/V) ; 20.4% / 22.3% / 18.4% ; +; Peak interconnect usage (total/H/V) ; 20.4% / 22.3% / 18.4% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; -; Total fan-out ; 660 ; +; Total fan-out ; 661 ; ; Average fan-out ; 2.77 ; +---------------------------------------------+-----------------------+ @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -261,8 +261,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -272,11 +272,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; -; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -422,7 +422,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2GS ; 174 (174) ; 98 ; 1 ; 63 ; 0 ; 76 (76) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ; +; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ @@ -491,8 +491,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[7] ; Input ; (1) ; ; Din[1] ; Input ; (1) ; +; Din[7] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -505,16 +505,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X4_Y3_N9 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X3_Y1_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X3_Y1_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ; +; CmdDRDIn~2 ; LC_X6_Y1_N1 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X6_Y1_N3 ; 3 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X2_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ; +; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X5_Y3_N9 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X5_Y2_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X7_Y2_N7 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~7 ; LC_X6_Y2_N0 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -523,10 +523,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+----------+---------+----------------------+------------------+ -; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ; +; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK1 ; ; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ; ; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK3 ; +-------+----------+---------+----------------------+------------------+ @@ -535,30 +535,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 138 / 784 ( 18 % ) ; -; Direct links ; 43 / 888 ( 5 % ) ; +; C4s ; 126 / 784 ( 16 % ) ; +; Direct links ; 61 / 888 ( 7 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; LAB clocks ; 14 / 32 ( 44 % ) ; -; LUT chains ; 16 / 216 ( 7 % ) ; +; LUT chains ; 20 / 216 ( 9 % ) ; ; Local interconnects ; 264 / 888 ( 30 % ) ; -; R4s ; 142 / 704 ( 20 % ) ; +; R4s ; 129 / 704 ( 18 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.57) ; Number of LABs (Total = 23) ; +; Number of Logic Elements (Average = 7.95) ; Number of LABs (Total = 22) ; +--------------------------------------------+------------------------------+ ; 1 ; 2 ; -; 2 ; 2 ; +; 2 ; 1 ; ; 3 ; 1 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 0 ; -; 9 ; 2 ; +; 8 ; 2 ; +; 9 ; 1 ; ; 10 ; 13 ; +--------------------------------------------+------------------------------+ @@ -566,77 +566,79 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.22) ; Number of LABs (Total = 23) ; +; LAB-wide Signals (Average = 1.36) ; Number of LABs (Total = 22) ; +------------------------------------+------------------------------+ -; 1 Clock ; 16 ; -; 1 Clock enable ; 1 ; -; 1 Sync. clear ; 4 ; -; 1 Sync. load ; 1 ; -; 2 Clocks ; 6 ; +; 1 Clock ; 15 ; +; 1 Clock enable ; 3 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 2 ; +; 2 Clocks ; 7 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.83) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced (Average = 8.23) ; Number of LABs (Total = 22) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 2 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 1 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 0 ; -; 9 ; 2 ; +; 8 ; 2 ; +; 9 ; 1 ; ; 10 ; 9 ; -; 11 ; 2 ; -; 12 ; 2 ; +; 11 ; 3 ; +; 12 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 4.91) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced Out (Average = 5.64) ; Number of LABs (Total = 22) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 2 ; -; 2 ; 4 ; -; 3 ; 3 ; -; 4 ; 2 ; -; 5 ; 1 ; -; 6 ; 2 ; -; 7 ; 5 ; +; 2 ; 2 ; +; 3 ; 2 ; +; 4 ; 1 ; +; 5 ; 5 ; +; 6 ; 0 ; +; 7 ; 4 ; ; 8 ; 2 ; -; 9 ; 2 ; +; 9 ; 1 ; +; 10 ; 3 ; +-------------------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 9.09) ; Number of LABs (Total = 23) ; +; Number of Distinct Inputs (Average = 9.73) ; Number of LABs (Total = 22) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 3 ; +; 2 ; 2 ; ; 3 ; 1 ; ; 4 ; 0 ; -; 5 ; 3 ; -; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 2 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 3 ; +; 8 ; 3 ; +; 9 ; 1 ; ; 10 ; 0 ; -; 11 ; 2 ; -; 12 ; 2 ; -; 13 ; 3 ; -; 14 ; 2 ; +; 11 ; 3 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; ; 15 ; 1 ; -; 16 ; 1 ; +; 16 ; 3 ; +; 17 ; 2 ; +---------------------------------------------+------------------------------+ @@ -659,8 +661,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; RCLK ; 3.1 ; -; I/O ; nCRAS ; 2.5 ; +; I/O ; RCLK ; 3.3 ; +; I/O ; nCRAS ; 3.0 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. @@ -671,9 +673,9 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 2.469 ; -; PHI2 ; PHI2r ; 1.523 ; -; nCRAS ; RASr ; 0.358 ; +; nCCAS ; CBR ; 3.041 ; +; nCRAS ; RASr ; 1.214 ; +; PHI2 ; PHI2r ; 1.107 ; +-----------------+----------------------+-------------------+ Note: This table only shows the top 3 path(s) that have the largest delay added for hold. @@ -726,7 +728,7 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -734,19 +736,19 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 18% of the available device resources - Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 17% of the available device resources + Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.23 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 5346 megabytes - Info: Processing ended: Sun Aug 13 01:12:53 2023 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 5345 megabytes + Info: Processing ended: Sun Aug 13 04:10:18 2023 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary index d0ac43e..a7d4510 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Sun Aug 13 01:12:53 2023 +Fitter Status : Successful - Sun Aug 13 04:10:18 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 174 / 240 ( 73 % ) +Total logic elements : 175 / 240 ( 73 % ) Total pins : 63 / 80 ( 79 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index d02ea55..1a0044f 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 01:12:57 2023 +Sun Aug 13 04:10:22 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 01:12:55 2023 ; +; Flow Status ; Successful - Sun Aug 13 04:10:20 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 174 / 240 ( 73 % ) ; +; Total logic elements ; 175 / 240 ( 73 % ) ; ; Total pins ; 63 / 80 ( 79 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 01:12:42 ; +; Start date & time ; 08/13/2023 04:10:06 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169190356209448 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169191420613564 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; @@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ; -; Fitter ; 00:00:01 ; 1.0 ; 5346 MB ; 00:00:02 ; +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4701 MB ; 00:00:23 ; +; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:02 ; ; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; -; Total ; 00:00:12 ; -- ; -- ; 00:00:25 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 4677 MB ; 00:00:01 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:26 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index 58e6867..9f405f9 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 01:12:51 2023 +Sun Aug 13 04:10:15 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 01:12:51 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:10:15 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; -; Total logic elements ; 183 ; +; Total logic elements ; 184 ; ; Total pins ; 63 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -161,20 +161,20 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 183 ; -; -- Combinational with no register ; 85 ; +; Total logic elements ; 184 ; +; -- Combinational with no register ; 86 ; ; -- Register only ; 30 ; ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 47 ; -; -- 2 input functions ; 40 ; +; -- 4 input functions ; 56 ; +; -- 3 input functions ; 48 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 167 ; +; -- normal mode ; 168 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; @@ -187,8 +187,8 @@ https://fpgasoftware.intel.com/eula. ; UFM blocks ; 1 ; ; Maximum fan-out node ; RCLK ; ; Maximum fan-out ; 55 ; -; Total fan-out ; 661 ; -; Average fan-out ; 2.68 ; +; Total fan-out ; 662 ; +; Average fan-out ; 2.67 ; +---------------------------------------------+-------+ @@ -197,7 +197,7 @@ https://fpgasoftware.intel.com/eula. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2GS ; 183 (183) ; 98 ; 1 ; 63 ; 0 ; 85 (85) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; +; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:12:42 2023 + Info: Processing started: Sun Aug 13 04:10:06 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -293,18 +293,18 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 -Info (21057): Implemented 247 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 183 logic cells + Info (21061): Implemented 184 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 4702 megabytes - Info: Processing ended: Sun Aug 13 01:12:51 2023 + Info: Peak virtual memory: 4701 megabytes + Info: Processing ended: Sun Aug 13 04:10:15 2023 Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:22 + Info: Total CPU time (on all processors): 00:00:23 +------------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index e701717..011c5ff 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 01:12:51 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 04:10:15 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX II -Total logic elements : 183 +Total logic elements : 184 Total pins : 63 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2GS.pof b/CPLD/MAXII/output_files/RAM2GS.pof index a95b1e8..e04b2fb 100644 Binary files a/CPLD/MAXII/output_files/RAM2GS.pof and b/CPLD/MAXII/output_files/RAM2GS.pof differ diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt index c3200be..c986c31 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sun Aug 13 01:12:57 2023 +Sun Aug 13 04:10:22 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -21,8 +21,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 13. Setup: 'PHI2' 14. Setup: 'RCLK' 15. Setup: 'nCRAS' - 16. Hold: 'ARCLK' - 17. Hold: 'DRCLK' + 16. Hold: 'DRCLK' + 17. Hold: 'ARCLK' 18. Hold: 'PHI2' 19. Hold: 'nCRAS' 20. Hold: 'RCLK' @@ -83,11 +83,10 @@ https://fpgasoftware.intel.com/eula. ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 2 ; +; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -105,16 +104,16 @@ https://fpgasoftware.intel.com/eula. +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 52.8 MHz ; 52.8 MHz ; PHI2 ; ; -; 117.79 MHz ; 117.79 MHz ; RCLK ; ; -+------------+-----------------+------------+------+ ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 51.58 MHz ; 51.58 MHz ; PHI2 ; ; +; 125.3 MHz ; 125.3 MHz ; RCLK ; ; ++-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -125,9 +124,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; ARCLK ; -99.000 ; -99.000 ; ; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -8.970 ; -99.540 ; -; RCLK ; -7.571 ; -261.130 ; -; nCRAS ; -1.200 ; -7.385 ; +; PHI2 ; -9.193 ; -97.128 ; +; RCLK ; -8.818 ; -246.083 ; +; nCRAS ; -1.245 ; -5.591 ; +-------+---------+---------------+ @@ -136,11 +135,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ +; DRCLK ; -16.888 ; -16.888 ; ; ARCLK ; -16.289 ; -16.289 ; -; DRCLK ; -16.286 ; -16.286 ; -; PHI2 ; -1.153 ; -1.956 ; -; nCRAS ; 0.098 ; 0.000 ; -; RCLK ; 1.148 ; 0.000 ; +; PHI2 ; -0.679 ; -2.377 ; +; nCRAS ; -0.104 ; -0.104 ; +; RCLK ; 1.157 ; 0.000 ; +-------+---------+---------------+ @@ -176,7 +175,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.711 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.594 ; 2.117 ; +; -22.711 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.711 ; 2.000 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -186,8 +185,8 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.724 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.559 ; -; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.549 ; +; -22.633 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.583 ; 2.050 ; +; -22.112 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.583 ; 1.529 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -196,215 +195,215 @@ No paths to report. +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -8.970 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.137 ; -; -8.811 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.978 ; -; -8.500 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.667 ; -; -8.341 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.508 ; -; -8.272 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.439 ; -; -8.190 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.357 ; -; -8.027 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.194 ; -; -8.001 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ; -; -8.001 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ; -; -8.001 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ; -; -7.895 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ; -; -7.895 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ; -; -7.895 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ; -; -7.895 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ; -; -7.875 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.042 ; -; -7.842 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ; -; -7.842 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ; -; -7.842 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ; -; -7.802 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.969 ; -; -7.800 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.967 ; -; -7.800 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.967 ; -; -7.762 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.929 ; -; -7.736 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ; -; -7.736 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ; -; -7.736 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ; -; -7.736 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ; -; -7.720 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.887 ; -; -7.641 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; -; -7.641 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; -; -7.557 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.724 ; -; -7.405 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.572 ; -; -7.379 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.546 ; -; -7.303 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ; -; -7.303 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ; -; -7.303 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ; -; -7.292 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.459 ; -; -7.221 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ; -; -7.221 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ; -; -7.221 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ; -; -7.220 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.387 ; -; -7.197 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ; -; -7.197 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ; -; -7.197 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ; -; -7.197 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ; -; -7.115 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ; -; -7.115 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ; -; -7.115 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ; -; -7.115 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ; -; -7.102 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.269 ; -; -7.102 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.269 ; -; -7.058 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ; -; -7.058 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ; -; -7.058 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ; -; -7.020 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.187 ; -; -7.020 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.187 ; -; -6.984 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ; -; -6.952 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ; -; -6.952 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ; -; -6.952 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ; -; -6.952 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ; -; -6.906 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ; -; -6.906 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ; -; -6.906 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ; -; -6.857 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.024 ; -; -6.857 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.024 ; -; -6.800 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ; -; -6.800 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ; -; -6.800 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ; -; -6.800 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ; -; -6.793 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ; -; -6.793 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ; -; -6.793 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ; -; -6.705 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.872 ; -; -6.705 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.872 ; -; -6.687 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ; -; -6.687 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ; -; -6.687 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ; -; -6.687 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ; -; -6.681 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.848 ; -; -6.599 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.766 ; -; -6.592 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.759 ; -; -6.592 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.759 ; -; -6.514 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.681 ; -; -6.436 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.603 ; -; -6.284 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.451 ; -; -6.171 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.338 ; -; -6.015 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ; -; -6.015 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ; -; -6.015 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ; -; -5.909 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ; -; -5.909 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ; -; -5.909 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ; -; -5.909 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ; -; -5.814 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.981 ; -; -5.814 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.981 ; -; -5.408 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ; -; -5.408 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ; -; -5.408 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ; -; -5.393 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.560 ; -; -4.901 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.568 ; +; -9.193 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.360 ; +; -9.057 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.224 ; +; -8.759 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.926 ; +; -8.623 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.790 ; +; -8.524 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.691 ; +; -8.432 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.599 ; +; -8.273 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.440 ; +; -8.143 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.310 ; +; -8.143 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.310 ; +; -8.143 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.310 ; +; -8.090 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.257 ; +; -8.007 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.174 ; +; -8.007 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.174 ; +; -8.007 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.174 ; +; -7.999 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.166 ; +; -7.998 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.165 ; +; -7.925 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ; +; -7.925 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ; +; -7.925 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ; +; -7.839 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.006 ; +; -7.789 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.956 ; +; -7.789 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.956 ; +; -7.789 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.956 ; +; -7.741 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; +; -7.565 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.732 ; +; -7.486 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.653 ; +; -7.474 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.641 ; +; -7.474 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.641 ; +; -7.474 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.641 ; +; -7.382 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.549 ; +; -7.382 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.549 ; +; -7.382 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.549 ; +; -7.350 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.517 ; +; -7.340 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.507 ; +; -7.340 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.507 ; +; -7.307 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.474 ; +; -7.256 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.423 ; +; -7.256 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.423 ; +; -7.256 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.423 ; +; -7.223 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.390 ; +; -7.223 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.390 ; +; -7.223 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.390 ; +; -7.223 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.390 ; +; -7.204 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.371 ; +; -7.204 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.371 ; +; -7.164 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.331 ; +; -7.164 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.331 ; +; -7.164 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.331 ; +; -7.005 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.172 ; +; -7.005 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.172 ; +; -7.005 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.172 ; +; -6.949 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.116 ; +; -6.949 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.116 ; +; -6.949 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.116 ; +; -6.817 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.984 ; +; -6.789 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.956 ; +; -6.731 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.898 ; +; -6.731 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.898 ; +; -6.731 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.898 ; +; -6.725 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.892 ; +; -6.691 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.858 ; +; -6.691 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.858 ; +; -6.691 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.858 ; +; -6.671 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.838 ; +; -6.671 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.838 ; +; -6.671 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.838 ; +; -6.579 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.746 ; +; -6.579 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.746 ; +; -6.566 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.733 ; +; -6.535 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.702 ; +; -6.473 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.640 ; +; -6.473 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.640 ; +; -6.473 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.640 ; +; -6.420 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.587 ; +; -6.420 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.587 ; +; -6.292 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.459 ; +; -6.173 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.340 ; +; -6.173 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.340 ; +; -6.173 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.340 ; +; -6.146 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.313 ; +; -6.146 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.313 ; +; -6.034 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.201 ; +; -6.002 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.169 ; +; -5.955 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.122 ; +; -5.955 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.122 ; +; -5.955 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.122 ; +; -5.910 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.077 ; +; -5.888 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.055 ; +; -5.888 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.055 ; +; -5.751 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.918 ; +; -5.649 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.316 ; +; -5.649 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.316 ; +; -5.649 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.316 ; +; -5.516 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.683 ; +; -5.477 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.644 ; +; -5.431 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.098 ; +; -5.431 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.098 ; +; -5.431 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.098 ; +; -5.370 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.537 ; +; -5.370 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.537 ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -+-----------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ -; -7.571 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 5.142 ; -; -7.490 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.157 ; -; -7.466 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.133 ; -; -7.389 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.056 ; -; -7.346 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.917 ; -; -7.336 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.003 ; -; -7.186 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.853 ; -; -7.161 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.828 ; -; -7.150 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.817 ; -; -7.143 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.810 ; -; -7.141 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 4.011 ; -; -7.134 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 4.004 ; -; -7.112 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.779 ; -; -7.097 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.764 ; -; -7.095 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.762 ; -; -7.093 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.760 ; -; -7.032 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.603 ; -; -7.025 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.596 ; -; -6.999 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.666 ; -; -6.979 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.849 ; -; -6.979 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.849 ; -; -6.953 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.620 ; -; -6.940 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.607 ; -; -6.934 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.601 ; -; -6.922 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.589 ; -; -6.871 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.538 ; -; -6.832 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.403 ; -; -6.819 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.486 ; -; -6.802 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.469 ; -; -6.795 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.366 ; -; -6.765 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.432 ; -; -6.754 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.421 ; -; -6.722 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.389 ; -; -6.702 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.369 ; -; -6.684 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.351 ; -; -6.632 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.299 ; -; -6.624 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.291 ; -; -6.601 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.172 ; -; -6.590 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.460 ; -; -6.583 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ; -; -6.575 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.242 ; -; -6.567 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.234 ; -; -6.556 ; S[0] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.223 ; -; -6.522 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.189 ; -; -6.463 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.130 ; -; -6.446 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.113 ; -; -6.432 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.099 ; -; -6.431 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.098 ; -; -6.407 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.074 ; -; -6.393 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.060 ; -; -6.390 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.057 ; -; -6.387 ; InitReady ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.054 ; -; -6.383 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.050 ; -; -6.358 ; S[0] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.025 ; -; -6.354 ; S[0] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.021 ; -; -6.335 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.002 ; -; -6.323 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.990 ; -; -6.318 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.985 ; -; -6.306 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.973 ; -; -6.293 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.864 ; -; -6.287 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.954 ; -; -6.287 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.157 ; -; -6.276 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.943 ; -; -6.269 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.840 ; -; -6.268 ; S[1] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.935 ; -; -6.256 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.827 ; -; -6.243 ; CmdLEDEN ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.113 ; -; -6.228 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.895 ; -; -6.189 ; InitReady ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.856 ; -; -6.185 ; InitReady ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.852 ; -; -6.178 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.845 ; -; -6.155 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.822 ; -; -6.154 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.821 ; -; -6.127 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.794 ; -; -6.122 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.789 ; -; -6.107 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.774 ; -; -6.107 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 2.977 ; -; -6.090 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.757 ; -; -6.076 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.743 ; -; -6.070 ; S[1] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.066 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.733 ; -; -6.054 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.721 ; -; -6.038 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.705 ; -; -6.036 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.703 ; -; -6.035 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.702 ; -; -6.020 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.687 ; -; -6.012 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.679 ; -; -5.975 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.642 ; -; -5.957 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.624 ; -; -5.940 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.607 ; -; -5.881 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.548 ; -; -5.760 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.427 ; -; -5.757 ; S[0] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.424 ; -; -5.744 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.411 ; -; -5.733 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.400 ; -; -5.721 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.388 ; -; -5.718 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.385 ; -; -5.712 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.379 ; -; -5.695 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.362 ; -; -5.671 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.338 ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -8.818 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 6.406 ; +; -8.660 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 5.532 ; +; -8.299 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 5.887 ; +; -8.291 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 5.879 ; +; -8.162 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 5.034 ; +; -8.155 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 5.027 ; +; -8.127 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 5.715 ; +; -7.772 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 5.360 ; +; -7.608 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 5.196 ; +; -7.489 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 4.361 ; +; -7.128 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 4.716 ; +; -7.094 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 4.682 ; +; -6.981 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.648 ; +; -6.856 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.523 ; +; -6.689 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.356 ; +; -6.689 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 3.561 ; +; -6.681 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 3.553 ; +; -6.675 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.342 ; +; -6.656 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.323 ; +; -6.575 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 4.163 ; +; -6.564 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.231 ; +; -6.533 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.200 ; +; -6.486 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.153 ; +; -6.449 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.116 ; +; -6.400 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.579 ; 3.988 ; +; -6.383 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.050 ; +; -6.378 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.045 ; +; -6.329 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.996 ; +; -6.324 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.991 ; +; -6.311 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.978 ; +; -6.276 ; CmdLEDEN ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 3.148 ; +; -6.247 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.914 ; +; -6.166 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.833 ; +; -6.157 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.824 ; +; -6.143 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.810 ; +; -6.143 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.583 ; 8.393 ; +; -6.142 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.809 ; +; -6.140 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.807 ; +; -6.138 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.805 ; +; -6.120 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.787 ; +; -6.119 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.786 ; +; -6.116 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.783 ; +; -6.067 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.734 ; +; -5.964 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.631 ; +; -5.957 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.624 ; +; -5.924 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.591 ; +; -5.896 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.563 ; +; -5.895 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.562 ; +; -5.859 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.526 ; +; -5.841 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.508 ; +; -5.827 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.494 ; +; -5.781 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.448 ; +; -5.735 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; RCLK ; 1.000 ; 1.583 ; 7.985 ; +; -5.720 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.387 ; +; -5.719 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 2.591 ; +; -5.716 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.383 ; +; -5.688 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.355 ; +; -5.678 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.345 ; +; -5.677 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.344 ; +; -5.658 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.325 ; +; -5.651 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.318 ; +; -5.639 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.306 ; +; -5.621 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.288 ; +; -5.587 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.254 ; +; -5.576 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.243 ; +; -5.549 ; FS[3] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.216 ; +; -5.538 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.205 ; +; -5.537 ; S[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.204 ; +; -5.535 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.202 ; +; -5.529 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.196 ; +; -5.528 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.195 ; +; -5.507 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.174 ; +; -5.496 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.163 ; +; -5.493 ; Ready ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.160 ; +; -5.491 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.158 ; +; -5.473 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.140 ; +; -5.430 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFMD ; DRCLK ; RCLK ; 1.000 ; 1.583 ; 7.680 ; +; -5.413 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.080 ; +; -5.407 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.074 ; +; -5.402 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.069 ; +; -5.401 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.068 ; +; -5.395 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.062 ; +; -5.379 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.046 ; +; -5.377 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.044 ; +; -5.377 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.044 ; +; -5.371 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.038 ; +; -5.347 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.014 ; +; -5.339 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.006 ; +; -5.327 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.994 ; +; -5.323 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.990 ; +; -5.279 ; CmdUFMErase ; UFMErase ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 2.151 ; +; -5.278 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.945 ; +; -5.278 ; CmdUFMErase ; UFMProgram ; PHI2 ; RCLK ; 0.500 ; -3.295 ; 2.150 ; +; -5.274 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.941 ; +; -5.255 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.922 ; +; -5.249 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.916 ; +; -5.247 ; S[1] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.914 ; +; -5.183 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.850 ; +; -5.181 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.848 ; +; -5.146 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.813 ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------+ @@ -412,172 +411,172 @@ No paths to report. +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -1.200 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.944 ; 7.311 ; -; -0.837 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.600 ; -; -0.837 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.600 ; -; -0.836 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.599 ; -; -0.829 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.592 ; -; -0.775 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.538 ; -; -0.711 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.474 ; -; -0.707 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.470 ; -; -0.700 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.944 ; 7.311 ; -; -0.653 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.416 ; -; 0.342 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.421 ; -; 0.346 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.417 ; -; 0.347 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.416 ; -; 0.348 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.415 ; +; -1.245 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.927 ; 7.339 ; +; -0.825 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.571 ; +; -0.745 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.927 ; 7.339 ; +; -0.595 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.341 ; +; -0.593 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.339 ; +; -0.592 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.338 ; +; -0.584 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.330 ; +; -0.323 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.069 ; +; -0.321 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.067 ; +; -0.317 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 3.063 ; +; -0.196 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 2.942 ; +; 0.344 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 2.402 ; +; 0.346 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 2.400 ; +; 0.550 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.579 ; 2.196 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.289 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.594 ; 2.117 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'DRCLK' ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.549 ; -; -16.276 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.559 ; +; -16.888 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.583 ; 1.529 ; +; -16.367 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.583 ; 2.050 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.289 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.711 ; 2.000 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + +-----------------------------------------------------------------------------------------------------------+ ; Hold: 'PHI2' ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -1.153 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.297 ; 1.865 ; -; -0.554 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.297 ; 2.464 ; -; -0.249 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.297 ; 3.269 ; -; 0.610 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.297 ; 4.128 ; -; 2.107 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.328 ; -; 2.145 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.366 ; -; 2.537 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.758 ; -; 3.233 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.454 ; -; 3.661 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.882 ; -; 3.747 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.968 ; -; 3.954 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.675 ; -; 4.175 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.396 ; -; 4.607 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.328 ; -; 4.617 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.338 ; -; 5.232 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.453 ; -; 5.347 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ; -; 5.347 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ; -; 5.347 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ; -; 5.347 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ; -; 5.385 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.106 ; -; 5.395 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.116 ; -; 5.498 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.219 ; -; 5.508 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.229 ; -; 5.650 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.371 ; -; 5.660 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.381 ; -; 5.813 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.534 ; -; 5.823 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.544 ; -; 5.839 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.560 ; -; 5.854 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ; -; 5.854 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ; -; 5.854 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ; -; 5.895 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.616 ; -; 5.905 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.626 ; -; 6.163 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.884 ; -; 6.355 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ; -; 6.355 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ; -; 6.355 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ; -; 6.355 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ; -; 6.434 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.155 ; -; 6.444 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.165 ; -; 6.461 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ; -; 6.461 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ; -; 6.461 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ; -; 6.591 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.312 ; -; 6.593 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.314 ; -; 6.603 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.324 ; -; 6.617 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.338 ; -; 6.730 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.451 ; -; 6.882 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.603 ; -; 6.941 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.662 ; -; 7.045 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.766 ; -; 7.054 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.775 ; -; 7.127 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.848 ; -; 7.133 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ; -; 7.133 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ; -; 7.133 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ; -; 7.133 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ; -; 7.206 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.927 ; -; 7.239 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ; -; 7.239 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ; -; 7.239 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ; -; 7.246 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ; -; 7.246 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ; -; 7.246 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ; -; 7.246 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ; -; 7.352 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ; -; 7.352 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ; -; 7.352 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ; -; 7.369 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.090 ; -; 7.369 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.090 ; -; 7.398 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ; -; 7.398 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ; -; 7.398 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ; -; 7.398 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ; -; 7.451 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.172 ; -; 7.482 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.203 ; -; 7.504 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ; -; 7.504 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ; -; 7.504 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ; -; 7.561 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ; -; 7.561 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ; -; 7.561 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ; -; 7.561 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ; -; 7.634 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.355 ; -; 7.643 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ; -; 7.643 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ; -; 7.643 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ; -; 7.643 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ; -; 7.666 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.387 ; -; 7.667 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ; -; 7.667 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ; -; 7.667 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ; -; 7.749 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ; -; 7.749 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ; -; 7.749 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ; -; 7.797 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.518 ; -; 7.825 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.546 ; -; 7.879 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.600 ; -; 7.990 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.711 ; -; 8.149 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.870 ; +; -0.679 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.295 ; 2.337 ; +; -0.636 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.295 ; 2.380 ; +; -0.607 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.295 ; 2.909 ; +; -0.455 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.295 ; 2.561 ; +; 0.653 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.295 ; 4.169 ; +; 2.356 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.577 ; +; 2.581 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 2.302 ; +; 3.301 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.522 ; +; 3.321 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.542 ; +; 3.348 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.569 ; +; 3.755 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.976 ; +; 4.097 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.318 ; +; 4.531 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.752 ; +; 4.623 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.844 ; +; 4.770 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.491 ; +; 5.147 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.868 ; +; 5.288 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.009 ; +; 5.438 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.659 ; +; 5.546 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.267 ; +; 5.590 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.311 ; +; 5.665 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.386 ; +; 5.820 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.541 ; +; 5.877 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.098 ; +; 5.877 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.098 ; +; 5.877 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.098 ; +; 5.923 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.644 ; +; 5.962 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.683 ; +; 5.979 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.700 ; +; 6.071 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.792 ; +; 6.095 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.316 ; +; 6.095 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.316 ; +; 6.095 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.316 ; +; 6.108 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.829 ; +; 6.197 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.918 ; +; 6.250 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.971 ; +; 6.356 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.077 ; +; 6.366 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.087 ; +; 6.401 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.122 ; +; 6.401 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.122 ; +; 6.401 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.122 ; +; 6.448 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.169 ; +; 6.480 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.201 ; +; 6.604 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.325 ; +; 6.619 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.340 ; +; 6.619 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.340 ; +; 6.619 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.340 ; +; 6.640 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.361 ; +; 6.738 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.459 ; +; 6.740 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.461 ; +; 6.768 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.489 ; +; 6.799 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.520 ; +; 6.814 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.535 ; +; 6.891 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.612 ; +; 6.919 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.640 ; +; 6.919 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.640 ; +; 6.919 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.640 ; +; 6.981 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.702 ; +; 7.012 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.733 ; +; 7.026 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.747 ; +; 7.117 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.838 ; +; 7.137 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.858 ; +; 7.137 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.858 ; +; 7.137 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.858 ; +; 7.171 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.892 ; +; 7.177 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.898 ; +; 7.177 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.898 ; +; 7.177 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.898 ; +; 7.263 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.984 ; +; 7.300 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.021 ; +; 7.332 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.053 ; +; 7.395 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.116 ; +; 7.395 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.116 ; +; 7.395 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.116 ; +; 7.424 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.145 ; +; 7.451 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.172 ; +; 7.451 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.172 ; +; 7.451 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.172 ; +; 7.459 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.180 ; +; 7.551 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.272 ; +; 7.560 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.281 ; +; 7.590 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.311 ; +; 7.610 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.331 ; +; 7.610 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.331 ; +; 7.610 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.331 ; +; 7.669 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.390 ; +; 7.669 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.390 ; +; 7.669 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.390 ; +; 7.702 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.423 ; +; 7.702 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.423 ; +; 7.702 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.423 ; +; 7.796 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.517 ; +; 7.828 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.549 ; +; 7.828 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.549 ; +; 7.828 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.549 ; +; 7.864 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.585 ; +; 7.920 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.641 ; +; 7.920 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.641 ; +; 7.920 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.641 ; +; 7.932 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.653 ; +; 8.023 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.744 ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 0.098 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.415 ; -; 0.099 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.416 ; -; 0.100 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.417 ; -; 0.104 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.421 ; -; 1.099 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.416 ; -; 1.146 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.944 ; 7.311 ; -; 1.153 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.470 ; -; 1.157 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.474 ; -; 1.221 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.538 ; -; 1.275 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.592 ; -; 1.282 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.599 ; -; 1.283 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.600 ; -; 1.283 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.600 ; -; 1.646 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.944 ; 7.311 ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.104 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 2.196 ; +; 0.100 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 2.400 ; +; 0.102 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 2.402 ; +; 0.642 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 2.942 ; +; 0.763 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.063 ; +; 0.767 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.067 ; +; 0.769 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.069 ; +; 1.030 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.330 ; +; 1.038 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.338 ; +; 1.039 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.339 ; +; 1.041 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.341 ; +; 1.191 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.927 ; 7.339 ; +; 1.271 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.579 ; 3.571 ; +; 1.691 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.927 ; 7.339 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------+ @@ -585,106 +584,106 @@ No paths to report. +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; 1.148 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.717 ; -; 1.174 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.743 ; -; 1.378 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.947 ; -; 1.639 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.860 ; -; 1.648 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.717 ; -; 1.658 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.879 ; -; 1.674 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.743 ; -; 1.822 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.043 ; -; 1.878 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.947 ; -; 1.887 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.108 ; -; 1.943 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.164 ; -; 1.959 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.180 ; -; 2.010 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.231 ; -; 2.011 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.232 ; -; 2.107 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.328 ; -; 2.116 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; +; 1.157 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.726 ; +; 1.194 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.763 ; +; 1.237 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.806 ; +; 1.402 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.623 ; +; 1.657 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.726 ; +; 1.659 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ; +; 1.694 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.763 ; +; 1.715 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.936 ; +; 1.721 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.942 ; +; 1.737 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.806 ; +; 1.772 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.993 ; +; 1.928 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.149 ; +; 1.965 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.186 ; +; 2.069 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.290 ; +; 2.107 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.328 ; +; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; ; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; ; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ; -; 2.125 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ; -; 2.134 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.355 ; -; 2.158 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.379 ; -; 2.192 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.413 ; -; 2.233 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; -; 2.240 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.461 ; -; 2.241 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; -; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; -; 2.250 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; -; 2.252 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.473 ; -; 2.259 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.480 ; -; 2.261 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.482 ; -; 2.261 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.482 ; -; 2.272 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.493 ; -; 2.275 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.496 ; -; 2.277 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.498 ; -; 2.284 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.505 ; -; 2.286 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.507 ; -; 2.288 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.509 ; -; 2.445 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.666 ; -; 2.471 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.692 ; -; 2.505 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.726 ; -; 2.529 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.750 ; -; 2.540 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.761 ; -; 2.554 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.775 ; -; 2.555 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.776 ; -; 2.560 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.781 ; -; 2.562 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.783 ; -; 2.575 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.796 ; -; 2.602 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.823 ; -; 2.612 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.833 ; -; 2.638 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.859 ; -; 2.641 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.862 ; -; 2.678 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.899 ; -; 2.696 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; -; 2.920 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.141 ; +; 2.117 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.120 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.341 ; +; 2.126 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; +; 2.145 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ; +; 2.147 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.368 ; +; 2.157 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.378 ; +; 2.161 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.382 ; +; 2.161 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.382 ; +; 2.171 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.392 ; +; 2.176 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.397 ; +; 2.182 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.403 ; +; 2.204 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.425 ; +; 2.212 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.433 ; +; 2.230 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; +; 2.239 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.240 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.461 ; +; 2.240 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.461 ; +; 2.243 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.464 ; +; 2.249 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.472 ; +; 2.378 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.599 ; +; 2.379 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.600 ; +; 2.395 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.616 ; +; 2.401 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.622 ; +; 2.407 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.628 ; +; 2.516 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.737 ; +; 2.534 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.755 ; +; 2.535 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.756 ; +; 2.605 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.826 ; +; 2.646 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.867 ; +; 2.656 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ; +; 2.659 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.880 ; +; 2.664 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.885 ; +; 2.671 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.892 ; +; 2.786 ; RASr2 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.007 ; +; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; ; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ; ; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.178 ; -; 2.966 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.187 ; -; 2.967 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ; -; 2.990 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.211 ; -; 3.015 ; RASr2 ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.236 ; -; 3.040 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.261 ; -; 3.058 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.279 ; +; 2.958 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.179 ; +; 2.979 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.200 ; +; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; ; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ; -; 3.068 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.289 ; -; 3.074 ; PHI2r3 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.295 ; -; 3.077 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.298 ; -; 3.080 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.301 ; -; 3.081 ; PHI2r3 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.302 ; -; 3.095 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.316 ; -; 3.095 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.316 ; -; 3.101 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.322 ; -; 3.107 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.328 ; -; 3.117 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.338 ; -; 3.158 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.379 ; +; 3.069 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.290 ; +; 3.069 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.290 ; +; 3.143 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.364 ; +; 3.152 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.373 ; +; 3.170 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; ; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.172 ; RCKE~reg0 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.393 ; -; 3.173 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.394 ; -; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; -; 3.179 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; -; 3.180 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.401 ; -; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ; -; 3.186 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.407 ; -; 3.195 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.416 ; -; 3.211 ; Ready ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.432 ; -; 3.276 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.497 ; +; 3.171 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; +; 3.179 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.180 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.401 ; +; 3.184 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; +; 3.189 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.410 ; +; 3.190 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.411 ; +; 3.191 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.412 ; +; 3.205 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.426 ; +; 3.240 ; IS[2] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.461 ; +; 3.247 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.468 ; +; 3.255 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.476 ; +; 3.281 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; ; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.283 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.504 ; -; 3.290 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; -; 3.291 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.512 ; -; 3.361 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.582 ; -; 3.372 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.593 ; -; 3.376 ; RASr2 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.597 ; -; 3.402 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.623 ; -; 3.417 ; IS[0] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.638 ; -; 3.422 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.643 ; -; 3.468 ; Ready ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.689 ; -; 3.471 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.692 ; +; 3.282 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; +; 3.290 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; +; 3.301 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.522 ; +; 3.352 ; CASr3 ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.573 ; +; 3.367 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.588 ; +; 3.383 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.604 ; +; 3.392 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.613 ; +; 3.401 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.622 ; +; 3.412 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.633 ; +; 3.429 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.650 ; +; 3.443 ; InitReady ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.664 ; +; 3.478 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.699 ; +; 3.492 ; FS[13] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; +; 3.492 ; FS[13] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ @@ -700,7 +699,7 @@ No paths to report. ; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; ; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; ; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ; -; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ; +; RCLK ; PHI2 ; 2 ; 0 ; 3 ; 0 ; ; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; ; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; ; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; @@ -722,7 +721,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not ; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; ; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; ; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ; -; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ; +; RCLK ; PHI2 ; 2 ; 0 ; 3 ; 0 ; ; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; ; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; ; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; @@ -752,7 +751,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 31 ; 31 ; -; Unconstrained Input Port Paths ; 257 ; 257 ; +; Unconstrained Input Port Paths ; 255 ; 255 ; ; Unconstrained Output Ports ; 38 ; 38 ; ; Unconstrained Output Port Paths ; 78 ; 78 ; +---------------------------------+-------+------+ @@ -948,7 +947,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:12:56 2023 + Info: Processing started: Sun Aug 13 04:10:21 2023 Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -974,17 +973,17 @@ Info (332146): Worst-case setup slack is -99.000 Info (332119): ========= =================== ===================== Info (332119): -99.000 -99.000 ARCLK Info (332119): -99.000 -99.000 DRCLK - Info (332119): -8.970 -99.540 PHI2 - Info (332119): -7.571 -261.130 RCLK - Info (332119): -1.200 -7.385 nCRAS -Info (332146): Worst-case hold slack is -16.289 + Info (332119): -9.193 -97.128 PHI2 + Info (332119): -8.818 -246.083 RCLK + Info (332119): -1.245 -5.591 nCRAS +Info (332146): Worst-case hold slack is -16.888 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== + Info (332119): -16.888 -16.888 DRCLK Info (332119): -16.289 -16.289 ARCLK - Info (332119): -16.286 -16.286 DRCLK - Info (332119): -1.153 -1.956 PHI2 - Info (332119): 0.098 0.000 nCRAS - Info (332119): 1.148 0.000 RCLK + Info (332119): -0.679 -2.377 PHI2 + Info (332119): -0.104 -0.104 nCRAS + Info (332119): 1.157 0.000 RCLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -29.500 @@ -1000,8 +999,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 4676 megabytes - Info: Processing ended: Sun Aug 13 01:12:57 2023 + Info: Peak virtual memory: 4677 megabytes + Info: Processing ended: Sun Aug 13 04:10:22 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.summary b/CPLD/MAXII/output_files/RAM2GS.sta.summary index 1493d48..256737a 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.summary +++ b/CPLD/MAXII/output_files/RAM2GS.sta.summary @@ -11,35 +11,35 @@ Slack : -99.000 TNS : -99.000 Type : Setup 'PHI2' -Slack : -8.970 -TNS : -99.540 +Slack : -9.193 +TNS : -97.128 Type : Setup 'RCLK' -Slack : -7.571 -TNS : -261.130 +Slack : -8.818 +TNS : -246.083 Type : Setup 'nCRAS' -Slack : -1.200 -TNS : -7.385 +Slack : -1.245 +TNS : -5.591 + +Type : Hold 'DRCLK' +Slack : -16.888 +TNS : -16.888 Type : Hold 'ARCLK' Slack : -16.289 TNS : -16.289 -Type : Hold 'DRCLK' -Slack : -16.286 -TNS : -16.286 - Type : Hold 'PHI2' -Slack : -1.153 -TNS : -1.956 +Slack : -0.679 +TNS : -2.377 Type : Hold 'nCRAS' -Slack : 0.098 -TNS : 0.000 +Slack : -0.104 +TNS : -0.104 Type : Hold 'RCLK' -Slack : 1.148 +Slack : 1.157 TNS : 0.000 Type : Minimum Pulse Width 'ARCLK' diff --git a/CPLD/MAXV/RAM2GS.mif b/CPLD/MAXV/RAM2GS.mif index 3382c37..4b2ca5a 100644 --- a/CPLD/MAXV/RAM2GS.mif +++ b/CPLD/MAXV/RAM2GS.mif @@ -23,6 +23,6 @@ DATA_RADIX=HEX; CONTENT BEGIN [000..0FD] : 0000; - 0FE : 5FFF; + 0FE : 7FFF; [0FF..1FF] : FFFF; END; diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws index ae9cf90..efac7a5 100644 Binary files a/CPLD/MAXV/RAM2GS.qws and b/CPLD/MAXV/RAM2GS.qws differ diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb index aca770c..44fdc4e 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb index 72b603e..4e17e94 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb index 2d7dfff..47b390b 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb index 0868d4b..fa45d57 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAXV/db/RAM2GS.asm.qmsg index 0dee2b1..d0edc93 100644 --- a/CPLD/MAXV/db/RAM2GS.asm.qmsg +++ b/CPLD/MAXV/db/RAM2GS.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903457578 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903457594 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:57 2023 " "Processing started: Sun Aug 13 01:10:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903457594 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903457594 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903457594 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903457797 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903457828 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903457828 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:57 2023 " "Processing ended: Sun Aug 13 01:10:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903457938 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915194082 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915194082 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:33 2023 " "Processing started: Sun Aug 13 04:26:33 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915194082 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691915194082 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691915194082 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691915194348 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691915194363 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691915194379 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:34 2023 " "Processing ended: Sun Aug 13 04:26:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691915194488 ""} diff --git a/CPLD/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAXV/db/RAM2GS.asm.rdb index c292f72..b611751 100644 Binary files a/CPLD/MAXV/db/RAM2GS.asm.rdb and b/CPLD/MAXV/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb index 93b3d50..a2dd879 100644 Binary files a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAXV/db/RAM2GS.cmp.cdb index a3870a7..4607ca8 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.cdb and b/CPLD/MAXV/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.hdb b/CPLD/MAXV/db/RAM2GS.cmp.hdb index 6c0a9f7..df23495 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.hdb and b/CPLD/MAXV/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAXV/db/RAM2GS.cmp.idb index e44e69b..ea02ef1 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.idb and b/CPLD/MAXV/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAXV/db/RAM2GS.cmp.rdb index 6ecb70d..6d18490 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.rdb and b/CPLD/MAXV/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp0.ddb b/CPLD/MAXV/db/RAM2GS.cmp0.ddb index dc6bd54..e3207b8 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp0.ddb and b/CPLD/MAXV/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/MAXV/db/RAM2GS.db_info b/CPLD/MAXV/db/RAM2GS.db_info index a117676..302dc98 100644 --- a/CPLD/MAXV/db/RAM2GS.db_info +++ b/CPLD/MAXV/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sun Aug 13 00:27:41 2023 +Creation_Time = Sun Aug 13 04:15:04 2023 diff --git a/CPLD/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAXV/db/RAM2GS.fit.qmsg index fac2c7c..f75997c 100644 --- a/CPLD/MAXV/db/RAM2GS.fit.qmsg +++ b/CPLD/MAXV/db/RAM2GS.fit.qmsg @@ -1,45 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903455438 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903455438 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903455438 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903455469 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903455469 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903455500 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903455500 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903455594 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903455641 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903455641 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903455641 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903455641 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903455656 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903455656 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903455672 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903455703 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903455703 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903455703 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903455703 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903455719 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903455719 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903455797 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903455906 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903455906 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903456234 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456234 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903456266 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903456375 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903456375 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903456500 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903456500 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456516 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903456516 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456531 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903456547 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903456578 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:56 2023 " "Processing ended: Sun Aug 13 01:10:56 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903456609 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691915191832 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691915191832 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691915191832 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915191879 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915191879 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691915191894 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691915191894 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691915192004 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691915192066 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691915192066 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691915192066 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691915192066 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691915192066 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915192066 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915192066 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915192066 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691915192082 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691915192098 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691915192129 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691915192129 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691915192129 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691915192129 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192144 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691915192160 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691915192238 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192332 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691915192348 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691915192676 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192676 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691915192691 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691915192816 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691915192816 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691915192957 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691915192957 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192957 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691915192957 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192973 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691915192988 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691915193020 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:33 2023 " "Processing ended: Sun Aug 13 04:26:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691915193057 ""} diff --git a/CPLD/MAXV/db/RAM2GS.hier_info b/CPLD/MAXV/db/RAM2GS.hier_info index f655925..01107ce 100644 --- a/CPLD/MAXV/db/RAM2GS.hier_info +++ b/CPLD/MAXV/db/RAM2GS.hier_info @@ -69,20 +69,20 @@ MAin[9] => RowA.DATAB MAin[9] => RDQML.DATAA CROW[0] => RBA.DATAB CROW[1] => RBA.DATAB +Din[0] => XOR8MEG.IN1 Din[0] => CmdDRDIn.DATAB -Din[0] => XOR8MEG.DATAB Din[0] => WRD[0].DATAIN Din[0] => Bank[0].DATAIN Din[0] => Equal14.IN2 Din[0] => Equal15.IN4 Din[0] => Cmdn8MEGEN.DATAB +Din[1] => XOR8MEG.IN1 Din[1] => CmdDRCLK.DATAB +Din[1] => CmdLEDEN.DATAB Din[1] => WRD[1].DATAIN Din[1] => Bank[1].DATAIN Din[1] => Equal14.IN7 Din[1] => Equal15.IN7 -Din[1] => Equal17.IN2 -Din[1] => CmdLEDEN.DATAB Din[2] => CmdUFMPrgm.DATAB Din[2] => WRD[2].DATAIN Din[2] => Bank[2].DATAIN @@ -124,14 +124,14 @@ Din[7] => Equal15.IN0 Din[7] => Equal16.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 -Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE -Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE -Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE -Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE -Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE -Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE -Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE -Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE +Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE nCCAS => WRD[0].CLK nCCAS => WRD[1].CLK nCCAS => WRD[2].CLK @@ -164,21 +164,21 @@ nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN -LED <= LED.DB_MAX_OUTPUT_PORT_TYPE -RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE -RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE +LED << LED.DB_MAX_OUTPUT_PORT_TYPE +RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE RD[0] <> RD[0] RD[1] <> RD[1] RD[2] <> RD[2] @@ -187,7 +187,7 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] -nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK @@ -243,12 +243,12 @@ RCLK => RASr.CLK RCLK => PHI2r3.CLK RCLK => PHI2r2.CLK RCLK => PHI2r.CLK -RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE -RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE +RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE +RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE |RAM2GS|UFM:UFM_inst diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif index cf97260..53614c0 100644 Binary files a/CPLD/MAXV/db/RAM2GS.hif and b/CPLD/MAXV/db/RAM2GS.hif differ diff --git a/CPLD/MAXV/db/RAM2GS.map.cdb b/CPLD/MAXV/db/RAM2GS.map.cdb index 8024be4..722b535 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.cdb and b/CPLD/MAXV/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.map.hdb b/CPLD/MAXV/db/RAM2GS.map.hdb index fc39e15..e392747 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.hdb and b/CPLD/MAXV/db/RAM2GS.map.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAXV/db/RAM2GS.map.qmsg index 10cac29..a88eb07 100644 --- a/CPLD/MAXV/db/RAM2GS.map.qmsg +++ b/CPLD/MAXV/db/RAM2GS.map.qmsg @@ -1,27 +1,27 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903444032 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903444032 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:43 2023 " "Processing started: Sun Aug 13 01:10:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903444032 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903444032 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903444032 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903444516 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903444516 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903453629 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903453629 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903453660 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903453660 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453660 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453660 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903453660 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903453707 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903453723 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903454031 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903454031 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903454078 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:54 2023 " "Processing ended: Sun Aug 13 01:10:54 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903454094 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915181672 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915181672 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:21 2023 " "Processing started: Sun Aug 13 04:26:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915181672 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915181672 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915181672 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691915181972 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691915181972 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691915190051 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190051 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190051 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915190082 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915190082 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190082 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190082 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190082 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915190129 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691915190410 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691915190410 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190457 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:30 2023 " "Processing ended: Sun Aug 13 04:26:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190488 ""} diff --git a/CPLD/MAXV/db/RAM2GS.map.rdb b/CPLD/MAXV/db/RAM2GS.map.rdb index 89c4807..f7b6ac8 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.rdb and b/CPLD/MAXV/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAXV/db/RAM2GS.pre_map.hdb index 5a435a8..5ea0562 100644 Binary files a/CPLD/MAXV/db/RAM2GS.pre_map.hdb and b/CPLD/MAXV/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAXV/db/RAM2GS.routing.rdb index d09de7b..83c925a 100644 Binary files a/CPLD/MAXV/db/RAM2GS.routing.rdb and b/CPLD/MAXV/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAXV/db/RAM2GS.rtlv.hdb index 9d58585..c94e9bc 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv.hdb and b/CPLD/MAXV/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb index ad3563e..0d90016 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb index 9706cf7..d8244d7 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAXV/db/RAM2GS.sta.qmsg index 493f545..a849a55 100644 --- a/CPLD/MAXV/db/RAM2GS.sta.qmsg +++ b/CPLD/MAXV/db/RAM2GS.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903459094 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903459110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:58 2023 " "Processing started: Sun Aug 13 01:10:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903459110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459110 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459110 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903459219 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903459328 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903459328 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459360 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459360 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903459407 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903459578 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903459610 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459610 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459610 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903459610 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903459625 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.792 -122.191 PHI2 " " -10.792 -122.191 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.864 -306.770 RCLK " " -8.864 -306.770 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.878 -11.627 nCRAS " " -2.878 -11.627 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.715 " "Worst-case hold slack is -16.715" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.715 -16.715 DRCLK " " -16.715 -16.715 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.888 -15.888 ARCLK " " -15.888 -15.888 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.520 -0.782 PHI2 " " -0.520 -0.782 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.622 0.000 nCRAS " " 0.622 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903459641 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459641 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903459703 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903459719 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903459719 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:59 2023 " "Processing ended: Sun Aug 13 01:10:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903459766 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915195644 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915195644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:35 2023 " "Processing started: Sun Aug 13 04:26:35 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915195644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915195644 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915195644 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691915195754 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691915195879 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691915195879 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915195910 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915195910 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691915195957 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691915196129 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691915196160 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196160 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691915196160 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691915196160 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691915196176 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691915196176 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196176 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691915196254 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915196269 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915196269 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:36 2023 " "Processing ended: Sun Aug 13 04:26:36 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915196317 ""} diff --git a/CPLD/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAXV/db/RAM2GS.sta.rdb index 15ada92..aa910fe 100644 Binary files a/CPLD/MAXV/db/RAM2GS.sta.rdb and b/CPLD/MAXV/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb index ceb12fd..deea71f 100644 Binary files a/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb and b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb differ diff --git a/CPLD/MAXV/db/RAM2GS.tmw_info b/CPLD/MAXV/db/RAM2GS.tmw_info index 6f8e418..dcc6637 100644 --- a/CPLD/MAXV/db/RAM2GS.tmw_info +++ b/CPLD/MAXV/db/RAM2GS.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:17 -start_analysis_synthesis:s:00:00:11-start_full_compilation +start_full_compilation:s:00:00:15 +start_analysis_synthesis:s:00:00:10-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:03-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:02-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/CPLD/MAXV/db/RAM2GS.vpr.ammdb b/CPLD/MAXV/db/RAM2GS.vpr.ammdb index 64c0be8..04358f8 100644 Binary files a/CPLD/MAXV/db/RAM2GS.vpr.ammdb and b/CPLD/MAXV/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg index aada0d4..94d78d8 100644 --- a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg +++ b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg @@ -1,112 +1,112 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903396510 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903396515 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:09:56 2023 " "Processing started: Sun Aug 13 01:09:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903396515 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903396515 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903396515 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903396906 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903396906 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903405936 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405936 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903405936 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903405967 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903405967 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405967 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903405967 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903406014 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406280 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406280 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903406311 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903406311 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903406358 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:06 2023 " "Processing ended: Sun Aug 13 01:10:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903406374 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691903407577 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903407577 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:07 2023 " "Processing started: Sun Aug 13 01:10:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903407577 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691903407577 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691903407577 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691903407686 ""} -{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691903407686 ""} -{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691903407686 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903407717 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903407717 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903407717 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903407764 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903407764 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903407795 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903407811 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903407906 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903407953 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903407953 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903407953 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903407953 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903407953 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903407953 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903407953 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903407953 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903407969 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903407985 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903408000 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903408000 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903408000 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903408000 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408031 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903408031 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903408110 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408219 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903408219 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903408578 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408578 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903408594 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "21 " "Router estimated average interconnect usage is 21% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903408703 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903408703 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903408860 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903408860 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408860 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903408860 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408875 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903408891 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903408922 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:08 2023 " "Processing ended: Sun Aug 13 01:10:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903408953 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691903409960 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903409976 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:09 2023 " "Processing started: Sun Aug 13 01:10:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903409976 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903409976 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903409976 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903410226 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903410242 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903410257 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:10 2023 " "Processing ended: Sun Aug 13 01:10:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903410351 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691903410976 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691903411523 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903411523 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:11 2023 " "Processing started: Sun Aug 13 01:10:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903411523 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903411523 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903411523 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903411632 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903411742 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903411742 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903411789 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903411789 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903411835 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903412007 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903412039 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412039 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903412039 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903412039 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903412054 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903412054 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.721 -118.450 PHI2 " " -10.721 -118.450 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.110 -293.269 RCLK " " -9.110 -293.269 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.660 -10.655 nCRAS " " -2.660 -10.655 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412054 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.633 " "Worst-case hold slack is -16.633" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.633 -16.633 DRCLK " " -16.633 -16.633 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.892 -15.892 ARCLK " " -15.892 -15.892 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.638 -1.005 PHI2 " " -0.638 -1.005 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 nCRAS " " 0.319 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903412132 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903412164 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903412164 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:12 2023 " "Processing ended: Sun Aug 13 01:10:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903412210 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903412851 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915089171 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915089172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:24:49 2023 " "Processing started: Sun Aug 13 04:24:49 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915089172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915089172 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915089172 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691915089467 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691915089467 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691915097582 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097582 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097613 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915097644 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915097644 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691915097942 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691915097942 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097988 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:24:58 2023 " "Processing ended: Sun Aug 13 04:24:58 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915098004 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691915099207 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915099207 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:24:58 2023 " "Processing started: Sun Aug 13 04:24:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915099207 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691915099207 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691915099207 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691915099301 ""} +{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691915099301 ""} +{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691915099301 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691915099379 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691915099379 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691915099379 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915099426 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915099426 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691915099441 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691915099457 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691915099551 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691915099598 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691915099598 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691915099598 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691915099598 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691915099598 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915099598 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915099598 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915099598 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691915099613 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691915099629 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691915099644 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691915099644 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691915099644 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691915099644 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915099676 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691915099676 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691915099754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915099863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691915099863 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691915100223 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100223 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691915100238 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691915100348 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691915100348 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691915100488 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691915100488 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100504 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691915100504 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100504 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691915100535 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691915100566 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:00 2023 " "Processing ended: Sun Aug 13 04:25:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691915100598 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691915101629 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915101629 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:25:01 2023 " "Processing started: Sun Aug 13 04:25:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915101629 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691915101629 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691915101629 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691915101879 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691915101894 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691915101894 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:02 2023 " "Processing ended: Sun Aug 13 04:25:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691915102004 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691915102613 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691915103146 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915103146 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:25:02 2023 " "Processing started: Sun Aug 13 04:25:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915103146 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103146 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103146 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691915103254 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691915103379 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691915103379 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103410 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103410 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691915103457 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691915103629 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691915103660 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691915103676 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915103691 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103691 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691915103754 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915103785 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915103785 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:03 2023 " "Processing ended: Sun Aug 13 04:25:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915103832 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915104519 ""} diff --git a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt index 425b2ac..e76c170 100644 Binary files a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt index 65d50b7..5ec12b8 100644 --- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 01:10:57 2023 +Sun Aug 13 04:26:34 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 01:10:57 2023 ; +; Assembler Status ; Successful - Sun Aug 13 04:26:34 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+--------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+--------------------------------------------------------------------------------+ -; JTAG usercode ; 0x0017386C ; -; Checksum ; 0x00173C5C ; +; JTAG usercode ; 0x0017116A ; +; Checksum ; 0x001714EA ; +----------------+--------------------------------------------------------------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:10:57 2023 + Info: Processing started: Sun Aug 13 04:26:33 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 4662 megabytes - Info: Processing ended: Sun Aug 13 01:10:57 2023 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 + Info: Processing ended: Sun Aug 13 04:26:34 2023 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done index 2b520e3..7c82637 100644 --- a/CPLD/MAXV/output_files/RAM2GS.done +++ b/CPLD/MAXV/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 01:11:00 2023 +Sun Aug 13 04:26:36 2023 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt index ebed07c..877e3f6 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 01:10:56 2023 +Sun Aug 13 04:26:33 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,14 +59,14 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 01:10:56 2023 ; +; Fitter Status ; Successful - Sun Aug 13 04:26:33 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; ; Device ; 5M240ZT100C4 ; ; Timing Models ; Final ; -; Total logic elements ; 174 / 240 ( 73 % ) ; +; Total logic elements ; 175 / 240 ( 73 % ) ; ; Total pins ; 63 / 79 ( 80 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -130,13 +130,13 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.05 ; +; Average used ; 1.04 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.6% ; -; Processors 3-4 ; 1.5% ; +; Processor 2 ; 1.5% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ @@ -151,20 +151,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o +---------------------------------------------+-----------------------+ ; Resource ; Usage ; +---------------------------------------------+-----------------------+ -; Total logic elements ; 174 / 240 ( 73 % ) ; -; -- Combinational with no register ; 76 ; +; Total logic elements ; 175 / 240 ( 73 % ) ; +; -- Combinational with no register ; 77 ; ; -- Register only ; 21 ; ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 47 ; -; -- 2 input functions ; 40 ; +; -- 4 input functions ; 56 ; +; -- 3 input functions ; 48 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 158 ; +; -- normal mode ; 159 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; @@ -172,7 +172,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 21 / 24 ( 88 % ) ; +; Total LABs ; 23 / 24 ( 96 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 79 ( 80 % ) ; @@ -186,11 +186,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 24.0% / 26.3% / 21.7% ; -; Peak interconnect usage (total/H/V) ; 24.0% / 26.3% / 21.7% ; +; Average interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; +; Peak interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; -; Total fan-out ; 660 ; +; Total fan-out ; 661 ; ; Average fan-out ; 2.77 ; +---------------------------------------------+-----------------------+ @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -241,12 +241,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; -; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -256,12 +256,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -425,7 +425,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2GS ; 174 (174) ; 98 ; 1 ; 63 ; 0 ; 76 (76) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ; +; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ @@ -494,8 +494,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[7] ; Input ; (1) ; ; Din[1] ; Input ; (1) ; +; Din[7] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -508,14 +508,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X5_Y4_N8 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X5_Y4_N5 ; 3 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X4_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~2 ; LC_X6_Y2_N0 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X6_Y2_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X5_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X4_Y3_N6 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X5_Y4_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X4_Y4_N8 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X3_Y3_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~7 ; LC_X5_Y2_N6 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X5_Y4_N1 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; ; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -538,110 +538,111 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 141 / 784 ( 18 % ) ; -; Direct links ; 52 / 888 ( 6 % ) ; +; C4s ; 144 / 784 ( 18 % ) ; +; Direct links ; 51 / 888 ( 6 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; -; LAB clocks ; 15 / 32 ( 47 % ) ; -; LUT chains ; 19 / 216 ( 9 % ) ; -; Local interconnects ; 269 / 888 ( 30 % ) ; -; R4s ; 149 / 704 ( 21 % ) ; +; LAB clocks ; 17 / 32 ( 53 % ) ; +; LUT chains ; 18 / 216 ( 8 % ) ; +; Local interconnects ; 286 / 888 ( 32 % ) ; +; R4s ; 167 / 704 ( 24 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 21) ; +; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ; +--------------------------------------------+------------------------------+ -; 1 ; 0 ; -; 2 ; 3 ; -; 3 ; 0 ; -; 4 ; 1 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 2 ; ; 5 ; 0 ; -; 6 ; 0 ; +; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 2 ; -; 9 ; 2 ; -; 10 ; 13 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 14 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 21) ; +; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ; +------------------------------------+------------------------------+ -; 1 Clock ; 11 ; -; 1 Clock enable ; 6 ; -; 1 Sync. clear ; 3 ; +; 1 Clock ; 13 ; +; 1 Clock enable ; 4 ; +; 1 Sync. clear ; 4 ; ; 1 Sync. load ; 2 ; -; 2 Clocks ; 10 ; +; 2 Clocks ; 9 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 8.57) ; Number of LABs (Total = 21) ; +; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 3 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 2 ; +; 5 ; 0 ; +; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 2 ; -; 9 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; ; 10 ; 10 ; -; 11 ; 4 ; +; 11 ; 2 ; +; 12 ; 2 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 21) ; +; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 5 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 2 ; -; 6 ; 4 ; -; 7 ; 3 ; -; 8 ; 1 ; -; 9 ; 3 ; -; 10 ; 1 ; +; 1 ; 2 ; +; 2 ; 2 ; +; 3 ; 3 ; +; 4 ; 3 ; +; 5 ; 1 ; +; 6 ; 3 ; +; 7 ; 2 ; +; 8 ; 2 ; +; 9 ; 2 ; +; 10 ; 3 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.19) ; Number of LABs (Total = 21) ; +; Number of Distinct Inputs (Average = 10.52) ; Number of LABs (Total = 23) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 1 ; -; 3 ; 2 ; +; 1 ; 0 ; +; 2 ; 2 ; +; 3 ; 1 ; ; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 2 ; -; 9 ; 1 ; -; 10 ; 2 ; -; 11 ; 3 ; -; 12 ; 2 ; -; 13 ; 0 ; -; 14 ; 1 ; -; 15 ; 1 ; -; 16 ; 2 ; +; 5 ; 3 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 2 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 1 ; +; 13 ; 4 ; +; 14 ; 3 ; +; 15 ; 0 ; +; 16 ; 1 ; ; 17 ; 1 ; -; 18 ; 0 ; +; 18 ; 1 ; ; 19 ; 1 ; +----------------------------------------------+------------------------------+ @@ -738,19 +739,19 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 18% of the available device resources - Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 20% of the available device resources + Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.23 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings Info: Peak virtual memory: 5345 megabytes - Info: Processing ended: Sun Aug 13 01:10:56 2023 - Info: Elapsed time: 00:00:01 + Info: Processing ended: Sun Aug 13 04:26:33 2023 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary index 1a4d304..2949ad4 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Sun Aug 13 01:10:56 2023 +Fitter Status : Successful - Sun Aug 13 04:26:33 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX V Device : 5M240ZT100C4 Timing Models : Final -Total logic elements : 174 / 240 ( 73 % ) +Total logic elements : 175 / 240 ( 73 % ) Total pins : 63 / 79 ( 80 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt index fb9261e..2c54bf4 100644 --- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 01:10:59 2023 +Sun Aug 13 04:26:36 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 01:10:57 2023 ; +; Flow Status ; Successful - Sun Aug 13 04:26:34 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; ; Device ; 5M240ZT100C4 ; ; Timing Models ; Final ; -; Total logic elements ; 174 / 240 ( 73 % ) ; +; Total logic elements ; 175 / 240 ( 73 % ) ; ; Total pins ; 63 / 79 ( 80 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 01:10:44 ; +; Start date & time ; 08/13/2023 04:26:21 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169190344412624 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169191518110472 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; @@ -84,11 +84,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4701 MB ; 00:00:24 ; -; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:02 ; -; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ; +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ; +; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:02 ; +; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; -; Total ; 00:00:13 ; -- ; -- ; 00:00:27 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:25 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 70fb58f..742df3f 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 01:10:54 2023 +Sun Aug 13 04:26:30 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 01:10:54 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:26:30 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; -; Total logic elements ; 183 ; +; Total logic elements ; 184 ; ; Total pins ; 63 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -161,20 +161,20 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 183 ; -; -- Combinational with no register ; 85 ; +; Total logic elements ; 184 ; +; -- Combinational with no register ; 86 ; ; -- Register only ; 30 ; ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 47 ; -; -- 2 input functions ; 40 ; +; -- 4 input functions ; 56 ; +; -- 3 input functions ; 48 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 167 ; +; -- normal mode ; 168 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; @@ -187,8 +187,8 @@ https://fpgasoftware.intel.com/eula. ; UFM blocks ; 1 ; ; Maximum fan-out node ; RCLK ; ; Maximum fan-out ; 55 ; -; Total fan-out ; 661 ; -; Average fan-out ; 2.68 ; +; Total fan-out ; 662 ; +; Average fan-out ; 2.67 ; +---------------------------------------------+-------+ @@ -197,7 +197,7 @@ https://fpgasoftware.intel.com/eula. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2GS ; 183 (183) ; 98 ; 1 ; 63 ; 0 ; 85 (85) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; +; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:10:43 2023 + Info: Processing started: Sun Aug 13 04:26:21 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -293,18 +293,18 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 -Info (21057): Implemented 247 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 183 logic cells + Info (21061): Implemented 184 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 4701 megabytes - Info: Processing ended: Sun Aug 13 01:10:54 2023 - Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:24 + Info: Peak virtual memory: 4702 megabytes + Info: Processing ended: Sun Aug 13 04:26:30 2023 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:22 +------------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index fcf4424..90e9085 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 01:10:54 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 04:26:30 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX V -Total logic elements : 183 +Total logic elements : 184 Total pins : 63 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2GS.pof b/CPLD/MAXV/output_files/RAM2GS.pof index 01fae2e..e4b2cb7 100644 Binary files a/CPLD/MAXV/output_files/RAM2GS.pof and b/CPLD/MAXV/output_files/RAM2GS.pof differ diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt index d256f44..76840b1 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sun Aug 13 01:10:59 2023 +Sun Aug 13 04:26:36 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -87,7 +87,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 0.1% ; +----------------------------+-------------+ @@ -105,16 +105,16 @@ https://fpgasoftware.intel.com/eula. +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 44.28 MHz ; 44.28 MHz ; PHI2 ; ; -; 101.38 MHz ; 101.38 MHz ; RCLK ; ; -+------------+-----------------+------------+------+ ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 46.89 MHz ; 46.89 MHz ; PHI2 ; ; +; 96.27 MHz ; 96.27 MHz ; RCLK ; ; ++-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -125,9 +125,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; ARCLK ; -99.000 ; -99.000 ; ; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -10.792 ; -122.191 ; -; RCLK ; -8.864 ; -306.770 ; -; nCRAS ; -2.878 ; -11.627 ; +; PHI2 ; -10.164 ; -118.093 ; +; RCLK ; -9.387 ; -288.937 ; +; nCRAS ; -2.870 ; -7.136 ; +-------+---------+---------------+ @@ -136,10 +136,10 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; DRCLK ; -16.715 ; -16.715 ; -; ARCLK ; -15.888 ; -15.888 ; -; PHI2 ; -0.520 ; -0.782 ; -; nCRAS ; 0.622 ; 0.000 ; +; DRCLK ; -16.578 ; -16.578 ; +; ARCLK ; -16.552 ; -16.552 ; +; PHI2 ; -0.611 ; -0.993 ; +; nCRAS ; 0.443 ; 0.000 ; ; RCLK ; 1.178 ; 0.000 ; +-------+---------+---------------+ @@ -176,7 +176,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -23.112 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.409 ; 1.703 ; +; -22.448 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.761 ; 1.687 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -186,8 +186,8 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.902 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.586 ; 2.316 ; -; -22.285 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.586 ; 1.699 ; +; -23.156 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.735 ; 2.421 ; +; -22.422 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.735 ; 1.687 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -196,106 +196,106 @@ No paths to report. +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -10.792 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.032 ; -; -10.792 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.032 ; -; -10.774 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.014 ; -; -10.774 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.014 ; -; -10.757 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.997 ; -; -10.703 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.943 ; -; -10.700 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.940 ; -; -10.596 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.836 ; -; -10.596 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.836 ; -; -10.578 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.818 ; -; -10.578 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.818 ; -; -10.561 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.801 ; -; -10.507 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.747 ; -; -10.504 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.744 ; -; -9.847 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.087 ; -; -9.847 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.087 ; -; -9.829 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.069 ; -; -9.829 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.069 ; -; -9.812 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.052 ; -; -9.758 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.998 ; -; -9.755 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.995 ; -; -9.747 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.987 ; -; -9.747 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.987 ; -; -9.729 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.969 ; -; -9.729 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.969 ; -; -9.712 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.952 ; -; -9.658 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.898 ; -; -9.655 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.895 ; -; -9.547 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.787 ; -; -9.547 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.787 ; -; -9.529 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.769 ; -; -9.529 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.769 ; -; -9.512 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.752 ; -; -9.458 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.698 ; -; -9.455 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.695 ; -; -9.286 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.526 ; -; -9.286 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.526 ; -; -9.130 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.370 ; -; -9.130 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.370 ; -; -9.112 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.352 ; -; -9.112 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.352 ; -; -9.095 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.335 ; -; -9.090 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.330 ; -; -9.090 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.330 ; -; -9.041 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.281 ; -; -9.038 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.278 ; -; -8.798 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.038 ; -; -8.798 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.038 ; -; -8.780 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.020 ; -; -8.780 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.020 ; -; -8.763 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.003 ; -; -8.709 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.949 ; -; -8.706 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.946 ; -; -8.560 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.800 ; -; -8.560 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.800 ; -; -8.364 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.604 ; -; -8.364 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.604 ; -; -8.341 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.581 ; -; -8.341 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.581 ; -; -8.241 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.481 ; -; -8.241 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.481 ; -; -8.082 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.322 ; -; -8.082 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.322 ; -; -8.064 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ; -; -8.064 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ; -; -8.064 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ; -; -8.047 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.287 ; -; -8.041 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.281 ; -; -8.041 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.281 ; -; -7.993 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.233 ; -; -7.990 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.230 ; -; -7.868 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ; -; -7.624 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.864 ; -; -7.624 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.864 ; -; -7.615 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.855 ; -; -7.615 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.855 ; -; -7.515 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.755 ; -; -7.515 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.755 ; -; -7.315 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.555 ; -; -7.315 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.555 ; -; -7.292 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.532 ; -; -7.292 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.532 ; -; -7.119 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.359 ; -; -7.019 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.259 ; -; -6.898 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.138 ; -; -6.898 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.138 ; -; -6.819 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.059 ; -; -6.576 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.816 ; -; -6.576 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.816 ; -; -6.566 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.806 ; -; -6.566 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.806 ; -; -6.410 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.150 ; -; -6.410 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.150 ; -; -6.402 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.642 ; -; -6.375 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.115 ; -; -6.070 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.310 ; -; -5.850 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.090 ; -; -5.850 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.090 ; -; -5.758 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.498 ; -; -5.758 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.498 ; +; -10.164 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; +; -10.164 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; +; -10.164 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; +; -10.084 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.324 ; +; -10.084 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.324 ; +; -9.954 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; +; -9.954 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; +; -9.954 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; +; -9.874 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.114 ; +; -9.874 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.114 ; +; -9.731 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; +; -9.731 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; +; -9.731 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; +; -9.696 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.936 ; +; -9.693 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.933 ; +; -9.663 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.903 ; +; -9.663 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.903 ; +; -9.651 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.891 ; +; -9.651 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.891 ; +; -9.531 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; +; -9.531 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; +; -9.531 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; +; -9.486 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.726 ; +; -9.483 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.723 ; +; -9.453 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.693 ; +; -9.453 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.693 ; +; -9.451 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.691 ; +; -9.451 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.691 ; +; -9.263 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.503 ; +; -9.260 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.500 ; +; -9.230 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.470 ; +; -9.230 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.470 ; +; -9.219 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; +; -9.219 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; +; -9.219 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; +; -9.139 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.379 ; +; -9.139 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.379 ; +; -9.063 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.303 ; +; -9.060 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.300 ; +; -9.030 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.270 ; +; -9.030 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.270 ; +; -8.791 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; +; -8.791 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; +; -8.791 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; +; -8.751 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.991 ; +; -8.748 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.988 ; +; -8.718 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.958 ; +; -8.718 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.958 ; +; -8.711 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.951 ; +; -8.711 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.951 ; +; -8.580 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; +; -8.503 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; +; -8.503 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; +; -8.503 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; +; -8.501 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.741 ; +; -8.501 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.741 ; +; -8.423 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.663 ; +; -8.423 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.663 ; +; -8.370 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.610 ; +; -8.323 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.563 ; +; -8.320 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.560 ; +; -8.291 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.531 ; +; -8.291 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.531 ; +; -8.290 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.530 ; +; -8.290 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.530 ; +; -8.147 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ; +; -8.068 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.308 ; +; -8.068 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.308 ; +; -8.066 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; +; -8.066 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; +; -8.066 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; +; -8.035 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.275 ; +; -8.032 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.272 ; +; -8.002 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.242 ; +; -8.002 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.242 ; +; -7.986 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.226 ; +; -7.986 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.226 ; +; -7.947 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.187 ; +; -7.868 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ; +; -7.868 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ; +; -7.635 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.875 ; +; -7.598 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.838 ; +; -7.595 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.835 ; +; -7.565 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.805 ; +; -7.565 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.805 ; +; -7.556 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.796 ; +; -7.556 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.796 ; +; -7.207 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.447 ; +; -7.128 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.368 ; +; -7.128 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.368 ; +; -6.919 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.159 ; +; -6.840 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.080 ; +; -6.840 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.080 ; +; -6.482 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.722 ; +; -6.403 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.643 ; +; -6.403 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.643 ; +; -5.870 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; +; -5.870 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; +; -5.870 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; +; -5.790 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.530 ; +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ @@ -304,106 +304,106 @@ No paths to report. +--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ -; -8.864 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.604 ; -; -8.716 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.456 ; -; -8.605 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 6.619 ; -; -8.582 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.322 ; -; -8.538 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.278 ; -; -8.430 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.627 ; -; -8.372 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.112 ; -; -8.349 ; S[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.089 ; -; -8.314 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.511 ; -; -8.271 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.011 ; -; -8.258 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.998 ; -; -8.237 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.977 ; -; -8.197 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.937 ; -; -8.093 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.833 ; -; -8.090 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.830 ; -; -8.068 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.808 ; -; -8.018 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.758 ; -; -8.014 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.754 ; -; -7.992 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.732 ; -; -7.965 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.162 ; -; -7.955 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.695 ; -; -7.910 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.924 ; -; -7.893 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.633 ; -; -7.890 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.630 ; -; -7.885 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.899 ; -; -7.877 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.891 ; -; -7.844 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.584 ; -; -7.826 ; FS[6] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.566 ; -; -7.799 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.539 ; -; -7.785 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.799 ; -; -7.752 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.492 ; -; -7.746 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.486 ; -; -7.734 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.474 ; -; -7.710 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.450 ; -; -7.697 ; FS[9] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.437 ; -; -7.688 ; UFMD ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.428 ; -; -7.663 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.403 ; -; -7.584 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.781 ; -; -7.555 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.295 ; -; -7.549 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.289 ; -; -7.542 ; UFMInitDone ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.282 ; -; -7.503 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.243 ; -; -7.494 ; FS[9] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.234 ; -; -7.452 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.192 ; -; -7.390 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.130 ; -; -7.386 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.126 ; -; -7.381 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.121 ; -; -7.377 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.574 ; -; -7.354 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.094 ; -; -7.308 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.048 ; -; -7.285 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.025 ; -; -7.279 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.019 ; -; -7.260 ; S[1] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.000 ; -; -7.234 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.974 ; -; -7.224 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.964 ; -; -7.185 ; UFMD ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.925 ; -; -7.182 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.196 ; -; -7.165 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.905 ; -; -7.163 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.903 ; -; -7.162 ; S[1] ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ; -; -7.157 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.171 ; -; -7.151 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.891 ; -; -7.146 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.886 ; -; -7.138 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.878 ; -; -7.099 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.296 ; -; -7.082 ; S[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.822 ; -; -7.061 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.801 ; -; -7.057 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.071 ; -; -7.050 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.790 ; -; -7.047 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.787 ; -; -7.041 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.781 ; -; -7.029 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.043 ; -; -7.000 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.740 ; -; -6.997 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.737 ; -; -6.954 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.694 ; -; -6.935 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.675 ; -; -6.918 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.658 ; -; -6.915 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.655 ; -; -6.914 ; FS[15] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.654 ; -; -6.911 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.651 ; -; -6.888 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.628 ; -; -6.880 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.620 ; -; -6.844 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.584 ; -; -6.817 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.557 ; -; -6.808 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.548 ; -; -6.741 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.481 ; -; -6.684 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.424 ; -; -6.670 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.410 ; -; -6.669 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.409 ; -; -6.616 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.356 ; -; -6.597 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.337 ; -; -6.579 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.319 ; -; -6.554 ; S[0] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.294 ; -; -6.552 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 4.566 ; -; -6.545 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.285 ; -; -6.539 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.539 ; Ready ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.525 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.265 ; -; -6.506 ; Ready ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.246 ; -; -6.495 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.235 ; +; -9.387 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 10.127 ; +; -9.117 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.857 ; +; -8.872 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.612 ; +; -8.682 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.422 ; +; -8.654 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.394 ; +; -8.600 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.340 ; +; -8.571 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.311 ; +; -8.559 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.299 ; +; -8.503 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.243 ; +; -8.442 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.182 ; +; -8.399 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.139 ; +; -8.384 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.124 ; +; -8.351 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.091 ; +; -8.335 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.075 ; +; -8.301 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.041 ; +; -8.292 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.032 ; +; -8.219 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 5.315 ; +; -8.172 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.912 ; +; -8.145 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.885 ; +; -8.117 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.857 ; +; -8.114 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.854 ; +; -8.045 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 6.088 ; +; -8.033 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.773 ; +; -8.003 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.743 ; +; -7.996 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.736 ; +; -7.992 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.732 ; +; -7.942 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.682 ; +; -7.869 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.609 ; +; -7.858 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.598 ; +; -7.780 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.520 ; +; -7.765 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.505 ; +; -7.763 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.503 ; +; -7.743 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.483 ; +; -7.740 ; FS[5] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.480 ; +; -7.727 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.467 ; +; -7.726 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.466 ; +; -7.697 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.437 ; +; -7.691 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.431 ; +; -7.642 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.382 ; +; -7.614 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.354 ; +; -7.611 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.351 ; +; -7.557 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.297 ; +; -7.556 ; S[1] ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.296 ; +; -7.556 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.296 ; +; -7.526 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.266 ; +; -7.506 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.602 ; +; -7.496 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.539 ; +; -7.472 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.212 ; +; -7.457 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.197 ; +; -7.433 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.173 ; +; -7.432 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.172 ; +; -7.395 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.135 ; +; -7.377 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.117 ; +; -7.340 ; InitReady ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.080 ; +; -7.338 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.381 ; +; -7.300 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.343 ; +; -7.287 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.027 ; +; -7.278 ; FS[15] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.018 ; +; -7.271 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.011 ; +; -7.265 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.005 ; +; -7.237 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.977 ; +; -7.223 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.963 ; +; -7.212 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.952 ; +; -7.211 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.951 ; +; -7.205 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.945 ; +; -7.193 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.933 ; +; -7.164 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.904 ; +; -7.162 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ; +; -7.162 ; FS[6] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ; +; -7.157 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.253 ; +; -7.155 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.251 ; +; -7.139 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.879 ; +; -7.108 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.848 ; +; -7.086 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.826 ; +; -7.074 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.814 ; +; -7.073 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.813 ; +; -7.019 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.759 ; +; -7.006 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.746 ; +; -7.000 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.740 ; +; -6.997 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.737 ; +; -6.993 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.733 ; +; -6.955 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.695 ; +; -6.954 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.694 ; +; -6.951 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.691 ; +; -6.936 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.979 ; +; -6.935 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.675 ; +; -6.921 ; FS[8] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.661 ; +; -6.917 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.013 ; +; -6.901 ; InitReady ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.641 ; +; -6.899 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.639 ; +; -6.875 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.615 ; +; -6.842 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.582 ; +; -6.827 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.567 ; +; -6.803 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.846 ; +; -6.783 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.523 ; +; -6.783 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.523 ; +; -6.770 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.813 ; +; -6.747 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.487 ; +; -6.729 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.469 ; +; -6.728 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.468 ; +--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ @@ -412,20 +412,20 @@ No paths to report. +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -2.878 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.942 ; 9.060 ; -; -2.378 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.942 ; 9.060 ; -; -1.724 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 4.190 ; -; -1.614 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 4.080 ; -; -0.911 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.377 ; -; -0.906 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.372 ; -; -0.905 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.371 ; -; -0.897 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.363 ; -; -0.896 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.362 ; -; -0.896 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.362 ; -; 0.035 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.431 ; -; 0.037 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.429 ; -; 0.041 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.425 ; -; 0.044 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.422 ; +; -2.870 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.913 ; 9.023 ; +; -2.370 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.913 ; 9.023 ; +; -1.177 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.614 ; +; -1.046 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.483 ; +; -0.854 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.291 ; +; -0.301 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.738 ; +; -0.299 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.736 ; +; -0.295 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.732 ; +; -0.294 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.731 ; +; 0.217 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.220 ; +; 0.218 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.219 ; +; 0.222 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.215 ; +; 0.222 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.215 ; +; 0.223 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.214 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -434,8 +434,8 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.715 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.586 ; 1.699 ; -; -16.098 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.586 ; 2.316 ; +; -16.578 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.735 ; 1.687 ; +; -15.844 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.735 ; 2.421 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -445,7 +445,7 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -15.888 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.409 ; 1.703 ; +; -16.552 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.761 ; 1.687 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -455,106 +455,106 @@ No paths to report. +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.520 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.043 ; 2.097 ; -; -0.262 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.043 ; 2.355 ; -; 0.491 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.043 ; 3.608 ; -; 0.692 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.043 ; 3.809 ; -; 2.016 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.090 ; -; 2.425 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.499 ; -; 3.402 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.476 ; -; 3.809 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.383 ; -; 4.217 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.291 ; -; 4.220 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.294 ; -; 4.348 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.422 ; -; 4.834 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.908 ; -; 4.837 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.911 ; -; 4.936 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.010 ; -; 4.936 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.010 ; -; 5.491 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.065 ; -; 5.501 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.075 ; -; 6.020 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.594 ; -; 6.207 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.781 ; -; 6.217 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.791 ; -; 6.424 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.498 ; -; 6.424 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.498 ; -; 6.539 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.113 ; -; 6.549 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.123 ; -; 6.595 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.169 ; -; 6.736 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.310 ; -; 6.956 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.530 ; -; 6.966 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.540 ; -; 7.041 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.115 ; -; 7.068 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.642 ; -; 7.076 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.150 ; -; 7.076 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.150 ; -; 7.156 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.730 ; -; 7.166 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.740 ; -; 7.242 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.816 ; -; 7.242 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.816 ; -; 7.256 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.830 ; -; 7.266 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.840 ; -; 7.311 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.885 ; -; 7.485 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.059 ; -; 7.643 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.217 ; -; 7.685 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.259 ; -; 7.785 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.359 ; -; 7.958 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.532 ; -; 7.958 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.532 ; -; 8.005 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.579 ; -; 8.015 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.589 ; -; 8.060 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.634 ; -; 8.201 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.775 ; -; 8.211 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.785 ; -; 8.260 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.834 ; -; 8.290 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.864 ; -; 8.290 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.864 ; -; 8.360 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.934 ; -; 8.534 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.108 ; -; 8.580 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.154 ; -; 8.707 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.281 ; -; 8.707 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.281 ; -; 8.713 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.287 ; -; 8.730 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ; -; 8.730 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ; -; 8.730 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ; -; 8.748 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.322 ; -; 8.748 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.322 ; -; 8.907 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.481 ; -; 8.907 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.481 ; -; 9.007 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.581 ; -; 9.007 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.581 ; -; 9.109 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.683 ; -; 9.296 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.870 ; -; 9.305 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.879 ; -; 9.429 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.003 ; -; 9.446 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.020 ; -; 9.446 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.020 ; -; 9.464 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.038 ; -; 9.464 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.038 ; -; 9.628 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.202 ; -; 9.756 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.330 ; -; 9.756 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.330 ; -; 9.761 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.335 ; -; 9.778 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.352 ; -; 9.778 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.352 ; -; 9.796 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.370 ; -; 9.796 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.370 ; -; 9.952 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.526 ; -; 9.952 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.526 ; -; 10.045 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.619 ; -; 10.178 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.752 ; -; 10.195 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.769 ; -; 10.195 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.769 ; -; 10.213 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.787 ; -; 10.213 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.787 ; -; 10.245 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.819 ; -; 10.345 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.919 ; -; 10.378 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.952 ; -; 10.395 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.969 ; -; 10.395 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.969 ; -; 10.413 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.987 ; -; 10.413 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.987 ; -; 10.478 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.052 ; +; -0.611 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 2.107 ; +; -0.382 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 2.336 ; +; 1.207 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 3.925 ; +; 1.322 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.144 ; 4.540 ; +; 1.473 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.144 ; 4.691 ; +; 1.990 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.064 ; +; 3.231 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.305 ; +; 3.250 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.324 ; +; 3.802 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.376 ; +; 4.489 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.063 ; +; 4.855 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.929 ; +; 4.858 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.932 ; +; 4.926 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.500 ; +; 4.952 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.026 ; +; 5.137 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.711 ; +; 5.214 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.788 ; +; 5.574 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.148 ; +; 5.612 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.686 ; +; 5.615 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.689 ; +; 5.642 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.216 ; +; 5.862 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.436 ; +; 5.954 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.528 ; +; 6.035 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.109 ; +; 6.035 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.109 ; +; 6.154 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.728 ; +; 6.254 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.828 ; +; 6.290 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.864 ; +; 6.377 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.951 ; +; 6.456 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.530 ; +; 6.456 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.530 ; +; 6.536 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; +; 6.536 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; +; 6.536 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; +; 6.587 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.161 ; +; 6.602 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.176 ; +; 6.691 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.265 ; +; 6.802 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.376 ; +; 6.979 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.553 ; +; 7.025 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.599 ; +; 7.148 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.722 ; +; 7.197 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.771 ; +; 7.235 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.809 ; +; 7.407 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.981 ; +; 7.585 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.159 ; +; 7.634 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.208 ; +; 7.719 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.293 ; +; 7.873 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.447 ; +; 7.919 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.493 ; +; 7.922 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.496 ; +; 8.142 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.716 ; +; 8.231 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.805 ; +; 8.231 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.805 ; +; 8.301 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.875 ; +; 8.350 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.924 ; +; 8.352 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.926 ; +; 8.613 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.187 ; +; 8.652 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.226 ; +; 8.652 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.226 ; +; 8.662 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.236 ; +; 8.668 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.242 ; +; 8.668 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.242 ; +; 8.732 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; +; 8.732 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; +; 8.732 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; +; 8.813 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ; +; 8.862 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.436 ; +; 8.956 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.530 ; +; 8.956 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.530 ; +; 9.036 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.610 ; +; 9.085 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.659 ; +; 9.089 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.663 ; +; 9.089 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.663 ; +; 9.169 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; +; 9.169 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; +; 9.169 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; +; 9.246 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; +; 9.295 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.869 ; +; 9.377 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.951 ; +; 9.377 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.951 ; +; 9.384 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.958 ; +; 9.384 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.958 ; +; 9.457 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; +; 9.457 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; +; 9.457 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; +; 9.696 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.270 ; +; 9.696 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.270 ; +; 9.805 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.379 ; +; 9.805 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.379 ; +; 9.885 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; +; 9.885 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; +; 9.885 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; +; 9.896 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.470 ; +; 9.896 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.470 ; +; 10.117 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.691 ; +; 10.117 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.691 ; +; 10.119 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.693 ; +; 10.119 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.693 ; +; 10.197 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; +; 10.197 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; +; 10.197 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ @@ -563,20 +563,20 @@ No paths to report. +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 0.622 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.422 ; -; 0.625 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.425 ; -; 0.629 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.429 ; -; 0.631 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.431 ; -; 1.562 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.362 ; -; 1.562 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.362 ; -; 1.563 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.363 ; -; 1.571 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.371 ; -; 1.572 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.372 ; -; 1.577 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.377 ; -; 2.280 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 4.080 ; -; 2.390 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 4.190 ; -; 3.044 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.942 ; 9.060 ; -; 3.544 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.942 ; 9.060 ; +; 0.443 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.214 ; +; 0.444 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.215 ; +; 0.444 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.215 ; +; 0.448 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.219 ; +; 0.449 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.220 ; +; 0.960 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.731 ; +; 0.961 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.732 ; +; 0.965 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.736 ; +; 0.967 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.738 ; +; 1.520 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.291 ; +; 1.712 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.483 ; +; 1.843 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.614 ; +; 3.036 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.913 ; 9.023 ; +; 3.536 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.913 ; 9.023 ; +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -587,104 +587,104 @@ No paths to report. +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ; 1.178 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.716 ; 4.968 ; ; 1.189 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.716 ; 4.979 ; -; 1.227 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.716 ; 5.017 ; +; 1.236 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.716 ; 5.026 ; ; 1.678 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.716 ; 4.968 ; ; 1.689 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.716 ; 4.979 ; -; 1.727 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.716 ; 5.017 ; +; 1.736 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.716 ; 5.026 ; ; 2.010 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.084 ; -; 2.073 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.147 ; -; 2.079 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.153 ; -; 2.276 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.350 ; -; 2.278 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.352 ; -; 2.292 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ; -; 2.512 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.586 ; -; 2.607 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.681 ; -; 2.732 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.806 ; -; 2.766 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.840 ; -; 2.798 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.872 ; -; 2.803 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ; +; 2.020 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.094 ; +; 2.038 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.112 ; +; 2.047 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.121 ; +; 2.060 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.134 ; +; 2.307 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.381 ; +; 2.318 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.392 ; +; 2.380 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; +; 2.672 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.746 ; +; 2.674 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.748 ; +; 2.736 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.810 ; +; 2.804 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.878 ; ; 2.812 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.886 ; ; 2.813 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; -; 2.823 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.897 ; -; 2.837 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.911 ; -; 2.842 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.916 ; -; 2.843 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; -; 2.845 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.919 ; -; 2.846 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.920 ; -; 2.892 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.966 ; -; 2.948 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.022 ; -; 2.949 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; +; 2.813 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; +; 2.813 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; +; 2.824 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.898 ; +; 2.843 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; +; 2.843 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; +; 2.845 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.919 ; +; 2.847 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.921 ; +; 2.852 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.926 ; +; 2.854 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.928 ; +; 2.932 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.006 ; +; 2.948 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.022 ; +; 2.949 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; ; 2.949 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; -; 2.957 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.031 ; -; 2.957 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.031 ; -; 2.958 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; +; 2.958 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; +; 2.958 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; ; 2.959 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.033 ; -; 2.961 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ; ; 2.961 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ; -; 2.967 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ; -; 2.967 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ; -; 3.029 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.103 ; -; 3.049 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.123 ; -; 3.191 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.265 ; -; 3.247 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.321 ; -; 3.266 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.340 ; -; 3.299 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.373 ; -; 3.382 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.456 ; -; 3.391 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.465 ; -; 3.393 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.467 ; -; 3.427 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.501 ; -; 3.487 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.561 ; -; 3.487 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.561 ; +; 2.965 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.039 ; +; 2.966 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.040 ; +; 2.967 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ; +; 2.974 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.048 ; +; 2.975 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.049 ; +; 2.978 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.052 ; +; 2.990 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.064 ; +; 2.995 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.069 ; +; 3.008 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.082 ; +; 3.032 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.106 ; +; 3.079 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.153 ; +; 3.086 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.160 ; +; 3.094 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.168 ; +; 3.136 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.210 ; +; 3.201 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.275 ; +; 3.217 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.291 ; +; 3.246 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.320 ; +; 3.250 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.324 ; +; 3.288 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.362 ; +; 3.318 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; +; 3.338 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.412 ; +; 3.405 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.479 ; +; 3.421 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.495 ; +; 3.423 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.497 ; +; 3.429 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; +; 3.460 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.534 ; +; 3.483 ; Ready ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.557 ; +; 3.525 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.599 ; ; 3.533 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.607 ; ; 3.534 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.608 ; -; 3.544 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.618 ; -; 3.558 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.632 ; -; 3.563 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.637 ; -; 3.566 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.640 ; +; 3.534 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.608 ; +; 3.564 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.638 ; +; 3.566 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.640 ; +; 3.638 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.712 ; +; 3.643 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.717 ; ; 3.646 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.720 ; -; 3.657 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.731 ; -; 3.671 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.745 ; -; 3.676 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.750 ; -; 3.679 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.753 ; -; 3.694 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.768 ; -; 3.731 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.805 ; +; 3.647 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.721 ; +; 3.647 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.721 ; +; 3.677 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.751 ; +; 3.679 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.753 ; ; 3.759 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.833 ; -; 3.782 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.856 ; -; 3.789 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.863 ; -; 3.797 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.871 ; -; 3.812 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.886 ; -; 3.813 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.887 ; +; 3.770 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.844 ; +; 3.775 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.849 ; +; 3.792 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.866 ; +; 3.813 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.887 ; +; 3.814 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.888 ; ; 3.814 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.888 ; -; 3.822 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.896 ; -; 3.823 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.897 ; +; 3.816 ; S[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.890 ; +; 3.823 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.897 ; ; 3.824 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.898 ; ; 3.826 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.900 ; -; 3.839 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.913 ; +; 3.830 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.904 ; +; 3.854 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.928 ; +; 3.854 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.928 ; ; 3.872 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.946 ; -; 3.875 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.949 ; -; 3.882 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.956 ; -; 3.911 ; Ready ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.985 ; -; 3.926 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.000 ; -; 3.935 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.009 ; -; 3.936 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.010 ; -; 3.953 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.027 ; -; 3.956 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.030 ; -; 3.978 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.052 ; -; 3.986 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.060 ; -; 4.039 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.113 ; -; 4.048 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.122 ; -; 4.049 ; RCKE~reg0 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.123 ; -; 4.149 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.223 ; -; 4.174 ; FS[0] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ; -; 4.174 ; FS[0] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ; -; 4.174 ; FS[0] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ; -; 4.174 ; FS[0] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ; -; 4.174 ; FS[0] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ; -; 4.182 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ; -; 4.182 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ; -; 4.182 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ; -; 4.182 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ; -; 4.190 ; InitReady ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.264 ; +; 3.926 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.000 ; +; 3.927 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.001 ; +; 3.936 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.010 ; +; 3.943 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.017 ; +; 3.972 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.046 ; +; 3.981 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.055 ; +; 4.034 ; S[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.108 ; +; 4.039 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.113 ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ @@ -700,7 +700,7 @@ No paths to report. ; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; ; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; ; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ; -; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ; +; RCLK ; PHI2 ; 2 ; 0 ; 3 ; 0 ; ; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; ; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; ; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; @@ -722,7 +722,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not ; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; ; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; ; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ; -; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ; +; RCLK ; PHI2 ; 2 ; 0 ; 3 ; 0 ; ; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; ; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; ; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; @@ -752,7 +752,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 31 ; 31 ; -; Unconstrained Input Port Paths ; 257 ; 257 ; +; Unconstrained Input Port Paths ; 255 ; 255 ; ; Unconstrained Output Ports ; 38 ; 38 ; ; Unconstrained Output Port Paths ; 78 ; 78 ; +---------------------------------+-------+------+ @@ -948,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 01:10:58 2023 + Info: Processing started: Sun Aug 13 04:26:35 2023 Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -974,16 +974,16 @@ Info (332146): Worst-case setup slack is -99.000 Info (332119): ========= =================== ===================== Info (332119): -99.000 -99.000 ARCLK Info (332119): -99.000 -99.000 DRCLK - Info (332119): -10.792 -122.191 PHI2 - Info (332119): -8.864 -306.770 RCLK - Info (332119): -2.878 -11.627 nCRAS -Info (332146): Worst-case hold slack is -16.715 + Info (332119): -10.164 -118.093 PHI2 + Info (332119): -9.387 -288.937 RCLK + Info (332119): -2.870 -7.136 nCRAS +Info (332146): Worst-case hold slack is -16.578 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -16.715 -16.715 DRCLK - Info (332119): -15.888 -15.888 ARCLK - Info (332119): -0.520 -0.782 PHI2 - Info (332119): 0.622 0.000 nCRAS + Info (332119): -16.578 -16.578 DRCLK + Info (332119): -16.552 -16.552 ARCLK + Info (332119): -0.611 -0.993 PHI2 + Info (332119): 0.443 0.000 nCRAS Info (332119): 1.178 0.000 RCLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report @@ -1001,7 +1001,7 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings Info: Peak virtual memory: 4676 megabytes - Info: Processing ended: Sun Aug 13 01:10:59 2023 + Info: Processing ended: Sun Aug 13 04:26:36 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.summary b/CPLD/MAXV/output_files/RAM2GS.sta.summary index 26bc439..b6bef3b 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.summary +++ b/CPLD/MAXV/output_files/RAM2GS.sta.summary @@ -11,31 +11,31 @@ Slack : -99.000 TNS : -99.000 Type : Setup 'PHI2' -Slack : -10.792 -TNS : -122.191 +Slack : -10.164 +TNS : -118.093 Type : Setup 'RCLK' -Slack : -8.864 -TNS : -306.770 +Slack : -9.387 +TNS : -288.937 Type : Setup 'nCRAS' -Slack : -2.878 -TNS : -11.627 +Slack : -2.870 +TNS : -7.136 Type : Hold 'DRCLK' -Slack : -16.715 -TNS : -16.715 +Slack : -16.578 +TNS : -16.578 Type : Hold 'ARCLK' -Slack : -15.888 -TNS : -15.888 +Slack : -16.552 +TNS : -16.552 Type : Hold 'PHI2' -Slack : -0.520 -TNS : -0.782 +Slack : -0.611 +TNS : -0.993 Type : Hold 'nCRAS' -Slack : 0.622 +Slack : 0.443 TNS : 0.000 Type : Hold 'RCLK' diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v index da452c7..30d48e1 100644 --- a/CPLD/RAM2GS-MAX.v +++ b/CPLD/RAM2GS-MAX.v @@ -346,7 +346,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2 XOR8MEG <= Din[0] || (LEDEN && Din[1]); end else if (Din[7:4]==4'h1) begin - CmdLEDEN <= ~Din[1]; + CmdLEDEN <= Din[1]; Cmdn8MEGEN <= ~Din[0]; CmdSubmitted <= 1'b1; end else if (Din[7:4]==4'h2) begin