diff --git a/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb deleted file mode 100755 index a80855d..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb deleted file mode 100755 index 1a1481b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb deleted file mode 100755 index 84cfd7b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb deleted file mode 100755 index 10dc2d1..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb deleted file mode 100755 index bf025da..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb deleted file mode 100755 index 7121330..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.asm.qmsg b/CPLD/AGM-src/db/RAM4GS.asm.qmsg deleted file mode 100755 index 4989b11..0000000 --- a/CPLD/AGM-src/db/RAM4GS.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.asm.rdb b/CPLD/AGM-src/db/RAM4GS.asm.rdb deleted file mode 100755 index 57f2d3d..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.asm.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb b/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb deleted file mode 100755 index c9b3243..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.cdb b/CPLD/AGM-src/db/RAM4GS.cmp.cdb deleted file mode 100755 index 660f5e1..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.hdb b/CPLD/AGM-src/db/RAM4GS.cmp.hdb deleted file mode 100755 index 27f7c43..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.idb b/CPLD/AGM-src/db/RAM4GS.cmp.idb deleted file mode 100755 index e91cbcb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.idb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.kpt b/CPLD/AGM-src/db/RAM4GS.cmp.kpt deleted file mode 100755 index 29f003a..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.kpt and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.rdb b/CPLD/AGM-src/db/RAM4GS.cmp.rdb deleted file mode 100755 index 8974ee5..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp0.ddb b/CPLD/AGM-src/db/RAM4GS.cmp0.ddb deleted file mode 100755 index db1bbdb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp0.ddb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.fit.qmsg b/CPLD/AGM-src/db/RAM4GS.fit.qmsg deleted file mode 100755 index f7f2a6b..0000000 --- a/CPLD/AGM-src/db/RAM4GS.fit.qmsg +++ /dev/null @@ -1,43 +0,0 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.hif b/CPLD/AGM-src/db/RAM4GS.hif deleted file mode 100755 index 662d74f..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.hif and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.ipinfo b/CPLD/AGM-src/db/RAM4GS.ipinfo deleted file mode 100755 index 482f1be..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.ipinfo and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.rdb b/CPLD/AGM-src/db/RAM4GS.lpc.rdb deleted file mode 100755 index 2c939fb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.lpc.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.cdb b/CPLD/AGM-src/db/RAM4GS.map.cdb deleted file mode 100755 index ca0a971..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.hdb b/CPLD/AGM-src/db/RAM4GS.map.hdb deleted file mode 100755 index 8ae41d2..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.qmsg b/CPLD/AGM-src/db/RAM4GS.map.qmsg deleted file mode 100755 index 543433e..0000000 --- a/CPLD/AGM-src/db/RAM4GS.map.qmsg +++ /dev/null @@ -1,26 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.map.rdb b/CPLD/AGM-src/db/RAM4GS.map.rdb deleted file mode 100755 index d27105c..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.pre_map.hdb b/CPLD/AGM-src/db/RAM4GS.pre_map.hdb deleted file mode 100755 index 6f71689..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.pre_map.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.qns b/CPLD/AGM-src/db/RAM4GS.qns deleted file mode 100755 index ef67c3e..0000000 --- a/CPLD/AGM-src/db/RAM4GS.qns +++ /dev/null @@ -1 +0,0 @@ -RAM4GS/done diff --git a/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb b/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb deleted file mode 100755 index a7aa640..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.routing.rdb b/CPLD/AGM-src/db/RAM4GS.routing.rdb deleted file mode 100755 index a1beb78..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.routing.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv.hdb b/CPLD/AGM-src/db/RAM4GS.rtlv.hdb deleted file mode 100755 index 802d93c..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb b/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb deleted file mode 100755 index 30b67ca..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb b/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb deleted file mode 100755 index e318de4..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb b/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb deleted file mode 100755 index 2d31b44..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb b/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb deleted file mode 100755 index 18597e6..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sta.qmsg b/CPLD/AGM-src/db/RAM4GS.sta.qmsg deleted file mode 100755 index e020392..0000000 --- a/CPLD/AGM-src/db/RAM4GS.sta.qmsg +++ /dev/null @@ -1,23 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.sta.rdb b/CPLD/AGM-src/db/RAM4GS.sta.rdb deleted file mode 100755 index 25f87ad..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sta.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb b/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb deleted file mode 100755 index 8b39503..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.vpr.ammdb b/CPLD/AGM-src/db/RAM4GS.vpr.ammdb deleted file mode 100755 index 2acc82b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.vpr.ammdb and /dev/null differ diff --git a/CPLD/AGM-src/db/logic_util_heursitic.dat b/CPLD/AGM-src/db/logic_util_heursitic.dat deleted file mode 100755 index c3752a7..0000000 Binary files a/CPLD/AGM-src/db/logic_util_heursitic.dat and /dev/null differ diff --git a/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg b/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg deleted file mode 100755 index 715eafe..0000000 --- a/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg +++ /dev/null @@ -1,106 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""} diff --git a/CPLD/AGM-src/greybox_tmp/cbx_args.txt b/CPLD/AGM-src/greybox_tmp/cbx_args.txt deleted file mode 100755 index b32fb07..0000000 --- a/CPLD/AGM-src/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,26 +0,0 @@ -ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=RAM4GS.mif -LPM_HINT=UNUSED -LPM_TYPE=altufm_none -OSC_FREQUENCY=180000 -PORT_ARCLKENA=PORT_UNUSED -PORT_DRCLKENA=PORT_UNUSED -PROGRAM_TIME=1600000 -WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" -CBX_AUTO_BLACKBOX=ALL -CBX_AUTO_BLACKBOX=ALL -arclk -ardin -arshft -busy -drclk -drdin -drdout -drshft -erase -osc -oscena -program -rtpbusy diff --git a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt b/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt deleted file mode 100755 index 4a04335..0000000 Binary files a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt and /dev/null differ diff --git a/CPLD/AGM-src/output_files/RAM4GS.cdf b/CPLD/AGM-src/output_files/RAM4GS.cdf deleted file mode 100755 index 43f46dc..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/CPLD/AGM-src/output_files/RAM4GS.done b/CPLD/AGM-src/output_files/RAM4GS.done deleted file mode 100755 index d7b20f4..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.done +++ /dev/null @@ -1 +0,0 @@ -Thu Jul 23 02:21:03 2020 diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.summary b/CPLD/AGM-src/output_files/RAM4GS.fit.summary deleted file mode 100755 index 530787c..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.fit.summary +++ /dev/null @@ -1,11 +0,0 @@ -Fitter Status : Successful - Thu Jul 23 02:20:50 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Device : EPM240T100C5 -Timing Models : Final -Total logic elements : 170 / 240 ( 71 % ) -Total pins : 62 / 80 ( 78 % ) -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.jdi b/CPLD/AGM-src/output_files/RAM4GS.jdi deleted file mode 100755 index 85a8d49..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.summary b/CPLD/AGM-src/output_files/RAM4GS.map.summary deleted file mode 100755 index 56e671c..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.map.summary +++ /dev/null @@ -1,9 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Total logic elements : 178 -Total pins : 62 -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.pof b/CPLD/AGM-src/output_files/RAM4GS.pof deleted file mode 100755 index a168b2e..0000000 Binary files a/CPLD/AGM-src/output_files/RAM4GS.pof and /dev/null differ diff --git a/CPLD/AGM-src/output_files/RAM4GS.sta.rpt b/CPLD/AGM-src/output_files/RAM4GS.sta.rpt deleted file mode 100755 index 6462353..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.sta.rpt +++ /dev/null @@ -1,1588 +0,0 @@ -TimeQuest Timing Analyzer report for RAM4GS -Thu Jul 23 02:21:02 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Fmax Summary - 7. Setup Summary - 8. Hold Summary - 9. Recovery Summary - 10. Removal Summary - 11. Minimum Pulse Width Summary - 12. Setup: 'ARCLK' - 13. Setup: 'DRCLK' - 14. Setup: 'PHI2' - 15. Setup: 'RCLK' - 16. Setup: 'nCRAS' - 17. Hold: 'DRCLK' - 18. Hold: 'ARCLK' - 19. Hold: 'RCLK' - 20. Hold: 'PHI2' - 21. Hold: 'nCRAS' - 22. Minimum Pulse Width: 'ARCLK' - 23. Minimum Pulse Width: 'DRCLK' - 24. Minimum Pulse Width: 'PHI2' - 25. Minimum Pulse Width: 'RCLK' - 26. Minimum Pulse Width: 'nCCAS' - 27. Minimum Pulse Width: 'nCRAS' - 28. Setup Times - 29. Hold Times - 30. Clock to Output Times - 31. Minimum Clock to Output Times - 32. Propagation Delay - 33. Minimum Propagation Delay - 34. Output Enable Times - 35. Minimum Output Enable Times - 36. Output Disable Times - 37. Minimum Output Disable Times - 38. Setup Transfers - 39. Hold Transfers - 40. Report TCCS - 41. Report RSKM - 42. Unconstrained Paths - 43. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+--------------------+-------------------------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; < 0.1% ; -+----------------------------+-------------+ - - -+-----------------------------------------------------+ -; SDC File List ; -+-----------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+-----------------+--------+--------------------------+ -; constraints.sdc ; OK ; Thu Jul 23 02:21:01 2020 ; -+-----------------+--------+--------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; -; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; -; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; -; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; -; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; -; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ - - -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 51.06 MHz ; 51.06 MHz ; PHI2 ; ; -; 128.87 MHz ; 128.87 MHz ; RCLK ; ; -+------------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+---------------------------------+ -; Setup Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -99.000 ; -99.000 ; -; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -9.292 ; -92.804 ; -; RCLK ; -8.365 ; -253.063 ; -; nCRAS ; -0.490 ; -0.577 ; -+-------+---------+---------------+ - - -+---------------------------------+ -; Hold Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; DRCLK ; -16.306 ; -16.306 ; -; ARCLK ; -16.272 ; -16.272 ; -; RCLK ; -0.874 ; -0.874 ; -; PHI2 ; -0.396 ; -0.396 ; -; nCRAS ; -0.125 ; -0.125 ; -+-------+---------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+---------------------------------+ -; Minimum Pulse Width Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -29.500 ; -59.000 ; -; DRCLK ; -29.500 ; -59.000 ; -; PHI2 ; -2.289 ; -2.289 ; -; RCLK ; -2.289 ; -2.289 ; -; nCCAS ; -2.289 ; -2.289 ; -; nCRAS ; -2.289 ; -2.289 ; -+-------+---------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.728 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.715 ; 2.013 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.549 ; -; -22.694 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.529 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Setup: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -9.292 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.121 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.288 ; -; -8.996 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.163 ; -; -8.949 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.857 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.024 ; -; -8.778 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.653 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.594 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.761 ; -; -8.514 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.300 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.467 ; -; -8.289 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.456 ; -; -8.251 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.118 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.285 ; -; -8.084 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.251 ; -; -8.043 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.210 ; -; -7.993 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.160 ; -; -7.957 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.872 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.039 ; -; -7.854 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.021 ; -; -7.799 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.966 ; -; -7.747 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.914 ; -; -7.741 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.608 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.775 ; -; -7.591 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.758 ; -; -7.456 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.345 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.512 ; -; -7.297 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.464 ; -; -7.205 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.372 ; -; -7.081 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.248 ; -; -7.051 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.218 ; -; -7.034 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.201 ; -; -6.909 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.076 ; -; -6.870 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.870 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.835 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.002 ; -; -6.796 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.963 ; -; -6.770 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.937 ; -; -6.745 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.912 ; -; -6.699 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.699 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.574 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.550 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.717 ; -; -6.507 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.674 ; -; -6.449 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.616 ; -; -6.435 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.435 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.310 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.477 ; -; -6.213 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.380 ; -; -6.172 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.172 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.047 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.214 ; -; -5.997 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.164 ; -; -5.878 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.878 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.753 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.920 ; -; -5.712 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.879 ; -; -5.662 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.662 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.537 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.704 ; -; -5.377 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.377 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.252 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.419 ; -; -5.004 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.671 ; -; -4.046 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.040 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.707 ; -; -4.001 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.668 ; -; -3.752 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.419 ; -; -3.694 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.861 ; -; -3.585 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.252 ; -; -2.929 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.596 ; -; -2.917 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.584 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; -8.365 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -8.365 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -7.591 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 5.180 ; -; -7.130 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.719 ; -; -7.061 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.650 ; -; -7.017 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.986 ; -; -6.760 ; FS[5] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.760 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.691 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.280 ; -; -6.669 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.258 ; -; -6.664 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.633 ; -; -6.612 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.612 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.588 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.255 ; -; -6.574 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.163 ; -; -6.549 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.549 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.526 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.115 ; -; -6.502 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.502 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.501 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.168 ; -; -6.482 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.149 ; -; -6.401 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.068 ; -; -6.399 ; FS[4] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.399 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.395 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.062 ; -; -6.380 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.047 ; -; -6.328 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.297 ; -; -6.258 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.847 ; -; -6.256 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.923 ; -; -6.253 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.920 ; -; -6.232 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.899 ; -; -6.198 ; FS[6] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.198 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.193 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.860 ; -; -6.190 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.857 ; -; -6.169 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ; -; -6.146 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.813 ; -; -6.143 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.810 ; -; -6.122 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.789 ; -; -6.070 ; UFMInitDone ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.070 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.044 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.633 ; -; -6.040 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.707 ; -; -6.032 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.699 ; -; -6.028 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.695 ; -; -6.022 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.689 ; -; -6.019 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.686 ; -; -5.996 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.585 ; -; -5.959 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.626 ; -; -5.958 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.625 ; -; -5.954 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.621 ; -; -5.949 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 2.918 ; -; -5.942 ; UFMReqErase ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.609 ; -; -5.915 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.582 ; -; -5.912 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.579 ; -; -5.852 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.852 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.839 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.506 ; -; -5.835 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.502 ; -; -5.818 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.485 ; -; -5.805 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.472 ; -; -5.739 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.406 ; -; -5.733 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 2.165 ; 8.565 ; -; -5.720 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.387 ; -; -5.714 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.381 ; -; -5.711 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.711 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.690 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.357 ; -; -5.688 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.355 ; -; -5.666 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ; -; -5.656 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.323 ; -; -5.596 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.263 ; -; -5.579 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.246 ; -; -5.563 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.230 ; -; -5.549 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.216 ; -; -5.503 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.170 ; -; -5.500 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.167 ; -; -5.487 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.154 ; -; -5.480 ; UFMInitDone ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.147 ; -; -5.479 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.146 ; -; -5.459 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.126 ; -; -5.453 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.120 ; -; -5.425 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.092 ; -; -5.420 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.087 ; -; -5.397 ; IS[2] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.064 ; -; -5.373 ; UFMInitDone ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.040 ; -; -5.363 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.030 ; -; -5.350 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.017 ; -; -5.345 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.345 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.333 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.000 ; -; -5.312 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.312 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.290 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.957 ; -; -5.267 ; FS[3] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.934 ; -; -5.230 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.230 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.208 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.875 ; -; -5.206 ; IS[3] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.873 ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Setup: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.490 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 3.235 ; -; -0.087 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.832 ; -; 0.071 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.926 ; 6.022 ; -; 0.079 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.666 ; -; 0.080 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.665 ; -; 0.081 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.664 ; -; 0.082 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.663 ; -; 0.084 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.661 ; -; 0.091 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.654 ; -; 0.095 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.650 ; -; 0.099 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.646 ; -; 0.104 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.641 ; -; 0.105 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.640 ; -; 0.571 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.926 ; 6.022 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.306 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.529 ; -; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.549 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.272 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.715 ; 2.013 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Hold: 'RCLK' ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.874 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 3.348 ; 3.071 ; -; -0.374 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 3.348 ; 3.071 ; -; 1.192 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.761 ; -; 1.264 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.833 ; -; 1.344 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.913 ; -; 1.400 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.621 ; -; 1.642 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.863 ; -; 1.670 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.891 ; -; 1.692 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.761 ; -; 1.695 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.916 ; -; 1.703 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.924 ; -; 1.706 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.927 ; -; 1.764 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.833 ; -; 1.844 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.913 ; -; 1.899 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.120 ; -; 1.948 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.169 ; -; 1.959 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.180 ; -; 1.976 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.197 ; -; 1.983 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.204 ; -; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; -; 2.117 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; -; 2.135 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.135 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.358 ; -; 2.141 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.362 ; -; 2.153 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.374 ; -; 2.212 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.433 ; -; 2.221 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.230 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.233 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.292 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.513 ; -; 2.332 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.553 ; -; 2.363 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.584 ; -; 2.380 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.601 ; -; 2.407 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.628 ; -; 2.522 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.743 ; -; 2.530 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.751 ; -; 2.542 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.763 ; -; 2.577 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.798 ; -; 2.582 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.803 ; -; 2.593 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.814 ; -; 2.615 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.836 ; -; 2.622 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.843 ; -; 2.837 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.058 ; -; 2.885 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.106 ; -; 2.912 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.133 ; -; 2.913 ; PHI2r3 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.134 ; -; 2.936 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.157 ; -; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; -; 2.949 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.178 ; -; 2.967 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ; -; 2.969 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.190 ; -; 3.028 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.249 ; -; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; -; 3.060 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.066 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.287 ; -; 3.068 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.289 ; -; 3.078 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.299 ; -; 3.109 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.330 ; -; 3.130 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.351 ; -; 3.159 ; S[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.380 ; -; 3.161 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.161 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.162 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.383 ; -; 3.170 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.179 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; -; 3.184 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; -; 3.241 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.462 ; -; 3.277 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.498 ; -; 3.281 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.282 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.289 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.289 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.290 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; -; 3.296 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.517 ; -; 3.306 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.527 ; -; 3.324 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.545 ; -; 3.328 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.549 ; -; 3.381 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.602 ; -; 3.383 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.604 ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Hold: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.396 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.023 ; -; 0.072 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.198 ; 2.991 ; -; 0.129 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.548 ; -; 1.927 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.148 ; -; 2.681 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.902 ; -; 3.162 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.383 ; -; 3.363 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.584 ; -; 3.375 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.596 ; -; 3.825 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.546 ; -; 4.031 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.252 ; -; 4.110 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.831 ; -; 4.140 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.861 ; -; 4.198 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.419 ; -; 4.265 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.986 ; -; 4.326 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.047 ; -; 4.447 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.668 ; -; 4.486 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.707 ; -; 4.492 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.550 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.271 ; -; 4.620 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.341 ; -; 4.766 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.487 ; -; 4.883 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.604 ; -; 5.022 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.743 ; -; 5.060 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.781 ; -; 5.064 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.785 ; -; 5.147 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.868 ; -; 5.318 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.039 ; -; 5.323 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.044 ; -; 5.349 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.070 ; -; 5.450 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.671 ; -; 5.462 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.183 ; -; 5.519 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.240 ; -; 5.565 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.286 ; -; 5.587 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.308 ; -; 5.758 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.479 ; -; 5.804 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.525 ; -; 5.859 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.580 ; -; 6.020 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.741 ; -; 6.122 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.843 ; -; 6.158 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.879 ; -; 6.261 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.982 ; -; 6.314 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.035 ; -; 6.386 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.107 ; -; 6.443 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.164 ; -; 6.557 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.278 ; -; 6.577 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.298 ; -; 6.659 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.380 ; -; 6.716 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.437 ; -; 6.841 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.562 ; -; 6.953 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.674 ; -; 7.012 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.733 ; -; 7.216 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.937 ; -; 7.242 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.963 ; -; 7.355 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.076 ; -; 7.480 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.201 ; -; 7.527 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.248 ; -; 7.651 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.372 ; -; 7.743 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.464 ; -; 7.902 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 8.037 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.758 ; -; 8.187 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.245 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.966 ; -; 8.300 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.021 ; -; 8.403 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.439 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.160 ; -; 8.530 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.251 ; -; 8.564 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.285 ; -; 8.697 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.735 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.456 ; -; 8.746 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.467 ; -; 8.960 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 9.040 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.761 ; -; 9.099 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.224 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.303 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.024 ; -; 9.395 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.116 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.125 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.926 ; 6.022 ; -; 0.341 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.640 ; -; 0.342 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.641 ; -; 0.347 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.646 ; -; 0.351 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.650 ; -; 0.355 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.654 ; -; 0.362 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.661 ; -; 0.364 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.663 ; -; 0.365 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.664 ; -; 0.366 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.665 ; -; 0.367 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.666 ; -; 0.375 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.926 ; 6.022 ; -; 0.533 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.832 ; -; 0.936 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 3.235 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'ARCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'DRCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI2' ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI2 ; Rise ; PHI2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'RCLK' ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; RCLK ; Rise ; RCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; nRCAS~reg0 ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCCAS' ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCCAS ; Rise ; nCCAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCRAS' ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCRAS ; Rise ; nCRAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.100 ; 0.100 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.099 ; 0.099 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.187 ; 0.187 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.377 ; 0.377 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.181 ; 0.181 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.431 ; 0.431 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; -0.141 ; -0.141 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; 6.507 ; 6.507 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 5.653 ; 5.653 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; 6.225 ; 6.225 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; 6.476 ; 6.476 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 5.332 ; 5.332 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; 5.239 ; 5.239 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; 5.246 ; 5.246 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 4.152 ; 4.152 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; 4.051 ; 4.051 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; 6.688 ; 6.688 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; 7.040 ; 7.040 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; 5.984 ; 5.984 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; 4.702 ; 4.702 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; 4.845 ; 4.845 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; 5.436 ; 5.436 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; 1.898 ; 1.898 ; Rise ; RCLK ; -; nCCAS ; RCLK ; 1.746 ; 1.746 ; Rise ; RCLK ; -; nCRAS ; RCLK ; 1.818 ; 1.818 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; -0.572 ; -0.572 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; -0.490 ; -0.490 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; -0.295 ; -0.295 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; -0.561 ; -0.561 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.097 ; 0.097 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; -0.478 ; -0.478 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; -0.222 ; -0.222 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; 1.618 ; 1.618 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; -0.639 ; -0.639 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.450 ; 0.450 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; -0.345 ; -0.345 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; -0.391 ; -0.391 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; -0.178 ; -0.178 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; -0.439 ; -0.439 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; -1.067 ; -1.067 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; -0.425 ; -0.425 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; -0.474 ; -0.474 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.429 ; 0.429 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; 2.878 ; 2.878 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.454 ; 0.454 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.455 ; 0.455 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.367 ; 0.367 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.177 ; 0.177 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.373 ; 0.373 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.123 ; 0.123 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; 0.695 ; 0.695 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; -0.378 ; -0.378 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 0.138 ; 0.138 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; -0.365 ; -0.365 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; -0.419 ; -0.419 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; -1.686 ; -1.686 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; -1.080 ; -1.080 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; -1.052 ; -1.052 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; -0.027 ; -0.027 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; -2.640 ; -2.640 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; -3.223 ; -3.223 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; -2.992 ; -2.992 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; -1.936 ; -1.936 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; -0.564 ; -0.564 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; -0.704 ; -0.704 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; -0.462 ; -0.462 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; -1.344 ; -1.344 ; Rise ; RCLK ; -; nCCAS ; RCLK ; -1.192 ; -1.192 ; Rise ; RCLK ; -; nCRAS ; RCLK ; -1.264 ; -1.264 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; 1.044 ; 1.044 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; 0.849 ; 0.849 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; 1.115 ; 1.115 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.457 ; 0.457 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.211 ; 0.211 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; 1.032 ; 1.032 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; 0.776 ; 0.776 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; -1.317 ; -1.317 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; 1.193 ; 1.193 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.104 ; 0.104 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; 0.899 ; 0.899 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.033 ; 0.033 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; 0.945 ; 0.945 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; 0.732 ; 0.732 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; 0.993 ; 0.993 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; 0.979 ; 0.979 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; 1.028 ; 1.028 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.125 ; 0.125 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; -2.324 ; -2.324 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+------------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+-----------------------------------------------------------------------+ -; Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Minimum Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 30 ; 30 ; -; Unconstrained Input Port Paths ; 231 ; 231 ; -; Unconstrained Output Ports ; 37 ; 37 ; -; Unconstrained Output Port Paths ; 75 ; 75 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:57 2020 -Info: Command: quartus_sta RAM4GS -c RAM4GS -Info: qsta_default_script.tcl version: #1 -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (306004): Started post-fitting delay annotation -Info (306005): Delay annotation completed successfully -Info (332104): Reading SDC File: 'constraints.sdc' -Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name DRCLK DRCLK - Info (332105): create_clock -period 1.000 -name ARCLK ARCLK - Info (332105): create_clock -period 1.000 -name RCLK RCLK - Info (332105): create_clock -period 1.000 -name nCRAS nCRAS - Info (332105): create_clock -period 1.000 -name PHI2 PHI2 - Info (332105): create_clock -period 1.000 -name nCCAS nCCAS -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -99.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -99.000 -99.000 ARCLK - Info (332119): -99.000 -99.000 DRCLK - Info (332119): -9.292 -92.804 PHI2 - Info (332119): -8.365 -253.063 RCLK - Info (332119): -0.490 -0.577 nCRAS -Info (332146): Worst-case hold slack is -16.306 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -16.306 -16.306 DRCLK - Info (332119): -16.272 -16.272 ARCLK - Info (332119): -0.874 -0.874 RCLK - Info (332119): -0.396 -0.396 PHI2 - Info (332119): -0.125 -0.125 nCRAS -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -29.500 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -29.500 -59.000 ARCLK - Info (332119): -29.500 -59.000 DRCLK - Info (332119): -2.289 -2.289 PHI2 - Info (332119): -2.289 -2.289 RCLK - Info (332119): -2.289 -2.289 nCCAS - Info (332119): -2.289 -2.289 nCRAS -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 288 megabytes - Info: Processing ended: Thu Jul 23 02:21:02 2020 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 - - diff --git a/CPLD/AGM-src/RAM4GS.qpf b/CPLD/MAX/MAXII/RAM2GS-MAXII.qpf old mode 100755 new mode 100644 similarity index 84% rename from CPLD/AGM-src/RAM4GS.qpf rename to CPLD/MAX/MAXII/RAM2GS-MAXII.qpf index aceec8c..74f038f --- a/CPLD/AGM-src/RAM4GS.qpf +++ b/CPLD/MAX/MAXII/RAM2GS-MAXII.qpf @@ -16,15 +16,15 @@ # # -------------------------------------------------------------------------- # # -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 21:16:34 March 08, 2020 +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 18:32:31 August 16, 2021 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" -DATE = "21:16:34 March 08, 2020" +DATE = "18:32:31 August 16, 2021" # Revisions -PROJECT_REVISION = "RAM4GS" +PROJECT_REVISION = "RAM2GS" diff --git a/CPLD/MAXII/RAM4GS.qsf b/CPLD/MAX/MAXII/RAM2GS.qsf old mode 100755 new mode 100644 similarity index 97% rename from CPLD/MAXII/RAM4GS.qsf rename to CPLD/MAX/MAXII/RAM2GS.qsf index ed8578e..5aa99ad --- a/CPLD/MAXII/RAM4GS.qsf +++ b/CPLD/MAX/MAXII/RAM2GS.qsf @@ -38,12 +38,10 @@ set_global_assignment -name FAMILY "MAX II" set_global_assignment -name DEVICE EPM240T100C5 -set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS +set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name SDC_FILE constraints.sdc -set_global_assignment -name VERILOG_FILE RAM4GS.v set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -174,7 +172,6 @@ set_location_assignment PIN_95 -to RD[6] set_location_assignment PIN_97 -to RD[7] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD -set_global_assignment -name MIF_FILE RAM4GS.mif set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE @@ -210,4 +207,6 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD set_instance_assignment -name SLOW_SLEW_RATE ON -to RD set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" +set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif" set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/CPLD/MAX/MAXII/RAM2GS.qws b/CPLD/MAX/MAXII/RAM2GS.qws new file mode 100644 index 0000000..b0761a5 Binary files /dev/null and b/CPLD/MAX/MAXII/RAM2GS.qws differ diff --git a/CPLD/AGM-src/UFM.qip b/CPLD/MAX/MAXII/UFM.qip old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/UFM.qip rename to CPLD/MAX/MAXII/UFM.qip diff --git a/CPLD/MAXII/UFM.v b/CPLD/MAX/MAXII/UFM.v old mode 100755 new mode 100644 similarity index 83% rename from CPLD/MAXII/UFM.v rename to CPLD/MAX/MAXII/UFM.v index c063115..f58dd72 --- a/CPLD/MAXII/UFM.v +++ b/CPLD/MAX/MAXII/UFM.v @@ -33,8 +33,8 @@ //applicable agreement for further details. -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy -//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 @@ -43,7 +43,7 @@ //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on -module UFM_altufm_none_1br +module UFM_altufm_none_imr ( arclk, ardin, @@ -117,23 +117,23 @@ module UFM_altufm_none_1br defparam maxii_ufm_block1.address_width = 9, maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "RAM4GS.mif", + maxii_ufm_block1.init_file = "RAM2GS-MAX.mif", maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.osc_sim_setting = 180000, maxii_ufm_block1.program_time = 1600000, maxii_ufm_block1.lpm_type = "maxii_ufm"; @@ -155,7 +155,7 @@ module UFM_altufm_none_1br ufm_osc = wire_maxii_ufm_block1_osc, ufm_oscena = oscena, ufm_program = program; -endmodule //UFM_altufm_none_1br +endmodule //UFM_altufm_none_imr //VALID FILE @@ -200,7 +200,7 @@ module UFM ( wire drdout = sub_wire2; wire busy = sub_wire3; - UFM_altufm_none_1br UFM_altufm_none_1br_component ( + UFM_altufm_none_imr UFM_altufm_none_imr_component ( .arshft (arshft), .drclk (drclk), .erase (erase), @@ -224,7 +224,7 @@ endmodule // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb new file mode 100644 index 0000000..b4b4e46 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb new file mode 100644 index 0000000..bc59c9d Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb new file mode 100644 index 0000000..f8b441f Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb new file mode 100644 index 0000000..619591b Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb new file mode 100644 index 0000000..0d88168 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb new file mode 100644 index 0000000..832159d Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg new file mode 100644 index 0000000..5738a14 --- /dev/null +++ b/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153617401 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing started: Mon Aug 16 18:40:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153617637 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153617652 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153617808 ""} diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb new file mode 100644 index 0000000..201b4bb Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb b/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb new file mode 100644 index 0000000..3d7511a Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb new file mode 100644 index 0000000..819e5d8 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb new file mode 100644 index 0000000..d79937a Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb new file mode 100644 index 0000000..a767c09 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt b/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt new file mode 100644 index 0000000..73afc77 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.logdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.logdb old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/db/RAM4GS.cmp.logdb rename to CPLD/MAX/MAXII/db/RAM2GS.cmp.logdb diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb new file mode 100644 index 0000000..8a93cad Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb new file mode 100644 index 0000000..ff3e753 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info b/CPLD/MAX/MAXII/db/RAM2GS.db_info old mode 100755 new mode 100644 similarity index 72% rename from CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info rename to CPLD/MAX/MAXII/db/RAM2GS.db_info index dda2847..c0baa44 --- a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info +++ b/CPLD/MAX/MAXII/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Mon Jun 15 13:43:18 2020 +Creation_Time = Mon Aug 16 18:36:28 2021 diff --git a/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg new file mode 100644 index 0000000..74840a8 --- /dev/null +++ b/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg @@ -0,0 +1,46 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153614132 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153614132 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153614309 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153614325 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153614465 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 336 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153614512 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153614512 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153614621 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153614621 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153614621 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153614621 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 332 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 334 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 333 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153614653 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153614668 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153614668 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153614699 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153614699 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153614715 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 18 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153614715 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153614746 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153614887 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615071 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153615085 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153615678 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615678 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153615709 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153615943 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153615943 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616286 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153616286 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616302 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153616333 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153616395 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing ended: Mon Aug 16 18:40:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153616427 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.hier_info b/CPLD/MAX/MAXII/db/RAM2GS.hier_info old mode 100755 new mode 100644 similarity index 93% rename from CPLD/AGM-src/db/RAM4GS.hier_info rename to CPLD/MAX/MAXII/db/RAM2GS.hier_info index 97bc269..ca4de37 --- a/CPLD/AGM-src/db/RAM4GS.hier_info +++ b/CPLD/MAX/MAXII/db/RAM2GS.hier_info @@ -1,4 +1,4 @@ -|RAM4GS +|RAM2GS PHI2 => Bank[0].CLK PHI2 => Bank[1].CLK PHI2 => Bank[2].CLK @@ -152,12 +152,14 @@ nCRAS => RowA[8].CLK nCRAS => RowA[9].CLK nCRAS => RBA[0]~reg0.CLK nCRAS => RBA[1]~reg0.CLK +nCRAS => comb.IN1 nCRAS => RASr.DATAIN nFWE => comb.IN1 nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN +LED <= comb.DB_MAX_OUTPUT_PORT_TYPE RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE @@ -184,9 +186,10 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK -RCLK => n8MEGEN.CLK +RCLK => LEDEN.CLK RCLK => UFMInitDone.CLK -RCLK => UFMD.CLK +RCLK => n8MEGEN.CLK +RCLK => UFMD[15].CLK RCLK => DRShift.CLK RCLK => DRDIn.CLK RCLK => DRCLK.CLK @@ -243,7 +246,7 @@ RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE -|RAM4GS|UFM:UFM_inst +|RAM2GS|UFM:UFM_inst arclk => arclk.IN1 ardin => ardin.IN1 arshft => arshft.IN1 @@ -253,13 +256,13 @@ drshft => drshft.IN1 erase => erase.IN1 oscena => oscena.IN1 program => program.IN1 -busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy -drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout -osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc -rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy +busy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.busy +drdout <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.drdout +osc <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.osc +rtpbusy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.rtpbusy -|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component +|RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component arclk => maxii_ufm_block1.ARCLK ardin => maxii_ufm_block1.ARDIN arshft => maxii_ufm_block1.ARSHFT diff --git a/CPLD/MAX/MAXII/db/RAM2GS.hif b/CPLD/MAX/MAXII/db/RAM2GS.hif new file mode 100644 index 0000000..98245db Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.hif differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.ipinfo b/CPLD/MAX/MAXII/db/RAM2GS.ipinfo new file mode 100644 index 0000000..fa2304d Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.ipinfo differ diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.html b/CPLD/MAX/MAXII/db/RAM2GS.lpc.html old mode 100755 new mode 100644 similarity index 93% rename from CPLD/AGM-src/db/RAM4GS.lpc.html rename to CPLD/MAX/MAXII/db/RAM2GS.lpc.html index d50a19d..76d3fb3 --- a/CPLD/AGM-src/db/RAM4GS.lpc.html +++ b/CPLD/MAX/MAXII/db/RAM2GS.lpc.html @@ -16,7 +16,7 @@ Output only Bidir -UFM_inst|UFM_altufm_none_1br_component +UFM_inst|UFM_altufm_none_imr_component 9 0 0 diff --git a/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb b/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb new file mode 100644 index 0000000..b40333d Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb differ diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.txt b/CPLD/MAX/MAXII/db/RAM2GS.lpc.txt old mode 100755 new mode 100644 similarity index 96% rename from CPLD/AGM-src/db/RAM4GS.lpc.txt rename to CPLD/MAX/MAXII/db/RAM2GS.lpc.txt index d8d214c..6debc2c --- a/CPLD/AGM-src/db/RAM4GS.lpc.txt +++ b/CPLD/MAX/MAXII/db/RAM2GS.lpc.txt @@ -3,6 +3,6 @@ +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; UFM_inst|UFM_altufm_none_1br_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; UFM_inst|UFM_altufm_none_imr_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; UFM_inst ; 9 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.cdb b/CPLD/MAX/MAXII/db/RAM2GS.map.cdb new file mode 100644 index 0000000..3a1913b Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.hdb b/CPLD/MAX/MAXII/db/RAM2GS.map.hdb new file mode 100644 index 0000000..5a4b799 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.hdb differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.logdb b/CPLD/MAX/MAXII/db/RAM2GS.map.logdb old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/db/RAM4GS.map.logdb rename to CPLD/MAX/MAXII/db/RAM2GS.map.logdb diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg new file mode 100644 index 0000000..c1f2c80 --- /dev/null +++ b/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg @@ -0,0 +1,27 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153611805 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:11 2021 " "Processing started: Mon Aug 16 18:40:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153612070 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153612117 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_imr " "Found entity 1: UFM_altufm_none_imr" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153612195 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_imr UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component " "Elaborating entity \"UFM_altufm_none_imr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component\"" { } { { "UFM.v" "UFM_altufm_none_imr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""} +{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0" { } { } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153612257 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153612865 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153612865 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153612943 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:12 2021 " "Processing ended: Mon Aug 16 18:40:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.rdb b/CPLD/MAX/MAXII/db/RAM2GS.map.rdb new file mode 100644 index 0000000..e611b88 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb new file mode 100644 index 0000000..b64e6b9 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb b/CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb old mode 100755 new mode 100644 similarity index 67% rename from CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb rename to CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb index 42a925d..89aa9b4 Binary files a/CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb and b/CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb b/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..dce5122 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb new file mode 100644 index 0000000..312e8ac Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb new file mode 100644 index 0000000..7950f8a Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb new file mode 100644 index 0000000..f549130 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb new file mode 100644 index 0000000..9f7460b Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb new file mode 100644 index 0000000..5b2fdc3 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb new file mode 100644 index 0000000..77a25c9 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb differ diff --git a/CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci old mode 100755 new mode 100644 similarity index 59% rename from CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci rename to CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci index 754b594..1d6d60f Binary files a/CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci and b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci differ diff --git a/CPLD/MAXII/db/RAM4GS.sld_design_entry.sci b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci old mode 100755 new mode 100644 similarity index 59% rename from CPLD/MAXII/db/RAM4GS.sld_design_entry.sci rename to CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci index 754b594..1d6d60f Binary files a/CPLD/MAXII/db/RAM4GS.sld_design_entry.sci and b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci differ diff --git a/CPLD/AGM-src/db/RAM4GS.smart_action.txt b/CPLD/MAX/MAXII/db/RAM2GS.smart_action.txt old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/db/RAM4GS.smart_action.txt rename to CPLD/MAX/MAXII/db/RAM2GS.smart_action.txt diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg new file mode 100644 index 0000000..33c9310 --- /dev/null +++ b/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg @@ -0,0 +1,23 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153618889 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:18 2021 " "Processing started: Mon Aug 16 18:40:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153618967 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153619091 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153619201 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153619419 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153619466 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153619466 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.339 -245.761 RCLK " " -8.339 -245.761 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.271 -88.383 PHI2 " " -8.271 -88.383 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.317 -2.784 nCRAS " " -0.317 -2.784 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.858 " "Worst-case hold slack is -16.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.858 -16.858 ARCLK " " -16.858 -16.858 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.363 -16.363 DRCLK " " -16.363 -16.363 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.103 -0.195 nCRAS " " -0.103 -0.195 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.060 -0.060 PHI2 " " -0.060 -0.060 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.192 0.000 RCLK " " 1.192 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153619559 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:19 2021 " "Processing ended: Mon Aug 16 18:40:19 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb new file mode 100644 index 0000000..1d00921 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb new file mode 100644 index 0000000..d59ad7a Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb differ diff --git a/CPLD/AGM-src/constraints.sdc b/CPLD/MAX/MAXII/db/RAM2GS.syn_hier_info old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/constraints.sdc rename to CPLD/MAX/MAXII/db/RAM2GS.syn_hier_info diff --git a/CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb b/CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb old mode 100755 new mode 100644 similarity index 67% rename from CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb rename to CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb index 61ca8da..91bbe10 Binary files a/CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb and b/CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb differ diff --git a/CPLD/MAX/MAXII/db/RAM2GS.tmw_info b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info new file mode 100644 index 0000000..162d740 --- /dev/null +++ b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:09 +start_analysis_synthesis:s:00:00:02-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:04-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb b/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb new file mode 100644 index 0000000..e64e992 Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAX/MAXII/db/logic_util_heursitic.dat b/CPLD/MAX/MAXII/db/logic_util_heursitic.dat new file mode 100644 index 0000000..ff5fe7f Binary files /dev/null and b/CPLD/MAX/MAXII/db/logic_util_heursitic.dat differ diff --git a/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg b/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg new file mode 100644 index 0000000..54a2998 --- /dev/null +++ b/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153597248 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:39:57 2021 " "Processing started: Mon Aug 16 18:39:57 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153597529 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153597576 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597592 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153597592 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153597638 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153597638 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_imr " "Found entity 1: UFM_altufm_none_imr" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""} +{ "Error" "EVRFX_SV_NO_SINGLE_VALUED_PACKED_DIMENSION" "RAM2GS-MAX.v(59) " "SystemVerilog error at RAM2GS-MAX.v(59): can't declare packed array dimension with a single-valued range" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 59 0 0 } } } 0 10989 "SystemVerilog error at %1!s!: can't declare packed array dimension with a single-valued range" 0 0 "Quartus II" 0 -1 1629153597638 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Aug 16 18:39:57 2021 " "Processing ended: Mon Aug 16 18:39:57 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153598258 ""} diff --git a/CPLD/AGM-src/incremental_db/README b/CPLD/MAX/MAXII/incremental_db/README old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/incremental_db/README rename to CPLD/MAX/MAXII/incremental_db/README diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info old mode 100755 new mode 100644 similarity index 72% rename from CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info rename to CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info index dda2847..414a0d6 --- a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info +++ b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Mon Jun 15 13:43:18 2020 +Creation_Time = Mon Aug 16 18:40:12 2021 diff --git a/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt new file mode 100644 index 0000000..0c26b10 Binary files /dev/null and b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/AGM-src/output_files/RAM4GS.asm.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt old mode 100755 new mode 100644 similarity index 73% rename from CPLD/AGM-src/output_files/RAM4GS.asm.rpt rename to CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt index 1915f58..878a98d --- a/CPLD/AGM-src/output_files/RAM4GS.asm.rpt +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt @@ -1,6 +1,6 @@ -Assembler report for RAM4GS -Thu Jul 23 02:20:55 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Assembler report for RAM2GS +Mon Aug 16 18:40:17 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof + 5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof 6. Assembler Messages @@ -37,9 +37,9 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Jul 23 02:20:55 2020 ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; +; Assembler Status ; Successful - Mon Aug 16 18:40:17 2021 ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; +-----------------------+---------------------------------------+ @@ -75,40 +75,40 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+-----------+---------------+ -+--------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------+ -; File Name ; -+--------------------------------------------+ -; /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ; -+--------------------------------------------+ ++-----------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------+ +; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ; ++-----------------------------------------------------------------------------+ -+----------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ; -+----------------+-----------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------+ -; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00173F26 ; -; Checksum ; 0x0017428E ; -+----------------+-----------------------------------------------------+ ++-------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ; ++----------------+--------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------------------------+ +; Device ; EPM240T100C5 ; +; JTAG usercode ; 0x001737AB ; +; Checksum ; 0x00173A1B ; ++----------------+--------------------------------------------------------------------------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Assembler +Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:53 2020 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS + Info: Processing started: Mon Aug 16 18:40:17 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files -Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 296 megabytes - Info: Processing ended: Thu Jul 23 02:20:55 2020 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 381 megabytes + Info: Processing ended: Mon Aug 16 18:40:17 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.done b/CPLD/MAX/MAXII/output_files/RAM2GS.done new file mode 100644 index 0000000..ad0c117 --- /dev/null +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.done @@ -0,0 +1 @@ +Mon Aug 16 18:40:20 2021 diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt old mode 100755 new mode 100644 similarity index 86% rename from CPLD/MAXII/output_files/RAM4GS.fit.rpt rename to CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt index 15a6629..29e0daf --- a/CPLD/MAXII/output_files/RAM4GS.fit.rpt +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt @@ -1,6 +1,6 @@ -Fitter report for RAM4GS -Thu Jul 23 02:20:50 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fitter report for RAM2GS +Mon Aug 16 18:40:16 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -59,15 +59,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Jul 23 02:20:50 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; +; Fitter Status ; Successful - Mon Aug 16 18:40:16 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 170 / 240 ( 71 % ) ; -; Total pins ; 62 / 80 ( 78 % ) ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; Total pins ; 63 / 80 ( 79 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -122,27 +122,21 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.33 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 33.3% ; -+----------------------------+-------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pin. +------------------------------------------------------------------+ @@ -150,43 +144,43 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 170 / 240 ( 71 % ) ; -; -- Combinational with no register ; 74 ; -; -- Register only ; 21 ; -; -- Combinational with a register ; 75 ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; -- Combinational with no register ; 71 ; +; -- Register only ; 20 ; +; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 42 ; +; -- 4 input functions ; 58 ; +; -- 3 input functions ; 40 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 154 ; +; -- normal mode ; 152 ; ; -- arithmetic mode ; 16 ; -; -- qfbk mode ; 6 ; +; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 25 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 / 240 ( 40 % ) ; -; Total LABs ; 22 / 24 ( 92 % ) ; +; Total registers ; 97 / 240 ( 40 % ) ; +; Total LABs ; 23 / 24 ( 96 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; -; I/O pins ; 62 / 80 ( 78 % ) ; +; I/O pins ; 63 / 80 ( 79 % ) ; ; -- Clock pins ; 2 / 4 ( 50 % ) ; ; ; ; ; Global signals ; 4 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 25% / 27% / 23% ; -; Peak interconnect usage (total/H/V) ; 25% / 27% / 23% ; -; Maximum fan-out ; 54 ; -; Highest non-global fan-out ; 38 ; -; Total fan-out ; 644 ; -; Average fan-out ; 2.76 ; +; Average interconnect usage (total/H/V) ; 21% / 23% / 19% ; +; Peak interconnect usage (total/H/V) ; 21% / 23% / 19% ; +; Maximum fan-out ; 55 ; +; Highest non-global fan-out ; 39 ; +; Total fan-out ; 643 ; +; Average fan-out ; 2.77 ; +---------------------------------------------+--------------------+ @@ -216,9 +210,9 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; -; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; -; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 15 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ @@ -236,6 +230,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; LED ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; ; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -249,11 +244,11 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -265,14 +260,14 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; -; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -282,7 +277,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+-------------------+---------------+--------------+ ; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; -; 2 ; 24 / 42 ( 57 % ) ; 3.3V ; -- ; +; 2 ; 25 / 42 ( 60 % ) ; 3.3V ; -- ; +----------+-------------------+---------------+--------------+ @@ -356,7 +351,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; ; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 66 ; 52 ; 2 ; LED ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; yes ; Off ; ; 67 ; 53 ; 2 ; nCRAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; ; 68 ; 54 ; 2 ; MAin[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; ; 69 ; 55 ; 2 ; MAin[5] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; @@ -416,9 +411,9 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |RAM4GS ; 170 (170) ; 96 ; 1 ; 62 ; 0 ; 74 (74) ; 21 (21) ; 75 (75) ; 17 (17) ; 6 (6) ; |RAM4GS ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ; -; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ; +; |RAM2GS ; 168 (168) ; 97 ; 1 ; 63 ; 0 ; 71 (71) ; 20 (20) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; work ; +; |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -428,6 +423,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +---------+----------+---------------+ +; nCRAS ; Input ; (0) ; ; MAin[0] ; Input ; (0) ; ; MAin[1] ; Input ; (0) ; ; MAin[2] ; Input ; (0) ; @@ -438,10 +434,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; MAin[7] ; Input ; (0) ; ; MAin[8] ; Input ; (0) ; ; MAin[9] ; Input ; (0) ; -; CROW[0] ; Input ; (1) ; -; nCRAS ; Input ; (0) ; -; CROW[1] ; Input ; (1) ; ; RCLK ; Input ; (0) ; +; CROW[0] ; Input ; (1) ; +; CROW[1] ; Input ; (1) ; ; PHI2 ; Input ; (0) ; ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; @@ -461,6 +456,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Dout[5] ; Output ; -- ; ; Dout[6] ; Output ; -- ; ; Dout[7] ; Output ; -- ; +; LED ; Output ; -- ; ; RBA[0] ; Output ; -- ; ; RBA[1] ; Output ; -- ; ; RA[0] ; Output ; -- ; @@ -498,16 +494,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~1 ; LC_X6_Y3_N3 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdSubmitted~0 ; LC_X6_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X2_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X6_Y2_N5 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdSubmitted~0 ; LC_X5_Y2_N5 ; 2 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X4_Y1_N2 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK3 ; -; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X3_Y2_N1 ; 38 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~5 ; LC_X5_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~2 ; LC_X4_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; +; Ready ; LC_X3_Y4_N6 ; 39 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~5 ; LC_X6_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~3 ; LC_X4_Y4_N9 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 15 ; Clock ; yes ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ; +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -517,9 +513,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+----------+---------+----------------------+------------------+ ; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK3 ; -; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ; +; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ; ; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 15 ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ; +-------+----------+---------+----------------------+------------------+ @@ -528,99 +524,99 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------+---------+ -; Ready ; 38 ; +; Ready ; 39 ; ; nRowColSel ; 13 ; ; S[1] ; 12 ; ; S[0] ; 12 ; ; RASr2 ; 9 ; ; Din[6] ; 8 ; -; comb~2 ; 8 ; -; FS[4] ; 8 ; +; comb~3 ; 8 ; ; Din[5] ; 7 ; ; Din[4] ; 7 ; -; FS[5] ; 7 ; ; IS[0]~0 ; 7 ; ; Din[7] ; 6 ; ; Din[0] ; 6 ; ; MAin[1] ; 6 ; -; FS[6] ; 6 ; -; always9~1 ; 6 ; ; IS[0] ; 6 ; +; FS[4] ; 6 ; ; Din[3] ; 5 ; ; Din[2] ; 5 ; ; MAin[0] ; 5 ; -; FS[8]~27 ; 5 ; +; FS[8]~31 ; 5 ; ; FS[3]~13 ; 5 ; ; FS[3] ; 5 ; -; always9~2 ; 5 ; -; FS[17] ; 5 ; -; FS[16] ; 5 ; ; IS[1] ; 5 ; ; CBR ; 5 ; ; FWEr ; 5 ; +; FS[6] ; 5 ; +; FS[5] ; 5 ; +; FS[17] ; 5 ; +; FS[16] ; 5 ; +; UFMD[15] ; 5 ; ; Din[1] ; 4 ; ; MAin[9] ; 4 ; ; MAin[7] ; 4 ; ; MAin[6] ; 4 ; ; CmdDRDIn~1 ; 4 ; -; UFMD ; 4 ; -; FS[13]~21 ; 4 ; +; FS[13]~27 ; 4 ; ; CMDWR~2 ; 4 ; ; UFMReqErase ; 4 ; +; always9~3 ; 4 ; +; DRCLK~0 ; 4 ; +; always9~2 ; 4 ; ; Equal9~0 ; 4 ; -; n8MEGEN ; 4 ; ; IS[3] ; 4 ; ; IS[2] ; 4 ; ; InitReady ; 4 ; +; always9~0 ; 4 ; ; nFWE ; 3 ; ; MAin[5] ; 3 ; ; MAin[4] ; 3 ; ; MAin[3] ; 3 ; ; MAin[2] ; 3 ; -; FS[0] ; 3 ; ; always8~5 ; 3 ; ; CMDWR ; 3 ; ; CmdEnable ; 3 ; +; FS[0] ; 3 ; ; always8~4 ; 3 ; ; always8~2 ; 3 ; ; Equal0~0 ; 3 ; -; always9~3 ; 3 ; -; UFMInitDone ; 3 ; ; nRCS~3 ; 3 ; +; n8MEGEN ; 3 ; +; UFMInitDone~0 ; 3 ; +; UFMInitDone ; 3 ; ; RCKE~reg0 ; 3 ; +; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; 3 ; ; MAin[8] ; 2 ; -; FS[1] ; 2 ; -; FS[2] ; 2 ; -; Equal25~0 ; 2 ; -; FS[9] ; 2 ; -; FS[8] ; 2 ; ; CmdSubmitted~0 ; 2 ; ; Equal17~0 ; 2 ; ; CmdDRDIn~0 ; 2 ; ; XOR8MEG~0 ; 2 ; ; Equal0~3 ; 2 ; +; Ready~0 ; 2 ; +; Equal26~0 ; 2 ; +; FS[9] ; 2 ; +; FS[8] ; 2 ; ; Equal5~1 ; 2 ; -; FS[15] ; 2 ; ; FS[14] ; 2 ; ; FS[13] ; 2 ; ; FS[12] ; 2 ; ; FS[11] ; 2 ; ; FS[10] ; 2 ; -; Ready~0 ; 2 ; +; FS[15] ; 2 ; +; Equal24~0 ; 2 ; +; FS[2] ; 2 ; +; FS[1] ; 2 ; ; UFMOscEN~0 ; 2 ; ; C1Submitted ; 2 ; ; Equal0~1 ; 2 ; ; always8~0 ; 2 ; ; CmdUFMErase ; 2 ; ; CmdUFMPrgm ; 2 ; -; always9~6 ; 2 ; -; always9~5 ; 2 ; -; ARCLK~1 ; 2 ; ; always9~4 ; 2 ; -; DRDIn~1 ; 2 ; -; FS[7] ; 2 ; -; always9~0 ; 2 ; ; PHI2r2 ; 2 ; +; DRDIn~1 ; 2 ; +; CmdSubmitted ; 2 ; ; RASr ; 2 ; ; RCKEEN ; 2 ; ; CASr2 ; 2 ; @@ -630,13 +626,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; XOR8MEG ; 2 ; ; RA10~0 ; 2 ; ; nRowColSel~0 ; 2 ; +; always9~1 ; 2 ; +; FS[7] ; 2 ; ; UFMOscEN ; 2 ; ; UFMErase ; 2 ; ; UFMProgram ; 2 ; -; ARShift ; 2 ; -; ARCLK ; 2 ; -; DRShift ; 2 ; -; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; 2 ; +; LEDEN ; 2 ; ; UFMProgram~_wirecell ; 1 ; ; UFMOscEN~_wirecell ; 1 ; ; UFMErase~_wirecell ; 1 ; @@ -652,37 +647,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; CROW[0] ; 1 ; ; CmdEnable~1 ; 1 ; ; CmdEnable~0 ; 1 ; -; UFMD~1 ; 1 ; -; FS[1]~33COUT1_50 ; 1 ; -; FS[1]~33 ; 1 ; -; UFMD~0 ; 1 ; -; UFMReqErase~0 ; 1 ; -; FS[2]~31COUT1_52 ; 1 ; -; FS[2]~31 ; 1 ; -; FS[9]~29COUT1_62 ; 1 ; -; FS[9]~29 ; 1 ; -; UFMInitDone~0 ; 1 ; ; PHI2r ; 1 ; ; RCKEEN~2 ; 1 ; ; RCKEEN~1 ; 1 ; ; RCKEEN~0 ; 1 ; ; CASr ; 1 ; ; Equal16~0 ; 1 ; +; n8MEGEN~3 ; 1 ; +; PHI2r3 ; 1 ; +; n8MEGEN~2 ; 1 ; +; n8MEGEN~1 ; 1 ; ; n8MEGEN~0 ; 1 ; ; Cmdn8MEGEN ; 1 ; ; IS[0]~3 ; 1 ; -; FS[15]~25COUT1_72 ; 1 ; -; FS[15]~25 ; 1 ; -; FS[14]~23COUT1_70 ; 1 ; -; FS[14]~23 ; 1 ; -; Equal5~0 ; 1 ; -; FS[12]~19COUT1_68 ; 1 ; -; FS[12]~19 ; 1 ; -; FS[11]~17COUT1_66 ; 1 ; -; FS[11]~17 ; 1 ; -; FS[10]~15COUT1_64 ; 1 ; -; FS[10]~15 ; 1 ; ; Ready~1 ; 1 ; +; FS[9]~33COUT1_62 ; 1 ; +; FS[9]~33 ; 1 ; +; FS[14]~29COUT1_70 ; 1 ; +; FS[14]~29 ; 1 ; +; Equal5~0 ; 1 ; +; FS[12]~25COUT1_68 ; 1 ; +; FS[12]~25 ; 1 ; +; FS[11]~23COUT1_66 ; 1 ; +; FS[11]~23 ; 1 ; +; FS[10]~21COUT1_64 ; 1 ; +; FS[10]~21 ; 1 ; +; FS[15]~19COUT1_72 ; 1 ; +; FS[15]~19 ; 1 ; +; UFMD[15]~0 ; 1 ; +; FS[2]~17COUT1_52 ; 1 ; +; FS[2]~17 ; 1 ; +; FS[1]~15COUT1_50 ; 1 ; +; FS[1]~15 ; 1 ; ; WRD[7] ; 1 ; ; WRD[6] ; 1 ; ; WRD[5] ; 1 ; @@ -704,23 +700,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Bank[2] ; 1 ; ; Bank[3] ; 1 ; ; Bank[1] ; 1 ; -; ARShift~0 ; 1 ; -; ARCLK~3 ; 1 ; -; ARCLK~2 ; 1 ; +; always9~5 ; 1 ; ; ARCLK~0 ; 1 ; ; CmdDRCLK ; 1 ; -; DRCLK~0 ; 1 ; -; FS[6]~11COUT1_58 ; 1 ; -; FS[6]~11 ; 1 ; -; FS[7]~9COUT1_60 ; 1 ; -; FS[7]~9 ; 1 ; -; FS[16]~5COUT1_74 ; 1 ; -; FS[16]~5 ; 1 ; -; FS[4]~3COUT1_54 ; 1 ; -; FS[4]~3 ; 1 ; -; FS[5]~1COUT1_56 ; 1 ; -; FS[5]~1 ; 1 ; -; CmdSubmitted ; 1 ; ; CmdDRDIn ; 1 ; ; nRCAS~1 ; 1 ; ; nRCAS~0 ; 1 ; @@ -729,10 +711,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nRCS~4 ; 1 ; ; nRCS~2 ; 1 ; ; nRowColSel~1 ; 1 ; +; FS[4]~11COUT1_54 ; 1 ; +; FS[4]~11 ; 1 ; +; FS[6]~9COUT1_58 ; 1 ; +; FS[6]~9 ; 1 ; +; FS[5]~7COUT1_56 ; 1 ; +; FS[5]~7 ; 1 ; +; FS[7]~5COUT1_60 ; 1 ; +; FS[7]~5 ; 1 ; +; FS[16]~1COUT1_74 ; 1 ; +; FS[16]~1 ; 1 ; +; ARShift ; 1 ; +; ARCLK ; 1 ; +; DRShift ; 1 ; ; DRCLK ; 1 ; ; DRDIn ; 1 ; +; comb~2 ; 1 ; ; comb~1 ; 1 ; -; comb~0 ; 1 ; ; nRCAS~reg0 ; 1 ; ; nRRAS~reg0 ; 1 ; ; nRWE~reg0 ; 1 ; @@ -761,6 +756,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RowA[0] ; 1 ; ; RBA[1]~reg0 ; 1 ; ; RBA[0]~reg0 ; 1 ; +; comb~0 ; 1 ; +---------------------------------------------------------------------------------------------+---------+ @@ -769,64 +765,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 152 / 784 ( 19 % ) ; -; Direct links ; 45 / 888 ( 5 % ) ; +; C4s ; 126 / 784 ( 16 % ) ; +; Direct links ; 41 / 888 ( 5 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; -; LAB clocks ; 15 / 32 ( 47 % ) ; -; LUT chains ; 22 / 216 ( 10 % ) ; -; Local interconnects ; 270 / 888 ( 30 % ) ; -; R4s ; 155 / 704 ( 22 % ) ; +; LAB clocks ; 16 / 32 ( 50 % ) ; +; LUT chains ; 17 / 216 ( 8 % ) ; +; Local interconnects ; 252 / 888 ( 28 % ) ; +; R4s ; 134 / 704 ( 19 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.73) ; Number of LABs (Total = 22) ; +; Number of Logic Elements (Average = 7.30) ; Number of LABs (Total = 23) ; +--------------------------------------------+------------------------------+ -; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 2 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 2 ; +; 1 ; 2 ; +; 2 ; 3 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 3 ; ; 9 ; 0 ; -; 10 ; 13 ; +; 10 ; 12 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.18) ; Number of LABs (Total = 22) ; +; LAB-wide Signals (Average = 1.26) ; Number of LABs (Total = 23) ; +------------------------------------+------------------------------+ -; 1 Clock ; 14 ; +; 1 Clock ; 17 ; ; 1 Clock enable ; 2 ; -; 1 Sync. clear ; 3 ; +; 1 Sync. clear ; 4 ; ; 1 Sync. load ; 1 ; -; 2 Clocks ; 6 ; +; 2 Clocks ; 5 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.91) ; Number of LABs (Total = 22) ; +; Number of Signals Sourced (Average = 7.57) ; Number of LABs (Total = 23) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 2 ; -; 4 ; 2 ; +; 1 ; 2 ; +; 2 ; 3 ; +; 3 ; 0 ; +; 4 ; 1 ; ; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 11 ; -; 11 ; 1 ; +; 6 ; 0 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 0 ; +; 10 ; 9 ; +; 11 ; 2 ; ; 12 ; 1 ; +---------------------------------------------+------------------------------+ @@ -834,48 +830,47 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.73) ; Number of LABs (Total = 22) ; +; Number of Signals Sourced Out (Average = 5.17) ; Number of LABs (Total = 23) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; +; 1 ; 3 ; ; 2 ; 2 ; -; 3 ; 3 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 4 ; -; 7 ; 2 ; -; 8 ; 1 ; -; 9 ; 3 ; -; 10 ; 3 ; +; 3 ; 0 ; +; 4 ; 4 ; +; 5 ; 3 ; +; 6 ; 3 ; +; 7 ; 4 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 1 ; +-------------------------------------------------+------------------------------+ -+-----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.18) ; Number of LABs (Total = 22) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 1 ; -; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 4 ; -; 10 ; 1 ; -; 11 ; 1 ; -; 12 ; 2 ; -; 13 ; 3 ; -; 14 ; 1 ; -; 15 ; 0 ; -; 16 ; 1 ; -; 17 ; 1 ; -; 18 ; 0 ; -; 19 ; 1 ; -+----------------------------------------------+------------------------------+ ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 9.04) ; Number of LABs (Total = 23) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 3 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 3 ; +; 8 ; 1 ; +; 9 ; 2 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 2 ; +; 14 ; 2 ; +; 15 ; 1 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 1 ; ++---------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -920,8 +915,8 @@ Note: This table only shows the top 3 path(s) that have the largest delay added +-----------------+ ; Fitter Messages ; +-----------------+ -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (119006): Selected device EPM240T100C5 for design "RAM4GS" +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EPM240T100C5 for design "RAM2GS" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance @@ -932,7 +927,9 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible -Info (332104): Reading SDC File: 'constraints.sdc' +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins + Info (169086): Pin LED not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement @@ -951,11 +948,12 @@ Info (186216): Automatically promoted some destinations of signal "PHI2" to use Info (186217): Destination "PHI2r" may be non-global or may not use global clock Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock + Info (186217): Destination "comb~0" may be non-global or may not use global clock Info (186217): Destination "RASr" may be non-global or may not use global clock Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock Info (186217): Destination "CBR" may be non-global or may not use global clock - Info (186217): Destination "comb~2" may be non-global or may not use global clock + Info (186217): Destination "comb~3" may be non-global or may not use global clock Info (186217): Destination "CASr" may be non-global or may not use global clock Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position Info (186079): Completed Auto Global Promotion Operation @@ -964,6 +962,13 @@ Info (186391): Fitter is using Normal packing mode for logic elements with Auto Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 18 pins available Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -971,23 +976,23 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 20% of the available device resources - Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 18% of the available device resources + Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 376 megabytes - Info: Processing ended: Thu Jul 23 02:20:50 2020 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:08 +Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 548 megabytes + Info: Processing ended: Mon Aug 16 18:40:16 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg. +The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.smsg b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/output_files/RAM4GS.fit.smsg rename to CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary new file mode 100644 index 0000000..6659118 --- /dev/null +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary @@ -0,0 +1,11 @@ +Fitter Status : Successful - Mon Aug 16 18:40:16 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2GS +Top-level Entity Name : RAM2GS +Family : MAX II +Device : EPM240T100C5 +Timing Models : Final +Total logic elements : 168 / 240 ( 70 % ) +Total pins : 63 / 80 ( 79 % ) +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM4GS.flow.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt old mode 100755 new mode 100644 similarity index 57% rename from CPLD/MAXII/output_files/RAM4GS.flow.rpt rename to CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt index cab50ca..cd5d6a1 --- a/CPLD/MAXII/output_files/RAM4GS.flow.rpt +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt @@ -1,6 +1,6 @@ -Flow report for RAM4GS -Thu Jul 23 02:21:02 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Flow report for RAM2GS +Mon Aug 16 18:40:19 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -40,15 +40,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Jul 23 02:20:55 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; +; Flow Status ; Successful - Mon Aug 16 18:40:17 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 170 / 240 ( 71 % ) ; -; Total pins ; 62 / 80 ( 78 % ) ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; Total pins ; 63 / 80 ( 79 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -59,34 +59,34 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 07/23/2020 02:20:37 ; +; Start date & time ; 08/16/2021 18:40:12 ; ; Main task ; Compilation ; -; Revision Name ; RAM4GS ; +; Revision Name ; RAM2GS ; +-------------------+---------------------+ -+------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ -; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.159548523602288 ; -- ; -- ; -- ; -; ENABLE_BUS_HOLD_CIRCUITRY ; On ; Off ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; -; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ; -; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; -; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; -; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ ++----------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 962837114763.162915361100164 ; -- ; -- ; -- ; +; ENABLE_BUS_HOLD_CIRCUITRY ; On ; Off ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; +; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ; +; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; +; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; +; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -94,33 +94,33 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 303 MB ; 00:00:05 ; -; Fitter ; 00:00:08 ; 1.3 ; 376 MB ; 00:00:07 ; -; Assembler ; 00:00:02 ; 1.0 ; 295 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 288 MB ; 00:00:04 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ; +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 421 MB ; 00:00:01 ; +; Fitter ; 00:00:03 ; 1.0 ; 548 MB ; 00:00:03 ; +; Assembler ; 00:00:00 ; 1.0 ; 381 MB ; 00:00:01 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 374 MB ; 00:00:01 ; +; Total ; 00:00:05 ; -- ; -- ; 00:00:06 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+-----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; Assembler ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; TimeQuest Timing Analyzer ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -+---------------------------+------------------+------------+------------+----------------+ ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ ------------ ; Flow Log ; ------------ -quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS -quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS -quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS -quartus_sta RAM4GS -c RAM4GS +quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_sta RAM2GS-MAXII -c RAM2GS diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.jdi b/CPLD/MAX/MAXII/output_files/RAM2GS.jdi new file mode 100644 index 0000000..8f5f174 --- /dev/null +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/MAXII/output_files/RAM4GS.map.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt old mode 100755 new mode 100644 similarity index 80% rename from CPLD/MAXII/output_files/RAM4GS.map.rpt rename to CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt index 9d88205..d013013 --- a/CPLD/MAXII/output_files/RAM4GS.map.rpt +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt @@ -1,6 +1,6 @@ -Analysis & Synthesis report for RAM4GS -Thu Jul 23 02:20:40 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Analysis & Synthesis report for RAM2GS +Mon Aug 16 18:40:12 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -45,13 +45,13 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; +; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:12 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; -; Total logic elements ; 178 ; -; Total pins ; 62 ; +; Total logic elements ; 177 ; +; Total pins ; 63 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+-------------------------------------------------+ @@ -63,7 +63,7 @@ applicable agreement for further details. ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EPM240T100C5 ; ; -; Top-level entity name ; RAM4GS ; RAM4GS ; +; Top-level entity name ; RAM2GS ; RAM2GS ; ; Family name ; MAX II ; Cyclone IV GX ; ; Safe State Machine ; On ; Off ; ; Power-Up Don't Care ; Off ; On ; @@ -130,32 +130,25 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------+--------------------+ -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; -+----------------------------+-------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ -; RAM4GS.v ; yes ; User Verilog HDL File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v ; ; -; RAM4GS.mif ; yes ; User Memory Initialization File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ; ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v ; ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +-----------------------------------------------------+ @@ -163,32 +156,32 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 178 ; -; -- Combinational with no register ; 82 ; +; Total logic elements ; 177 ; +; -- Combinational with no register ; 80 ; ; -- Register only ; 29 ; -; -- Combinational with a register ; 67 ; +; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 42 ; +; -- 4 input functions ; 58 ; +; -- 3 input functions ; 40 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 162 ; +; -- normal mode ; 161 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 9 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 ; +; Total registers ; 97 ; ; Total logic cells in carry chains ; 17 ; -; I/O pins ; 62 ; +; I/O pins ; 63 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; RCLK ; -; Maximum fan-out ; 54 ; +; Maximum fan-out ; 55 ; ; Total fan-out ; 643 ; ; Average fan-out ; 2.67 ; +---------------------------------------------+-------+ @@ -199,20 +192,20 @@ applicable agreement for further details. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |RAM4GS ; 178 (178) ; 96 ; 1 ; 62 ; 0 ; 82 (82) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM4GS ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ; -; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ; +; |RAM2GS ; 177 (177) ; 97 ; 1 ; 63 ; 0 ; 80 (80) ; 29 (29) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; work ; +; |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis IP Cores Summary ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ -; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+ +; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v ; ++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+ +------------------------------------------------------+ @@ -220,7 +213,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 96 ; +; Total registers ; 97 ; ; Number of registers using Synchronous Clear ; 6 ; ; Number of registers using Synchronous Load ; 3 ; ; Number of registers using Asynchronous Clear ; 0 ; @@ -248,8 +241,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|S[0] ; -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|C1Submitted ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|ADSubmitted ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -269,22 +262,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Analysis & Synthesis +Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:35 2020 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v - Info (12023): Found entity 1: RAM4GS + Info: Processing started: Mon Aug 16 18:40:11 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_1br + Info (12023): Found entity 1: UFM_altufm_none_imr Info (12023): Found entity 2: UFM -Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2) -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18) -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4) +Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2) +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18) +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4) Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" -Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component" +Info (12128): Elaborating entity "UFM_altufm_none_imr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component" +Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0 Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated @@ -295,21 +289,21 @@ Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins - Info (21059): Implemented 29 output pins + Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 178 logic cells + Info (21061): Implemented 177 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 303 megabytes - Info: Processing ended: Thu Jul 23 02:20:41 2020 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 +Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings + Info: Peak virtual memory: 421 megabytes + Info: Processing ended: Mon Aug 16 18:40:12 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg. +The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg. diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.smsg b/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg old mode 100755 new mode 100644 similarity index 71% rename from CPLD/AGM-src/output_files/RAM4GS.map.smsg rename to CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg index 4c14264..a8e8eb9 --- a/CPLD/AGM-src/output_files/RAM4GS.map.smsg +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM4GS.v(52): extended using "x" or "z" +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z" Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary new file mode 100644 index 0000000..4c4a5bb --- /dev/null +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:12 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2GS +Top-level Entity Name : RAM2GS +Family : MAX II +Total logic elements : 177 +Total pins : 63 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.pin b/CPLD/MAX/MAXII/output_files/RAM2GS.pin old mode 100755 new mode 100644 similarity index 98% rename from CPLD/AGM-src/output_files/RAM4GS.pin rename to CPLD/MAX/MAXII/output_files/RAM2GS.pin index 86ba0f4..4acd586 --- a/CPLD/AGM-src/output_files/RAM4GS.pin +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.pin @@ -57,8 +57,8 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -CHIP "RAM4GS" ASSIGNED TO AN: EPM240T100C5 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "RAM2GS" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- @@ -127,7 +127,7 @@ GND* : 62 : : : VCCINT : 63 : power : : 2.5V/3.3V : : GND* : 64 : : : : 2 : GNDINT : 65 : gnd : : : : -GND* : 66 : : : : 2 : +LED : 66 : output : 3.3-V LVTTL : : 2 : N nCRAS : 67 : input : 3.3-V LVCMOS : : 2 : Y MAin[7] : 68 : input : 3.3-V LVCMOS : : 2 : Y MAin[5] : 69 : input : 3.3-V LVCMOS : : 2 : Y diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.pof b/CPLD/MAX/MAXII/output_files/RAM2GS.pof new file mode 100644 index 0000000..f288ab0 Binary files /dev/null and b/CPLD/MAX/MAXII/output_files/RAM2GS.pof differ diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt new file mode 100644 index 0000000..b9aa2bf --- /dev/null +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt @@ -0,0 +1,1576 @@ +TimeQuest Timing Analyzer report for RAM2GS +Mon Aug 16 18:40:19 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Fmax Summary + 6. Setup Summary + 7. Hold Summary + 8. Recovery Summary + 9. Removal Summary + 10. Minimum Pulse Width Summary + 11. Setup: 'ARCLK' + 12. Setup: 'DRCLK' + 13. Setup: 'RCLK' + 14. Setup: 'PHI2' + 15. Setup: 'nCRAS' + 16. Hold: 'ARCLK' + 17. Hold: 'DRCLK' + 18. Hold: 'nCRAS' + 19. Hold: 'PHI2' + 20. Hold: 'RCLK' + 21. Minimum Pulse Width: 'ARCLK' + 22. Minimum Pulse Width: 'DRCLK' + 23. Minimum Pulse Width: 'PHI2' + 24. Minimum Pulse Width: 'RCLK' + 25. Minimum Pulse Width: 'nCCAS' + 26. Minimum Pulse Width: 'nCRAS' + 27. Setup Times + 28. Hold Times + 29. Clock to Output Times + 30. Minimum Clock to Output Times + 31. Propagation Delay + 32. Minimum Propagation Delay + 33. Output Enable Times + 34. Minimum Output Enable Times + 35. Output Disable Times + 36. Minimum Output Disable Times + 37. Setup Transfers + 38. Hold Transfers + 39. Report TCCS + 40. Report RSKM + 41. Unconstrained Paths + 42. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; +; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; +; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; +; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; +; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++--------------------------------------------------+ +; Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 57.01 MHz ; 57.01 MHz ; PHI2 ; ; +; 121.57 MHz ; 121.57 MHz ; RCLK ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -99.000 ; -99.000 ; +; DRCLK ; -99.000 ; -99.000 ; +; RCLK ; -8.339 ; -245.761 ; +; PHI2 ; -8.271 ; -88.383 ; +; nCRAS ; -0.317 ; -2.784 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -16.858 ; -16.858 ; +; DRCLK ; -16.363 ; -16.363 ; +; nCRAS ; -0.103 ; -0.195 ; +; PHI2 ; -0.060 ; -0.060 ; +; RCLK ; 1.192 ; 0.000 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -29.500 ; -59.000 ; +; DRCLK ; -29.500 ; -59.000 ; +; PHI2 ; -2.289 ; -2.289 ; +; RCLK ; -2.289 ; -2.289 ; +; nCCAS ; -2.289 ; -2.289 ; +; nCRAS ; -2.289 ; -2.289 ; ++-------+---------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.142 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.613 ; 1.529 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.699 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.595 ; 2.104 ; +; -22.637 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.595 ; 2.042 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -8.339 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 5.262 ; +; -7.863 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 4.786 ; +; -7.540 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 5.138 ; +; -7.536 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 5.134 ; +; -7.431 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 4.354 ; +; -7.397 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 4.320 ; +; -7.226 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.893 ; +; -7.147 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.814 ; +; -7.078 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.745 ; +; -7.033 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 4.631 ; +; -7.000 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 4.598 ; +; -6.983 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.650 ; +; -6.966 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.633 ; +; -6.929 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 4.527 ; +; -6.898 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.565 ; +; -6.794 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.461 ; +; -6.759 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.426 ; +; -6.748 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 4.346 ; +; -6.664 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.331 ; +; -6.657 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.324 ; +; -6.657 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 4.255 ; +; -6.654 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.321 ; +; -6.621 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.288 ; +; -6.620 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 3.543 ; +; -6.611 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.278 ; +; -6.559 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.226 ; +; -6.552 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.219 ; +; -6.549 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; +; -6.541 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.208 ; +; -6.499 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.166 ; +; -6.451 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.118 ; +; -6.444 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.111 ; +; -6.441 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.108 ; +; -6.431 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.098 ; +; -6.416 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.083 ; +; -6.389 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 3.987 ; +; -6.373 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.595 ; 8.635 ; +; -6.359 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.026 ; +; -6.351 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.018 ; +; -6.312 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.244 ; 3.235 ; +; -6.282 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.949 ; +; -6.257 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 3.855 ; +; -6.254 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.921 ; +; -6.250 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.569 ; 3.848 ; +; -6.203 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.870 ; +; -6.195 ; FS[16] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.862 ; +; -6.159 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.826 ; +; -6.146 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.813 ; +; -6.099 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.766 ; +; -6.090 ; FS[17] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.757 ; +; -6.074 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.741 ; +; -6.054 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.721 ; +; -6.023 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.690 ; +; -5.982 ; FS[7] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.649 ; +; -5.946 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.613 ; +; -5.885 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.552 ; +; -5.827 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.494 ; +; -5.783 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.450 ; +; -5.753 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.420 ; +; -5.751 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.418 ; +; -5.703 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; RCLK ; 1.000 ; 1.595 ; 7.965 ; +; -5.684 ; FS[2] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.351 ; +; -5.666 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ; +; -5.664 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.331 ; +; -5.663 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.330 ; +; -5.657 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.324 ; +; -5.655 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.322 ; +; -5.650 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.317 ; +; -5.648 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.315 ; +; -5.647 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.314 ; +; -5.645 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.312 ; +; -5.626 ; FS[6] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.293 ; +; -5.604 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.271 ; +; -5.594 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.261 ; +; -5.578 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.245 ; +; -5.571 ; Ready ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.238 ; +; -5.568 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.235 ; +; -5.558 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.225 ; +; -5.555 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.222 ; +; -5.552 ; FS[0] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.219 ; +; -5.548 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.215 ; +; -5.545 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.212 ; +; -5.544 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.211 ; +; -5.535 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.202 ; +; -5.451 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFMD[15] ; DRCLK ; RCLK ; 1.000 ; 1.595 ; 7.713 ; +; -5.438 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.105 ; +; -5.430 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.097 ; +; -5.398 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.065 ; +; -5.395 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.062 ; +; -5.386 ; RASr2 ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.053 ; +; -5.363 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.030 ; +; -5.357 ; FS[3] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.024 ; +; -5.356 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.023 ; +; -5.353 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.020 ; +; -5.345 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; +; -5.333 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.000 ; +; -5.332 ; FS[5] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.999 ; +; -5.329 ; FS[4] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.996 ; +; -5.329 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.996 ; +; -5.325 ; FS[15] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.992 ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Setup: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -8.271 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.438 ; +; -8.271 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.438 ; +; -8.271 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.438 ; +; -8.271 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.438 ; +; -8.251 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; +; -8.115 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.282 ; +; -8.115 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.282 ; +; -8.115 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.282 ; +; -8.115 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.282 ; +; -8.095 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.262 ; +; -7.799 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.966 ; +; -7.799 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.966 ; +; -7.643 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.810 ; +; -7.643 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.810 ; +; -7.577 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.744 ; +; -7.577 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.744 ; +; -7.577 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.744 ; +; -7.577 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.744 ; +; -7.557 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.724 ; +; -7.105 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.272 ; +; -7.105 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.272 ; +; -7.088 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.255 ; +; -7.088 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.255 ; +; -7.075 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.242 ; +; -7.075 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.242 ; +; -7.075 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.242 ; +; -7.075 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.242 ; +; -7.055 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.222 ; +; -7.054 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.221 ; +; -7.054 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.221 ; +; -7.054 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.221 ; +; -7.054 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.221 ; +; -7.034 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.201 ; +; -6.998 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.165 ; +; -6.932 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.099 ; +; -6.932 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.099 ; +; -6.900 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.067 ; +; -6.900 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.067 ; +; -6.900 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.067 ; +; -6.900 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.067 ; +; -6.880 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.047 ; +; -6.872 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.039 ; +; -6.842 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.009 ; +; -6.716 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.883 ; +; -6.603 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.770 ; +; -6.603 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.770 ; +; -6.582 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.749 ; +; -6.582 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.749 ; +; -6.428 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.595 ; +; -6.428 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.595 ; +; -6.394 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.561 ; +; -6.394 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.561 ; +; -6.362 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.529 ; +; -6.362 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.529 ; +; -6.362 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.529 ; +; -6.362 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.529 ; +; -6.342 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.509 ; +; -6.304 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.471 ; +; -6.178 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.345 ; +; -5.892 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.059 ; +; -5.892 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.059 ; +; -5.890 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.057 ; +; -5.890 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.057 ; +; -5.871 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.038 ; +; -5.871 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.038 ; +; -5.847 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.014 ; +; -5.847 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.014 ; +; -5.847 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.014 ; +; -5.847 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.014 ; +; -5.827 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.994 ; +; -5.802 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.969 ; +; -5.781 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.948 ; +; -5.717 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.884 ; +; -5.717 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.884 ; +; -5.676 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.843 ; +; -5.655 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.822 ; +; -5.627 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.794 ; +; -5.501 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.668 ; +; -5.375 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.542 ; +; -5.375 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.542 ; +; -5.179 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.346 ; +; -5.179 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.346 ; +; -5.089 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.256 ; +; -4.963 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.130 ; +; -4.664 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 4.831 ; +; -4.664 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 4.831 ; +; -4.574 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 4.741 ; +; -4.448 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 4.615 ; +; -4.234 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.901 ; +; -4.234 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.901 ; +; -3.754 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.421 ; +; -3.695 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.362 ; +; -3.674 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.341 ; +; -3.674 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.341 ; +; -3.674 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.341 ; +; -3.674 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.341 ; +; -3.404 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.571 ; +; -3.307 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.974 ; +; -3.297 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.964 ; +; -2.824 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.491 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Setup: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.317 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.053 ; +; -0.311 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.047 ; +; -0.310 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.046 ; +; -0.277 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.013 ; +; -0.276 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.012 ; +; -0.275 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.011 ; +; -0.267 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 3.003 ; +; -0.253 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 2.989 ; +; -0.252 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 2.988 ; +; -0.246 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 2.982 ; +; 0.038 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.917 ; 6.046 ; +; 0.079 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 2.657 ; +; 0.538 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.917 ; 6.046 ; +; 0.549 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.569 ; 2.187 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.858 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.613 ; 1.529 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.363 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.595 ; 2.042 ; +; -16.301 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.595 ; 2.104 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.103 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 2.187 ; +; -0.092 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.917 ; 6.046 ; +; 0.367 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 2.657 ; +; 0.408 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.917 ; 6.046 ; +; 0.692 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 2.982 ; +; 0.698 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 2.988 ; +; 0.699 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 2.989 ; +; 0.713 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.003 ; +; 0.721 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.011 ; +; 0.722 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.012 ; +; 0.723 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.013 ; +; 0.756 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.046 ; +; 0.757 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.047 ; +; 0.763 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.569 ; 3.053 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -0.060 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.244 ; 3.405 ; +; 0.172 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.244 ; 3.137 ; +; 0.206 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.244 ; 3.671 ; +; 2.578 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.799 ; +; 2.676 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.897 ; +; 3.054 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.275 ; +; 3.270 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.491 ; +; 3.565 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.286 ; +; 3.566 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.287 ; +; 3.743 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.964 ; +; 3.753 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.974 ; +; 3.850 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.571 ; +; 4.080 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.801 ; +; 4.081 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.802 ; +; 4.120 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.341 ; +; 4.120 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.341 ; +; 4.120 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.341 ; +; 4.120 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.341 ; +; 4.141 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.362 ; +; 4.200 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.421 ; +; 4.618 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.339 ; +; 4.619 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.340 ; +; 4.680 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.901 ; +; 4.680 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.901 ; +; 4.772 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.493 ; +; 4.773 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.494 ; +; 4.774 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.495 ; +; 4.793 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.514 ; +; 4.794 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.515 ; +; 4.894 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.615 ; +; 5.025 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.746 ; +; 5.289 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.010 ; +; 5.295 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.016 ; +; 5.296 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.017 ; +; 5.409 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.130 ; +; 5.540 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.261 ; +; 5.821 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.542 ; +; 5.821 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.542 ; +; 5.827 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.548 ; +; 5.833 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.554 ; +; 5.834 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.555 ; +; 5.947 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.668 ; +; 5.981 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.702 ; +; 5.989 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.710 ; +; 5.990 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.711 ; +; 6.002 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.723 ; +; 6.078 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.799 ; +; 6.101 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.822 ; +; 6.122 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.843 ; +; 6.232 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.953 ; +; 6.253 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.974 ; +; 6.293 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.014 ; +; 6.293 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.014 ; +; 6.293 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.014 ; +; 6.293 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.014 ; +; 6.336 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.057 ; +; 6.336 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.057 ; +; 6.504 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.225 ; +; 6.624 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.345 ; +; 6.755 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.476 ; +; 6.808 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.529 ; +; 6.808 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.529 ; +; 6.808 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.529 ; +; 6.808 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.529 ; +; 6.874 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.595 ; +; 6.874 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.595 ; +; 7.028 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.749 ; +; 7.028 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.749 ; +; 7.042 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.763 ; +; 7.049 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.770 ; +; 7.049 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.770 ; +; 7.162 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.883 ; +; 7.198 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.919 ; +; 7.293 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.014 ; +; 7.318 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.039 ; +; 7.346 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.067 ; +; 7.346 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.067 ; +; 7.346 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.067 ; +; 7.346 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.067 ; +; 7.449 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.170 ; +; 7.500 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.221 ; +; 7.500 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.221 ; +; 7.500 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.221 ; +; 7.500 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.221 ; +; 7.521 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.242 ; +; 7.521 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.242 ; +; 7.521 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.242 ; +; 7.521 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.242 ; +; 7.551 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.272 ; +; 7.551 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.272 ; +; 8.023 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.744 ; +; 8.023 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.744 ; +; 8.023 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.744 ; +; 8.023 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.744 ; +; 8.089 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.810 ; +; 8.089 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.810 ; +; 8.245 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.966 ; +; 8.245 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.966 ; +; 8.561 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.282 ; +; 8.561 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.282 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Hold: 'RCLK' ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; 1.192 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.761 ; +; 1.245 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.814 ; +; 1.338 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.907 ; +; 1.659 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ; +; 1.692 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.761 ; +; 1.693 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.914 ; +; 1.703 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.924 ; +; 1.704 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.925 ; +; 1.706 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.927 ; +; 1.745 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.814 ; +; 1.809 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.030 ; +; 1.829 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.050 ; +; 1.838 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.907 ; +; 1.952 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.173 ; +; 1.961 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.182 ; +; 1.966 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.187 ; +; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; +; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.124 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.345 ; +; 2.126 ; UFMD[15] ; UFMD[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; +; 2.143 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.364 ; +; 2.144 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ; +; 2.144 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ; +; 2.145 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ; +; 2.148 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.369 ; +; 2.151 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.372 ; +; 2.160 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.381 ; +; 2.164 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.385 ; +; 2.215 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.436 ; +; 2.230 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.239 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; +; 2.242 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.463 ; +; 2.250 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; +; 2.250 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; +; 2.267 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.488 ; +; 2.270 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.491 ; +; 2.271 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.492 ; +; 2.282 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.503 ; +; 2.332 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.553 ; +; 2.385 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.606 ; +; 2.395 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.616 ; +; 2.414 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.635 ; +; 2.596 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.817 ; +; 2.605 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.826 ; +; 2.647 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.868 ; +; 2.674 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.895 ; +; 2.689 ; S[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.910 ; +; 2.704 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.925 ; +; 2.741 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.962 ; +; 2.744 ; Ready ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.965 ; +; 2.748 ; Ready ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.969 ; +; 2.797 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.018 ; +; 2.799 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.020 ; +; 2.825 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.046 ; +; 2.939 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.160 ; +; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; +; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ; +; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; +; 2.974 ; Ready ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.195 ; +; 2.976 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.197 ; +; 2.976 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.197 ; +; 2.996 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.217 ; +; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; +; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ; +; 3.060 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; +; 3.076 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.297 ; +; 3.087 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.308 ; +; 3.087 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.308 ; +; 3.089 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.310 ; +; 3.106 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.327 ; +; 3.107 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.328 ; +; 3.112 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.333 ; +; 3.117 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.338 ; +; 3.161 ; S[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; +; 3.170 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; +; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; +; 3.174 ; RASr2 ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.395 ; +; 3.179 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ; +; 3.182 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.403 ; +; 3.184 ; Ready ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; +; 3.198 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.419 ; +; 3.199 ; IS[0] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.420 ; +; 3.201 ; InitReady ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.422 ; +; 3.226 ; Ready ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.447 ; +; 3.257 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.478 ; +; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; +; 3.285 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.506 ; +; 3.289 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; +; 3.290 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'ARCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'DRCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'PHI2' ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI2 ; Rise ; PHI2 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; ADSubmitted ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; ADSubmitted ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[4] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[5] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[6] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[7] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; C1Submitted ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; C1Submitted ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdEnable ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdEnable ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; RA11 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; RA11 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; UFMOscEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; UFMOscEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; XOR8MEG ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; XOR8MEG ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; PHI2|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; PHI2|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; RA11|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; RA11|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'RCLK' ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; RCLK ; Rise ; RCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARCLK ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARShift ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARShift ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr2 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr2 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr3 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr3 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRCLK ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRDIn ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRDIn ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRShift ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRShift ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[10] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[10] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[11] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[11] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[12] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[12] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[13] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[13] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[14] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[14] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[15] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[15] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[16] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[16] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[17] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[17] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[4] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[4] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[5] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[5] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[6] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[6] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[7] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[7] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[8] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[8] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[9] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[9] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; InitReady ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; InitReady ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; LEDEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; LEDEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r2 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r2 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r3 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r3 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RA10 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RA10 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr2 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr2 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr3 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr3 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKEEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKEEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; Ready ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; Ready ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMD[15] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMD[15] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMErase ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMErase ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMInitDone ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMInitDone ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMProgram ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMProgram ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMReqErase ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMReqErase ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; n8MEGEN ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ + + ++------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'nCCAS' ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCCAS ; Rise ; nCCAS ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[4] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[4] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[5] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[5] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[6] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[6] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[7] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[7] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'nCRAS' ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCRAS ; Rise ; nCRAS ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; CBR ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; CBR ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; FWEr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; FWEr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[4] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[4] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[5] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[5] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[6] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[6] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[7] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[7] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[8] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[8] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[9] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[9] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; CBR|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; CBR|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; FWEr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; FWEr|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; Din[*] ; PHI2 ; 1.258 ; 1.258 ; Rise ; PHI2 ; +; Din[0] ; PHI2 ; -0.399 ; -0.399 ; Rise ; PHI2 ; +; Din[1] ; PHI2 ; -0.465 ; -0.465 ; Rise ; PHI2 ; +; Din[2] ; PHI2 ; -0.419 ; -0.419 ; Rise ; PHI2 ; +; Din[3] ; PHI2 ; -0.432 ; -0.432 ; Rise ; PHI2 ; +; Din[4] ; PHI2 ; -0.403 ; -0.403 ; Rise ; PHI2 ; +; Din[5] ; PHI2 ; -0.284 ; -0.284 ; Rise ; PHI2 ; +; Din[6] ; PHI2 ; 1.258 ; 1.258 ; Rise ; PHI2 ; +; Din[7] ; PHI2 ; -0.455 ; -0.455 ; Rise ; PHI2 ; +; Din[*] ; PHI2 ; 6.350 ; 6.350 ; Fall ; PHI2 ; +; Din[0] ; PHI2 ; 6.350 ; 6.350 ; Fall ; PHI2 ; +; Din[1] ; PHI2 ; 5.955 ; 5.955 ; Fall ; PHI2 ; +; Din[2] ; PHI2 ; 5.770 ; 5.770 ; Fall ; PHI2 ; +; Din[3] ; PHI2 ; 6.091 ; 6.091 ; Fall ; PHI2 ; +; Din[4] ; PHI2 ; 6.121 ; 6.121 ; Fall ; PHI2 ; +; Din[5] ; PHI2 ; 5.943 ; 5.943 ; Fall ; PHI2 ; +; Din[6] ; PHI2 ; 5.355 ; 5.355 ; Fall ; PHI2 ; +; Din[7] ; PHI2 ; 5.526 ; 5.526 ; Fall ; PHI2 ; +; MAin[*] ; PHI2 ; 6.395 ; 6.395 ; Fall ; PHI2 ; +; MAin[0] ; PHI2 ; 3.121 ; 3.121 ; Fall ; PHI2 ; +; MAin[1] ; PHI2 ; 3.011 ; 3.011 ; Fall ; PHI2 ; +; MAin[2] ; PHI2 ; 6.395 ; 6.395 ; Fall ; PHI2 ; +; MAin[3] ; PHI2 ; 5.274 ; 5.274 ; Fall ; PHI2 ; +; MAin[4] ; PHI2 ; 5.540 ; 5.540 ; Fall ; PHI2 ; +; MAin[5] ; PHI2 ; 6.213 ; 6.213 ; Fall ; PHI2 ; +; MAin[6] ; PHI2 ; 4.745 ; 4.745 ; Fall ; PHI2 ; +; MAin[7] ; PHI2 ; 5.629 ; 5.629 ; Fall ; PHI2 ; +; nFWE ; PHI2 ; 4.554 ; 4.554 ; Fall ; PHI2 ; +; PHI2 ; RCLK ; 1.892 ; 1.892 ; Rise ; RCLK ; +; nCCAS ; RCLK ; 1.746 ; 1.746 ; Rise ; RCLK ; +; nCRAS ; RCLK ; 1.799 ; 1.799 ; Rise ; RCLK ; +; Din[*] ; nCCAS ; -0.186 ; -0.186 ; Fall ; nCCAS ; +; Din[0] ; nCCAS ; -0.211 ; -0.211 ; Fall ; nCCAS ; +; Din[1] ; nCCAS ; -0.524 ; -0.524 ; Fall ; nCCAS ; +; Din[2] ; nCCAS ; -0.467 ; -0.467 ; Fall ; nCCAS ; +; Din[3] ; nCCAS ; -0.495 ; -0.495 ; Fall ; nCCAS ; +; Din[4] ; nCCAS ; -0.201 ; -0.201 ; Fall ; nCCAS ; +; Din[5] ; nCCAS ; -0.387 ; -0.387 ; Fall ; nCCAS ; +; Din[6] ; nCCAS ; -0.186 ; -0.186 ; Fall ; nCCAS ; +; Din[7] ; nCCAS ; -0.459 ; -0.459 ; Fall ; nCCAS ; +; CROW[*] ; nCRAS ; 1.569 ; 1.569 ; Fall ; nCRAS ; +; CROW[0] ; nCRAS ; 1.396 ; 1.396 ; Fall ; nCRAS ; +; CROW[1] ; nCRAS ; 1.569 ; 1.569 ; Fall ; nCRAS ; +; MAin[*] ; nCRAS ; -0.660 ; -0.660 ; Fall ; nCRAS ; +; MAin[0] ; nCRAS ; -0.660 ; -0.660 ; Fall ; nCRAS ; +; MAin[1] ; nCRAS ; -0.783 ; -0.783 ; Fall ; nCRAS ; +; MAin[2] ; nCRAS ; -1.185 ; -1.185 ; Fall ; nCRAS ; +; MAin[3] ; nCRAS ; -1.355 ; -1.355 ; Fall ; nCRAS ; +; MAin[4] ; nCRAS ; -1.507 ; -1.507 ; Fall ; nCRAS ; +; MAin[5] ; nCRAS ; -1.728 ; -1.728 ; Fall ; nCRAS ; +; MAin[6] ; nCRAS ; -1.433 ; -1.433 ; Fall ; nCRAS ; +; MAin[7] ; nCRAS ; -1.123 ; -1.123 ; Fall ; nCRAS ; +; MAin[8] ; nCRAS ; -1.416 ; -1.416 ; Fall ; nCRAS ; +; MAin[9] ; nCRAS ; -1.500 ; -1.500 ; Fall ; nCRAS ; +; nCCAS ; nCRAS ; 0.462 ; 0.462 ; Fall ; nCRAS ; +; nFWE ; nCRAS ; 1.077 ; 1.077 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; Din[*] ; PHI2 ; 1.019 ; 1.019 ; Rise ; PHI2 ; +; Din[0] ; PHI2 ; 0.953 ; 0.953 ; Rise ; PHI2 ; +; Din[1] ; PHI2 ; 1.019 ; 1.019 ; Rise ; PHI2 ; +; Din[2] ; PHI2 ; 0.973 ; 0.973 ; Rise ; PHI2 ; +; Din[3] ; PHI2 ; 0.986 ; 0.986 ; Rise ; PHI2 ; +; Din[4] ; PHI2 ; 0.957 ; 0.957 ; Rise ; PHI2 ; +; Din[5] ; PHI2 ; 0.838 ; 0.838 ; Rise ; PHI2 ; +; Din[6] ; PHI2 ; 0.033 ; 0.033 ; Rise ; PHI2 ; +; Din[7] ; PHI2 ; 1.009 ; 1.009 ; Rise ; PHI2 ; +; Din[*] ; PHI2 ; 0.456 ; 0.456 ; Fall ; PHI2 ; +; Din[0] ; PHI2 ; 0.456 ; 0.456 ; Fall ; PHI2 ; +; Din[1] ; PHI2 ; 0.037 ; 0.037 ; Fall ; PHI2 ; +; Din[2] ; PHI2 ; -0.029 ; -0.029 ; Fall ; PHI2 ; +; Din[3] ; PHI2 ; -0.577 ; -0.577 ; Fall ; PHI2 ; +; Din[4] ; PHI2 ; 0.113 ; 0.113 ; Fall ; PHI2 ; +; Din[5] ; PHI2 ; -1.945 ; -1.945 ; Fall ; PHI2 ; +; Din[6] ; PHI2 ; -1.358 ; -1.358 ; Fall ; PHI2 ; +; Din[7] ; PHI2 ; -1.521 ; -1.521 ; Fall ; PHI2 ; +; MAin[*] ; PHI2 ; 0.373 ; 0.373 ; Fall ; PHI2 ; +; MAin[0] ; PHI2 ; 0.263 ; 0.263 ; Fall ; PHI2 ; +; MAin[1] ; PHI2 ; 0.373 ; 0.373 ; Fall ; PHI2 ; +; MAin[2] ; PHI2 ; -1.645 ; -1.645 ; Fall ; PHI2 ; +; MAin[3] ; PHI2 ; -0.524 ; -0.524 ; Fall ; PHI2 ; +; MAin[4] ; PHI2 ; -0.790 ; -0.790 ; Fall ; PHI2 ; +; MAin[5] ; PHI2 ; -1.463 ; -1.463 ; Fall ; PHI2 ; +; MAin[6] ; PHI2 ; -1.361 ; -1.361 ; Fall ; PHI2 ; +; MAin[7] ; PHI2 ; -2.245 ; -2.245 ; Fall ; PHI2 ; +; nFWE ; PHI2 ; -1.272 ; -1.272 ; Fall ; PHI2 ; +; PHI2 ; RCLK ; -1.338 ; -1.338 ; Rise ; RCLK ; +; nCCAS ; RCLK ; -1.192 ; -1.192 ; Rise ; RCLK ; +; nCRAS ; RCLK ; -1.245 ; -1.245 ; Rise ; RCLK ; +; Din[*] ; nCCAS ; 1.078 ; 1.078 ; Fall ; nCCAS ; +; Din[0] ; nCCAS ; 0.765 ; 0.765 ; Fall ; nCCAS ; +; Din[1] ; nCCAS ; 1.078 ; 1.078 ; Fall ; nCCAS ; +; Din[2] ; nCCAS ; 1.021 ; 1.021 ; Fall ; nCCAS ; +; Din[3] ; nCCAS ; 1.049 ; 1.049 ; Fall ; nCCAS ; +; Din[4] ; nCCAS ; 0.755 ; 0.755 ; Fall ; nCCAS ; +; Din[5] ; nCCAS ; 0.941 ; 0.941 ; Fall ; nCCAS ; +; Din[6] ; nCCAS ; 0.740 ; 0.740 ; Fall ; nCCAS ; +; Din[7] ; nCCAS ; 1.013 ; 1.013 ; Fall ; nCCAS ; +; CROW[*] ; nCRAS ; -0.842 ; -0.842 ; Fall ; nCRAS ; +; CROW[0] ; nCRAS ; -0.842 ; -0.842 ; Fall ; nCRAS ; +; CROW[1] ; nCRAS ; -1.015 ; -1.015 ; Fall ; nCRAS ; +; MAin[*] ; nCRAS ; 2.282 ; 2.282 ; Fall ; nCRAS ; +; MAin[0] ; nCRAS ; 1.214 ; 1.214 ; Fall ; nCRAS ; +; MAin[1] ; nCRAS ; 1.337 ; 1.337 ; Fall ; nCRAS ; +; MAin[2] ; nCRAS ; 1.739 ; 1.739 ; Fall ; nCRAS ; +; MAin[3] ; nCRAS ; 1.909 ; 1.909 ; Fall ; nCRAS ; +; MAin[4] ; nCRAS ; 2.061 ; 2.061 ; Fall ; nCRAS ; +; MAin[5] ; nCRAS ; 2.282 ; 2.282 ; Fall ; nCRAS ; +; MAin[6] ; nCRAS ; 1.987 ; 1.987 ; Fall ; nCRAS ; +; MAin[7] ; nCRAS ; 1.677 ; 1.677 ; Fall ; nCRAS ; +; MAin[8] ; nCRAS ; 1.970 ; 1.970 ; Fall ; nCRAS ; +; MAin[9] ; nCRAS ; 2.054 ; 2.054 ; Fall ; nCRAS ; +; nCCAS ; nCRAS ; 0.092 ; 0.092 ; Fall ; nCRAS ; +; nFWE ; nCRAS ; -0.523 ; -0.523 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; RA[*] ; PHI2 ; 12.060 ; 12.060 ; Rise ; PHI2 ; +; RA[11] ; PHI2 ; 12.060 ; 12.060 ; Rise ; PHI2 ; +; LED ; RCLK ; 9.813 ; 9.813 ; Rise ; RCLK ; +; RA[*] ; RCLK ; 12.293 ; 12.293 ; Rise ; RCLK ; +; RA[0] ; RCLK ; 12.293 ; 12.293 ; Rise ; RCLK ; +; RA[1] ; RCLK ; 11.412 ; 11.412 ; Rise ; RCLK ; +; RA[2] ; RCLK ; 11.273 ; 11.273 ; Rise ; RCLK ; +; RA[3] ; RCLK ; 10.539 ; 10.539 ; Rise ; RCLK ; +; RA[4] ; RCLK ; 11.236 ; 11.236 ; Rise ; RCLK ; +; RA[5] ; RCLK ; 11.157 ; 11.157 ; Rise ; RCLK ; +; RA[6] ; RCLK ; 11.290 ; 11.290 ; Rise ; RCLK ; +; RA[7] ; RCLK ; 11.217 ; 11.217 ; Rise ; RCLK ; +; RA[8] ; RCLK ; 11.381 ; 11.381 ; Rise ; RCLK ; +; RA[9] ; RCLK ; 11.302 ; 11.302 ; Rise ; RCLK ; +; RA[10] ; RCLK ; 8.195 ; 8.195 ; Rise ; RCLK ; +; RCKE ; RCLK ; 7.518 ; 7.518 ; Rise ; RCLK ; +; RDQMH ; RCLK ; 10.547 ; 10.547 ; Rise ; RCLK ; +; RDQML ; RCLK ; 11.010 ; 11.010 ; Rise ; RCLK ; +; nRCAS ; RCLK ; 7.518 ; 7.518 ; Rise ; RCLK ; +; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; +; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; +; nRWE ; RCLK ; 8.637 ; 8.637 ; Rise ; RCLK ; +; RD[*] ; nCCAS ; 19.663 ; 19.663 ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 18.824 ; 18.824 ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 18.920 ; 18.920 ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 18.917 ; 18.917 ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 19.501 ; 19.501 ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 18.823 ; 18.823 ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 18.946 ; 18.946 ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 19.663 ; 19.663 ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 18.951 ; 18.951 ; Fall ; nCCAS ; +; LED ; nCRAS ; 6.153 ; 6.153 ; Rise ; nCRAS ; +; LED ; nCRAS ; 6.153 ; 6.153 ; Fall ; nCRAS ; +; RA[*] ; nCRAS ; 13.196 ; 13.196 ; Fall ; nCRAS ; +; RA[0] ; nCRAS ; 12.954 ; 12.954 ; Fall ; nCRAS ; +; RA[1] ; nCRAS ; 12.928 ; 12.928 ; Fall ; nCRAS ; +; RA[2] ; nCRAS ; 12.374 ; 12.374 ; Fall ; nCRAS ; +; RA[3] ; nCRAS ; 13.196 ; 13.196 ; Fall ; nCRAS ; +; RA[4] ; nCRAS ; 12.862 ; 12.862 ; Fall ; nCRAS ; +; RA[5] ; nCRAS ; 12.781 ; 12.781 ; Fall ; nCRAS ; +; RA[6] ; nCRAS ; 13.093 ; 13.093 ; Fall ; nCRAS ; +; RA[7] ; nCRAS ; 13.020 ; 13.020 ; Fall ; nCRAS ; +; RA[8] ; nCRAS ; 13.070 ; 13.070 ; Fall ; nCRAS ; +; RA[9] ; nCRAS ; 13.106 ; 13.106 ; Fall ; nCRAS ; +; RBA[*] ; nCRAS ; 10.091 ; 10.091 ; Fall ; nCRAS ; +; RBA[0] ; nCRAS ; 10.087 ; 10.087 ; Fall ; nCRAS ; +; RBA[1] ; nCRAS ; 10.091 ; 10.091 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; RA[*] ; PHI2 ; 12.060 ; 12.060 ; Rise ; PHI2 ; +; RA[11] ; PHI2 ; 12.060 ; 12.060 ; Rise ; PHI2 ; +; LED ; RCLK ; 9.813 ; 9.813 ; Rise ; RCLK ; +; RA[*] ; RCLK ; 8.195 ; 8.195 ; Rise ; RCLK ; +; RA[0] ; RCLK ; 12.293 ; 12.293 ; Rise ; RCLK ; +; RA[1] ; RCLK ; 11.412 ; 11.412 ; Rise ; RCLK ; +; RA[2] ; RCLK ; 11.273 ; 11.273 ; Rise ; RCLK ; +; RA[3] ; RCLK ; 10.539 ; 10.539 ; Rise ; RCLK ; +; RA[4] ; RCLK ; 11.236 ; 11.236 ; Rise ; RCLK ; +; RA[5] ; RCLK ; 11.157 ; 11.157 ; Rise ; RCLK ; +; RA[6] ; RCLK ; 11.290 ; 11.290 ; Rise ; RCLK ; +; RA[7] ; RCLK ; 11.217 ; 11.217 ; Rise ; RCLK ; +; RA[8] ; RCLK ; 11.381 ; 11.381 ; Rise ; RCLK ; +; RA[9] ; RCLK ; 11.302 ; 11.302 ; Rise ; RCLK ; +; RA[10] ; RCLK ; 8.195 ; 8.195 ; Rise ; RCLK ; +; RCKE ; RCLK ; 7.518 ; 7.518 ; Rise ; RCLK ; +; RDQMH ; RCLK ; 10.547 ; 10.547 ; Rise ; RCLK ; +; RDQML ; RCLK ; 11.010 ; 11.010 ; Rise ; RCLK ; +; nRCAS ; RCLK ; 7.518 ; 7.518 ; Rise ; RCLK ; +; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; +; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; +; nRWE ; RCLK ; 8.637 ; 8.637 ; Rise ; RCLK ; +; RD[*] ; nCCAS ; 18.823 ; 18.823 ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 18.824 ; 18.824 ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 18.920 ; 18.920 ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 18.917 ; 18.917 ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 19.501 ; 19.501 ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 18.823 ; 18.823 ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 18.946 ; 18.946 ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 19.663 ; 19.663 ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 18.951 ; 18.951 ; Fall ; nCCAS ; +; LED ; nCRAS ; 6.153 ; 6.153 ; Rise ; nCRAS ; +; LED ; nCRAS ; 6.153 ; 6.153 ; Fall ; nCRAS ; +; RA[*] ; nCRAS ; 12.374 ; 12.374 ; Fall ; nCRAS ; +; RA[0] ; nCRAS ; 12.954 ; 12.954 ; Fall ; nCRAS ; +; RA[1] ; nCRAS ; 12.928 ; 12.928 ; Fall ; nCRAS ; +; RA[2] ; nCRAS ; 12.374 ; 12.374 ; Fall ; nCRAS ; +; RA[3] ; nCRAS ; 13.196 ; 13.196 ; Fall ; nCRAS ; +; RA[4] ; nCRAS ; 12.862 ; 12.862 ; Fall ; nCRAS ; +; RA[5] ; nCRAS ; 12.781 ; 12.781 ; Fall ; nCRAS ; +; RA[6] ; nCRAS ; 13.093 ; 13.093 ; Fall ; nCRAS ; +; RA[7] ; nCRAS ; 13.020 ; 13.020 ; Fall ; nCRAS ; +; RA[8] ; nCRAS ; 13.070 ; 13.070 ; Fall ; nCRAS ; +; RA[9] ; nCRAS ; 13.106 ; 13.106 ; Fall ; nCRAS ; +; RBA[*] ; nCRAS ; 10.087 ; 10.087 ; Fall ; nCRAS ; +; RBA[0] ; nCRAS ; 10.087 ; 10.087 ; Fall ; nCRAS ; +; RBA[1] ; nCRAS ; 10.091 ; 10.091 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; MAin[0] ; RA[0] ; 10.197 ; ; ; 10.197 ; +; MAin[1] ; RA[1] ; 9.846 ; ; ; 9.846 ; +; MAin[2] ; RA[2] ; 9.051 ; ; ; 9.051 ; +; MAin[3] ; RA[3] ; 8.214 ; ; ; 8.214 ; +; MAin[4] ; RA[4] ; 8.144 ; ; ; 8.144 ; +; MAin[5] ; RA[5] ; 8.753 ; ; ; 8.753 ; +; MAin[6] ; RA[6] ; 8.281 ; ; ; 8.281 ; +; MAin[7] ; RA[7] ; 9.251 ; ; ; 9.251 ; +; MAin[8] ; RA[8] ; 8.196 ; ; ; 8.196 ; +; MAin[9] ; RA[9] ; 8.221 ; ; ; 8.221 ; +; MAin[9] ; RDQMH ; 7.373 ; ; ; 7.373 ; +; MAin[9] ; RDQML ; 7.833 ; ; ; 7.833 ; +; RD[0] ; Dout[0] ; 6.115 ; ; ; 6.115 ; +; RD[1] ; Dout[1] ; 6.297 ; ; ; 6.297 ; +; RD[2] ; Dout[2] ; 6.244 ; ; ; 6.244 ; +; RD[3] ; Dout[3] ; 6.825 ; ; ; 6.825 ; +; RD[4] ; Dout[4] ; 6.717 ; ; ; 6.717 ; +; RD[5] ; Dout[5] ; 6.723 ; ; ; 6.723 ; +; RD[6] ; Dout[6] ; 6.184 ; ; ; 6.184 ; +; RD[7] ; Dout[7] ; 6.756 ; ; ; 6.756 ; +; nFWE ; RD[0] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[1] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[2] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[3] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[4] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[5] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[6] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[7] ; 16.365 ; ; ; 16.365 ; ++------------+-------------+--------+----+----+--------+ + + ++------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; MAin[0] ; RA[0] ; 10.197 ; ; ; 10.197 ; +; MAin[1] ; RA[1] ; 9.846 ; ; ; 9.846 ; +; MAin[2] ; RA[2] ; 9.051 ; ; ; 9.051 ; +; MAin[3] ; RA[3] ; 8.214 ; ; ; 8.214 ; +; MAin[4] ; RA[4] ; 8.144 ; ; ; 8.144 ; +; MAin[5] ; RA[5] ; 8.753 ; ; ; 8.753 ; +; MAin[6] ; RA[6] ; 8.281 ; ; ; 8.281 ; +; MAin[7] ; RA[7] ; 9.251 ; ; ; 9.251 ; +; MAin[8] ; RA[8] ; 8.196 ; ; ; 8.196 ; +; MAin[9] ; RA[9] ; 8.221 ; ; ; 8.221 ; +; MAin[9] ; RDQMH ; 7.373 ; ; ; 7.373 ; +; MAin[9] ; RDQML ; 7.833 ; ; ; 7.833 ; +; RD[0] ; Dout[0] ; 6.115 ; ; ; 6.115 ; +; RD[1] ; Dout[1] ; 6.297 ; ; ; 6.297 ; +; RD[2] ; Dout[2] ; 6.244 ; ; ; 6.244 ; +; RD[3] ; Dout[3] ; 6.825 ; ; ; 6.825 ; +; RD[4] ; Dout[4] ; 6.717 ; ; ; 6.717 ; +; RD[5] ; Dout[5] ; 6.723 ; ; ; 6.723 ; +; RD[6] ; Dout[6] ; 6.184 ; ; ; 6.184 ; +; RD[7] ; Dout[7] ; 6.756 ; ; ; 6.756 ; +; nFWE ; RD[0] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[1] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[2] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[3] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[4] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[5] ; 16.324 ; ; ; 16.324 ; +; nFWE ; RD[6] ; 16.365 ; ; ; 16.365 ; +; nFWE ; RD[7] ; 16.365 ; ; ; 16.365 ; ++------------+-------------+--------+----+----+--------+ + + ++-----------------------------------------------------------------------+ +; Output Enable Times ; ++-----------+------------+--------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+------+------------+-----------------+ +; RD[*] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; ++-----------+------------+--------+------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+--------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+------+------------+-----------------+ +; RD[*] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; ++-----------+------------+--------+------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; RD[*] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; RD[*] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 13.659 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 13.700 ; ; Fall ; nCCAS ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 31 ; 31 ; +; Unconstrained Input Port Paths ; 232 ; 232 ; +; Unconstrained Output Ports ; 38 ; 38 ; +; Unconstrained Output Port Paths ; 77 ; 77 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon Aug 16 18:40:18 2021 +Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name DRCLK DRCLK + Info (332105): create_clock -period 1.000 -name ARCLK ARCLK + Info (332105): create_clock -period 1.000 -name RCLK RCLK + Info (332105): create_clock -period 1.000 -name nCRAS nCRAS + Info (332105): create_clock -period 1.000 -name PHI2 PHI2 + Info (332105): create_clock -period 1.000 -name nCCAS nCCAS +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -99.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -99.000 -99.000 ARCLK + Info (332119): -99.000 -99.000 DRCLK + Info (332119): -8.339 -245.761 RCLK + Info (332119): -8.271 -88.383 PHI2 + Info (332119): -0.317 -2.784 nCRAS +Info (332146): Worst-case hold slack is -16.858 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -16.858 -16.858 ARCLK + Info (332119): -16.363 -16.363 DRCLK + Info (332119): -0.103 -0.195 nCRAS + Info (332119): -0.060 -0.060 PHI2 + Info (332119): 1.192 0.000 RCLK +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -29.500 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -29.500 -59.000 ARCLK + Info (332119): -29.500 -59.000 DRCLK + Info (332119): -2.289 -2.289 PHI2 + Info (332119): -2.289 -2.289 RCLK + Info (332119): -2.289 -2.289 nCCAS + Info (332119): -2.289 -2.289 nCRAS +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 374 megabytes + Info: Processing ended: Mon Aug 16 18:40:19 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CPLD/MAXII/output_files/RAM4GS.sta.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary old mode 100755 new mode 100644 similarity index 78% rename from CPLD/MAXII/output_files/RAM4GS.sta.summary rename to CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary index a4c9ebf..adebd09 --- a/CPLD/MAXII/output_files/RAM4GS.sta.summary +++ b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary @@ -10,37 +10,37 @@ Type : Setup 'DRCLK' Slack : -99.000 TNS : -99.000 -Type : Setup 'PHI2' -Slack : -9.292 -TNS : -92.804 - Type : Setup 'RCLK' -Slack : -8.365 -TNS : -253.063 +Slack : -8.339 +TNS : -245.761 + +Type : Setup 'PHI2' +Slack : -8.271 +TNS : -88.383 Type : Setup 'nCRAS' -Slack : -0.490 -TNS : -0.577 - -Type : Hold 'DRCLK' -Slack : -16.306 -TNS : -16.306 +Slack : -0.317 +TNS : -2.784 Type : Hold 'ARCLK' -Slack : -16.272 -TNS : -16.272 +Slack : -16.858 +TNS : -16.858 -Type : Hold 'RCLK' -Slack : -0.874 -TNS : -0.874 - -Type : Hold 'PHI2' -Slack : -0.396 -TNS : -0.396 +Type : Hold 'DRCLK' +Slack : -16.363 +TNS : -16.363 Type : Hold 'nCRAS' -Slack : -0.125 -TNS : -0.125 +Slack : -0.103 +TNS : -0.195 + +Type : Hold 'PHI2' +Slack : -0.060 +TNS : -0.060 + +Type : Hold 'RCLK' +Slack : 1.192 +TNS : 0.000 Type : Minimum Pulse Width 'ARCLK' Slack : -29.500 diff --git a/CPLD/MAXII/RAM4GS.qpf b/CPLD/MAX/MAXV/RAM2GS-MAXV.qpf old mode 100755 new mode 100644 similarity index 84% rename from CPLD/MAXII/RAM4GS.qpf rename to CPLD/MAX/MAXV/RAM2GS-MAXV.qpf index aceec8c..8fb201a --- a/CPLD/MAXII/RAM4GS.qpf +++ b/CPLD/MAX/MAXV/RAM2GS-MAXV.qpf @@ -16,15 +16,15 @@ # # -------------------------------------------------------------------------- # # -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 21:16:34 March 08, 2020 +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 18:33:17 August 16, 2021 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" -DATE = "21:16:34 March 08, 2020" +DATE = "18:33:17 August 16, 2021" # Revisions -PROJECT_REVISION = "RAM4GS" +PROJECT_REVISION = "RAM2GS" diff --git a/CPLD/AGM-src/RAM4GS.qsf b/CPLD/MAX/MAXV/RAM2GS.qsf old mode 100755 new mode 100644 similarity index 96% rename from CPLD/AGM-src/RAM4GS.qsf rename to CPLD/MAX/MAXV/RAM2GS.qsf index ed8578e..ecad28a --- a/CPLD/AGM-src/RAM4GS.qsf +++ b/CPLD/MAX/MAXV/RAM2GS.qsf @@ -36,14 +36,12 @@ # -------------------------------------------------------------------------- # -set_global_assignment -name FAMILY "MAX II" -set_global_assignment -name DEVICE EPM240T100C5 -set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M240ZT100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name SDC_FILE constraints.sdc -set_global_assignment -name VERILOG_FILE RAM4GS.v set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -174,7 +172,6 @@ set_location_assignment PIN_95 -to RD[6] set_location_assignment PIN_97 -to RD[7] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD -set_global_assignment -name MIF_FILE RAM4GS.mif set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE @@ -210,4 +207,6 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD set_instance_assignment -name SLOW_SLEW_RATE ON -to RD set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" +set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif" set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/CPLD/MAX/MAXV/RAM2GS.qws b/CPLD/MAX/MAXV/RAM2GS.qws new file mode 100644 index 0000000..9b19765 Binary files /dev/null and b/CPLD/MAX/MAXV/RAM2GS.qws differ diff --git a/CPLD/MAXII/UFM.qip b/CPLD/MAX/MAXV/UFM.qip old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/UFM.qip rename to CPLD/MAX/MAXV/UFM.qip diff --git a/CPLD/AGM-src/UFM.v b/CPLD/MAX/MAXV/UFM.v old mode 100755 new mode 100644 similarity index 80% rename from CPLD/AGM-src/UFM.v rename to CPLD/MAX/MAXV/UFM.v index c063115..16db83a --- a/CPLD/AGM-src/UFM.v +++ b/CPLD/MAX/MAXV/UFM.v @@ -9,7 +9,7 @@ // ALTUFM_NONE // // Simulation Library Files(s): -// maxii +// maxv // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -33,17 +33,17 @@ //applicable agreement for further details. -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy -//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 -//synthesis_resources = maxii_ufm 1 +//synthesis_resources = maxv_ufm 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on -module UFM_altufm_none_1br +module UFM_altufm_none_mjr ( arclk, ardin, @@ -90,7 +90,7 @@ module UFM_altufm_none_1br wire ufm_oscena; wire ufm_program; - maxii_ufm maxii_ufm_block1 + maxv_ufm maxii_ufm_block1 ( .arclk(ufm_arclk), .ardin(ufm_ardin), @@ -117,26 +117,26 @@ module UFM_altufm_none_1br defparam maxii_ufm_block1.address_width = 9, maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "RAM4GS.mif", + maxii_ufm_block1.init_file = "RAM2GS-MAX.mif", maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.osc_sim_setting = 180000, maxii_ufm_block1.program_time = 1600000, - maxii_ufm_block1.lpm_type = "maxii_ufm"; + maxii_ufm_block1.lpm_type = "maxv_ufm"; assign busy = ufm_busy, drdout = ufm_drdout, @@ -155,7 +155,7 @@ module UFM_altufm_none_1br ufm_osc = wire_maxii_ufm_block1_osc, ufm_oscena = oscena, ufm_program = program; -endmodule //UFM_altufm_none_1br +endmodule //UFM_altufm_none_mjr //VALID FILE @@ -200,7 +200,7 @@ module UFM ( wire drdout = sub_wire2; wire busy = sub_wire3; - UFM_altufm_none_1br UFM_altufm_none_1br_component ( + UFM_altufm_none_mjr UFM_altufm_none_mjr_component ( .arshft (arshft), .drclk (drclk), .erase (erase), @@ -221,10 +221,10 @@ endmodule // CNX file retrieval info // ============================================================ // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V" // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" @@ -265,4 +265,4 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE -// Retrieval info: LIB_FILE: maxii +// Retrieval info: LIB_FILE: maxv diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb new file mode 100644 index 0000000..b4b4e46 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb new file mode 100644 index 0000000..54a1d9d Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb new file mode 100644 index 0000000..8cd9b78 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb new file mode 100644 index 0000000..eb76e4a Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb new file mode 100644 index 0000000..0d88168 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb new file mode 100644 index 0000000..0a94ff8 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg new file mode 100644 index 0000000..1db2993 --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153622162 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing started: Mon Aug 16 18:40:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153622381 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153622381 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:22 2021 " "Processing ended: Mon Aug 16 18:40:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153622537 ""} diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb new file mode 100644 index 0000000..d5c4ae9 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb new file mode 100644 index 0000000..f0193ba Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb new file mode 100644 index 0000000..7958469 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb new file mode 100644 index 0000000..32f50d6 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb new file mode 100644 index 0000000..8b3dcdc Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt b/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt new file mode 100644 index 0000000..73afc77 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.logdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.logdb old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/db/RAM4GS.cmp.logdb rename to CPLD/MAX/MAXV/db/RAM2GS.cmp.logdb diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb new file mode 100644 index 0000000..4c11aeb Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb b/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb new file mode 100644 index 0000000..62186e1 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.db_info b/CPLD/MAX/MAXV/db/RAM2GS.db_info new file mode 100644 index 0000000..816de1e --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon Aug 16 18:36:34 2021 diff --git a/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg new file mode 100644 index 0000000..5f9e7a9 --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg @@ -0,0 +1,46 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153618530 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153618530 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153618639 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153618639 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153618748 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 336 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153618764 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153618764 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153618842 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153618842 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153618857 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 332 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 334 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 333 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153618873 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153618889 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153618889 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153618904 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153618904 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153618920 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153618920 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 17 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 17 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153618920 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153618951 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153619045 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619232 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153619247 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153619871 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619871 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153619903 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153620137 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153620137 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621129 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153621129 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621139 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153621169 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153621219 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing ended: Mon Aug 16 18:40:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153621239 ""} diff --git a/CPLD/MAXII/db/RAM4GS.hier_info b/CPLD/MAX/MAXV/db/RAM2GS.hier_info old mode 100755 new mode 100644 similarity index 93% rename from CPLD/MAXII/db/RAM4GS.hier_info rename to CPLD/MAX/MAXV/db/RAM2GS.hier_info index 97bc269..d04c06b --- a/CPLD/MAXII/db/RAM4GS.hier_info +++ b/CPLD/MAX/MAXV/db/RAM2GS.hier_info @@ -1,4 +1,4 @@ -|RAM4GS +|RAM2GS PHI2 => Bank[0].CLK PHI2 => Bank[1].CLK PHI2 => Bank[2].CLK @@ -152,12 +152,14 @@ nCRAS => RowA[8].CLK nCRAS => RowA[9].CLK nCRAS => RBA[0]~reg0.CLK nCRAS => RBA[1]~reg0.CLK +nCRAS => comb.IN1 nCRAS => RASr.DATAIN nFWE => comb.IN1 nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN +LED <= comb.DB_MAX_OUTPUT_PORT_TYPE RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE @@ -184,9 +186,10 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK -RCLK => n8MEGEN.CLK +RCLK => LEDEN.CLK RCLK => UFMInitDone.CLK -RCLK => UFMD.CLK +RCLK => n8MEGEN.CLK +RCLK => UFMD[15].CLK RCLK => DRShift.CLK RCLK => DRDIn.CLK RCLK => DRCLK.CLK @@ -243,7 +246,7 @@ RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE -|RAM4GS|UFM:UFM_inst +|RAM2GS|UFM:UFM_inst arclk => arclk.IN1 ardin => ardin.IN1 arshft => arshft.IN1 @@ -253,13 +256,13 @@ drshft => drshft.IN1 erase => erase.IN1 oscena => oscena.IN1 program => program.IN1 -busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy -drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout -osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc -rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy +busy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.busy +drdout <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.drdout +osc <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.osc +rtpbusy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.rtpbusy -|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component +|RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component arclk => maxii_ufm_block1.ARCLK ardin => maxii_ufm_block1.ARDIN arshft => maxii_ufm_block1.ARSHFT diff --git a/CPLD/MAX/MAXV/db/RAM2GS.hif b/CPLD/MAX/MAXV/db/RAM2GS.hif new file mode 100644 index 0000000..6fb7059 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.hif differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.ipinfo b/CPLD/MAX/MAXV/db/RAM2GS.ipinfo new file mode 100644 index 0000000..fa2304d Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.ipinfo differ diff --git a/CPLD/MAXII/db/RAM4GS.lpc.html b/CPLD/MAX/MAXV/db/RAM2GS.lpc.html old mode 100755 new mode 100644 similarity index 93% rename from CPLD/MAXII/db/RAM4GS.lpc.html rename to CPLD/MAX/MAXV/db/RAM2GS.lpc.html index d50a19d..707f37e --- a/CPLD/MAXII/db/RAM4GS.lpc.html +++ b/CPLD/MAX/MAXV/db/RAM2GS.lpc.html @@ -16,7 +16,7 @@ Output only Bidir -UFM_inst|UFM_altufm_none_1br_component +UFM_inst|UFM_altufm_none_mjr_component 9 0 0 diff --git a/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb b/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb new file mode 100644 index 0000000..8216994 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb differ diff --git a/CPLD/MAXII/db/RAM4GS.lpc.txt b/CPLD/MAX/MAXV/db/RAM2GS.lpc.txt old mode 100755 new mode 100644 similarity index 96% rename from CPLD/MAXII/db/RAM4GS.lpc.txt rename to CPLD/MAX/MAXV/db/RAM2GS.lpc.txt index d8d214c..17b369e --- a/CPLD/MAXII/db/RAM4GS.lpc.txt +++ b/CPLD/MAX/MAXV/db/RAM2GS.lpc.txt @@ -3,6 +3,6 @@ +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; UFM_inst|UFM_altufm_none_1br_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; UFM_inst|UFM_altufm_none_mjr_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; UFM_inst ; 9 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.cdb b/CPLD/MAX/MAXV/db/RAM2GS.map.cdb new file mode 100644 index 0000000..e4871a7 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.hdb b/CPLD/MAX/MAXV/db/RAM2GS.map.hdb new file mode 100644 index 0000000..c9ffc10 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.hdb differ diff --git a/CPLD/MAXII/db/RAM4GS.map.logdb b/CPLD/MAX/MAXV/db/RAM2GS.map.logdb old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/db/RAM4GS.map.logdb rename to CPLD/MAX/MAXV/db/RAM2GS.map.logdb diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg new file mode 100644 index 0000000..92e65f5 --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg @@ -0,0 +1,27 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153616333 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing started: Mon Aug 16 18:40:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153616598 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153616661 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_mjr " "Found entity 1: UFM_altufm_none_mjr" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153616739 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_mjr UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component " "Elaborating entity \"UFM_altufm_none_mjr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component\"" { } { { "UFM.v" "UFM_altufm_none_mjr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""} +{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0" { } { } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153616785 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153617319 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153617319 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153617350 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.rdb b/CPLD/MAX/MAXV/db/RAM2GS.map.rdb new file mode 100644 index 0000000..c7c7800 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb b/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb new file mode 100644 index 0000000..723fcab Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb new file mode 100644 index 0000000..36b866e Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/MAXII/db/RAM4GS.tis_db_list.ddb b/CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb old mode 100755 new mode 100644 similarity index 67% rename from CPLD/MAXII/db/RAM4GS.tis_db_list.ddb rename to CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb index 42a925d..89aa9b4 Binary files a/CPLD/MAXII/db/RAM4GS.tis_db_list.ddb and b/CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb b/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..dce5122 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb new file mode 100644 index 0000000..98f9da2 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb new file mode 100644 index 0000000..e1281ba Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb new file mode 100644 index 0000000..3d52775 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb new file mode 100644 index 0000000..d1b2728 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb new file mode 100644 index 0000000..b5e30c4 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb new file mode 100644 index 0000000..ea82e76 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb differ diff --git a/CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci old mode 100755 new mode 100644 similarity index 59% rename from CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci rename to CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci index 754b594..1d6d60f Binary files a/CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci and b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci differ diff --git a/CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci old mode 100755 new mode 100644 similarity index 59% rename from CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci rename to CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci index 754b594..1d6d60f Binary files a/CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci and b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci differ diff --git a/CPLD/MAXII/db/RAM4GS.smart_action.txt b/CPLD/MAX/MAXV/db/RAM2GS.smart_action.txt old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/db/RAM4GS.smart_action.txt rename to CPLD/MAX/MAXV/db/RAM2GS.smart_action.txt diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg new file mode 100644 index 0000000..734cddd --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg @@ -0,0 +1,23 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153623584 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:23 2021 " "Processing started: Mon Aug 16 18:40:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153623662 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153623787 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153623896 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153624208 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153624255 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153624255 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -23.638 -216.621 PHI2 " " -23.638 -216.621 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -19.942 -610.547 RCLK " " -19.942 -610.547 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.072 -6.479 nCRAS " " -3.072 -6.479 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.153 " "Worst-case hold slack is -16.153" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.153 -16.153 ARCLK " " -16.153 -16.153 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.623 -14.623 DRCLK " " -14.623 -14.623 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.569 -3.433 PHI2 " " -2.569 -3.433 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.713 -2.822 nCRAS " " -0.713 -2.822 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.127 0.000 RCLK " " 2.127 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153624348 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:24 2021 " "Processing ended: Mon Aug 16 18:40:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb new file mode 100644 index 0000000..e9c2f8b Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb new file mode 100644 index 0000000..c40c26a Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb differ diff --git a/CPLD/AGM-src/db/RAM4GS.syn_hier_info b/CPLD/MAX/MAXV/db/RAM2GS.syn_hier_info old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/db/RAM4GS.syn_hier_info rename to CPLD/MAX/MAXV/db/RAM2GS.syn_hier_info diff --git a/CPLD/MAXII/db/RAM4GS.pti_db_list.ddb b/CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb old mode 100755 new mode 100644 similarity index 67% rename from CPLD/MAXII/db/RAM4GS.pti_db_list.ddb rename to CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb index 61ca8da..91bbe10 Binary files a/CPLD/MAXII/db/RAM4GS.pti_db_list.ddb and b/CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb differ diff --git a/CPLD/MAX/MAXV/db/RAM2GS.tmw_info b/CPLD/MAX/MAXV/db/RAM2GS.tmw_info new file mode 100644 index 0000000..69e9cce --- /dev/null +++ b/CPLD/MAX/MAXV/db/RAM2GS.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:10 +start_analysis_synthesis:s:00:00:02-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:04-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb b/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb new file mode 100644 index 0000000..e64e992 Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAX/MAXV/db/logic_util_heursitic.dat b/CPLD/MAX/MAXV/db/logic_util_heursitic.dat new file mode 100644 index 0000000..ff5fe7f Binary files /dev/null and b/CPLD/MAX/MAXV/db/logic_util_heursitic.dat differ diff --git a/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg b/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg new file mode 100644 index 0000000..7bedb77 --- /dev/null +++ b/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153397464 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:36:37 2021 " "Processing started: Mon Aug 16 18:36:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""} +{ "Warning" "WACF_MISSING_TCL_FILE" "UFM.qip " "Tcl Script File UFM.qip not found" { { "Info" "IACF_ACF_ASSIGNMENT_INFO" "set_global_assignment -name QIP_FILE UFM.qip " "set_global_assignment -name QIP_FILE UFM.qip" { } { } 0 125063 "%1!s!" 0 0 "Quartus II" 0 -1 1629153397588 ""} } { } 0 125092 "Tcl Script File %1!s! not found" 0 0 "Quartus II" 0 -1 1629153397588 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153397744 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "RAM4GS.v " "Can't analyze file -- file RAM4GS.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1629153397807 ""} +{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "RAM2GS " "Top-level design entity \"RAM2GS\" is undefined" { } { } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Quartus II" 0 -1 1629153397854 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 3 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Aug 16 18:36:37 2021 " "Processing ended: Mon Aug 16 18:36:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 3 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153398462 ""} diff --git a/CPLD/MAXII/incremental_db/README b/CPLD/MAX/MAXV/incremental_db/README old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/incremental_db/README rename to CPLD/MAX/MAXV/incremental_db/README diff --git a/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info new file mode 100644 index 0000000..4382c8d --- /dev/null +++ b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Mon Aug 16 18:40:16 2021 diff --git a/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt new file mode 100644 index 0000000..2a67174 Binary files /dev/null and b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/MAXII/output_files/RAM4GS.asm.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt old mode 100755 new mode 100644 similarity index 70% rename from CPLD/MAXII/output_files/RAM4GS.asm.rpt rename to CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt index 1915f58..f918f0d --- a/CPLD/MAXII/output_files/RAM4GS.asm.rpt +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt @@ -1,6 +1,6 @@ -Assembler report for RAM4GS -Thu Jul 23 02:20:55 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Assembler report for RAM2GS +Mon Aug 16 18:40:22 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof + 5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof 6. Assembler Messages @@ -37,11 +37,11 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Jul 23 02:20:55 2020 ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; +; Assembler Status ; Successful - Mon Aug 16 18:40:22 2021 ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; +-----------------------+---------------------------------------+ @@ -75,40 +75,40 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+-----------+---------------+ -+--------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------+ -; File Name ; -+--------------------------------------------+ -; /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ; -+--------------------------------------------+ ++----------------------------------------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------------------------------------+ +; File Name ; ++----------------------------------------------------------------------------+ +; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ; ++----------------------------------------------------------------------------+ -+----------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ; -+----------------+-----------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------+ -; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00173F26 ; -; Checksum ; 0x0017428E ; -+----------------+-----------------------------------------------------+ ++------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ; ++----------------+-------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------------------------------------------------------+ +; Device ; 5M240ZT100C5 ; +; JTAG usercode ; 0x00172F05 ; +; Checksum ; 0x001732F5 ; ++----------------+-------------------------------------------------------------------------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Assembler +Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:53 2020 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS + Info: Processing started: Mon Aug 16 18:40:21 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files -Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 296 megabytes - Info: Processing ended: Thu Jul 23 02:20:55 2020 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 381 megabytes + Info: Processing ended: Mon Aug 16 18:40:22 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.done b/CPLD/MAX/MAXV/output_files/RAM2GS.done new file mode 100644 index 0000000..576e1e8 --- /dev/null +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.done @@ -0,0 +1 @@ +Mon Aug 16 18:40:25 2021 diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt old mode 100755 new mode 100644 similarity index 77% rename from CPLD/AGM-src/output_files/RAM4GS.fit.rpt rename to CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt index 15a6629..1cd6280 --- a/CPLD/AGM-src/output_files/RAM4GS.fit.rpt +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt @@ -1,6 +1,6 @@ -Fitter report for RAM4GS -Thu Jul 23 02:20:50 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Fitter report for RAM2GS +Mon Aug 16 18:40:21 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -59,15 +59,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Jul 23 02:20:50 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; +; Fitter Status ; Successful - Mon Aug 16 18:40:21 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 170 / 240 ( 71 % ) ; -; Total pins ; 62 / 80 ( 78 % ) ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; Total pins ; 63 / 79 ( 80 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -78,7 +78,7 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EPM240T100C5 ; ; +; Device ; 5M240ZT100C5 ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Placement Effort Multiplier ; 10 ; 1.0 ; @@ -122,27 +122,21 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.33 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 33.3% ; -+----------------------------+-------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pin. +------------------------------------------------------------------+ @@ -150,43 +144,43 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 170 / 240 ( 71 % ) ; -; -- Combinational with no register ; 74 ; -; -- Register only ; 21 ; -; -- Combinational with a register ; 75 ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; -- Combinational with no register ; 71 ; +; -- Register only ; 20 ; +; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 42 ; +; -- 4 input functions ; 58 ; +; -- 3 input functions ; 40 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 154 ; +; -- normal mode ; 152 ; ; -- arithmetic mode ; 16 ; -; -- qfbk mode ; 6 ; +; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 25 ; +; -- synchronous clear/load mode ; 24 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 / 240 ( 40 % ) ; -; Total LABs ; 22 / 24 ( 92 % ) ; +; Total registers ; 97 / 240 ( 40 % ) ; +; Total LABs ; 21 / 24 ( 88 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; -; I/O pins ; 62 / 80 ( 78 % ) ; -; -- Clock pins ; 2 / 4 ( 50 % ) ; +; I/O pins ; 63 / 79 ( 80 % ) ; +; -- Clock pins ; 3 / 4 ( 75 % ) ; ; ; ; ; Global signals ; 4 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 25% / 27% / 23% ; -; Peak interconnect usage (total/H/V) ; 25% / 27% / 23% ; -; Maximum fan-out ; 54 ; -; Highest non-global fan-out ; 38 ; -; Total fan-out ; 644 ; -; Average fan-out ; 2.76 ; +; Average interconnect usage (total/H/V) ; 27% / 29% / 25% ; +; Peak interconnect usage (total/H/V) ; 27% / 29% / 25% ; +; Maximum fan-out ; 55 ; +; Highest non-global fan-out ; 39 ; +; Total fan-out ; 643 ; +; Average fan-out ; 2.77 ; +---------------------------------------------+--------------------+ @@ -216,9 +210,9 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; -; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; -; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 15 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; ; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ; +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ @@ -236,6 +230,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; LED ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; ; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -243,17 +238,17 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -265,14 +260,14 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; -; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~3 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~3 ; - ; +; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~3 ; - ; +; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -282,116 +277,116 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin. ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+-------------------+---------------+--------------+ ; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; -; 2 ; 24 / 42 ( 57 % ) ; 3.3V ; -- ; +; 2 ; 25 / 41 ( 61 % ) ; 3.3V ; -- ; +----------+-------------------+---------------+--------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 2 ; 0 ; 1 ; RDQMH ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 3 ; 1 ; 1 ; nRCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 4 ; 2 ; 1 ; nRCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 5 ; 3 ; 1 ; RBA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 6 ; 4 ; 1 ; nRRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 8 ; 6 ; 1 ; RCKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; RCLK ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; RBA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 28 ; 22 ; 1 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 34 ; 26 ; 1 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 35 ; 27 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 36 ; 28 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 37 ; 29 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 38 ; 30 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 39 ; 31 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 40 ; 32 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 41 ; 33 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 42 ; 34 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 43 ; 35 ; 1 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 44 ; 36 ; 1 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 47 ; 37 ; 1 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 48 ; 38 ; 1 ; nFWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 49 ; 39 ; 1 ; MAin[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 50 ; 40 ; 1 ; MAin[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 51 ; 41 ; 1 ; MAin[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 52 ; 42 ; 2 ; PHI2 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 53 ; 43 ; 2 ; nCCAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 54 ; 44 ; 2 ; CROW[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 55 ; 45 ; 2 ; CROW[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 56 ; 46 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 57 ; 47 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 58 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 62 ; 50 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 67 ; 53 ; 2 ; nCRAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 68 ; 54 ; 2 ; MAin[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 69 ; 55 ; 2 ; MAin[5] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 70 ; 56 ; 2 ; MAin[4] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 71 ; 57 ; 2 ; MAin[3] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 72 ; 58 ; 2 ; MAin[6] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 73 ; 59 ; 2 ; MAin[8] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 74 ; 60 ; 2 ; MAin[9] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; -; 75 ; 61 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 63 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 84 ; 68 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 89 ; 73 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 92 ; 76 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 96 ; 78 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 97 ; 79 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 98 ; 80 ; 2 ; RDQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 99 ; 81 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 100 ; 82 ; 2 ; nRWE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 2 ; 0 ; 1 ; RDQMH ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 3 ; 1 ; 1 ; nRCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 4 ; 2 ; 1 ; nRCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 5 ; 3 ; 1 ; RBA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 6 ; 4 ; 1 ; nRRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 8 ; 6 ; 1 ; RCKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 7 ; 1 ; RCLK ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; +; 14 ; 8 ; 1 ; RBA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 28 ; 22 ; 1 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 25 ; 1 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 34 ; 26 ; 1 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 35 ; 27 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 36 ; 28 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 37 ; 29 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 38 ; 30 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 39 ; 31 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 40 ; 32 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 41 ; 33 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 42 ; 34 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 43 ; 35 ; 1 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 44 ; 36 ; 1 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 37 ; 1 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 48 ; 38 ; 1 ; nFWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 49 ; 39 ; 1 ; MAin[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 50 ; 40 ; 1 ; MAin[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 51 ; 41 ; 1 ; MAin[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 52 ; 42 ; 2 ; PHI2 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 53 ; 43 ; 2 ; nCCAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 54 ; 44 ; 2 ; CROW[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 55 ; 45 ; 2 ; CROW[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 56 ; 46 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 57 ; 47 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 58 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 62 ; 50 ; 2 ; LED ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; yes ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; +; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 67 ; 53 ; 2 ; nCRAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 68 ; 54 ; 2 ; MAin[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 69 ; 55 ; 2 ; MAin[5] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 70 ; 56 ; 2 ; MAin[4] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 71 ; 57 ; 2 ; MAin[3] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 72 ; 58 ; 2 ; MAin[6] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 73 ; 59 ; 2 ; MAin[8] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 74 ; 60 ; 2 ; MAin[9] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ; +; 75 ; 61 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 63 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 68 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 73 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 92 ; 76 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 96 ; 78 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 97 ; 79 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 98 ; 80 ; 2 ; RDQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 99 ; 81 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 100 ; 82 ; 2 ; nRWE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -407,6 +402,9 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; 1.5 V ; 10 pF ; Not Available ; ; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; ; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; +; 1.2 V ; 10 pF ; Not Available ; +; LVDS_E_3R ; 10 pF ; Not Available ; +; RSDS_E_3R ; 10 pF ; Not Available ; +----------------------------+-------+------------------------+ Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. @@ -416,9 +414,9 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |RAM4GS ; 170 (170) ; 96 ; 1 ; 62 ; 0 ; 74 (74) ; 21 (21) ; 75 (75) ; 17 (17) ; 6 (6) ; |RAM4GS ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ; -; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ; +; |RAM2GS ; 168 (168) ; 97 ; 1 ; 63 ; 0 ; 71 (71) ; 20 (20) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; work ; +; |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -428,6 +426,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +---------+----------+---------------+ +; nCRAS ; Input ; (0) ; ; MAin[0] ; Input ; (0) ; ; MAin[1] ; Input ; (0) ; ; MAin[2] ; Input ; (0) ; @@ -438,10 +437,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; MAin[7] ; Input ; (0) ; ; MAin[8] ; Input ; (0) ; ; MAin[9] ; Input ; (0) ; -; CROW[0] ; Input ; (1) ; -; nCRAS ; Input ; (0) ; -; CROW[1] ; Input ; (1) ; ; RCLK ; Input ; (0) ; +; CROW[0] ; Input ; (1) ; +; CROW[1] ; Input ; (1) ; ; PHI2 ; Input ; (0) ; ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; @@ -461,6 +459,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Dout[5] ; Output ; -- ; ; Dout[6] ; Output ; -- ; ; Dout[7] ; Output ; -- ; +; LED ; Output ; -- ; ; RBA[0] ; Output ; -- ; ; RBA[1] ; Output ; -- ; ; RA[0] ; Output ; -- ; @@ -498,16 +497,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~1 ; LC_X6_Y3_N3 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdSubmitted~0 ; LC_X6_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X2_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; -; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK3 ; -; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X3_Y2_N1 ; 38 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~5 ; LC_X5_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~2 ; LC_X4_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X5_Y4_N5 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdSubmitted~0 ; LC_X6_Y2_N4 ; 2 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X4_Y1_N2 ; 2 ; Clock enable ; no ; -- ; -- ; +; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK1 ; +; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; +; Ready ; LC_X3_Y2_N8 ; 39 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~5 ; LC_X7_Y3_N1 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~3 ; LC_X4_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 15 ; Clock ; yes ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -516,10 +515,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+----------+---------+----------------------+------------------+ -; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK3 ; -; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ; +; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK1 ; +; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ; ; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ; -; nCRAS ; PIN_67 ; 15 ; Global Clock ; GCLK1 ; +; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK3 ; +-------+----------+---------+----------------------+------------------+ @@ -528,99 +527,99 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------+---------+ -; Ready ; 38 ; +; Ready ; 39 ; ; nRowColSel ; 13 ; ; S[1] ; 12 ; ; S[0] ; 12 ; ; RASr2 ; 9 ; ; Din[6] ; 8 ; -; comb~2 ; 8 ; -; FS[4] ; 8 ; +; comb~3 ; 8 ; ; Din[5] ; 7 ; ; Din[4] ; 7 ; -; FS[5] ; 7 ; ; IS[0]~0 ; 7 ; ; Din[7] ; 6 ; ; Din[0] ; 6 ; ; MAin[1] ; 6 ; -; FS[6] ; 6 ; -; always9~1 ; 6 ; ; IS[0] ; 6 ; +; FS[4] ; 6 ; ; Din[3] ; 5 ; ; Din[2] ; 5 ; ; MAin[0] ; 5 ; -; FS[8]~27 ; 5 ; +; FS[8]~31 ; 5 ; ; FS[3]~13 ; 5 ; ; FS[3] ; 5 ; -; always9~2 ; 5 ; -; FS[17] ; 5 ; -; FS[16] ; 5 ; ; IS[1] ; 5 ; ; CBR ; 5 ; ; FWEr ; 5 ; +; FS[6] ; 5 ; +; FS[5] ; 5 ; +; FS[17] ; 5 ; +; FS[16] ; 5 ; +; UFMD[15] ; 5 ; ; Din[1] ; 4 ; ; MAin[9] ; 4 ; ; MAin[7] ; 4 ; ; MAin[6] ; 4 ; ; CmdDRDIn~1 ; 4 ; -; UFMD ; 4 ; -; FS[13]~21 ; 4 ; +; FS[13]~27 ; 4 ; ; CMDWR~2 ; 4 ; ; UFMReqErase ; 4 ; +; always9~3 ; 4 ; +; DRCLK~0 ; 4 ; +; always9~2 ; 4 ; ; Equal9~0 ; 4 ; -; n8MEGEN ; 4 ; ; IS[3] ; 4 ; ; IS[2] ; 4 ; ; InitReady ; 4 ; +; always9~0 ; 4 ; ; nFWE ; 3 ; ; MAin[5] ; 3 ; ; MAin[4] ; 3 ; ; MAin[3] ; 3 ; ; MAin[2] ; 3 ; -; FS[0] ; 3 ; ; always8~5 ; 3 ; ; CMDWR ; 3 ; ; CmdEnable ; 3 ; +; FS[0] ; 3 ; ; always8~4 ; 3 ; ; always8~2 ; 3 ; ; Equal0~0 ; 3 ; -; always9~3 ; 3 ; -; UFMInitDone ; 3 ; ; nRCS~3 ; 3 ; +; n8MEGEN ; 3 ; +; UFMInitDone~0 ; 3 ; +; UFMInitDone ; 3 ; ; RCKE~reg0 ; 3 ; +; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; 3 ; ; MAin[8] ; 2 ; -; FS[1] ; 2 ; -; FS[2] ; 2 ; -; Equal25~0 ; 2 ; -; FS[9] ; 2 ; -; FS[8] ; 2 ; ; CmdSubmitted~0 ; 2 ; ; Equal17~0 ; 2 ; ; CmdDRDIn~0 ; 2 ; ; XOR8MEG~0 ; 2 ; ; Equal0~3 ; 2 ; +; Ready~0 ; 2 ; +; Equal26~0 ; 2 ; +; FS[9] ; 2 ; +; FS[8] ; 2 ; ; Equal5~1 ; 2 ; -; FS[15] ; 2 ; ; FS[14] ; 2 ; ; FS[13] ; 2 ; ; FS[12] ; 2 ; ; FS[11] ; 2 ; ; FS[10] ; 2 ; -; Ready~0 ; 2 ; +; FS[15] ; 2 ; +; Equal24~0 ; 2 ; +; FS[2] ; 2 ; +; FS[1] ; 2 ; ; UFMOscEN~0 ; 2 ; ; C1Submitted ; 2 ; ; Equal0~1 ; 2 ; ; always8~0 ; 2 ; ; CmdUFMErase ; 2 ; ; CmdUFMPrgm ; 2 ; -; always9~6 ; 2 ; -; always9~5 ; 2 ; -; ARCLK~1 ; 2 ; ; always9~4 ; 2 ; -; DRDIn~1 ; 2 ; -; FS[7] ; 2 ; -; always9~0 ; 2 ; ; PHI2r2 ; 2 ; +; DRDIn~1 ; 2 ; +; CmdSubmitted ; 2 ; ; RASr ; 2 ; ; RCKEEN ; 2 ; ; CASr2 ; 2 ; @@ -630,13 +629,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; XOR8MEG ; 2 ; ; RA10~0 ; 2 ; ; nRowColSel~0 ; 2 ; +; always9~1 ; 2 ; +; FS[7] ; 2 ; ; UFMOscEN ; 2 ; ; UFMErase ; 2 ; ; UFMProgram ; 2 ; -; ARShift ; 2 ; -; ARCLK ; 2 ; -; DRShift ; 2 ; -; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; 2 ; +; LEDEN ; 2 ; ; UFMProgram~_wirecell ; 1 ; ; UFMOscEN~_wirecell ; 1 ; ; UFMErase~_wirecell ; 1 ; @@ -652,37 +650,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; CROW[0] ; 1 ; ; CmdEnable~1 ; 1 ; ; CmdEnable~0 ; 1 ; -; UFMD~1 ; 1 ; -; FS[1]~33COUT1_50 ; 1 ; -; FS[1]~33 ; 1 ; -; UFMD~0 ; 1 ; -; UFMReqErase~0 ; 1 ; -; FS[2]~31COUT1_52 ; 1 ; -; FS[2]~31 ; 1 ; -; FS[9]~29COUT1_62 ; 1 ; -; FS[9]~29 ; 1 ; -; UFMInitDone~0 ; 1 ; ; PHI2r ; 1 ; ; RCKEEN~2 ; 1 ; ; RCKEEN~1 ; 1 ; ; RCKEEN~0 ; 1 ; ; CASr ; 1 ; ; Equal16~0 ; 1 ; +; n8MEGEN~3 ; 1 ; +; PHI2r3 ; 1 ; +; n8MEGEN~2 ; 1 ; +; n8MEGEN~1 ; 1 ; ; n8MEGEN~0 ; 1 ; ; Cmdn8MEGEN ; 1 ; ; IS[0]~3 ; 1 ; -; FS[15]~25COUT1_72 ; 1 ; -; FS[15]~25 ; 1 ; -; FS[14]~23COUT1_70 ; 1 ; -; FS[14]~23 ; 1 ; -; Equal5~0 ; 1 ; -; FS[12]~19COUT1_68 ; 1 ; -; FS[12]~19 ; 1 ; -; FS[11]~17COUT1_66 ; 1 ; -; FS[11]~17 ; 1 ; -; FS[10]~15COUT1_64 ; 1 ; -; FS[10]~15 ; 1 ; ; Ready~1 ; 1 ; +; FS[9]~33COUT1_62 ; 1 ; +; FS[9]~33 ; 1 ; +; FS[14]~29COUT1_70 ; 1 ; +; FS[14]~29 ; 1 ; +; Equal5~0 ; 1 ; +; FS[12]~25COUT1_68 ; 1 ; +; FS[12]~25 ; 1 ; +; FS[11]~23COUT1_66 ; 1 ; +; FS[11]~23 ; 1 ; +; FS[10]~21COUT1_64 ; 1 ; +; FS[10]~21 ; 1 ; +; FS[15]~19COUT1_72 ; 1 ; +; FS[15]~19 ; 1 ; +; UFMD[15]~0 ; 1 ; +; FS[2]~17COUT1_52 ; 1 ; +; FS[2]~17 ; 1 ; +; FS[1]~15COUT1_50 ; 1 ; +; FS[1]~15 ; 1 ; ; WRD[7] ; 1 ; ; WRD[6] ; 1 ; ; WRD[5] ; 1 ; @@ -704,23 +703,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Bank[2] ; 1 ; ; Bank[3] ; 1 ; ; Bank[1] ; 1 ; -; ARShift~0 ; 1 ; -; ARCLK~3 ; 1 ; -; ARCLK~2 ; 1 ; +; always9~5 ; 1 ; ; ARCLK~0 ; 1 ; ; CmdDRCLK ; 1 ; -; DRCLK~0 ; 1 ; -; FS[6]~11COUT1_58 ; 1 ; -; FS[6]~11 ; 1 ; -; FS[7]~9COUT1_60 ; 1 ; -; FS[7]~9 ; 1 ; -; FS[16]~5COUT1_74 ; 1 ; -; FS[16]~5 ; 1 ; -; FS[4]~3COUT1_54 ; 1 ; -; FS[4]~3 ; 1 ; -; FS[5]~1COUT1_56 ; 1 ; -; FS[5]~1 ; 1 ; -; CmdSubmitted ; 1 ; ; CmdDRDIn ; 1 ; ; nRCAS~1 ; 1 ; ; nRCAS~0 ; 1 ; @@ -729,10 +714,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nRCS~4 ; 1 ; ; nRCS~2 ; 1 ; ; nRowColSel~1 ; 1 ; +; FS[4]~11COUT1_54 ; 1 ; +; FS[4]~11 ; 1 ; +; FS[6]~9COUT1_58 ; 1 ; +; FS[6]~9 ; 1 ; +; FS[5]~7COUT1_56 ; 1 ; +; FS[5]~7 ; 1 ; +; FS[7]~5COUT1_60 ; 1 ; +; FS[7]~5 ; 1 ; +; FS[16]~1COUT1_74 ; 1 ; +; FS[16]~1 ; 1 ; +; ARShift ; 1 ; +; ARCLK ; 1 ; +; DRShift ; 1 ; ; DRCLK ; 1 ; ; DRDIn ; 1 ; +; comb~2 ; 1 ; ; comb~1 ; 1 ; -; comb~0 ; 1 ; ; nRCAS~reg0 ; 1 ; ; nRRAS~reg0 ; 1 ; ; nRWE~reg0 ; 1 ; @@ -761,6 +759,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RowA[0] ; 1 ; ; RBA[1]~reg0 ; 1 ; ; RBA[0]~reg0 ; 1 ; +; comb~0 ; 1 ; +---------------------------------------------------------------------------------------------+---------+ @@ -769,112 +768,112 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 152 / 784 ( 19 % ) ; -; Direct links ; 45 / 888 ( 5 % ) ; +; C4s ; 162 / 784 ( 21 % ) ; +; Direct links ; 39 / 888 ( 4 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; LAB clocks ; 15 / 32 ( 47 % ) ; -; LUT chains ; 22 / 216 ( 10 % ) ; -; Local interconnects ; 270 / 888 ( 30 % ) ; -; R4s ; 155 / 704 ( 22 % ) ; +; LUT chains ; 20 / 216 ( 9 % ) ; +; Local interconnects ; 275 / 888 ( 31 % ) ; +; R4s ; 173 / 704 ( 25 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.73) ; Number of LABs (Total = 22) ; +; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 21) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; -; 2 ; 2 ; +; 2 ; 1 ; ; 3 ; 2 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 2 ; -; 9 ; 0 ; -; 10 ; 13 ; +; 4 ; 0 ; +; 5 ; 3 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 12 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.18) ; Number of LABs (Total = 22) ; +; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 21) ; +------------------------------------+------------------------------+ -; 1 Clock ; 14 ; +; 1 Clock ; 12 ; ; 1 Clock enable ; 2 ; -; 1 Sync. clear ; 3 ; +; 1 Sync. clear ; 4 ; ; 1 Sync. load ; 1 ; -; 2 Clocks ; 6 ; +; 2 Clocks ; 9 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.91) ; Number of LABs (Total = 22) ; +; Number of Signals Sourced (Average = 8.29) ; Number of LABs (Total = 21) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 2 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 1 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; ; 9 ; 1 ; -; 10 ; 11 ; -; 11 ; 1 ; -; 12 ; 1 ; +; 10 ; 9 ; +; 11 ; 4 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.73) ; Number of LABs (Total = 22) ; +; Number of Signals Sourced Out (Average = 5.76) ; Number of LABs (Total = 21) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; +; 1 ; 0 ; ; 2 ; 2 ; -; 3 ; 3 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 4 ; +; 3 ; 2 ; +; 4 ; 4 ; +; 5 ; 2 ; +; 6 ; 3 ; ; 7 ; 2 ; -; 8 ; 1 ; -; 9 ; 3 ; -; 10 ; 3 ; +; 8 ; 3 ; +; 9 ; 1 ; +; 10 ; 2 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.18) ; Number of LABs (Total = 22) ; +; Number of Distinct Inputs (Average = 11.29) ; Number of LABs (Total = 21) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 1 ; -; 6 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 2 ; ; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 4 ; -; 10 ; 1 ; -; 11 ; 1 ; -; 12 ; 2 ; -; 13 ; 3 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 2 ; +; 11 ; 2 ; +; 12 ; 4 ; +; 13 ; 1 ; ; 14 ; 1 ; -; 15 ; 0 ; -; 16 ; 1 ; -; 17 ; 1 ; +; 15 ; 1 ; +; 16 ; 2 ; +; 17 ; 0 ; ; 18 ; 0 ; ; 19 ; 1 ; +; 20 ; 1 ; +----------------------------------------------+------------------------------+ @@ -898,8 +897,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; nCRAS ; 1.3 ; -; I/O ; RCLK ; 1.2 ; +; I/O ; nCRAS ; 1.4 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. @@ -910,29 +908,32 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 1.303 ; -; PHI2 ; PHI2r ; 0.610 ; -; nCRAS ; RASr ; 0.301 ; +; nCCAS ; CBR ; 1.374 ; +; PHI2 ; PHI2r ; 0.176 ; +-----------------+----------------------+-------------------+ -Note: This table only shows the top 3 path(s) that have the largest delay added for hold. +Note: This table only shows the top 2 path(s) that have the largest delay added for hold. +-----------------+ ; Fitter Messages ; +-----------------+ -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (119006): Selected device EPM240T100C5 for design "RAM4GS" +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EPM240T100I5 is compatible - Info (176445): Device EPM240T100A5 is compatible - Info (176445): Device EPM570T100C5 is compatible - Info (176445): Device EPM570T100I5 is compatible - Info (176445): Device EPM570T100A5 is compatible -Info (332104): Reading SDC File: 'constraints.sdc' + Info (176445): Device 5M80ZT100C5 is compatible + Info (176445): Device 5M80ZT100I5 is compatible + Info (176445): Device 5M160ZT100C5 is compatible + Info (176445): Device 5M160ZT100I5 is compatible + Info (176445): Device 5M240ZT100I5 is compatible + Info (176445): Device 5M570ZT100C5 is compatible + Info (176445): Device 5M570ZT100I5 is compatible +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins + Info (169086): Pin LED not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement @@ -951,11 +952,12 @@ Info (186216): Automatically promoted some destinations of signal "PHI2" to use Info (186217): Destination "PHI2r" may be non-global or may not use global clock Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock + Info (186217): Destination "comb~0" may be non-global or may not use global clock Info (186217): Destination "RASr" may be non-global or may not use global clock Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock Info (186217): Destination "CBR" may be non-global or may not use global clock - Info (186217): Destination "comb~2" may be non-global or may not use global clock + Info (186217): Destination "comb~3" may be non-global or may not use global clock Info (186217): Destination "CASr" may be non-global or may not use global clock Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position Info (186079): Completed Auto Global Promotion Operation @@ -964,6 +966,13 @@ Info (186391): Fitter is using Normal packing mode for logic elements with Auto Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 17 pins available Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -974,20 +983,20 @@ Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 20% of the available device resources Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 376 megabytes - Info: Processing ended: Thu Jul 23 02:20:50 2020 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:08 +Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 548 megabytes + Info: Processing ended: Mon Aug 16 18:40:21 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg. +The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.smsg b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg old mode 100755 new mode 100644 similarity index 100% rename from CPLD/MAXII/output_files/RAM4GS.fit.smsg rename to CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary new file mode 100644 index 0000000..9f20503 --- /dev/null +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary @@ -0,0 +1,11 @@ +Fitter Status : Successful - Mon Aug 16 18:40:21 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2GS +Top-level Entity Name : RAM2GS +Family : MAX V +Device : 5M240ZT100C5 +Timing Models : Final +Total logic elements : 168 / 240 ( 70 % ) +Total pins : 63 / 79 ( 80 % ) +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.flow.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt old mode 100755 new mode 100644 similarity index 55% rename from CPLD/AGM-src/output_files/RAM4GS.flow.rpt rename to CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt index cab50ca..3bd2467 --- a/CPLD/AGM-src/output_files/RAM4GS.flow.rpt +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt @@ -1,6 +1,6 @@ -Flow report for RAM4GS -Thu Jul 23 02:21:02 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Flow report for RAM2GS +Mon Aug 16 18:40:24 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -40,15 +40,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Jul 23 02:20:55 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; +; Flow Status ; Successful - Mon Aug 16 18:40:22 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 170 / 240 ( 71 % ) ; -; Total pins ; 62 / 80 ( 78 % ) ; +; Total logic elements ; 168 / 240 ( 70 % ) ; +; Total pins ; 63 / 79 ( 80 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -59,34 +59,34 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 07/23/2020 02:20:37 ; +; Start date & time ; 08/16/2021 18:40:16 ; ; Main task ; Compilation ; -; Revision Name ; RAM4GS ; +; Revision Name ; RAM2GS ; +-------------------+---------------------+ -+------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ -; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.159548523602288 ; -- ; -- ; -- ; -; ENABLE_BUS_HOLD_CIRCUITRY ; On ; Off ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; -; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ; -; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; -; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; -; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+--------------------------------------------+--------------------------------+---------------+-------------+------------+ ++----------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 962837114763.162915361605944 ; -- ; -- ; -- ; +; ENABLE_BUS_HOLD_CIRCUITRY ; On ; Off ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; +; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ; +; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; +; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ; +; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++--------------------------------------------+------------------------------+---------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -94,33 +94,33 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 303 MB ; 00:00:05 ; -; Fitter ; 00:00:08 ; 1.3 ; 376 MB ; 00:00:07 ; -; Assembler ; 00:00:02 ; 1.0 ; 295 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 288 MB ; 00:00:04 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ; +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 421 MB ; 00:00:01 ; +; Fitter ; 00:00:03 ; 1.0 ; 548 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:01 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 368 MB ; 00:00:01 ; +; Total ; 00:00:06 ; -- ; -- ; 00:00:06 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+-----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; Assembler ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; TimeQuest Timing Analyzer ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -+---------------------------+------------------+------------+------------+----------------+ ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; +; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ ------------ ; Flow Log ; ------------ -quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS -quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS -quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS -quartus_sta RAM4GS -c RAM4GS +quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS +quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS +quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS +quartus_sta RAM2GS-MAXV -c RAM2GS diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.jdi b/CPLD/MAX/MAXV/output_files/RAM2GS.jdi new file mode 100644 index 0000000..448e697 --- /dev/null +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt old mode 100755 new mode 100644 similarity index 80% rename from CPLD/AGM-src/output_files/RAM4GS.map.rpt rename to CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt index 9d88205..ac1eb15 --- a/CPLD/AGM-src/output_files/RAM4GS.map.rpt +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt @@ -1,6 +1,6 @@ -Analysis & Synthesis report for RAM4GS -Thu Jul 23 02:20:40 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Analysis & Synthesis report for RAM2GS +Mon Aug 16 18:40:17 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -45,13 +45,13 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Top-level Entity Name ; RAM4GS ; -; Family ; MAX II ; -; Total logic elements ; 178 ; -; Total pins ; 62 ; +; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:17 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX V ; +; Total logic elements ; 177 ; +; Total pins ; 63 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+-------------------------------------------------+ @@ -62,9 +62,9 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EPM240T100C5 ; ; -; Top-level entity name ; RAM4GS ; RAM4GS ; -; Family name ; MAX II ; Cyclone IV GX ; +; Device ; 5M240ZT100C5 ; ; +; Top-level entity name ; RAM2GS ; RAM2GS ; +; Family name ; MAX V ; Cyclone IV GX ; ; Safe State Machine ; On ; Off ; ; Power-Up Don't Care ; Off ; On ; ; Use smart compilation ; Off ; Off ; @@ -130,32 +130,25 @@ applicable agreement for further details. +----------------------------------------------------------------------------+--------------------+--------------------+ -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; -+----------------------------+-------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ -; RAM4GS.v ; yes ; User Verilog HDL File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v ; ; -; RAM4GS.mif ; yes ; User Memory Initialization File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ; ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v ; ; ++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+ +-----------------------------------------------------+ @@ -163,32 +156,32 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 178 ; -; -- Combinational with no register ; 82 ; +; Total logic elements ; 177 ; +; -- Combinational with no register ; 80 ; ; -- Register only ; 29 ; -; -- Combinational with a register ; 67 ; +; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 57 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 42 ; +; -- 4 input functions ; 58 ; +; -- 3 input functions ; 40 ; +; -- 2 input functions ; 41 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 162 ; +; -- normal mode ; 161 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 9 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 ; +; Total registers ; 97 ; ; Total logic cells in carry chains ; 17 ; -; I/O pins ; 62 ; +; I/O pins ; 63 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; RCLK ; -; Maximum fan-out ; 54 ; +; Maximum fan-out ; 55 ; ; Total fan-out ; 643 ; ; Average fan-out ; 2.67 ; +---------------------------------------------+-------+ @@ -199,20 +192,20 @@ applicable agreement for further details. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |RAM4GS ; 178 (178) ; 96 ; 1 ; 62 ; 0 ; 82 (82) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM4GS ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ; -; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ; +; |RAM2GS ; 177 (177) ; 97 ; 1 ; 63 ; 0 ; 80 (80) ; 29 (29) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; work ; +; |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis IP Cores Summary ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ -; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ; -+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+ +; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v ; ++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+ +------------------------------------------------------+ @@ -220,7 +213,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 96 ; +; Total registers ; 97 ; ; Number of registers using Synchronous Clear ; 6 ; ; Number of registers using Synchronous Load ; 3 ; ; Number of registers using Asynchronous Clear ; 0 ; @@ -248,8 +241,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|S[0] ; -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|C1Submitted ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|ADSubmitted ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -269,22 +262,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Analysis & Synthesis +Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:35 2020 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v - Info (12023): Found entity 1: RAM4GS + Info: Processing started: Mon Aug 16 18:40:16 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_1br + Info (12023): Found entity 1: UFM_altufm_none_mjr Info (12023): Found entity 2: UFM -Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2) -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18) -Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4) +Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2) +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18) +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4) Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" -Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component" +Info (12128): Elaborating entity "UFM_altufm_none_mjr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component" +Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0 Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated @@ -295,21 +289,21 @@ Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins - Info (21059): Implemented 29 output pins + Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 178 logic cells + Info (21061): Implemented 177 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 303 megabytes - Info: Processing ended: Thu Jul 23 02:20:41 2020 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 +Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings + Info: Peak virtual memory: 421 megabytes + Info: Processing ended: Mon Aug 16 18:40:17 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg. +The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM4GS.map.smsg b/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg old mode 100755 new mode 100644 similarity index 71% rename from CPLD/MAXII/output_files/RAM4GS.map.smsg rename to CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg index 4c14264..a8e8eb9 --- a/CPLD/MAXII/output_files/RAM4GS.map.smsg +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM4GS.v(52): extended using "x" or "z" +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z" Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary new file mode 100644 index 0000000..68f556c --- /dev/null +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:17 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2GS +Top-level Entity Name : RAM2GS +Family : MAX V +Total logic elements : 177 +Total pins : 63 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM4GS.pin b/CPLD/MAX/MAXV/output_files/RAM2GS.pin old mode 100755 new mode 100644 similarity index 93% rename from CPLD/MAXII/output_files/RAM4GS.pin rename to CPLD/MAX/MAXV/output_files/RAM2GS.pin index 86ba0f4..299181b --- a/CPLD/MAXII/output_files/RAM4GS.pin +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.pin @@ -23,7 +23,7 @@ --------------------------------------------------------------------------------- -- NC : No Connect. This pin has no internal connection to the device. -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V). -- VCCIO : Dedicated power pin, which MUST be connected to VCC -- of its bank. -- Bank 1: 3.3V @@ -57,12 +57,12 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -CHIP "RAM4GS" ASSIGNED TO AN: EPM240T100C5 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- -GND* : 1 : : : : 2 : +GND : 1 : gnd : : : : RDQMH : 2 : output : 3.3-V LVCMOS : : 1 : Y nRCS : 3 : output : 3.3-V LVCMOS : : 1 : Y nRCAS : 4 : output : 3.3-V LVCMOS : : 1 : Y @@ -71,10 +71,10 @@ nRRAS : 6 : output : 3.3-V LVCMOS : RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y RCKE : 8 : output : 3.3-V LVCMOS : : 1 : Y VCCIO1 : 9 : power : : 3.3V : 1 : -GNDIO : 10 : gnd : : : : -GNDINT : 11 : gnd : : : : +GND : 10 : gnd : : : : +GND : 11 : gnd : : : : RCLK : 12 : input : 3.3-V LVCMOS : : 1 : Y -VCCINT : 13 : power : : 2.5V/3.3V : : +VCCINT : 13 : power : : 1.8V : : RBA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y @@ -93,7 +93,7 @@ Dout[5] : 28 : output : 3.3-V LVCMOS : RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y VCCIO1 : 31 : power : : 3.3V : 1 : -GNDIO : 32 : gnd : : : : +GND : 32 : gnd : : : : Dout[0] : 33 : output : 3.3-V LVCMOS : : 1 : Y Dout[6] : 34 : output : 3.3-V LVCMOS : : 1 : Y Din[2] : 35 : input : 3.3-V LVCMOS : : 1 : Y @@ -107,7 +107,7 @@ Din[0] : 42 : input : 3.3-V LVCMOS : Dout[7] : 43 : output : 3.3-V LVCMOS : : 1 : Y Dout[4] : 44 : output : 3.3-V LVCMOS : : 1 : Y VCCIO1 : 45 : power : : 3.3V : 1 : -GNDIO : 46 : gnd : : : : +GND : 46 : gnd : : : : Dout[3] : 47 : output : 3.3-V LVCMOS : : 1 : Y nFWE : 48 : input : 3.3-V LVCMOS : : 1 : Y MAin[0] : 49 : input : 3.3-V LVCMOS : : 1 : Y @@ -121,12 +121,12 @@ Dout[2] : 56 : output : 3.3-V LVCMOS : Dout[1] : 57 : output : 3.3-V LVCMOS : : 2 : Y GND* : 58 : : : : 2 : VCCIO2 : 59 : power : : 3.3V : 2 : -GNDIO : 60 : gnd : : : : +GND : 60 : gnd : : : : GND* : 61 : : : : 2 : -GND* : 62 : : : : 2 : -VCCINT : 63 : power : : 2.5V/3.3V : : +LED : 62 : output : 3.3-V LVTTL : : 2 : N +VCCINT : 63 : power : : 1.8V : : GND* : 64 : : : : 2 : -GNDINT : 65 : gnd : : : : +GND : 65 : gnd : : : : GND* : 66 : : : : 2 : nCRAS : 67 : input : 3.3-V LVCMOS : : 2 : Y MAin[7] : 68 : input : 3.3-V LVCMOS : : 2 : Y @@ -140,7 +140,7 @@ GND* : 75 : : : GND* : 76 : : : : 2 : GND* : 77 : : : : 2 : GND* : 78 : : : : 2 : -GNDIO : 79 : gnd : : : : +GND : 79 : gnd : : : : VCCIO2 : 80 : power : : 3.3V : 2 : GND* : 81 : : : : 2 : GND* : 82 : : : : 2 : @@ -154,7 +154,7 @@ RD[2] : 89 : bidir : 3.3-V LVCMOS : RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y RD[5] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y RD[4] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y -GNDIO : 93 : gnd : : : : +GND : 93 : gnd : : : : VCCIO2 : 94 : power : : 3.3V : 2 : RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y RD[0] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.pof b/CPLD/MAX/MAXV/output_files/RAM2GS.pof new file mode 100644 index 0000000..b9b6f58 Binary files /dev/null and b/CPLD/MAX/MAXV/output_files/RAM2GS.pof differ diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt new file mode 100644 index 0000000..34ffbe8 --- /dev/null +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt @@ -0,0 +1,1576 @@ +TimeQuest Timing Analyzer report for RAM2GS +Mon Aug 16 18:40:24 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Fmax Summary + 6. Setup Summary + 7. Hold Summary + 8. Recovery Summary + 9. Removal Summary + 10. Minimum Pulse Width Summary + 11. Setup: 'ARCLK' + 12. Setup: 'DRCLK' + 13. Setup: 'PHI2' + 14. Setup: 'RCLK' + 15. Setup: 'nCRAS' + 16. Hold: 'ARCLK' + 17. Hold: 'DRCLK' + 18. Hold: 'PHI2' + 19. Hold: 'nCRAS' + 20. Hold: 'RCLK' + 21. Minimum Pulse Width: 'ARCLK' + 22. Minimum Pulse Width: 'DRCLK' + 23. Minimum Pulse Width: 'PHI2' + 24. Minimum Pulse Width: 'RCLK' + 25. Minimum Pulse Width: 'nCCAS' + 26. Minimum Pulse Width: 'nCRAS' + 27. Setup Times + 28. Hold Times + 29. Clock to Output Times + 30. Minimum Clock to Output Times + 31. Propagation Delay + 32. Minimum Propagation Delay + 33. Output Enable Times + 34. Minimum Output Enable Times + 35. Output Disable Times + 36. Minimum Output Disable Times + 37. Setup Transfers + 38. Hold Transfers + 39. Report TCCS + 40. Report RSKM + 41. Unconstrained Paths + 42. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; RAM2GS ; +; Device Family ; MAX V ; +; Device Name ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; +; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; +; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; +; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; +; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 20.71 MHz ; 20.71 MHz ; PHI2 ; ; +; 47.75 MHz ; 47.75 MHz ; RCLK ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -99.000 ; -99.000 ; +; DRCLK ; -99.000 ; -99.000 ; +; PHI2 ; -23.638 ; -216.621 ; +; RCLK ; -19.942 ; -610.547 ; +; nCRAS ; -3.072 ; -6.479 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -16.153 ; -16.153 ; +; DRCLK ; -14.623 ; -14.623 ; +; PHI2 ; -2.569 ; -3.433 ; +; nCRAS ; -0.713 ; -2.822 ; +; RCLK ; 2.127 ; 0.000 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -29.500 ; -59.000 ; +; DRCLK ; -29.500 ; -59.000 ; +; PHI2 ; -2.289 ; -2.289 ; +; RCLK ; -2.289 ; -2.289 ; +; nCCAS ; -2.289 ; -2.289 ; +; nCRAS ; -2.289 ; -2.289 ; ++-------+---------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.847 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -0.884 ; 2.963 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; +; -24.468 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -0.994 ; 4.474 ; +; -24.377 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -0.994 ; 4.383 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Setup: 'PHI2' ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -23.638 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 23.817 ; +; -23.413 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 23.592 ; +; -22.503 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 22.682 ; +; -21.937 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 22.116 ; +; -21.404 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 21.583 ; +; -21.232 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 21.411 ; +; -21.179 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 21.358 ; +; -20.812 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.991 ; +; -20.269 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.448 ; +; -20.229 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.408 ; +; -20.229 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.408 ; +; -20.229 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.408 ; +; -20.229 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.408 ; +; -20.189 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.368 ; +; -20.004 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.183 ; +; -20.004 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.183 ; +; -20.004 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.183 ; +; -20.004 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.183 ; +; -19.703 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.882 ; +; -19.309 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.488 ; +; -19.309 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.488 ; +; -19.094 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.273 ; +; -19.094 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.273 ; +; -19.094 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.273 ; +; -19.094 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.273 ; +; -19.084 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.263 ; +; -19.084 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.263 ; +; -18.998 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.177 ; +; -18.578 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.757 ; +; -18.528 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.707 ; +; -18.528 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.707 ; +; -18.528 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.707 ; +; -18.528 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.707 ; +; -18.174 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.353 ; +; -18.174 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.353 ; +; -17.993 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.172 ; +; -17.955 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.134 ; +; -17.823 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.002 ; +; -17.823 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.002 ; +; -17.823 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.002 ; +; -17.823 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.002 ; +; -17.608 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.787 ; +; -17.608 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.787 ; +; -17.403 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.582 ; +; -17.403 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.582 ; +; -17.403 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.582 ; +; -17.403 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.582 ; +; -16.903 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.082 ; +; -16.903 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.082 ; +; -16.780 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.959 ; +; -16.780 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.959 ; +; -16.780 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.959 ; +; -16.780 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.959 ; +; -16.483 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.662 ; +; -16.483 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.662 ; +; -15.860 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.039 ; +; -15.860 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.039 ; +; -15.759 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.938 ; +; -15.305 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.484 ; +; -15.305 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.484 ; +; -15.080 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.259 ; +; -15.080 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.259 ; +; -14.777 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.956 ; +; -14.584 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.763 ; +; -14.584 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.763 ; +; -14.584 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.763 ; +; -14.584 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.763 ; +; -14.552 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.731 ; +; -14.170 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.349 ; +; -14.170 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.349 ; +; -13.664 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.843 ; +; -13.664 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.843 ; +; -13.642 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.821 ; +; -13.604 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.783 ; +; -13.604 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.783 ; +; -13.076 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.255 ; +; -12.899 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.078 ; +; -12.899 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.078 ; +; -12.479 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.658 ; +; -12.479 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.658 ; +; -12.415 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.094 ; +; -12.415 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.094 ; +; -12.415 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.094 ; +; -12.415 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.094 ; +; -12.371 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.550 ; +; -11.951 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.130 ; +; -11.942 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.621 ; +; -11.942 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.621 ; +; -11.856 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.035 ; +; -11.856 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.035 ; +; -11.414 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.093 ; +; -11.328 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.507 ; +; -9.660 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.839 ; +; -9.660 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.839 ; +; -9.132 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.311 ; +; -8.463 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.142 ; +; -8.261 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.940 ; +; -7.499 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.178 ; +; -6.906 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.585 ; +; -6.658 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.837 ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -19.942 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.621 ; +; -19.941 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.620 ; +; -19.634 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.313 ; +; -19.633 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.312 ; +; -18.886 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.565 ; +; -18.787 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.466 ; +; -18.771 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.450 ; +; -18.770 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.449 ; +; -18.479 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.158 ; +; -18.118 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.797 ; +; -17.725 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -6.837 ; 11.067 ; +; -17.709 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 13.152 ; +; -17.616 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.295 ; +; -17.380 ; FS[6] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.059 ; +; -17.379 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.058 ; +; -17.204 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.883 ; +; -17.204 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.883 ; +; -17.203 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.882 ; +; -16.737 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.416 ; +; -16.735 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.414 ; +; -16.583 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -6.837 ; 9.925 ; +; -16.436 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.115 ; +; -16.429 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.108 ; +; -16.427 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.106 ; +; -16.336 ; FS[17] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.015 ; +; -16.318 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.997 ; +; -16.095 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.774 ; +; -16.049 ; UFMInitDone ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.728 ; +; -16.028 ; FS[16] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.707 ; +; -15.980 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 11.423 ; +; -15.962 ; FS[5] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.641 ; +; -15.961 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.640 ; +; -15.903 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -6.837 ; 9.245 ; +; -15.834 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.513 ; +; -15.712 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.391 ; +; -15.711 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 11.154 ; +; -15.707 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 11.150 ; +; -15.566 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.245 ; +; -15.564 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.243 ; +; -15.554 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.233 ; +; -15.538 ; Ready ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.217 ; +; -15.499 ; Ready ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.178 ; +; -15.419 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.098 ; +; -15.371 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 10.814 ; +; -15.367 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 10.810 ; +; -15.320 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.999 ; +; -15.308 ; FS[4] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.987 ; +; -15.304 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -6.837 ; 8.646 ; +; -15.236 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.915 ; +; -15.235 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.914 ; +; -15.165 ; FS[7] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.844 ; +; -15.036 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.715 ; +; -14.996 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.675 ; +; -14.925 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.604 ; +; -14.894 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.573 ; +; -14.868 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.547 ; +; -14.852 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.531 ; +; -14.765 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.444 ; +; -14.728 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.407 ; +; -14.670 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.349 ; +; -14.620 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 10.063 ; +; -14.568 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.247 ; +; -14.564 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.243 ; +; -14.562 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.241 ; +; -14.536 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.215 ; +; -14.469 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.148 ; +; -14.469 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.148 ; +; -14.420 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.099 ; +; -14.370 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.049 ; +; -14.285 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.964 ; +; -14.280 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 9.723 ; +; -14.270 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.949 ; +; -14.267 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.946 ; +; -14.182 ; Ready ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.861 ; +; -14.180 ; Ready ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.859 ; +; -14.177 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.856 ; +; -14.175 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.854 ; +; -14.142 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.821 ; +; -14.059 ; S[1] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.738 ; +; -14.045 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.724 ; +; -14.017 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.696 ; +; -13.999 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.678 ; +; -13.997 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.676 ; +; -13.987 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.666 ; +; -13.985 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.664 ; +; -13.979 ; IS[2] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.658 ; +; -13.957 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.636 ; +; -13.920 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 0.994 ; 15.593 ; +; -13.911 ; RASr2 ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.590 ; +; -13.902 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.581 ; +; -13.816 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.495 ; +; -13.814 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.493 ; +; -13.804 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -4.736 ; 9.247 ; +; -13.774 ; FS[6] ; UFMD[15] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.453 ; +; -13.771 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.450 ; +; -13.744 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.423 ; +; -13.663 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.342 ; +; -13.640 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.319 ; +; -13.640 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.319 ; +; -13.631 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.310 ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Setup: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -3.072 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 9.682 ; 12.933 ; +; -2.572 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 9.682 ; 12.933 ; +; -1.936 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 6.851 ; +; -1.471 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 6.386 ; +; 0.029 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.886 ; +; 0.030 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.885 ; +; 0.031 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.884 ; +; 0.033 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.882 ; +; 0.042 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.873 ; +; 0.042 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 4.873 ; +; 1.342 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 3.573 ; +; 1.343 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 3.572 ; +; 1.344 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 3.571 ; +; 1.353 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 4.736 ; 3.562 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.153 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -0.884 ; 2.963 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -14.623 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -0.994 ; 4.383 ; +; -14.532 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -0.994 ; 4.474 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -2.569 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 6.837 ; 3.807 ; +; -0.864 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.837 ; 6.012 ; +; -0.191 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.837 ; 6.685 ; +; 5.284 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.323 ; +; 5.457 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.496 ; +; 6.515 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.554 ; +; 7.298 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.837 ; +; 7.546 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.585 ; +; 8.139 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.178 ; +; 8.901 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.940 ; +; 9.103 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.142 ; +; 9.772 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.311 ; +; 10.300 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.839 ; +; 10.300 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.839 ; +; 10.451 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.990 ; +; 10.454 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.993 ; +; 11.968 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.507 ; +; 12.054 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.093 ; +; 12.106 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.645 ; +; 12.496 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.035 ; +; 12.496 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.035 ; +; 12.582 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.621 ; +; 12.582 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.621 ; +; 12.591 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.130 ; +; 12.647 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.186 ; +; 12.650 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.189 ; +; 13.011 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.550 ; +; 13.055 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.094 ; +; 13.055 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.094 ; +; 13.055 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.094 ; +; 13.055 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.094 ; +; 13.119 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.658 ; +; 13.119 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.658 ; +; 13.270 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.809 ; +; 13.273 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.812 ; +; 13.539 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.078 ; +; 13.539 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.078 ; +; 13.663 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.202 ; +; 13.690 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.229 ; +; 13.693 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.232 ; +; 13.716 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.255 ; +; 14.244 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.783 ; +; 14.244 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.783 ; +; 14.282 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.821 ; +; 14.302 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.841 ; +; 14.395 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.934 ; +; 14.398 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.937 ; +; 14.810 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.349 ; +; 14.810 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.349 ; +; 14.925 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.464 ; +; 14.961 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.500 ; +; 14.964 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.503 ; +; 15.192 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.731 ; +; 15.224 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.763 ; +; 15.224 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.763 ; +; 15.224 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.763 ; +; 15.224 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.763 ; +; 15.345 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.884 ; +; 15.417 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.956 ; +; 15.720 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.259 ; +; 15.720 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.259 ; +; 15.859 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.398 ; +; 15.871 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.410 ; +; 15.874 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.413 ; +; 15.945 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.484 ; +; 15.945 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.484 ; +; 16.050 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.589 ; +; 16.096 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.635 ; +; 16.099 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.638 ; +; 16.482 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.021 ; +; 16.616 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.155 ; +; 16.902 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.441 ; +; 17.420 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.959 ; +; 17.420 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.959 ; +; 17.420 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.959 ; +; 17.420 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.959 ; +; 17.526 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.065 ; +; 17.607 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.146 ; +; 17.751 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.290 ; +; 18.043 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.582 ; +; 18.043 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.582 ; +; 18.043 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.582 ; +; 18.043 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.582 ; +; 18.173 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.712 ; +; 18.463 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.002 ; +; 18.463 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.002 ; +; 18.463 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.002 ; +; 18.463 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.002 ; +; 19.083 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.622 ; +; 19.168 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.707 ; +; 19.168 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.707 ; +; 19.168 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.707 ; +; 19.168 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.707 ; +; 19.308 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.847 ; +; 19.734 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.273 ; +; 19.734 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.273 ; +; 19.734 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.273 ; +; 19.734 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.273 ; +; 20.644 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 20.183 ; +; 20.644 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 20.183 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.713 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 3.562 ; +; -0.704 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 3.571 ; +; -0.703 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 3.572 ; +; -0.702 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 3.573 ; +; 0.598 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.873 ; +; 0.598 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.873 ; +; 0.607 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.882 ; +; 0.609 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.884 ; +; 0.610 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.885 ; +; 0.611 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 4.886 ; +; 2.111 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 6.386 ; +; 2.576 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 4.736 ; 6.851 ; +; 3.212 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 9.682 ; 12.933 ; +; 3.712 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 9.682 ; 12.933 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Hold: 'RCLK' ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; 2.127 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 4.946 ; 7.112 ; +; 2.325 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 4.946 ; 7.310 ; +; 2.627 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 4.946 ; 7.112 ; +; 2.825 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 4.946 ; 7.310 ; +; 3.362 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.401 ; +; 3.382 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.421 ; +; 3.813 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.852 ; +; 3.827 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.866 ; +; 3.902 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.941 ; +; 3.997 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 4.946 ; 8.982 ; +; 4.411 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.450 ; +; 4.478 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.517 ; +; 4.497 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 4.946 ; 8.982 ; +; 4.580 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.619 ; +; 4.581 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.620 ; +; 5.217 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.256 ; +; 5.228 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.267 ; +; 5.228 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.267 ; +; 5.229 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.268 ; +; 5.229 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.268 ; +; 5.229 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.268 ; +; 5.241 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.280 ; +; 5.244 ; RCKEEN ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.283 ; +; 5.254 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.293 ; +; 5.269 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.308 ; +; 5.275 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.314 ; +; 5.335 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.374 ; +; 5.337 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.376 ; +; 5.392 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.431 ; +; 5.431 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.470 ; +; 5.440 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.479 ; +; 5.440 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.479 ; +; 5.441 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.480 ; +; 5.441 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.480 ; +; 5.444 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.483 ; +; 5.444 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.483 ; +; 5.452 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.491 ; +; 5.452 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.491 ; +; 5.454 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.493 ; +; 5.466 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.505 ; +; 5.498 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.537 ; +; 5.502 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.541 ; +; 5.521 ; UFMD[15] ; UFMD[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.560 ; +; 5.523 ; UFMD[15] ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.562 ; +; 5.524 ; UFMD[15] ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.563 ; +; 5.525 ; UFMD[15] ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.564 ; +; 5.551 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.590 ; +; 5.564 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.603 ; +; 5.595 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.634 ; +; 5.690 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.729 ; +; 5.715 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.754 ; +; 5.717 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.756 ; +; 5.730 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.769 ; +; 5.730 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.769 ; +; 5.952 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.991 ; +; 5.963 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.002 ; +; 5.963 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.002 ; +; 5.964 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.003 ; +; 5.964 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.003 ; +; 5.969 ; CASr3 ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.008 ; +; 5.989 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.028 ; +; 6.025 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.064 ; +; 6.096 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.135 ; +; 6.107 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.146 ; +; 6.107 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.146 ; +; 6.108 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.147 ; +; 6.113 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.152 ; +; 6.133 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.172 ; +; 6.173 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.212 ; +; 6.251 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.290 ; +; 6.251 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.290 ; +; 6.334 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.373 ; +; 6.395 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.434 ; +; 6.433 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.472 ; +; 6.442 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.481 ; +; 6.442 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.481 ; +; 6.443 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.482 ; +; 6.454 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.493 ; +; 6.454 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.493 ; +; 6.456 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.495 ; +; 6.534 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.573 ; +; 6.560 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.599 ; +; 6.586 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.625 ; +; 6.587 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.626 ; +; 6.595 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.634 ; +; 6.598 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.637 ; +; 6.598 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.637 ; +; 6.730 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.769 ; +; 6.742 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.781 ; +; 6.742 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.781 ; +; 6.744 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.783 ; +; 6.744 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.783 ; +; 6.744 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.783 ; +; 6.744 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.783 ; +; 6.769 ; FS[1] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.808 ; +; 6.769 ; FS[1] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.808 ; +; 6.769 ; FS[1] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.808 ; +; 6.769 ; FS[1] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.808 ; +; 6.769 ; FS[1] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.808 ; +; 6.785 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.824 ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'ARCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'DRCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'PHI2' ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI2 ; Rise ; PHI2 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; ADSubmitted ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; ADSubmitted ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[2] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[3] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[4] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[5] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[6] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; Bank[7] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; C1Submitted ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; C1Submitted ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdEnable ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdEnable ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Rise ; RA11 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Rise ; RA11 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; UFMOscEN ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; UFMOscEN ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; PHI2 ; Fall ; XOR8MEG ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; PHI2 ; Fall ; XOR8MEG ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; PHI2|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; PHI2|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; RA11|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; RA11|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; ++--------+--------------+----------------+------------------+-------+------------+------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'RCLK' ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; RCLK ; Rise ; RCLK ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; ARCLK ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; ARCLK ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; ARShift ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; ARShift ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; CASr ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; CASr ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; CASr2 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; CASr2 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; CASr3 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; CASr3 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; DRCLK ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; DRCLK ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; DRDIn ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; DRDIn ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; DRShift ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; DRShift ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[10] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[10] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[11] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[11] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[12] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[12] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[13] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[13] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[14] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[14] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[15] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[15] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[16] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[16] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[17] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[17] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[2] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[2] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[3] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[3] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[4] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[4] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[5] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[5] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[6] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[6] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[7] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[7] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[8] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[8] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; FS[9] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; FS[9] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; IS[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; IS[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; IS[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; IS[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; IS[2] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; IS[2] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; IS[3] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; IS[3] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; InitReady ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; InitReady ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; LEDEN ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; LEDEN ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; PHI2r ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; PHI2r ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; PHI2r2 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; PHI2r2 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; PHI2r3 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; PHI2r3 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RA10 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RA10 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RASr ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RASr ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RASr2 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RASr2 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RASr3 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RASr3 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RCKEEN ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RCKEEN ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; Ready ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; Ready ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; S[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; S[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; S[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; S[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; UFMD[15] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; UFMD[15] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; UFMErase ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; UFMErase ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; UFMInitDone ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; UFMInitDone ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; UFMProgram ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; UFMProgram ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; UFMReqErase ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; RCLK ; Rise ; UFMReqErase ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; RCLK ; Rise ; n8MEGEN ; ++--------+--------------+----------------+------------------+-------+------------+-------------+ + + ++------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'nCCAS' ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCCAS ; Rise ; nCCAS ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[2] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[2] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[3] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[3] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[4] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[4] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[5] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[5] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[6] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[6] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCCAS ; Fall ; WRD[7] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCCAS ; Fall ; WRD[7] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; ++--------+--------------+----------------+------------------+-------+------------+---------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'nCRAS' ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCRAS ; Rise ; nCRAS ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; CBR ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; CBR ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; FWEr ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; FWEr ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[0] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[0] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[1] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[1] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[2] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[2] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[3] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[3] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[4] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[4] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[5] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[5] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[6] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[6] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[7] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[7] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[8] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[8] ; +; 0.161 ; 0.500 ; 0.339 ; High Pulse Width ; nCRAS ; Fall ; RowA[9] ; +; 0.161 ; 0.500 ; 0.339 ; Low Pulse Width ; nCRAS ; Fall ; RowA[9] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; CBR|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; CBR|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; FWEr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; FWEr|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; Din[*] ; PHI2 ; 5.619 ; 5.619 ; Rise ; PHI2 ; +; Din[0] ; PHI2 ; 1.618 ; 1.618 ; Rise ; PHI2 ; +; Din[1] ; PHI2 ; 1.922 ; 1.922 ; Rise ; PHI2 ; +; Din[2] ; PHI2 ; 3.930 ; 3.930 ; Rise ; PHI2 ; +; Din[3] ; PHI2 ; 1.790 ; 1.790 ; Rise ; PHI2 ; +; Din[4] ; PHI2 ; 5.619 ; 5.619 ; Rise ; PHI2 ; +; Din[5] ; PHI2 ; 1.892 ; 1.892 ; Rise ; PHI2 ; +; Din[6] ; PHI2 ; 0.488 ; 0.488 ; Rise ; PHI2 ; +; Din[7] ; PHI2 ; -1.895 ; -1.895 ; Rise ; PHI2 ; +; Din[*] ; PHI2 ; 18.851 ; 18.851 ; Fall ; PHI2 ; +; Din[0] ; PHI2 ; 15.527 ; 15.527 ; Fall ; PHI2 ; +; Din[1] ; PHI2 ; 18.391 ; 18.391 ; Fall ; PHI2 ; +; Din[2] ; PHI2 ; 18.150 ; 18.150 ; Fall ; PHI2 ; +; Din[3] ; PHI2 ; 18.836 ; 18.836 ; Fall ; PHI2 ; +; Din[4] ; PHI2 ; 18.731 ; 18.731 ; Fall ; PHI2 ; +; Din[5] ; PHI2 ; 18.851 ; 18.851 ; Fall ; PHI2 ; +; Din[6] ; PHI2 ; 16.140 ; 16.140 ; Fall ; PHI2 ; +; Din[7] ; PHI2 ; 17.790 ; 17.790 ; Fall ; PHI2 ; +; MAin[*] ; PHI2 ; 27.296 ; 27.296 ; Fall ; PHI2 ; +; MAin[0] ; PHI2 ; 18.855 ; 18.855 ; Fall ; PHI2 ; +; MAin[1] ; PHI2 ; 17.223 ; 17.223 ; Fall ; PHI2 ; +; MAin[2] ; PHI2 ; 22.057 ; 22.057 ; Fall ; PHI2 ; +; MAin[3] ; PHI2 ; 26.915 ; 26.915 ; Fall ; PHI2 ; +; MAin[4] ; PHI2 ; 22.048 ; 22.048 ; Fall ; PHI2 ; +; MAin[5] ; PHI2 ; 27.296 ; 27.296 ; Fall ; PHI2 ; +; MAin[6] ; PHI2 ; 23.411 ; 23.411 ; Fall ; PHI2 ; +; MAin[7] ; PHI2 ; 26.379 ; 26.379 ; Fall ; PHI2 ; +; nFWE ; PHI2 ; 15.594 ; 15.594 ; Fall ; PHI2 ; +; PHI2 ; RCLK ; 2.487 ; 2.487 ; Rise ; RCLK ; +; nCCAS ; RCLK ; 2.685 ; 2.685 ; Rise ; RCLK ; +; nCRAS ; RCLK ; 4.357 ; 4.357 ; Rise ; RCLK ; +; Din[*] ; nCCAS ; 0.702 ; 0.702 ; Fall ; nCCAS ; +; Din[0] ; nCCAS ; -0.028 ; -0.028 ; Fall ; nCCAS ; +; Din[1] ; nCCAS ; -1.852 ; -1.852 ; Fall ; nCCAS ; +; Din[2] ; nCCAS ; -1.623 ; -1.623 ; Fall ; nCCAS ; +; Din[3] ; nCCAS ; -1.611 ; -1.611 ; Fall ; nCCAS ; +; Din[4] ; nCCAS ; -1.202 ; -1.202 ; Fall ; nCCAS ; +; Din[5] ; nCCAS ; -1.860 ; -1.860 ; Fall ; nCCAS ; +; Din[6] ; nCCAS ; 0.702 ; 0.702 ; Fall ; nCCAS ; +; Din[7] ; nCCAS ; -1.657 ; -1.657 ; Fall ; nCCAS ; +; CROW[*] ; nCRAS ; 5.538 ; 5.538 ; Fall ; nCRAS ; +; CROW[0] ; nCRAS ; 5.538 ; 5.538 ; Fall ; nCRAS ; +; CROW[1] ; nCRAS ; 3.990 ; 3.990 ; Fall ; nCRAS ; +; MAin[*] ; nCRAS ; 5.521 ; 5.521 ; Fall ; nCRAS ; +; MAin[0] ; nCRAS ; 2.776 ; 2.776 ; Fall ; nCRAS ; +; MAin[1] ; nCRAS ; 2.635 ; 2.635 ; Fall ; nCRAS ; +; MAin[2] ; nCRAS ; 2.575 ; 2.575 ; Fall ; nCRAS ; +; MAin[3] ; nCRAS ; 1.972 ; 1.972 ; Fall ; nCRAS ; +; MAin[4] ; nCRAS ; 3.637 ; 3.637 ; Fall ; nCRAS ; +; MAin[5] ; nCRAS ; 4.180 ; 4.180 ; Fall ; nCRAS ; +; MAin[6] ; nCRAS ; 2.129 ; 2.129 ; Fall ; nCRAS ; +; MAin[7] ; nCRAS ; 5.521 ; 5.521 ; Fall ; nCRAS ; +; MAin[8] ; nCRAS ; 3.654 ; 3.654 ; Fall ; nCRAS ; +; MAin[9] ; nCRAS ; 2.363 ; 2.363 ; Fall ; nCRAS ; +; nCCAS ; nCRAS ; 3.572 ; 3.572 ; Fall ; nCRAS ; +; nFWE ; nCRAS ; 2.828 ; 2.828 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+---------+---------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+---------+---------+------------+-----------------+ +; Din[*] ; PHI2 ; 2.255 ; 2.255 ; Rise ; PHI2 ; +; Din[0] ; PHI2 ; -1.258 ; -1.258 ; Rise ; PHI2 ; +; Din[1] ; PHI2 ; -1.562 ; -1.562 ; Rise ; PHI2 ; +; Din[2] ; PHI2 ; -3.570 ; -3.570 ; Rise ; PHI2 ; +; Din[3] ; PHI2 ; -1.430 ; -1.430 ; Rise ; PHI2 ; +; Din[4] ; PHI2 ; -5.259 ; -5.259 ; Rise ; PHI2 ; +; Din[5] ; PHI2 ; -1.532 ; -1.532 ; Rise ; PHI2 ; +; Din[6] ; PHI2 ; 0.023 ; 0.023 ; Rise ; PHI2 ; +; Din[7] ; PHI2 ; 2.255 ; 2.255 ; Rise ; PHI2 ; +; Din[*] ; PHI2 ; 1.977 ; 1.977 ; Fall ; PHI2 ; +; Din[0] ; PHI2 ; 1.489 ; 1.489 ; Fall ; PHI2 ; +; Din[1] ; PHI2 ; 1.963 ; 1.963 ; Fall ; PHI2 ; +; Din[2] ; PHI2 ; 0.106 ; 0.106 ; Fall ; PHI2 ; +; Din[3] ; PHI2 ; -0.228 ; -0.228 ; Fall ; PHI2 ; +; Din[4] ; PHI2 ; 1.977 ; 1.977 ; Fall ; PHI2 ; +; Din[5] ; PHI2 ; -5.179 ; -5.179 ; Fall ; PHI2 ; +; Din[6] ; PHI2 ; -4.432 ; -4.432 ; Fall ; PHI2 ; +; Din[7] ; PHI2 ; -6.067 ; -6.067 ; Fall ; PHI2 ; +; MAin[*] ; PHI2 ; -1.458 ; -1.458 ; Fall ; PHI2 ; +; MAin[0] ; PHI2 ; -3.579 ; -3.579 ; Fall ; PHI2 ; +; MAin[1] ; PHI2 ; -1.458 ; -1.458 ; Fall ; PHI2 ; +; MAin[2] ; PHI2 ; -10.193 ; -10.193 ; Fall ; PHI2 ; +; MAin[3] ; PHI2 ; -15.051 ; -15.051 ; Fall ; PHI2 ; +; MAin[4] ; PHI2 ; -10.184 ; -10.184 ; Fall ; PHI2 ; +; MAin[5] ; PHI2 ; -15.432 ; -15.432 ; Fall ; PHI2 ; +; MAin[6] ; PHI2 ; -10.945 ; -10.945 ; Fall ; PHI2 ; +; MAin[7] ; PHI2 ; -11.673 ; -11.673 ; Fall ; PHI2 ; +; nFWE ; PHI2 ; -6.373 ; -6.373 ; Fall ; PHI2 ; +; PHI2 ; RCLK ; -2.127 ; -2.127 ; Rise ; RCLK ; +; nCCAS ; RCLK ; -2.325 ; -2.325 ; Rise ; RCLK ; +; nCRAS ; RCLK ; -3.997 ; -3.997 ; Rise ; RCLK ; +; Din[*] ; nCCAS ; 2.220 ; 2.220 ; Fall ; nCCAS ; +; Din[0] ; nCCAS ; 0.388 ; 0.388 ; Fall ; nCCAS ; +; Din[1] ; nCCAS ; 2.212 ; 2.212 ; Fall ; nCCAS ; +; Din[2] ; nCCAS ; 1.983 ; 1.983 ; Fall ; nCCAS ; +; Din[3] ; nCCAS ; 1.971 ; 1.971 ; Fall ; nCCAS ; +; Din[4] ; nCCAS ; 1.562 ; 1.562 ; Fall ; nCCAS ; +; Din[5] ; nCCAS ; 2.220 ; 2.220 ; Fall ; nCCAS ; +; Din[6] ; nCCAS ; -0.342 ; -0.342 ; Fall ; nCCAS ; +; Din[7] ; nCCAS ; 2.017 ; 2.017 ; Fall ; nCCAS ; +; CROW[*] ; nCRAS ; -3.630 ; -3.630 ; Fall ; nCRAS ; +; CROW[0] ; nCRAS ; -5.178 ; -5.178 ; Fall ; nCRAS ; +; CROW[1] ; nCRAS ; -3.630 ; -3.630 ; Fall ; nCRAS ; +; MAin[*] ; nCRAS ; -1.612 ; -1.612 ; Fall ; nCRAS ; +; MAin[0] ; nCRAS ; -2.416 ; -2.416 ; Fall ; nCRAS ; +; MAin[1] ; nCRAS ; -2.275 ; -2.275 ; Fall ; nCRAS ; +; MAin[2] ; nCRAS ; -2.215 ; -2.215 ; Fall ; nCRAS ; +; MAin[3] ; nCRAS ; -1.612 ; -1.612 ; Fall ; nCRAS ; +; MAin[4] ; nCRAS ; -3.277 ; -3.277 ; Fall ; nCRAS ; +; MAin[5] ; nCRAS ; -3.820 ; -3.820 ; Fall ; nCRAS ; +; MAin[6] ; nCRAS ; -1.769 ; -1.769 ; Fall ; nCRAS ; +; MAin[7] ; nCRAS ; -5.161 ; -5.161 ; Fall ; nCRAS ; +; MAin[8] ; nCRAS ; -3.294 ; -3.294 ; Fall ; nCRAS ; +; MAin[9] ; nCRAS ; -2.003 ; -2.003 ; Fall ; nCRAS ; +; nCCAS ; nCRAS ; -3.212 ; -3.212 ; Fall ; nCRAS ; +; nFWE ; nCRAS ; -2.468 ; -2.468 ; Fall ; nCRAS ; ++-----------+------------+---------+---------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; RA[*] ; PHI2 ; 24.450 ; 24.450 ; Rise ; PHI2 ; +; RA[11] ; PHI2 ; 24.450 ; 24.450 ; Rise ; PHI2 ; +; LED ; RCLK ; 15.471 ; 15.471 ; Rise ; RCLK ; +; RA[*] ; RCLK ; 25.685 ; 25.685 ; Rise ; RCLK ; +; RA[0] ; RCLK ; 25.623 ; 25.623 ; Rise ; RCLK ; +; RA[1] ; RCLK ; 21.305 ; 21.305 ; Rise ; RCLK ; +; RA[2] ; RCLK ; 21.360 ; 21.360 ; Rise ; RCLK ; +; RA[3] ; RCLK ; 18.901 ; 18.901 ; Rise ; RCLK ; +; RA[4] ; RCLK ; 21.634 ; 21.634 ; Rise ; RCLK ; +; RA[5] ; RCLK ; 15.577 ; 15.577 ; Rise ; RCLK ; +; RA[6] ; RCLK ; 25.685 ; 25.685 ; Rise ; RCLK ; +; RA[7] ; RCLK ; 20.958 ; 20.958 ; Rise ; RCLK ; +; RA[8] ; RCLK ; 15.905 ; 15.905 ; Rise ; RCLK ; +; RA[9] ; RCLK ; 24.925 ; 24.925 ; Rise ; RCLK ; +; RA[10] ; RCLK ; 14.506 ; 14.506 ; Rise ; RCLK ; +; RCKE ; RCLK ; 10.963 ; 10.963 ; Rise ; RCLK ; +; RDQMH ; RCLK ; 15.935 ; 15.935 ; Rise ; RCLK ; +; RDQML ; RCLK ; 15.786 ; 15.786 ; Rise ; RCLK ; +; nRCAS ; RCLK ; 8.987 ; 8.987 ; Rise ; RCLK ; +; nRCS ; RCLK ; 10.963 ; 10.963 ; Rise ; RCLK ; +; nRRAS ; RCLK ; 8.992 ; 8.992 ; Rise ; RCLK ; +; nRWE ; RCLK ; 12.898 ; 12.898 ; Rise ; RCLK ; +; RD[*] ; nCCAS ; 28.474 ; 28.474 ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 26.092 ; 26.092 ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 22.744 ; 22.744 ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 22.737 ; 22.737 ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 28.474 ; 28.474 ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 28.317 ; 28.317 ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 26.726 ; 26.726 ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.737 ; 22.737 ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 28.330 ; 28.330 ; Fall ; nCCAS ; +; LED ; nCRAS ; 19.187 ; 19.187 ; Rise ; nCRAS ; +; LED ; nCRAS ; 19.187 ; 19.187 ; Fall ; nCRAS ; +; RA[*] ; nCRAS ; 23.706 ; 23.706 ; Fall ; nCRAS ; +; RA[0] ; nCRAS ; 22.368 ; 22.368 ; Fall ; nCRAS ; +; RA[1] ; nCRAS ; 23.706 ; 23.706 ; Fall ; nCRAS ; +; RA[2] ; nCRAS ; 21.361 ; 21.361 ; Fall ; nCRAS ; +; RA[3] ; nCRAS ; 22.589 ; 22.589 ; Fall ; nCRAS ; +; RA[4] ; nCRAS ; 20.580 ; 20.580 ; Fall ; nCRAS ; +; RA[5] ; nCRAS ; 16.352 ; 16.352 ; Fall ; nCRAS ; +; RA[6] ; nCRAS ; 20.958 ; 20.958 ; Fall ; nCRAS ; +; RA[7] ; nCRAS ; 19.907 ; 19.907 ; Fall ; nCRAS ; +; RA[8] ; nCRAS ; 17.186 ; 17.186 ; Fall ; nCRAS ; +; RA[9] ; nCRAS ; 20.624 ; 20.624 ; Fall ; nCRAS ; +; RBA[*] ; nCRAS ; 15.699 ; 15.699 ; Fall ; nCRAS ; +; RBA[0] ; nCRAS ; 15.699 ; 15.699 ; Fall ; nCRAS ; +; RBA[1] ; nCRAS ; 13.728 ; 13.728 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; RA[*] ; PHI2 ; 24.450 ; 24.450 ; Rise ; PHI2 ; +; RA[11] ; PHI2 ; 24.450 ; 24.450 ; Rise ; PHI2 ; +; LED ; RCLK ; 15.471 ; 15.471 ; Rise ; RCLK ; +; RA[*] ; RCLK ; 14.506 ; 14.506 ; Rise ; RCLK ; +; RA[0] ; RCLK ; 25.623 ; 25.623 ; Rise ; RCLK ; +; RA[1] ; RCLK ; 21.305 ; 21.305 ; Rise ; RCLK ; +; RA[2] ; RCLK ; 21.360 ; 21.360 ; Rise ; RCLK ; +; RA[3] ; RCLK ; 18.901 ; 18.901 ; Rise ; RCLK ; +; RA[4] ; RCLK ; 21.634 ; 21.634 ; Rise ; RCLK ; +; RA[5] ; RCLK ; 15.577 ; 15.577 ; Rise ; RCLK ; +; RA[6] ; RCLK ; 25.685 ; 25.685 ; Rise ; RCLK ; +; RA[7] ; RCLK ; 20.958 ; 20.958 ; Rise ; RCLK ; +; RA[8] ; RCLK ; 15.905 ; 15.905 ; Rise ; RCLK ; +; RA[9] ; RCLK ; 24.925 ; 24.925 ; Rise ; RCLK ; +; RA[10] ; RCLK ; 14.506 ; 14.506 ; Rise ; RCLK ; +; RCKE ; RCLK ; 10.963 ; 10.963 ; Rise ; RCLK ; +; RDQMH ; RCLK ; 15.935 ; 15.935 ; Rise ; RCLK ; +; RDQML ; RCLK ; 15.786 ; 15.786 ; Rise ; RCLK ; +; nRCAS ; RCLK ; 8.987 ; 8.987 ; Rise ; RCLK ; +; nRCS ; RCLK ; 10.963 ; 10.963 ; Rise ; RCLK ; +; nRRAS ; RCLK ; 8.992 ; 8.992 ; Rise ; RCLK ; +; nRWE ; RCLK ; 12.898 ; 12.898 ; Rise ; RCLK ; +; RD[*] ; nCCAS ; 22.737 ; 22.737 ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 26.092 ; 26.092 ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 22.744 ; 22.744 ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 22.737 ; 22.737 ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 28.474 ; 28.474 ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 28.317 ; 28.317 ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 26.726 ; 26.726 ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.737 ; 22.737 ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 28.330 ; 28.330 ; Fall ; nCCAS ; +; LED ; nCRAS ; 19.187 ; 19.187 ; Rise ; nCRAS ; +; LED ; nCRAS ; 19.187 ; 19.187 ; Fall ; nCRAS ; +; RA[*] ; nCRAS ; 16.352 ; 16.352 ; Fall ; nCRAS ; +; RA[0] ; nCRAS ; 22.368 ; 22.368 ; Fall ; nCRAS ; +; RA[1] ; nCRAS ; 23.706 ; 23.706 ; Fall ; nCRAS ; +; RA[2] ; nCRAS ; 21.361 ; 21.361 ; Fall ; nCRAS ; +; RA[3] ; nCRAS ; 22.589 ; 22.589 ; Fall ; nCRAS ; +; RA[4] ; nCRAS ; 20.580 ; 20.580 ; Fall ; nCRAS ; +; RA[5] ; nCRAS ; 16.352 ; 16.352 ; Fall ; nCRAS ; +; RA[6] ; nCRAS ; 20.958 ; 20.958 ; Fall ; nCRAS ; +; RA[7] ; nCRAS ; 19.907 ; 19.907 ; Fall ; nCRAS ; +; RA[8] ; nCRAS ; 17.186 ; 17.186 ; Fall ; nCRAS ; +; RA[9] ; nCRAS ; 20.624 ; 20.624 ; Fall ; nCRAS ; +; RBA[*] ; nCRAS ; 13.728 ; 13.728 ; Fall ; nCRAS ; +; RBA[0] ; nCRAS ; 15.699 ; 15.699 ; Fall ; nCRAS ; +; RBA[1] ; nCRAS ; 13.728 ; 13.728 ; Fall ; nCRAS ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; MAin[0] ; RA[0] ; 17.864 ; ; ; 17.864 ; +; MAin[1] ; RA[1] ; 16.466 ; ; ; 16.466 ; +; MAin[2] ; RA[2] ; 16.451 ; ; ; 16.451 ; +; MAin[3] ; RA[3] ; 16.947 ; ; ; 16.947 ; +; MAin[4] ; RA[4] ; 17.984 ; ; ; 17.984 ; +; MAin[5] ; RA[5] ; 14.301 ; ; ; 14.301 ; +; MAin[6] ; RA[6] ; 18.987 ; ; ; 18.987 ; +; MAin[7] ; RA[7] ; 19.195 ; ; ; 19.195 ; +; MAin[8] ; RA[8] ; 14.224 ; ; ; 14.224 ; +; MAin[9] ; RA[9] ; 15.902 ; ; ; 15.902 ; +; MAin[9] ; RDQMH ; 17.747 ; ; ; 17.747 ; +; MAin[9] ; RDQML ; 17.598 ; ; ; 17.598 ; +; RD[0] ; Dout[0] ; 10.392 ; ; ; 10.392 ; +; RD[1] ; Dout[1] ; 12.469 ; ; ; 12.469 ; +; RD[2] ; Dout[2] ; 10.547 ; ; ; 10.547 ; +; RD[3] ; Dout[3] ; 12.366 ; ; ; 12.366 ; +; RD[4] ; Dout[4] ; 12.337 ; ; ; 12.337 ; +; RD[5] ; Dout[5] ; 12.176 ; ; ; 12.176 ; +; RD[6] ; Dout[6] ; 10.385 ; ; ; 10.385 ; +; RD[7] ; Dout[7] ; 12.251 ; ; ; 12.251 ; +; nFWE ; RD[0] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[1] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[2] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[3] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[4] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[5] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[6] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[7] ; 24.642 ; ; ; 24.642 ; ++------------+-------------+--------+----+----+--------+ + + ++------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; MAin[0] ; RA[0] ; 17.864 ; ; ; 17.864 ; +; MAin[1] ; RA[1] ; 16.466 ; ; ; 16.466 ; +; MAin[2] ; RA[2] ; 16.451 ; ; ; 16.451 ; +; MAin[3] ; RA[3] ; 16.947 ; ; ; 16.947 ; +; MAin[4] ; RA[4] ; 17.984 ; ; ; 17.984 ; +; MAin[5] ; RA[5] ; 14.301 ; ; ; 14.301 ; +; MAin[6] ; RA[6] ; 18.987 ; ; ; 18.987 ; +; MAin[7] ; RA[7] ; 19.195 ; ; ; 19.195 ; +; MAin[8] ; RA[8] ; 14.224 ; ; ; 14.224 ; +; MAin[9] ; RA[9] ; 15.902 ; ; ; 15.902 ; +; MAin[9] ; RDQMH ; 17.747 ; ; ; 17.747 ; +; MAin[9] ; RDQML ; 17.598 ; ; ; 17.598 ; +; RD[0] ; Dout[0] ; 10.392 ; ; ; 10.392 ; +; RD[1] ; Dout[1] ; 12.469 ; ; ; 12.469 ; +; RD[2] ; Dout[2] ; 10.547 ; ; ; 10.547 ; +; RD[3] ; Dout[3] ; 12.366 ; ; ; 12.366 ; +; RD[4] ; Dout[4] ; 12.337 ; ; ; 12.337 ; +; RD[5] ; Dout[5] ; 12.176 ; ; ; 12.176 ; +; RD[6] ; Dout[6] ; 10.385 ; ; ; 10.385 ; +; RD[7] ; Dout[7] ; 12.251 ; ; ; 12.251 ; +; nFWE ; RD[0] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[1] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[2] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[3] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[4] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[5] ; 22.824 ; ; ; 22.824 ; +; nFWE ; RD[6] ; 24.642 ; ; ; 24.642 ; +; nFWE ; RD[7] ; 24.642 ; ; ; 24.642 ; ++------------+-------------+--------+----+----+--------+ + + ++-----------------------------------------------------------------------+ +; Output Enable Times ; ++-----------+------------+--------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+------+------------+-----------------+ +; RD[*] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; ++-----------+------------+--------+------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+--------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+------+------------+-----------------+ +; RD[*] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; ++-----------+------------+--------+------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; RD[*] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; RD[*] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Rise ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Rise ; nCCAS ; +; RD[*] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[0] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[1] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[2] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[3] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[4] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[5] ; nCCAS ; 20.845 ; ; Fall ; nCCAS ; +; RD[6] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; +; RD[7] ; nCCAS ; 22.663 ; ; Fall ; nCCAS ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 31 ; 31 ; +; Unconstrained Input Port Paths ; 232 ; 232 ; +; Unconstrained Output Ports ; 38 ; 38 ; +; Unconstrained Output Port Paths ; 77 ; 77 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Mon Aug 16 18:40:23 2021 +Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name DRCLK DRCLK + Info (332105): create_clock -period 1.000 -name ARCLK ARCLK + Info (332105): create_clock -period 1.000 -name RCLK RCLK + Info (332105): create_clock -period 1.000 -name nCRAS nCRAS + Info (332105): create_clock -period 1.000 -name PHI2 PHI2 + Info (332105): create_clock -period 1.000 -name nCCAS nCCAS +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -99.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -99.000 -99.000 ARCLK + Info (332119): -99.000 -99.000 DRCLK + Info (332119): -23.638 -216.621 PHI2 + Info (332119): -19.942 -610.547 RCLK + Info (332119): -3.072 -6.479 nCRAS +Info (332146): Worst-case hold slack is -16.153 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -16.153 -16.153 ARCLK + Info (332119): -14.623 -14.623 DRCLK + Info (332119): -2.569 -3.433 PHI2 + Info (332119): -0.713 -2.822 nCRAS + Info (332119): 2.127 0.000 RCLK +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -29.500 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -29.500 -59.000 ARCLK + Info (332119): -29.500 -59.000 DRCLK + Info (332119): -2.289 -2.289 PHI2 + Info (332119): -2.289 -2.289 RCLK + Info (332119): -2.289 -2.289 nCCAS + Info (332119): -2.289 -2.289 nCRAS +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 368 megabytes + Info: Processing ended: Mon Aug 16 18:40:24 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CPLD/AGM-src/output_files/RAM4GS.sta.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary old mode 100755 new mode 100644 similarity index 78% rename from CPLD/AGM-src/output_files/RAM4GS.sta.summary rename to CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary index a4c9ebf..44e8308 --- a/CPLD/AGM-src/output_files/RAM4GS.sta.summary +++ b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary @@ -11,36 +11,36 @@ Slack : -99.000 TNS : -99.000 Type : Setup 'PHI2' -Slack : -9.292 -TNS : -92.804 +Slack : -23.638 +TNS : -216.621 Type : Setup 'RCLK' -Slack : -8.365 -TNS : -253.063 +Slack : -19.942 +TNS : -610.547 Type : Setup 'nCRAS' -Slack : -0.490 -TNS : -0.577 - -Type : Hold 'DRCLK' -Slack : -16.306 -TNS : -16.306 +Slack : -3.072 +TNS : -6.479 Type : Hold 'ARCLK' -Slack : -16.272 -TNS : -16.272 +Slack : -16.153 +TNS : -16.153 -Type : Hold 'RCLK' -Slack : -0.874 -TNS : -0.874 +Type : Hold 'DRCLK' +Slack : -14.623 +TNS : -14.623 Type : Hold 'PHI2' -Slack : -0.396 -TNS : -0.396 +Slack : -2.569 +TNS : -3.433 Type : Hold 'nCRAS' -Slack : -0.125 -TNS : -0.125 +Slack : -0.713 +TNS : -2.822 + +Type : Hold 'RCLK' +Slack : 2.127 +TNS : 0.000 Type : Minimum Pulse Width 'ARCLK' Slack : -29.500 diff --git a/CPLD/AGM-src/RAM4GS.mif b/CPLD/MAX/RAM2GS-MAX.mif old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/RAM4GS.mif rename to CPLD/MAX/RAM2GS-MAX.mif diff --git a/CPLD/RAM4GS-MAX.v b/CPLD/MAX/RAM2GS-MAX.v old mode 100755 new mode 100644 similarity index 99% rename from CPLD/RAM4GS-MAX.v rename to CPLD/MAX/RAM2GS-MAX.v index 3969024..8be9f35 --- a/CPLD/RAM4GS-MAX.v +++ b/CPLD/MAX/RAM2GS-MAX.v @@ -56,7 +56,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ; /* UFM Interface */ - reg [15] UFMD = 0; // UFM data register bit 15 + reg [15:15] UFMD = 0; // UFM data register bit 15 reg ARCLK = 0; // UFM address register clock // UFM address register data input tied to 0 reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment diff --git a/CPLD/AGM-src/output_files/UFM.qip b/CPLD/MAX/UFM.qip old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/output_files/UFM.qip rename to CPLD/MAX/UFM.qip diff --git a/CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt b/CPLD/MAX/greybox_tmp/cbx_args.txt old mode 100755 new mode 100644 similarity index 78% rename from CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt rename to CPLD/MAX/greybox_tmp/cbx_args.txt index e714d49..941c71c --- a/CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt +++ b/CPLD/MAX/greybox_tmp/cbx_args.txt @@ -1,6 +1,6 @@ ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=RAM4GS.mif +INTENDED_DEVICE_FAMILY="MAX V" +LPM_FILE=RAM2GS-MAX.mif LPM_HINT=UNUSED LPM_TYPE=altufm_none OSC_FREQUENCY=180000 @@ -8,7 +8,7 @@ PORT_ARCLKENA=PORT_UNUSED PORT_DRCLKENA=PORT_UNUSED PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" +DEVICE_FAMILY="MAX V" CBX_AUTO_BLACKBOX=ALL arclk ardin diff --git a/CPLD/MAXII/RAM4GS.mif b/CPLD/MAXII/RAM4GS.mif deleted file mode 100755 index 65c8441..0000000 --- a/CPLD/MAXII/RAM4GS.mif +++ /dev/null @@ -1,27 +0,0 @@ --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - --- Quartus II generated Memory Initialization File (.mif) - -WIDTH=16; -DEPTH=512; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - [000..0FD] : 0000; - 0FE : 7FFF; - [0FF..1FF] : FFFF; -END; diff --git a/CPLD/MAXII/constraints.sdc b/CPLD/MAXII/constraints.sdc deleted file mode 100755 index e69de29..0000000 diff --git a/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb deleted file mode 100755 index a80855d..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb deleted file mode 100755 index 1a1481b..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb deleted file mode 100755 index 84cfd7b..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb deleted file mode 100755 index 10dc2d1..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb deleted file mode 100755 index bf025da..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb deleted file mode 100755 index 7121330..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.asm.qmsg b/CPLD/MAXII/db/RAM4GS.asm.qmsg deleted file mode 100755 index 4989b11..0000000 --- a/CPLD/MAXII/db/RAM4GS.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""} diff --git a/CPLD/MAXII/db/RAM4GS.asm.rdb b/CPLD/MAXII/db/RAM4GS.asm.rdb deleted file mode 100755 index 57f2d3d..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.asm.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.asm_labs.ddb b/CPLD/MAXII/db/RAM4GS.asm_labs.ddb deleted file mode 100755 index c9b3243..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.asm_labs.ddb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.cdb b/CPLD/MAXII/db/RAM4GS.cmp.cdb deleted file mode 100755 index 660f5e1..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.hdb b/CPLD/MAXII/db/RAM4GS.cmp.hdb deleted file mode 100755 index 27f7c43..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.idb b/CPLD/MAXII/db/RAM4GS.cmp.idb deleted file mode 100755 index e91cbcb..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp.idb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.kpt b/CPLD/MAXII/db/RAM4GS.cmp.kpt deleted file mode 100755 index 29f003a..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp.kpt and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp.rdb b/CPLD/MAXII/db/RAM4GS.cmp.rdb deleted file mode 100755 index 8974ee5..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.cmp0.ddb b/CPLD/MAXII/db/RAM4GS.cmp0.ddb deleted file mode 100755 index db1bbdb..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.cmp0.ddb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.fit.qmsg b/CPLD/MAXII/db/RAM4GS.fit.qmsg deleted file mode 100755 index f7f2a6b..0000000 --- a/CPLD/MAXII/db/RAM4GS.fit.qmsg +++ /dev/null @@ -1,43 +0,0 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""} diff --git a/CPLD/MAXII/db/RAM4GS.hif b/CPLD/MAXII/db/RAM4GS.hif deleted file mode 100755 index 662d74f..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.hif and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.ipinfo b/CPLD/MAXII/db/RAM4GS.ipinfo deleted file mode 100755 index 482f1be..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.ipinfo and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.lpc.rdb b/CPLD/MAXII/db/RAM4GS.lpc.rdb deleted file mode 100755 index 2c939fb..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.lpc.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.map.cdb b/CPLD/MAXII/db/RAM4GS.map.cdb deleted file mode 100755 index ca0a971..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.map.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.map.hdb b/CPLD/MAXII/db/RAM4GS.map.hdb deleted file mode 100755 index 8ae41d2..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.map.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.map.qmsg b/CPLD/MAXII/db/RAM4GS.map.qmsg deleted file mode 100755 index 543433e..0000000 --- a/CPLD/MAXII/db/RAM4GS.map.qmsg +++ /dev/null @@ -1,26 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} diff --git a/CPLD/MAXII/db/RAM4GS.map.rdb b/CPLD/MAXII/db/RAM4GS.map.rdb deleted file mode 100755 index d27105c..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.map.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.pre_map.hdb b/CPLD/MAXII/db/RAM4GS.pre_map.hdb deleted file mode 100755 index 6f71689..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.pre_map.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.qns b/CPLD/MAXII/db/RAM4GS.qns deleted file mode 100755 index ef67c3e..0000000 --- a/CPLD/MAXII/db/RAM4GS.qns +++ /dev/null @@ -1 +0,0 @@ -RAM4GS/done diff --git a/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb b/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb deleted file mode 100755 index a7aa640..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.routing.rdb b/CPLD/MAXII/db/RAM4GS.routing.rdb deleted file mode 100755 index a1beb78..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.routing.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.rtlv.hdb b/CPLD/MAXII/db/RAM4GS.rtlv.hdb deleted file mode 100755 index 802d93c..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.rtlv.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb deleted file mode 100755 index 30b67ca..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb deleted file mode 100755 index e318de4..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.sgdiff.cdb b/CPLD/MAXII/db/RAM4GS.sgdiff.cdb deleted file mode 100755 index 2d31b44..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.sgdiff.cdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.sgdiff.hdb b/CPLD/MAXII/db/RAM4GS.sgdiff.hdb deleted file mode 100755 index 18597e6..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.sgdiff.hdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.sta.qmsg b/CPLD/MAXII/db/RAM4GS.sta.qmsg deleted file mode 100755 index e020392..0000000 --- a/CPLD/MAXII/db/RAM4GS.sta.qmsg +++ /dev/null @@ -1,23 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} diff --git a/CPLD/MAXII/db/RAM4GS.sta.rdb b/CPLD/MAXII/db/RAM4GS.sta.rdb deleted file mode 100755 index 25f87ad..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.sta.rdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb deleted file mode 100755 index 8b39503..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb and /dev/null differ diff --git a/CPLD/MAXII/db/RAM4GS.syn_hier_info b/CPLD/MAXII/db/RAM4GS.syn_hier_info deleted file mode 100755 index e69de29..0000000 diff --git a/CPLD/MAXII/db/RAM4GS.vpr.ammdb b/CPLD/MAXII/db/RAM4GS.vpr.ammdb deleted file mode 100755 index 2acc82b..0000000 Binary files a/CPLD/MAXII/db/RAM4GS.vpr.ammdb and /dev/null differ diff --git a/CPLD/MAXII/db/logic_util_heursitic.dat b/CPLD/MAXII/db/logic_util_heursitic.dat deleted file mode 100755 index c3752a7..0000000 Binary files a/CPLD/MAXII/db/logic_util_heursitic.dat and /dev/null differ diff --git a/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg b/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg deleted file mode 100755 index 715eafe..0000000 --- a/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg +++ /dev/null @@ -1,106 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""} diff --git a/CPLD/MAXII/greybox_tmp/cbx_args.txt b/CPLD/MAXII/greybox_tmp/cbx_args.txt deleted file mode 100755 index b32fb07..0000000 --- a/CPLD/MAXII/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,26 +0,0 @@ -ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=RAM4GS.mif -LPM_HINT=UNUSED -LPM_TYPE=altufm_none -OSC_FREQUENCY=180000 -PORT_ARCLKENA=PORT_UNUSED -PORT_DRCLKENA=PORT_UNUSED -PROGRAM_TIME=1600000 -WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" -CBX_AUTO_BLACKBOX=ALL -CBX_AUTO_BLACKBOX=ALL -arclk -ardin -arshft -busy -drclk -drdin -drdout -drshft -erase -osc -oscena -program -rtpbusy diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt deleted file mode 100755 index 4a04335..0000000 Binary files a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt and /dev/null differ diff --git a/CPLD/MAXII/output_files/RAM4GS.cdf b/CPLD/MAXII/output_files/RAM4GS.cdf deleted file mode 100755 index 43f46dc..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/CPLD/MAXII/output_files/RAM4GS.done b/CPLD/MAXII/output_files/RAM4GS.done deleted file mode 100755 index d7b20f4..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.done +++ /dev/null @@ -1 +0,0 @@ -Thu Jul 23 02:21:03 2020 diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.summary b/CPLD/MAXII/output_files/RAM4GS.fit.summary deleted file mode 100755 index 530787c..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.fit.summary +++ /dev/null @@ -1,11 +0,0 @@ -Fitter Status : Successful - Thu Jul 23 02:20:50 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Device : EPM240T100C5 -Timing Models : Final -Total logic elements : 170 / 240 ( 71 % ) -Total pins : 62 / 80 ( 78 % ) -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM4GS.jdi b/CPLD/MAXII/output_files/RAM4GS.jdi deleted file mode 100755 index 85a8d49..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/MAXII/output_files/RAM4GS.map.summary b/CPLD/MAXII/output_files/RAM4GS.map.summary deleted file mode 100755 index 56e671c..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.map.summary +++ /dev/null @@ -1,9 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Total logic elements : 178 -Total pins : 62 -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM4GS.pof b/CPLD/MAXII/output_files/RAM4GS.pof deleted file mode 100755 index a168b2e..0000000 Binary files a/CPLD/MAXII/output_files/RAM4GS.pof and /dev/null differ diff --git a/CPLD/MAXII/output_files/RAM4GS.sta.rpt b/CPLD/MAXII/output_files/RAM4GS.sta.rpt deleted file mode 100755 index 6462353..0000000 --- a/CPLD/MAXII/output_files/RAM4GS.sta.rpt +++ /dev/null @@ -1,1588 +0,0 @@ -TimeQuest Timing Analyzer report for RAM4GS -Thu Jul 23 02:21:02 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Fmax Summary - 7. Setup Summary - 8. Hold Summary - 9. Recovery Summary - 10. Removal Summary - 11. Minimum Pulse Width Summary - 12. Setup: 'ARCLK' - 13. Setup: 'DRCLK' - 14. Setup: 'PHI2' - 15. Setup: 'RCLK' - 16. Setup: 'nCRAS' - 17. Hold: 'DRCLK' - 18. Hold: 'ARCLK' - 19. Hold: 'RCLK' - 20. Hold: 'PHI2' - 21. Hold: 'nCRAS' - 22. Minimum Pulse Width: 'ARCLK' - 23. Minimum Pulse Width: 'DRCLK' - 24. Minimum Pulse Width: 'PHI2' - 25. Minimum Pulse Width: 'RCLK' - 26. Minimum Pulse Width: 'nCCAS' - 27. Minimum Pulse Width: 'nCRAS' - 28. Setup Times - 29. Hold Times - 30. Clock to Output Times - 31. Minimum Clock to Output Times - 32. Propagation Delay - 33. Minimum Propagation Delay - 34. Output Enable Times - 35. Minimum Output Enable Times - 36. Output Disable Times - 37. Minimum Output Disable Times - 38. Setup Transfers - 39. Hold Transfers - 40. Report TCCS - 41. Report RSKM - 42. Unconstrained Paths - 43. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+--------------------+-------------------------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; < 0.1% ; -+----------------------------+-------------+ - - -+-----------------------------------------------------+ -; SDC File List ; -+-----------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+-----------------+--------+--------------------------+ -; constraints.sdc ; OK ; Thu Jul 23 02:21:01 2020 ; -+-----------------+--------+--------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; -; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; -; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; -; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; -; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; -; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ - - -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 51.06 MHz ; 51.06 MHz ; PHI2 ; ; -; 128.87 MHz ; 128.87 MHz ; RCLK ; ; -+------------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+---------------------------------+ -; Setup Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -99.000 ; -99.000 ; -; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -9.292 ; -92.804 ; -; RCLK ; -8.365 ; -253.063 ; -; nCRAS ; -0.490 ; -0.577 ; -+-------+---------+---------------+ - - -+---------------------------------+ -; Hold Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; DRCLK ; -16.306 ; -16.306 ; -; ARCLK ; -16.272 ; -16.272 ; -; RCLK ; -0.874 ; -0.874 ; -; PHI2 ; -0.396 ; -0.396 ; -; nCRAS ; -0.125 ; -0.125 ; -+-------+---------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+---------------------------------+ -; Minimum Pulse Width Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -29.500 ; -59.000 ; -; DRCLK ; -29.500 ; -59.000 ; -; PHI2 ; -2.289 ; -2.289 ; -; RCLK ; -2.289 ; -2.289 ; -; nCCAS ; -2.289 ; -2.289 ; -; nCRAS ; -2.289 ; -2.289 ; -+-------+---------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.728 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.715 ; 2.013 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.549 ; -; -22.694 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.529 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Setup: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -9.292 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.121 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.288 ; -; -8.996 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.163 ; -; -8.949 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.857 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.024 ; -; -8.778 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.653 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.594 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.761 ; -; -8.514 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.300 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.467 ; -; -8.289 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.456 ; -; -8.251 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.118 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.285 ; -; -8.084 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.251 ; -; -8.043 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.210 ; -; -7.993 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.160 ; -; -7.957 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.872 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.039 ; -; -7.854 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.021 ; -; -7.799 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.966 ; -; -7.747 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.914 ; -; -7.741 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.608 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.775 ; -; -7.591 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.758 ; -; -7.456 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.345 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.512 ; -; -7.297 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.464 ; -; -7.205 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.372 ; -; -7.081 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.248 ; -; -7.051 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.218 ; -; -7.034 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.201 ; -; -6.909 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.076 ; -; -6.870 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.870 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.835 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.002 ; -; -6.796 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.963 ; -; -6.770 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.937 ; -; -6.745 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.912 ; -; -6.699 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.699 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.574 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.550 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.717 ; -; -6.507 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.674 ; -; -6.449 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.616 ; -; -6.435 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.435 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.310 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.477 ; -; -6.213 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.380 ; -; -6.172 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.172 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.047 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.214 ; -; -5.997 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.164 ; -; -5.878 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.878 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.753 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.920 ; -; -5.712 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.879 ; -; -5.662 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.662 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.537 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.704 ; -; -5.377 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.377 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.252 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.419 ; -; -5.004 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.671 ; -; -4.046 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.040 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.707 ; -; -4.001 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.668 ; -; -3.752 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.419 ; -; -3.694 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.861 ; -; -3.585 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.252 ; -; -2.929 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.596 ; -; -2.917 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.584 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; -8.365 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -8.365 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -7.591 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 5.180 ; -; -7.130 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.719 ; -; -7.061 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.650 ; -; -7.017 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.986 ; -; -6.760 ; FS[5] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.760 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.691 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.280 ; -; -6.669 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.258 ; -; -6.664 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.633 ; -; -6.612 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.612 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.588 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.255 ; -; -6.574 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.163 ; -; -6.549 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.549 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.526 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.115 ; -; -6.502 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.502 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.501 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.168 ; -; -6.482 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.149 ; -; -6.401 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.068 ; -; -6.399 ; FS[4] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.399 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.395 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.062 ; -; -6.380 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.047 ; -; -6.328 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.297 ; -; -6.258 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.847 ; -; -6.256 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.923 ; -; -6.253 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.920 ; -; -6.232 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.899 ; -; -6.198 ; FS[6] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.198 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.193 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.860 ; -; -6.190 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.857 ; -; -6.169 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ; -; -6.146 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.813 ; -; -6.143 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.810 ; -; -6.122 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.789 ; -; -6.070 ; UFMInitDone ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.070 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.044 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.633 ; -; -6.040 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.707 ; -; -6.032 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.699 ; -; -6.028 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.695 ; -; -6.022 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.689 ; -; -6.019 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.686 ; -; -5.996 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.585 ; -; -5.959 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.626 ; -; -5.958 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.625 ; -; -5.954 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.621 ; -; -5.949 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 2.918 ; -; -5.942 ; UFMReqErase ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.609 ; -; -5.915 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.582 ; -; -5.912 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.579 ; -; -5.852 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.852 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.839 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.506 ; -; -5.835 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.502 ; -; -5.818 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.485 ; -; -5.805 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.472 ; -; -5.739 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.406 ; -; -5.733 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 2.165 ; 8.565 ; -; -5.720 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.387 ; -; -5.714 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.381 ; -; -5.711 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.711 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.690 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.357 ; -; -5.688 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.355 ; -; -5.666 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ; -; -5.656 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.323 ; -; -5.596 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.263 ; -; -5.579 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.246 ; -; -5.563 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.230 ; -; -5.549 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.216 ; -; -5.503 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.170 ; -; -5.500 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.167 ; -; -5.487 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.154 ; -; -5.480 ; UFMInitDone ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.147 ; -; -5.479 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.146 ; -; -5.459 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.126 ; -; -5.453 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.120 ; -; -5.425 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.092 ; -; -5.420 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.087 ; -; -5.397 ; IS[2] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.064 ; -; -5.373 ; UFMInitDone ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.040 ; -; -5.363 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.030 ; -; -5.350 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.017 ; -; -5.345 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.345 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.333 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.000 ; -; -5.312 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.312 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.290 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.957 ; -; -5.267 ; FS[3] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.934 ; -; -5.230 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.230 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.208 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.875 ; -; -5.206 ; IS[3] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.873 ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Setup: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.490 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 3.235 ; -; -0.087 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.832 ; -; 0.071 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.926 ; 6.022 ; -; 0.079 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.666 ; -; 0.080 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.665 ; -; 0.081 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.664 ; -; 0.082 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.663 ; -; 0.084 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.661 ; -; 0.091 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.654 ; -; 0.095 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.650 ; -; 0.099 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.646 ; -; 0.104 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.641 ; -; 0.105 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.640 ; -; 0.571 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.926 ; 6.022 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.306 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.529 ; -; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.549 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.272 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.715 ; 2.013 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Hold: 'RCLK' ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.874 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 3.348 ; 3.071 ; -; -0.374 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 3.348 ; 3.071 ; -; 1.192 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.761 ; -; 1.264 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.833 ; -; 1.344 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.913 ; -; 1.400 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.621 ; -; 1.642 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.863 ; -; 1.670 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.891 ; -; 1.692 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.761 ; -; 1.695 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.916 ; -; 1.703 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.924 ; -; 1.706 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.927 ; -; 1.764 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.833 ; -; 1.844 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.913 ; -; 1.899 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.120 ; -; 1.948 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.169 ; -; 1.959 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.180 ; -; 1.976 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.197 ; -; 1.983 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.204 ; -; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; -; 2.117 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; -; 2.135 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.135 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.358 ; -; 2.141 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.362 ; -; 2.153 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.374 ; -; 2.212 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.433 ; -; 2.221 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.230 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.233 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.292 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.513 ; -; 2.332 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.553 ; -; 2.363 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.584 ; -; 2.380 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.601 ; -; 2.407 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.628 ; -; 2.522 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.743 ; -; 2.530 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.751 ; -; 2.542 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.763 ; -; 2.577 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.798 ; -; 2.582 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.803 ; -; 2.593 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.814 ; -; 2.615 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.836 ; -; 2.622 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.843 ; -; 2.837 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.058 ; -; 2.885 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.106 ; -; 2.912 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.133 ; -; 2.913 ; PHI2r3 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.134 ; -; 2.936 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.157 ; -; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; -; 2.949 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.178 ; -; 2.967 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ; -; 2.969 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.190 ; -; 3.028 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.249 ; -; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; -; 3.060 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.066 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.287 ; -; 3.068 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.289 ; -; 3.078 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.299 ; -; 3.109 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.330 ; -; 3.130 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.351 ; -; 3.159 ; S[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.380 ; -; 3.161 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.161 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.162 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.383 ; -; 3.170 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.179 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; -; 3.184 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; -; 3.241 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.462 ; -; 3.277 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.498 ; -; 3.281 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.282 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.289 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.289 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.290 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; -; 3.296 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.517 ; -; 3.306 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.527 ; -; 3.324 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.545 ; -; 3.328 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.549 ; -; 3.381 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.602 ; -; 3.383 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.604 ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Hold: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.396 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.023 ; -; 0.072 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.198 ; 2.991 ; -; 0.129 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.548 ; -; 1.927 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.148 ; -; 2.681 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.902 ; -; 3.162 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.383 ; -; 3.363 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.584 ; -; 3.375 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.596 ; -; 3.825 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.546 ; -; 4.031 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.252 ; -; 4.110 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.831 ; -; 4.140 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.861 ; -; 4.198 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.419 ; -; 4.265 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.986 ; -; 4.326 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.047 ; -; 4.447 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.668 ; -; 4.486 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.707 ; -; 4.492 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.550 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.271 ; -; 4.620 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.341 ; -; 4.766 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.487 ; -; 4.883 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.604 ; -; 5.022 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.743 ; -; 5.060 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.781 ; -; 5.064 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.785 ; -; 5.147 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.868 ; -; 5.318 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.039 ; -; 5.323 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.044 ; -; 5.349 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.070 ; -; 5.450 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.671 ; -; 5.462 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.183 ; -; 5.519 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.240 ; -; 5.565 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.286 ; -; 5.587 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.308 ; -; 5.758 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.479 ; -; 5.804 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.525 ; -; 5.859 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.580 ; -; 6.020 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.741 ; -; 6.122 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.843 ; -; 6.158 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.879 ; -; 6.261 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.982 ; -; 6.314 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.035 ; -; 6.386 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.107 ; -; 6.443 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.164 ; -; 6.557 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.278 ; -; 6.577 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.298 ; -; 6.659 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.380 ; -; 6.716 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.437 ; -; 6.841 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.562 ; -; 6.953 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.674 ; -; 7.012 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.733 ; -; 7.216 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.937 ; -; 7.242 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.963 ; -; 7.355 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.076 ; -; 7.480 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.201 ; -; 7.527 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.248 ; -; 7.651 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.372 ; -; 7.743 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.464 ; -; 7.902 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 8.037 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.758 ; -; 8.187 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.245 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.966 ; -; 8.300 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.021 ; -; 8.403 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.439 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.160 ; -; 8.530 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.251 ; -; 8.564 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.285 ; -; 8.697 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.735 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.456 ; -; 8.746 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.467 ; -; 8.960 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 9.040 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.761 ; -; 9.099 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.224 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.303 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.024 ; -; 9.395 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.116 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.125 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.926 ; 6.022 ; -; 0.341 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.640 ; -; 0.342 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.641 ; -; 0.347 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.646 ; -; 0.351 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.650 ; -; 0.355 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.654 ; -; 0.362 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.661 ; -; 0.364 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.663 ; -; 0.365 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.664 ; -; 0.366 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.665 ; -; 0.367 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.666 ; -; 0.375 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.926 ; 6.022 ; -; 0.533 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.832 ; -; 0.936 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 3.235 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'ARCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'DRCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI2' ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI2 ; Rise ; PHI2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'RCLK' ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; RCLK ; Rise ; RCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; nRCAS~reg0 ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCCAS' ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCCAS ; Rise ; nCCAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCRAS' ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCRAS ; Rise ; nCRAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.100 ; 0.100 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.099 ; 0.099 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.187 ; 0.187 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.377 ; 0.377 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.181 ; 0.181 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.431 ; 0.431 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; -0.141 ; -0.141 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; 6.507 ; 6.507 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 5.653 ; 5.653 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; 6.225 ; 6.225 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; 6.476 ; 6.476 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 5.332 ; 5.332 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; 5.239 ; 5.239 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; 5.246 ; 5.246 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 4.152 ; 4.152 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; 4.051 ; 4.051 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; 6.688 ; 6.688 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; 7.040 ; 7.040 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; 5.984 ; 5.984 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; 4.702 ; 4.702 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; 4.845 ; 4.845 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; 5.436 ; 5.436 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; 1.898 ; 1.898 ; Rise ; RCLK ; -; nCCAS ; RCLK ; 1.746 ; 1.746 ; Rise ; RCLK ; -; nCRAS ; RCLK ; 1.818 ; 1.818 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; -0.572 ; -0.572 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; -0.490 ; -0.490 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; -0.295 ; -0.295 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; -0.561 ; -0.561 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.097 ; 0.097 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; -0.478 ; -0.478 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; -0.222 ; -0.222 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; 1.618 ; 1.618 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; -0.639 ; -0.639 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.450 ; 0.450 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; -0.345 ; -0.345 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; -0.391 ; -0.391 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; -0.178 ; -0.178 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; -0.439 ; -0.439 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; -1.067 ; -1.067 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; -0.425 ; -0.425 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; -0.474 ; -0.474 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.429 ; 0.429 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; 2.878 ; 2.878 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.454 ; 0.454 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.455 ; 0.455 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.367 ; 0.367 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.177 ; 0.177 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.373 ; 0.373 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.123 ; 0.123 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; 0.695 ; 0.695 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; -0.378 ; -0.378 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 0.138 ; 0.138 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; -0.365 ; -0.365 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; -0.419 ; -0.419 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; -1.686 ; -1.686 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; -1.080 ; -1.080 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; -1.052 ; -1.052 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; -0.027 ; -0.027 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; -2.640 ; -2.640 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; -3.223 ; -3.223 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; -2.992 ; -2.992 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; -1.936 ; -1.936 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; -0.564 ; -0.564 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; -0.704 ; -0.704 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; -0.462 ; -0.462 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; -1.344 ; -1.344 ; Rise ; RCLK ; -; nCCAS ; RCLK ; -1.192 ; -1.192 ; Rise ; RCLK ; -; nCRAS ; RCLK ; -1.264 ; -1.264 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; 1.044 ; 1.044 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; 0.849 ; 0.849 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; 1.115 ; 1.115 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.457 ; 0.457 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.211 ; 0.211 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; 1.032 ; 1.032 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; 0.776 ; 0.776 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; -1.317 ; -1.317 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; 1.193 ; 1.193 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.104 ; 0.104 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; 0.899 ; 0.899 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.033 ; 0.033 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; 0.945 ; 0.945 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; 0.732 ; 0.732 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; 0.993 ; 0.993 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; 0.979 ; 0.979 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; 1.028 ; 1.028 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.125 ; 0.125 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; -2.324 ; -2.324 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+------------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+-----------------------------------------------------------------------+ -; Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Minimum Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 30 ; 30 ; -; Unconstrained Input Port Paths ; 231 ; 231 ; -; Unconstrained Output Ports ; 37 ; 37 ; -; Unconstrained Output Port Paths ; 75 ; 75 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:57 2020 -Info: Command: quartus_sta RAM4GS -c RAM4GS -Info: qsta_default_script.tcl version: #1 -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (306004): Started post-fitting delay annotation -Info (306005): Delay annotation completed successfully -Info (332104): Reading SDC File: 'constraints.sdc' -Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name DRCLK DRCLK - Info (332105): create_clock -period 1.000 -name ARCLK ARCLK - Info (332105): create_clock -period 1.000 -name RCLK RCLK - Info (332105): create_clock -period 1.000 -name nCRAS nCRAS - Info (332105): create_clock -period 1.000 -name PHI2 PHI2 - Info (332105): create_clock -period 1.000 -name nCCAS nCCAS -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -99.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -99.000 -99.000 ARCLK - Info (332119): -99.000 -99.000 DRCLK - Info (332119): -9.292 -92.804 PHI2 - Info (332119): -8.365 -253.063 RCLK - Info (332119): -0.490 -0.577 nCRAS -Info (332146): Worst-case hold slack is -16.306 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -16.306 -16.306 DRCLK - Info (332119): -16.272 -16.272 ARCLK - Info (332119): -0.874 -0.874 RCLK - Info (332119): -0.396 -0.396 PHI2 - Info (332119): -0.125 -0.125 nCRAS -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -29.500 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -29.500 -59.000 ARCLK - Info (332119): -29.500 -59.000 DRCLK - Info (332119): -2.289 -2.289 PHI2 - Info (332119): -2.289 -2.289 RCLK - Info (332119): -2.289 -2.289 nCCAS - Info (332119): -2.289 -2.289 nCRAS -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 288 megabytes - Info: Processing ended: Thu Jul 23 02:21:02 2020 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 - - diff --git a/CPLD/MAXII/output_files/UFM.qip b/CPLD/MAXII/output_files/UFM.qip deleted file mode 100755 index e69de29..0000000 diff --git a/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt b/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt deleted file mode 100755 index e714d49..0000000 --- a/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,25 +0,0 @@ -ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=RAM4GS.mif -LPM_HINT=UNUSED -LPM_TYPE=altufm_none -OSC_FREQUENCY=180000 -PORT_ARCLKENA=PORT_UNUSED -PORT_DRCLKENA=PORT_UNUSED -PROGRAM_TIME=1600000 -WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" -CBX_AUTO_BLACKBOX=ALL -arclk -ardin -arshft -busy -drclk -drdin -drdout -drshft -erase -osc -oscena -program -rtpbusy