diff --git a/CPLD/LCMXO2-1200HC-IntOsc/._Real_._Math_.vhd b/CPLD/LCMXO2-1200HC-IntOsc/._Real_._Math_.vhd new file mode 100644 index 0000000..ad185b2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/._Real_._Math_.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/CPLD/LCMXO2-1200HC-IntOsc/.setting.ini b/CPLD/LCMXO2-1200HC-IntOsc/.setting.ini new file mode 100644 index 0000000..9dfa11f --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/.setting.ini @@ -0,0 +1,4 @@ +[General] +Map.auto_tasks=@@empty() +PAR.auto_tasks=@@empty() +Export.auto_tasks=Jedecgen diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS-LCMXO2.ccl b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS-LCMXO2.ccl new file mode 100644 index 0000000..43a374b --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS-LCMXO2.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf new file mode 100644 index 0000000..4ef4543 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC1.sty b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC1.sty new file mode 100644 index 0000000..c2a00cf --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC1.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC_tcl.html new file mode 100644 index 0000000..378ffbb --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC_tcl.html @@ -0,0 +1,72 @@ + +Lattice TCL Log + + +
pn240714185505
+#Start recording tcl command: 7/14/2024 18:47:20
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf"
+prj_src add "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v"
+prj_run Export -impl impl1 -task IBIS
+prj_run Export -impl impl1
+#Stop recording: 7/14/2024 18:55:05
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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.edn b/CPLD/LCMXO2-1200HC-IntOsc/REFB.edn new file mode 100644 index 0000000..5383ac2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.edn @@ -0,0 +1,550 @@ +(edif REFB + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2023 9 21 4 34 49) + (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) + (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell EFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port WBCLKI + (direction INPUT)) + (port WBRSTI + (direction INPUT)) + (port WBCYCI + (direction INPUT)) + (port WBSTBI + (direction INPUT)) + (port WBWEI + (direction INPUT)) + (port WBADRI7 + (direction INPUT)) + (port WBADRI6 + (direction INPUT)) + (port WBADRI5 + (direction INPUT)) + (port WBADRI4 + (direction INPUT)) + (port WBADRI3 + (direction INPUT)) + (port WBADRI2 + (direction INPUT)) + (port WBADRI1 + (direction INPUT)) + (port WBADRI0 + (direction INPUT)) + (port WBDATI7 + (direction INPUT)) + (port WBDATI6 + (direction INPUT)) + (port WBDATI5 + (direction INPUT)) + (port WBDATI4 + (direction INPUT)) + (port WBDATI3 + (direction INPUT)) + (port WBDATI2 + (direction INPUT)) + (port WBDATI1 + (direction INPUT)) + (port WBDATI0 + (direction INPUT)) + (port PLL0DATI7 + (direction INPUT)) + (port PLL0DATI6 + (direction INPUT)) + (port PLL0DATI5 + (direction INPUT)) + (port PLL0DATI4 + (direction INPUT)) + (port PLL0DATI3 + (direction INPUT)) + (port PLL0DATI2 + (direction INPUT)) + (port PLL0DATI1 + (direction INPUT)) + (port PLL0DATI0 + (direction INPUT)) + (port PLL0ACKI + (direction INPUT)) + (port PLL1DATI7 + (direction INPUT)) + (port PLL1DATI6 + (direction INPUT)) + (port PLL1DATI5 + (direction INPUT)) + (port PLL1DATI4 + (direction INPUT)) + (port PLL1DATI3 + (direction INPUT)) + (port PLL1DATI2 + (direction INPUT)) + (port PLL1DATI1 + (direction INPUT)) + (port PLL1DATI0 + (direction INPUT)) + (port PLL1ACKI + (direction INPUT)) + (port I2C1SCLI + (direction INPUT)) + (port I2C1SDAI + (direction INPUT)) + (port I2C2SCLI + (direction INPUT)) + (port I2C2SDAI + (direction INPUT)) + (port SPISCKI + (direction INPUT)) + (port SPIMISOI + (direction INPUT)) + (port SPIMOSII + (direction INPUT)) + (port SPISCSN + (direction INPUT)) + (port TCCLKI + (direction INPUT)) + (port TCRSTN + (direction INPUT)) + (port TCIC + (direction INPUT)) + (port UFMSN + (direction INPUT)) + (port WBDATO7 + (direction OUTPUT)) + (port WBDATO6 + (direction OUTPUT)) + (port WBDATO5 + (direction OUTPUT)) + (port WBDATO4 + (direction OUTPUT)) + (port WBDATO3 + (direction OUTPUT)) + (port WBDATO2 + (direction OUTPUT)) + (port WBDATO1 + (direction OUTPUT)) + (port WBDATO0 + (direction OUTPUT)) + (port WBACKO + (direction OUTPUT)) + (port PLLCLKO + (direction OUTPUT)) + (port PLLRSTO + (direction OUTPUT)) + (port PLL0STBO + (direction OUTPUT)) + (port PLL1STBO + (direction OUTPUT)) + (port PLLWEO + (direction OUTPUT)) + (port PLLADRO4 + (direction OUTPUT)) + (port PLLADRO3 + (direction OUTPUT)) + (port PLLADRO2 + (direction OUTPUT)) + (port PLLADRO1 + (direction OUTPUT)) + (port PLLADRO0 + (direction OUTPUT)) + (port PLLDATO7 + (direction OUTPUT)) + (port PLLDATO6 + (direction OUTPUT)) + (port PLLDATO5 + (direction OUTPUT)) + (port PLLDATO4 + (direction OUTPUT)) + (port PLLDATO3 + (direction OUTPUT)) + (port PLLDATO2 + (direction OUTPUT)) + (port PLLDATO1 + (direction OUTPUT)) + (port PLLDATO0 + (direction OUTPUT)) + (port I2C1SCLO + (direction OUTPUT)) + (port I2C1SCLOEN + (direction OUTPUT)) + (port I2C1SDAO + (direction OUTPUT)) + (port I2C1SDAOEN + (direction OUTPUT)) + (port I2C2SCLO + (direction OUTPUT)) + (port I2C2SCLOEN + (direction OUTPUT)) + (port I2C2SDAO + (direction OUTPUT)) + (port I2C2SDAOEN + (direction OUTPUT)) + (port I2C1IRQO + (direction OUTPUT)) + (port I2C2IRQO + (direction OUTPUT)) + (port SPISCKO + (direction OUTPUT)) + (port SPISCKEN + (direction OUTPUT)) + (port SPIMISOO + (direction OUTPUT)) + (port SPIMISOEN + (direction OUTPUT)) + (port SPIMOSIO + (direction OUTPUT)) + (port SPIMOSIEN + (direction OUTPUT)) + (port SPIMCSN7 + (direction OUTPUT)) + (port SPIMCSN6 + (direction OUTPUT)) + (port SPIMCSN5 + (direction OUTPUT)) + (port SPIMCSN4 + (direction OUTPUT)) + (port SPIMCSN3 + (direction OUTPUT)) + (port SPIMCSN2 + (direction OUTPUT)) + (port SPIMCSN1 + (direction OUTPUT)) + (port SPIMCSN0 + (direction OUTPUT)) + (port SPICSNEN + (direction OUTPUT)) + (port SPIIRQO + (direction OUTPUT)) + (port TCINT + (direction OUTPUT)) + (port TCOC + (direction OUTPUT)) + (port WBCUFMIRQ + (direction OUTPUT)) + (port CFGWAKE + (direction OUTPUT)) + (port CFGSTDBY + (direction OUTPUT))))) + (cell REFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port wb_clk_i + (direction INPUT)) + (port wb_rst_i + (direction INPUT)) + (port wb_cyc_i + (direction INPUT)) + (port wb_stb_i + (direction INPUT)) + (port wb_we_i + (direction INPUT)) + (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8) + (direction OUTPUT)) + (port wb_ack_o + (direction OUTPUT)) + (port wbc_ufm_irq + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance EFBInst_0 + (viewRef view1 + (cellRef EFB)) + (property UFM_INIT_FILE_FORMAT + (string "HEX")) + (property UFM_INIT_FILE_NAME + (string "../RAM2GS-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS + (string "DISABLED")) + (property UFM_INIT_START_PAGE + (string "190")) + (property UFM_INIT_PAGES + (string "321")) + (property DEV_DENSITY + (string "1200L")) + (property EFB_UFM + (string "ENABLED")) + (property TC_ICAPTURE + (string "DISABLED")) + (property TC_OVERFLOW + (string "DISABLED")) + (property TC_ICR_INT + (string "OFF")) + (property TC_OCR_INT + (string "OFF")) + (property TC_OV_INT + (string "OFF")) + (property TC_TOP_SEL + (string "OFF")) + (property TC_RESETN + (string "ENABLED")) + (property TC_OC_MODE + (string "TOGGLE")) + (property TC_OCR_SET + (string "32767")) + (property TC_TOP_SET + (string "65535")) + (property GSR + (string "ENABLED")) + (property TC_CCLK_SEL + (string "1")) + (property TC_MODE + (string "CTCM")) + (property TC_SCLK_SEL + (string "PCLOCK")) + (property EFB_TC_PORTMODE + (string "WB")) + (property EFB_TC + (string "DISABLED")) + (property SPI_WAKEUP + (string "DISABLED")) + (property SPI_INTR_RXOVR + (string "DISABLED")) + (property SPI_INTR_TXOVR + (string "DISABLED")) + (property SPI_INTR_RXRDY + (string "DISABLED")) + (property SPI_INTR_TXRDY + (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE + (string "DISABLED")) + (property SPI_PHASE_ADJ + (string "DISABLED")) + (property SPI_CLK_INV + (string "DISABLED")) + (property SPI_LSB_FIRST + (string "DISABLED")) + (property SPI_CLK_DIVIDER + (string "1")) + (property SPI_MODE + (string "MASTER")) + (property EFB_SPI + (string "DISABLED")) + (property I2C2_WAKEUP + (string "DISABLED")) + (property I2C2_GEN_CALL + (string "DISABLED")) + (property I2C2_CLK_DIVIDER + (string "1")) + (property I2C2_BUS_PERF + (string "100kHz")) + (property I2C2_SLAVE_ADDR + (string "0b1000010")) + (property I2C2_ADDRESSING + (string "7BIT")) + (property EFB_I2C2 + (string "DISABLED")) + (property I2C1_WAKEUP + (string "DISABLED")) + (property I2C1_GEN_CALL + (string "DISABLED")) + (property I2C1_CLK_DIVIDER + (string "1")) + (property I2C1_BUS_PERF + (string "100kHz")) + (property I2C1_SLAVE_ADDR + (string "0b1000001")) + (property I2C1_ADDRESSING + (string "7BIT")) + (property EFB_I2C1 + (string "DISABLED")) + (property EFB_WB_CLK_FREQ + (string "66.7"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef UFMSN (instanceRef EFBInst_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)))) + (net wbc_ufm_irq + (joined + (portRef wbc_ufm_irq) + (portRef WBCUFMIRQ (instanceRef EFBInst_0)))) + (net wb_ack_o + (joined + (portRef wb_ack_o) + (portRef WBACKO (instanceRef EFBInst_0)))) + (net wb_dat_o7 + (joined + (portRef (member wb_dat_o 0)) + (portRef WBDATO7 (instanceRef EFBInst_0)))) + (net wb_dat_o6 + (joined + (portRef (member wb_dat_o 1)) + (portRef WBDATO6 (instanceRef EFBInst_0)))) + (net wb_dat_o5 + (joined + (portRef (member wb_dat_o 2)) + (portRef WBDATO5 (instanceRef EFBInst_0)))) + (net wb_dat_o4 + (joined + (portRef (member wb_dat_o 3)) + (portRef WBDATO4 (instanceRef EFBInst_0)))) + (net wb_dat_o3 + (joined + (portRef (member wb_dat_o 4)) + (portRef WBDATO3 (instanceRef EFBInst_0)))) + (net wb_dat_o2 + (joined + (portRef (member wb_dat_o 5)) + (portRef WBDATO2 (instanceRef EFBInst_0)))) + (net wb_dat_o1 + (joined + (portRef (member wb_dat_o 6)) + (portRef WBDATO1 (instanceRef EFBInst_0)))) + (net wb_dat_o0 + (joined + (portRef (member wb_dat_o 7)) + (portRef WBDATO0 (instanceRef EFBInst_0)))) + (net wb_dat_i7 + (joined + (portRef (member wb_dat_i 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)))) + (net wb_dat_i6 + (joined + (portRef (member wb_dat_i 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)))) + (net wb_dat_i5 + (joined + (portRef (member wb_dat_i 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)))) + (net wb_dat_i4 + (joined + (portRef (member wb_dat_i 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)))) + (net wb_dat_i3 + (joined + (portRef (member wb_dat_i 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)))) + (net wb_dat_i2 + (joined + (portRef (member wb_dat_i 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)))) + (net wb_dat_i1 + (joined + (portRef (member wb_dat_i 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)))) + (net wb_dat_i0 + (joined + (portRef (member wb_dat_i 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)))) + (net wb_adr_i7 + (joined + (portRef (member wb_adr_i 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)))) + (net wb_adr_i6 + (joined + (portRef (member wb_adr_i 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)))) + (net wb_adr_i5 + (joined + (portRef (member wb_adr_i 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)))) + (net wb_adr_i4 + (joined + (portRef (member wb_adr_i 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)))) + (net wb_adr_i3 + (joined + (portRef (member wb_adr_i 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)))) + (net wb_adr_i2 + (joined + (portRef (member wb_adr_i 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)))) + (net wb_adr_i1 + (joined + (portRef (member wb_adr_i 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)))) + (net wb_adr_i0 + (joined + (portRef (member wb_adr_i 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)))) + (net wb_we_i + (joined + (portRef wb_we_i) + (portRef WBWEI (instanceRef EFBInst_0)))) + (net wb_stb_i + (joined + (portRef wb_stb_i) + (portRef WBSTBI (instanceRef EFBInst_0)))) + (net wb_cyc_i + (joined + (portRef wb_cyc_i) + (portRef WBCYCI (instanceRef EFBInst_0)))) + (net wb_rst_i + (joined + (portRef wb_rst_i) + (portRef WBRSTI (instanceRef EFBInst_0)))) + (net wb_clk_i + (joined + (portRef wb_clk_i) + (portRef WBCLKI (instanceRef EFBInst_0)))))))) + (design REFB + (cellRef REFB + (libraryRef ORCLIB))) +) diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.ipx b/CPLD/LCMXO2-1200HC-IntOsc/REFB.ipx new file mode 100644 index 0000000..5f4a3d3 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.lpc b/CPLD/LCMXO2-1200HC-IntOsc/REFB.lpc new file mode 100644 index 0000000..4c1ff09 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.lpc @@ -0,0 +1,141 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-1200HC +PartName=LCMXO2-1200HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=REFB +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=09/21/2023 +Time=04:34:49 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +ufm0=0 +ufm1=0 +ufm2=0 +ufm3=0 +ufm_cfg0=0 +ufm_cfg1=0 +wb_clk_freq=66.7 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=190 +ufm_remain= +mem_size=321 +ufm_start= +ufm_init=mem +memfile=../RAM2GS-LCMXO2.mem +ufm_dt=hex +ufm0_ebr= +mem_size0=1 +ufm0_init=0 +memfile0= +ufm0_dt=hex +ufm1_ebr= +mem_size1=1 +ufm1_init=0 +memfile1= +ufm1_dt=hex +ufm2_ebr= +mem_size2=1 +ufm2_init=0 +memfile2= +ufm2_dt=hex +ufm3_ebr= +mem_size3=1 +ufm3_init=0 +memfile3= +ufm3_dt=hex +ufm_cfg0_ebr= +mem_size_cfg0=1 +ufm_cfg0_init=0 +memfile_cfg0= +ufm_cfg0_dt=hex +ufm_cfg1_ebr= +mem_size_cfg1=1 +ufm_cfg1_init=0 +memfile_cfg1= +ufm_cfg1_dt=hex +wb=1 +boot_option=Internal +efb_ufm=0 +boot_option_internal=Single Boot +internal_ufm0=0 +internal_ufm1=0 +efb_ufm_boot= +tamperdr=0 +t_pwd=0 +t_lockflash=0 +t_manmode=0 +t_jtagport=0 +t_sspiport=0 +t_sic2port=0 +t_wbport=0 +t_portlock=0 + +[Command] +cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.naf b/CPLD/LCMXO2-1200HC-IntOsc/REFB.naf new file mode 100644 index 0000000..5c239f5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.naf @@ -0,0 +1,31 @@ +wb_clk_i i +wb_rst_i i +wb_cyc_i i +wb_stb_i i +wb_we_i i +wb_adr_i[7] i +wb_adr_i[6] i +wb_adr_i[5] i +wb_adr_i[4] i +wb_adr_i[3] i +wb_adr_i[2] i +wb_adr_i[1] i +wb_adr_i[0] i +wb_dat_i[7] i +wb_dat_i[6] i +wb_dat_i[5] i +wb_dat_i[4] i +wb_dat_i[3] i +wb_dat_i[2] i +wb_dat_i[1] i +wb_dat_i[0] i +wb_dat_o[7] o +wb_dat_o[6] o +wb_dat_o[5] o +wb_dat_o[4] o +wb_dat_o[3] o +wb_dat_o[2] o +wb_dat_o[1] o +wb_dat_o[0] o +wb_ack_o o +wbc_ufm_irq o diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.sort b/CPLD/LCMXO2-1200HC-IntOsc/REFB.sort new file mode 100644 index 0000000..96fe0d5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.sort @@ -0,0 +1 @@ +REFB.v diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.srp b/CPLD/LCMXO2-1200HC-IntOsc/REFB.srp new file mode 100644 index 0000000..f6a3646 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Thu Sep 21 04:34:49 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Element Usage : + EFB : 1 + Estimated Resource Usage: diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.sym b/CPLD/LCMXO2-1200HC-IntOsc/REFB.sym new file mode 100644 index 0000000..6588d30 Binary files /dev/null and b/CPLD/LCMXO2-1200HC-IntOsc/REFB.sym differ diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB.v b/CPLD/LCMXO2-1200HC-IntOsc/REFB.v new file mode 100644 index 0000000..5851aa7 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB.v @@ -0,0 +1,113 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 */ +/* Thu Sep 21 04:34:49 2023 */ + + +`timescale 1 ns / 1 ps +module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, + wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */; + input wire wb_clk_i; + input wire wb_rst_i; + input wire wb_cyc_i; + input wire wb_stb_i; + input wire wb_we_i; + input wire [7:0] wb_adr_i; + input wire [7:0] wb_dat_i; + output wire [7:0] wb_dat_o; + output wire wb_ack_o; + output wire wbc_ufm_irq; + + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; + defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ; + defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ; + defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ; + defparam EFBInst_0.UFM_INIT_PAGES = 321 ; + defparam EFBInst_0.DEV_DENSITY = "1200L" ; + defparam EFBInst_0.EFB_UFM = "ENABLED" ; + defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ; + defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ; + defparam EFBInst_0.TC_ICR_INT = "OFF" ; + defparam EFBInst_0.TC_OCR_INT = "OFF" ; + defparam EFBInst_0.TC_OV_INT = "OFF" ; + defparam EFBInst_0.TC_TOP_SEL = "OFF" ; + defparam EFBInst_0.TC_RESETN = "ENABLED" ; + defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ; + defparam EFBInst_0.TC_OCR_SET = 32767 ; + defparam EFBInst_0.TC_TOP_SET = 65535 ; + defparam EFBInst_0.GSR = "ENABLED" ; + defparam EFBInst_0.TC_CCLK_SEL = 1 ; + defparam EFBInst_0.TC_MODE = "CTCM" ; + defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ; + defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ; + defparam EFBInst_0.EFB_TC = "DISABLED" ; + defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ; + defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ; + defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ; + defparam EFBInst_0.SPI_MODE = "MASTER" ; + defparam EFBInst_0.EFB_SPI = "DISABLED" ; + defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ; + defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C2 = "DISABLED" ; + defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; + defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; + defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ; + EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), + .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), + .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), + .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), + .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), + .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), + .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), + .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), + .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), + .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), + .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), + .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), + .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), + .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), + .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo), + .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), + .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), + .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), + .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), + .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), + .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), + .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(), + .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), + .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), + .WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY()); + + + + // exemplar begin + // exemplar end + +endmodule diff --git a/CPLD/LCMXO2-1200HC-IntOsc/REFB_tmpl.v b/CPLD/LCMXO2-1200HC-IntOsc/REFB_tmpl.v new file mode 100644 index 0000000..06abdb6 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/REFB_tmpl.v @@ -0,0 +1,8 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* Thu Sep 21 04:34:49 2023 */ + +/* parameterized module instance */ +REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), + .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), + .wbc_ufm_irq( )); diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.edn b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.edn new file mode 100644 index 0000000..82b86ad --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.edn @@ -0,0 +1,297 @@ +(edif RPLL + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2024 7 14 22 23 22) + (program "SCUBA" (version "Diamond (64-bit) 3.11.3.469")))) + (comment "C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell EHXPLLJ + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKFB + (direction INPUT)) + (port PHASESEL1 + (direction INPUT)) + (port PHASESEL0 + (direction INPUT)) + (port PHASEDIR + (direction INPUT)) + (port PHASESTEP + (direction INPUT)) + (port LOADREG + (direction INPUT)) + (port STDBY + (direction INPUT)) + (port PLLWAKESYNC + (direction INPUT)) + (port RST + (direction INPUT)) + (port RESETM + (direction INPUT)) + (port RESETC + (direction INPUT)) + (port RESETD + (direction INPUT)) + (port ENCLKOP + (direction INPUT)) + (port ENCLKOS + (direction INPUT)) + (port ENCLKOS2 + (direction INPUT)) + (port ENCLKOS3 + (direction INPUT)) + (port PLLCLK + (direction INPUT)) + (port PLLRST + (direction INPUT)) + (port PLLSTB + (direction INPUT)) + (port PLLWE + (direction INPUT)) + (port PLLADDR4 + (direction INPUT)) + (port PLLADDR3 + (direction INPUT)) + (port PLLADDR2 + (direction INPUT)) + (port PLLADDR1 + (direction INPUT)) + (port PLLADDR0 + (direction INPUT)) + (port PLLDATI7 + (direction INPUT)) + (port PLLDATI6 + (direction INPUT)) + (port PLLDATI5 + (direction INPUT)) + (port PLLDATI4 + (direction INPUT)) + (port PLLDATI3 + (direction INPUT)) + (port PLLDATI2 + (direction INPUT)) + (port PLLDATI1 + (direction INPUT)) + (port PLLDATI0 + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOS2 + (direction OUTPUT)) + (port CLKOS3 + (direction OUTPUT)) + (port LOCK + (direction OUTPUT)) + (port INTLOCK + (direction OUTPUT)) + (port REFCLK + (direction OUTPUT)) + (port CLKINTFB + (direction OUTPUT)) + (port DPHSRC + (direction OUTPUT)) + (port PLLACK + (direction OUTPUT)) + (port PLLDATO7 + (direction OUTPUT)) + (port PLLDATO6 + (direction OUTPUT)) + (port PLLDATO5 + (direction OUTPUT)) + (port PLLDATO4 + (direction OUTPUT)) + (port PLLDATO3 + (direction OUTPUT)) + (port PLLDATO2 + (direction OUTPUT)) + (port PLLDATO1 + (direction OUTPUT)) + (port PLLDATO0 + (direction OUTPUT))))) + (cell RPLL + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKOP + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance PLLInst_0 + (viewRef view1 + (cellRef EHXPLLJ)) + (property DDRST_ENA + (string "DISABLED")) + (property DCRST_ENA + (string "DISABLED")) + (property MRST_ENA + (string "DISABLED")) + (property PLLRST_ENA + (string "DISABLED")) + (property INTFB_WAKE + (string "DISABLED")) + (property STDBY_ENABLE + (string "DISABLED")) + (property DPHASE_SOURCE + (string "DISABLED")) + (property PLL_USE_WB + (string "DISABLED")) + (property CLKOS3_FPHASE + (string "0")) + (property CLKOS3_CPHASE + (string "0")) + (property CLKOS2_FPHASE + (string "0")) + (property CLKOS2_CPHASE + (string "0")) + (property CLKOS_FPHASE + (string "0")) + (property CLKOS_CPHASE + (string "0")) + (property CLKOP_FPHASE + (string "0")) + (property CLKOP_CPHASE + (string "7")) + (property PLL_LOCK_MODE + (string "0")) + (property CLKOS_TRIM_DELAY + (string "0")) + (property CLKOS_TRIM_POL + (string "FALLING")) + (property CLKOP_TRIM_DELAY + (string "0")) + (property CLKOP_TRIM_POL + (string "RISING")) + (property FRACN_DIV + (string "0")) + (property FRACN_ENABLE + (string "DISABLED")) + (property OUTDIVIDER_MUXD2 + (string "DIVD")) + (property PREDIVIDER_MUXD1 + (string "0")) + (property VCO_BYPASS_D0 + (string "DISABLED")) + (property CLKOS3_ENABLE + (string "DISABLED")) + (property OUTDIVIDER_MUXC2 + (string "DIVC")) + (property PREDIVIDER_MUXC1 + (string "0")) + (property VCO_BYPASS_C0 + (string "DISABLED")) + (property CLKOS2_ENABLE + (string "DISABLED")) + (property OUTDIVIDER_MUXB2 + (string "DIVB")) + (property PREDIVIDER_MUXB1 + (string "0")) + (property VCO_BYPASS_B0 + (string "DISABLED")) + (property CLKOS_ENABLE + (string "DISABLED")) + (property FREQUENCY_PIN_CLKOP + (string "61.384615")) + (property OUTDIVIDER_MUXA2 + (string "DIVA")) + (property PREDIVIDER_MUXA1 + (string "0")) + (property VCO_BYPASS_A0 + (string "DISABLED")) + (property CLKOP_ENABLE + (string "ENABLED")) + (property FREQUENCY_PIN_CLKI + (string "133.000000")) + (property ICP_CURRENT + (string "7")) + (property LPF_RESISTOR + (string "8")) + (property CLKOS3_DIV + (string "1")) + (property CLKOS2_DIV + (string "1")) + (property CLKOS_DIV + (string "1")) + (property CLKOP_DIV + (string "8")) + (property CLKFB_DIV + (string "6")) + (property CLKI_DIV + (string "13")) + (property FEEDBK_PATH + (string "CLKOP"))) + (net LOCK + (joined + (portRef LOCK (instanceRef PLLInst_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef PLLADDR4 (instanceRef PLLInst_0)) + (portRef PLLADDR3 (instanceRef PLLInst_0)) + (portRef PLLADDR2 (instanceRef PLLInst_0)) + (portRef PLLADDR1 (instanceRef PLLInst_0)) + (portRef PLLADDR0 (instanceRef PLLInst_0)) + (portRef PLLDATI7 (instanceRef PLLInst_0)) + (portRef PLLDATI6 (instanceRef PLLInst_0)) + (portRef PLLDATI5 (instanceRef PLLInst_0)) + (portRef PLLDATI4 (instanceRef PLLInst_0)) + (portRef PLLDATI3 (instanceRef PLLInst_0)) + (portRef PLLDATI2 (instanceRef PLLInst_0)) + (portRef PLLDATI1 (instanceRef PLLInst_0)) + (portRef PLLDATI0 (instanceRef PLLInst_0)) + (portRef PLLWE (instanceRef PLLInst_0)) + (portRef PLLSTB (instanceRef PLLInst_0)) + (portRef PLLRST (instanceRef PLLInst_0)) + (portRef PLLCLK (instanceRef PLLInst_0)) + (portRef ENCLKOS3 (instanceRef PLLInst_0)) + (portRef ENCLKOS2 (instanceRef PLLInst_0)) + (portRef ENCLKOS (instanceRef PLLInst_0)) + (portRef ENCLKOP (instanceRef PLLInst_0)) + (portRef RESETD (instanceRef PLLInst_0)) + (portRef RESETC (instanceRef PLLInst_0)) + (portRef RESETM (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)) + (portRef PLLWAKESYNC (instanceRef PLLInst_0)) + (portRef STDBY (instanceRef PLLInst_0)) + (portRef LOADREG (instanceRef PLLInst_0)) + (portRef PHASESTEP (instanceRef PLLInst_0)) + (portRef PHASEDIR (instanceRef PLLInst_0)) + (portRef PHASESEL1 (instanceRef PLLInst_0)) + (portRef PHASESEL0 (instanceRef PLLInst_0)))) + (net CLKOP + (joined + (portRef CLKOP) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOP (instanceRef PLLInst_0)))) + (net CLKI + (joined + (portRef CLKI) + (portRef CLKI (instanceRef PLLInst_0)))))))) + (design RPLL + (cellRef RPLL + (libraryRef ORCLIB))) +) diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.ipx b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.ipx new file mode 100644 index 0000000..37b4f8c --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.lpc b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.lpc new file mode 100644 index 0000000..b3c5941 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.lpc @@ -0,0 +1,87 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-1200HC +PartName=LCMXO2-1200HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=RPLL +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=07/14/2024 +Time=22:23:22 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +mode=Frequency +CLKI=133.0 +CLKI_DIV=13 +BW=0.955 +VCO=491.077 +fb_mode=CLKOP +CLKFB_DIV=6 +FRACN_ENABLE=0 +FRACN_DIV=0 +DynamicPhase=STATIC +ClkEnable=0 +Standby=0 +Enable_sel=0 +PLLRst=0 +PLLMRst=0 +ClkOS2Rst=0 +ClkOS3Rst=0 +LockSig=0 +LockStk=0 +WBProt=0 +OPBypass=0 +OPUseDiv=0 +CLKOP_DIV=8 +FREQ_PIN_CLKOP=61 +OP_Tol=1.0 +CLKOP_AFREQ=61.384615 +CLKOP_PHASEADJ=0 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +EnCLKOS=0 +OSBypass=0 +OSUseDiv=0 +CLKOS_DIV=1 +FREQ_PIN_CLKOS=100 +OS_Tol=0.0 +CLKOS_AFREQ= +CLKOS_PHASEADJ=0 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +EnCLKOS2=0 +OS2Bypass=0 +OS2UseDiv=0 +CLKOS2_DIV=1 +FREQ_PIN_CLKOS2=100 +OS2_Tol=0.0 +CLKOS2_AFREQ= +CLKOS2_PHASEADJ=0 +EnCLKOS3=0 +OS3Bypass=0 +OS3UseDiv=0 +CLKOS3_DIV=1 +FREQ_PIN_CLKOS3=100 +OS3_Tol=0.0 +CLKOS3_AFREQ= +CLKOS3_PHASEADJ=0 + +[Command] +cmd_line= -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.naf b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.naf new file mode 100644 index 0000000..e2b2c17 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.naf @@ -0,0 +1,2 @@ +CLKI i +CLKOP o diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sort b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sort new file mode 100644 index 0000000..d606ae7 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sort @@ -0,0 +1 @@ +RPLL.v diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.srp b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.srp new file mode 100644 index 0000000..e29b224 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.11.3.469 +Sun Jul 14 22:23:22 2024 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 + Circuit name : RPLL + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLKI + Outputs : CLKOP + I/O buffer : not inserted + EDIF output : RPLL.edn + Verilog output : RPLL.v + Verilog template : RPLL_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : RPLL.srp + Element Usage : + EHXPLLJ : 1 + Estimated Resource Usage: diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sym b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sym new file mode 100644 index 0000000..6bda405 Binary files /dev/null and b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.sym differ diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v new file mode 100644 index 0000000..cd80f98 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v @@ -0,0 +1,93 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.3.469 */ +/* Module Version: 5.7 */ +/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 */ +/* Sun Jul 14 22:23:22 2024 */ + + +`timescale 1 ns / 1 ps +module RPLL (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire LOCK; + wire CLKOP_t; + wire scuba_vlo; + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.DDRST_ENA = "DISABLED" ; + defparam PLLInst_0.DCRST_ENA = "DISABLED" ; + defparam PLLInst_0.MRST_ENA = "DISABLED" ; + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.PLL_USE_WB = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 7 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ; + defparam PLLInst_0.FRACN_DIV = 0 ; + defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ; + defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ; + defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ; + defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ; + defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 8 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 13 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo), + .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo), + .PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo), + .PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo), + .PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo), + .PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo), + .PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), .PLLACK(), + .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0()) + /* synthesis FREQUENCY_PIN_CLKOP="61.384615" */ + /* synthesis FREQUENCY_PIN_CLKI="133.000000" */ + /* synthesis ICP_CURRENT="7" */ + /* synthesis LPF_RESISTOR="8" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 61.384615 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 133.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 7 + // exemplar attribute PLLInst_0 LPF_RESISTOR 8 + // exemplar end + +endmodule diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL_generate.log b/CPLD/LCMXO2-1200HC-IntOsc/RPLL_generate.log new file mode 100644 index 0000000..343c5c5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.11.3.469 +Sun Jul 14 22:23:22 2024 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 + Circuit name : RPLL + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLKI + Outputs : CLKOP + I/O buffer : not inserted + EDIF output : RPLL.edn + Verilog output : RPLL.v + Verilog template : RPLL_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : RPLL.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: RPLL.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/RPLL_tmpl.v b/CPLD/LCMXO2-1200HC-IntOsc/RPLL_tmpl.v new file mode 100644 index 0000000..9ca87ed --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/RPLL_tmpl.v @@ -0,0 +1,6 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.3.469 */ +/* Module Version: 5.7 */ +/* Sun Jul 14 22:23:22 2024 */ + +/* parameterized module instance */ +RPLL __ (.CLKI( ), .CLKOP( )); diff --git a/CPLD/LCMXO2-1200HC-IntOsc/_math_real.vhd b/CPLD/LCMXO2-1200HC-IntOsc/_math_real.vhd new file mode 100644 index 0000000..e1215d8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/_math_real.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/CPLD/LCMXO2-1200HC-IntOsc/generate_core.tcl b/CPLD/LCMXO2-1200HC-IntOsc/generate_core.tcl new file mode 100644 index 0000000..df06424 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/generate_core.tcl @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "RPLL" +set lang "verilog" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "xo2c00" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg diff --git a/CPLD/LCMXO2-1200HC-IntOsc/generate_ngd.tcl b/CPLD/LCMXO2-1200HC-IntOsc/generate_ngd.tcl new file mode 100644 index 0000000..9c4553c --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/generate_ngd.tcl @@ -0,0 +1,115 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "RPLL" +set Para(Module) "PLL" +set Para(libname) machxo2 +set Para(arch_name) xo2c00 +set Para(PartType) "LCMXO2-1200HC" + +set Para(tech_syn) machxo2 +set Para(tech_cae) machxo2 +set Para(Package) "TQFP100" +set Para(SpeedGrade) "4" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#create response file(*.cmd) for Synpwrap +proc CreateCmdFile {} { + global Para + + file mkdir "$Para(sbp_path)/syn_results" + if [catch {open $Para(ModuleName).cmd w} rspFile] { + puts "Cannot create response file $Para(ModuleName).cmd." + exit -1 + } else { + puts $rspFile "PROJECT: $Para(ModuleName) + working_path: \"$Para(sbp_path)/syn_results\" + module: $Para(ModuleName) + verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\" + vlog_std_v2001: true + constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\" + suffix_name: edn + output_file_name: $Para(ModuleName) + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: $Para(FMax) + fanout_limit: 50 + retiming: false + pipe: false + part: $Para(PartType) + speed_grade: $Para(SpeedGrade) + " + close $rspFile + } +} + +#synpwrap +CreateCmdFile +set synpwrap "$Para(bin_dir)/synpwrap" +if {[file exists $fdcfile] == 0} { + set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg] +} else { + set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg] +} +#puts $msg + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt new file mode 100644 index 0000000..b17fbdc --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt @@ -0,0 +1,71 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Sun Jul 14 22:31:30 2024 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS RDQML : 48 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS RCLKout : 60 : out * +NOTE PINS nRCS : 57 : out * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 62 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS RBA[1] : 47 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS LED : 34 : out * +NOTE PINS nFWE : 15 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr new file mode 100644 index 0000000..8a22cee --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr @@ -0,0 +1,58 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.verilog + +Register bits: 106 of 1280 (8%) +PIC Latch: 0 +I/O cells: 63 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + EFB 1 100.0 + EHXPLLJ 1 100.0 + FD1P3AX 28 100.0 + FD1P3IX 3 100.0 + FD1S3AX 37 100.0 + FD1S3IX 3 100.0 + GSR 1 100.0 + IB 24 100.0 + IFS1P3DX 9 100.0 + IFS1P3IX 10 100.0 + IFS1P3JX 2 100.0 + INV 7 100.0 + OB 31 100.0 + ODDRXE 1 100.0 + OFS1P3BX 4 100.0 + OFS1P3DX 8 100.0 + OFS1P3IX 1 100.0 + OFS1P3JX 1 100.0 + ORCALUT4 186 100.0 + OSCH 1 100.0 + PFUMX 2 100.0 + PUR 1 100.0 + VHI 2 100.0 + VLO 3 100.0 +SUB MODULES + REFB 1 100.0 + RPLL 1 100.0 + + TOTAL 387 +---------------------------------------------------------------------- +Report for cell REFB.netlist + Instance path: ufmefb + Cell usage: + cell count Res Usage(%) + EFB 1 100.0 + VHI 1 50.0 + VLO 1 33.3 + + TOTAL 3 +---------------------------------------------------------------------- +Report for cell RPLL.netlist + Instance path: rpll + Cell usage: + cell count Res Usage(%) + EHXPLLJ 1 100.0 + VLO 1 33.3 + + TOTAL 2 diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn new file mode 100644 index 0000000..6efed6b --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sun Jul 14 22:31:27 2024 + + +Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga. +Package Status: Final Version 1.42. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 321 Pages (Page 190 to Page 510). + +Total CPU Time: 3 secs +Total REAL Time: 3 secs +Peak Memory Usage: 275 MB diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi new file mode 100644 index 0000000..d3ca2c3 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi @@ -0,0 +1,4572 @@ +(edif RAM2GS + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2024 7 14 22 31 13) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "N-2018.03L-SP1-1, mapper maplat2018q2p1, Build 055R")) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell OSCH (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port STDBY (direction INPUT)) + (port OSC (direction OUTPUT)) + (port SEDSTDBY (direction OUTPUT)) + ) + (property NOM_FREQ (string "2.08")) + ) + ) + (cell CCU2D (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A0 (direction INPUT)) + (port B0 (direction INPUT)) + (port C0 (direction INPUT)) + (port D0 (direction INPUT)) + (port A1 (direction INPUT)) + (port B1 (direction INPUT)) + (port C1 (direction INPUT)) + (port D1 (direction INPUT)) + (port CIN (direction INPUT)) + (port COUT (direction OUTPUT)) + (port S0 (direction OUTPUT)) + (port S1 (direction OUTPUT)) + ) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0000")) + (property INIT0 (string "0000")) + ) + ) + (cell BB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port B (direction INOUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell OB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell FD1S3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3JX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3JX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3BX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell ORCALUT4 (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell PFUMX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port ALUT (direction INPUT)) + (port BLUT (direction INPUT)) + (port C0 (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell EFB (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port WBCLKI (direction INPUT)) + (port WBRSTI (direction INPUT)) + (port WBCYCI (direction INPUT)) + (port WBSTBI (direction INPUT)) + (port WBWEI (direction INPUT)) + (port WBADRI7 (direction INPUT)) + (port WBADRI6 (direction INPUT)) + (port WBADRI5 (direction INPUT)) + (port WBADRI4 (direction INPUT)) + (port WBADRI3 (direction INPUT)) + (port WBADRI2 (direction INPUT)) + (port WBADRI1 (direction INPUT)) + (port WBADRI0 (direction INPUT)) + (port WBDATI7 (direction INPUT)) + (port WBDATI6 (direction INPUT)) + (port WBDATI5 (direction INPUT)) + (port WBDATI4 (direction INPUT)) + (port WBDATI3 (direction INPUT)) + (port WBDATI2 (direction INPUT)) + (port WBDATI1 (direction INPUT)) + (port WBDATI0 (direction INPUT)) + (port PLL0DATI7 (direction INPUT)) + (port PLL0DATI6 (direction INPUT)) + (port PLL0DATI5 (direction INPUT)) + (port PLL0DATI4 (direction INPUT)) + (port PLL0DATI3 (direction INPUT)) + (port PLL0DATI2 (direction INPUT)) + (port PLL0DATI1 (direction INPUT)) + (port PLL0DATI0 (direction INPUT)) + (port PLL0ACKI (direction INPUT)) + (port PLL1DATI7 (direction INPUT)) + (port PLL1DATI6 (direction INPUT)) + (port PLL1DATI5 (direction INPUT)) + (port PLL1DATI4 (direction INPUT)) + (port PLL1DATI3 (direction INPUT)) + (port PLL1DATI2 (direction INPUT)) + (port PLL1DATI1 (direction INPUT)) + (port PLL1DATI0 (direction INPUT)) + (port PLL1ACKI (direction INPUT)) + (port I2C1SCLI (direction INPUT)) + (port I2C1SDAI (direction INPUT)) + (port I2C2SCLI (direction INPUT)) + (port I2C2SDAI (direction INPUT)) + (port SPISCKI (direction INPUT)) + (port SPIMISOI (direction INPUT)) + (port SPIMOSII (direction INPUT)) + (port SPISCSN (direction INPUT)) + (port TCCLKI (direction INPUT)) + (port TCRSTN (direction INPUT)) + (port TCIC (direction INPUT)) + (port UFMSN (direction INPUT)) + (port WBDATO7 (direction OUTPUT)) + (port WBDATO6 (direction OUTPUT)) + (port WBDATO5 (direction OUTPUT)) + (port WBDATO4 (direction OUTPUT)) + (port WBDATO3 (direction OUTPUT)) + (port WBDATO2 (direction OUTPUT)) + (port WBDATO1 (direction OUTPUT)) + (port WBDATO0 (direction OUTPUT)) + (port WBACKO (direction OUTPUT)) + (port PLLCLKO (direction OUTPUT)) + (port PLLRSTO (direction OUTPUT)) + (port PLL0STBO (direction OUTPUT)) + (port PLL1STBO (direction OUTPUT)) + (port PLLWEO (direction OUTPUT)) + (port PLLADRO4 (direction OUTPUT)) + (port PLLADRO3 (direction OUTPUT)) + (port PLLADRO2 (direction OUTPUT)) + (port PLLADRO1 (direction OUTPUT)) + (port PLLADRO0 (direction OUTPUT)) + (port PLLDATO7 (direction OUTPUT)) + (port PLLDATO6 (direction OUTPUT)) + (port PLLDATO5 (direction OUTPUT)) + (port PLLDATO4 (direction OUTPUT)) + (port PLLDATO3 (direction OUTPUT)) + (port PLLDATO2 (direction OUTPUT)) + (port PLLDATO1 (direction OUTPUT)) + (port PLLDATO0 (direction OUTPUT)) + (port I2C1SCLO (direction OUTPUT)) + (port I2C1SCLOEN (direction OUTPUT)) + (port I2C1SDAO (direction OUTPUT)) + (port I2C1SDAOEN (direction OUTPUT)) + (port I2C2SCLO (direction OUTPUT)) + (port I2C2SCLOEN (direction OUTPUT)) + (port I2C2SDAO (direction OUTPUT)) + (port I2C2SDAOEN (direction OUTPUT)) + (port I2C1IRQO (direction OUTPUT)) + (port I2C2IRQO (direction OUTPUT)) + (port SPISCKO (direction OUTPUT)) + (port SPISCKEN (direction OUTPUT)) + (port SPIMISOO (direction OUTPUT)) + (port SPIMISOEN (direction OUTPUT)) + (port SPIMOSIO (direction OUTPUT)) + (port SPIMOSIEN (direction OUTPUT)) + (port SPIMCSN0 (direction OUTPUT)) + (port SPIMCSN1 (direction OUTPUT)) + (port SPIMCSN2 (direction OUTPUT)) + (port SPIMCSN3 (direction OUTPUT)) + (port SPIMCSN4 (direction OUTPUT)) + (port SPIMCSN5 (direction OUTPUT)) + (port SPIMCSN6 (direction OUTPUT)) + (port SPIMCSN7 (direction OUTPUT)) + (port SPICSNEN (direction OUTPUT)) + (port SPIIRQO (direction OUTPUT)) + (port TCINT (direction OUTPUT)) + (port TCOC (direction OUTPUT)) + (port WBCUFMIRQ (direction OUTPUT)) + (port CFGWAKE (direction OUTPUT)) + (port CFGSTDBY (direction OUTPUT)) + ) + (property TC_ICAPTURE (string "DISABLED")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICR_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_TOP_SEL (string "OFF")) + (property TC_RESETN (string "ENABLED")) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_OCR_SET (integer 32767)) + (property TC_TOP_SET (integer 65535)) + (property GSR (string "ENABLED")) + (property TC_CCLK_SEL (integer 1)) + (property TC_SCLK_SEL (string "PCLOCK")) + (property TC_MODE (string "CTCM")) + (property SPI_WAKEUP (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_MODE (string "MASTER")) + (property I2C2_WAKEUP (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C2_ADDRESSING (string "7BIT")) + (property I2C1_ADDRESSING (string "7BIT")) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + (property UFM_INIT_FILE_NAME (string "../RAM2GS-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_PAGES (integer 321)) + (property DEV_DENSITY (string "1200L")) + (property EFB_WB_CLK_FREQ (string "66.7")) + (property EFB_UFM (string "ENABLED")) + (property EFB_TC_PORTMODE (string "WB")) + (property EFB_TC (string "DISABLED")) + (property EFB_SPI (string "DISABLED")) + (property EFB_I2C2 (string "DISABLED")) + (property EFB_I2C1 (string "DISABLED")) + (property orig_inst_of (string "EFB")) + ) + ) + (cell EHXPLLJ (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port CLKI (direction INPUT)) + (port CLKFB (direction INPUT)) + (port PHASESEL1 (direction INPUT)) + (port PHASESEL0 (direction INPUT)) + (port PHASEDIR (direction INPUT)) + (port PHASESTEP (direction INPUT)) + (port LOADREG (direction INPUT)) + (port STDBY (direction INPUT)) + (port PLLWAKESYNC (direction INPUT)) + (port RST (direction INPUT)) + (port RESETM (direction INPUT)) + (port RESETC (direction INPUT)) + (port RESETD (direction INPUT)) + (port ENCLKOP (direction INPUT)) + (port ENCLKOS (direction INPUT)) + (port ENCLKOS2 (direction INPUT)) + (port ENCLKOS3 (direction INPUT)) + (port PLLCLK (direction INPUT)) + (port PLLRST (direction INPUT)) + (port PLLSTB (direction INPUT)) + (port PLLWE (direction INPUT)) + (port PLLDATI7 (direction INPUT)) + (port PLLDATI6 (direction INPUT)) + (port PLLDATI5 (direction INPUT)) + (port PLLDATI4 (direction INPUT)) + (port PLLDATI3 (direction INPUT)) + (port PLLDATI2 (direction INPUT)) + (port PLLDATI1 (direction INPUT)) + (port PLLDATI0 (direction INPUT)) + (port PLLADDR4 (direction INPUT)) + (port PLLADDR3 (direction INPUT)) + (port PLLADDR2 (direction INPUT)) + (port PLLADDR1 (direction INPUT)) + (port PLLADDR0 (direction INPUT)) + (port CLKOP (direction OUTPUT)) + (port CLKOS (direction OUTPUT)) + (port CLKOS2 (direction OUTPUT)) + (port CLKOS3 (direction OUTPUT)) + (port LOCK (direction OUTPUT)) + (port INTLOCK (direction OUTPUT)) + (port REFCLK (direction OUTPUT)) + (port PLLDATO7 (direction OUTPUT)) + (port PLLDATO6 (direction OUTPUT)) + (port PLLDATO5 (direction OUTPUT)) + (port PLLDATO4 (direction OUTPUT)) + (port PLLDATO3 (direction OUTPUT)) + (port PLLDATO2 (direction OUTPUT)) + (port PLLDATO1 (direction OUTPUT)) + (port PLLDATO0 (direction OUTPUT)) + (port PLLACK (direction OUTPUT)) + (port DPHSRC (direction OUTPUT)) + (port CLKINTFB (direction OUTPUT)) + ) + (property INTFB_WAKE (string "DISABLED")) + (property DDRST_ENA (string "DISABLED")) + (property DCRST_ENA (string "DISABLED")) + (property MRST_ENA (string "DISABLED")) + (property PLLRST_ENA (string "DISABLED")) + (property DPHASE_SOURCE (string "DISABLED")) + (property STDBY_ENABLE (string "DISABLED")) + (property PLL_LOCK_MODE (integer 0)) + (property OUTDIVIDER_MUXD2 (string "DIVD")) + (property OUTDIVIDER_MUXC2 (string "DIVC")) + (property OUTDIVIDER_MUXB2 (string "DIVB")) + (property OUTDIVIDER_MUXA2 (string "DIVA")) + (property PREDIVIDER_MUXD1 (integer 0)) + (property PREDIVIDER_MUXC1 (integer 0)) + (property PREDIVIDER_MUXB1 (integer 0)) + (property PREDIVIDER_MUXA1 (integer 0)) + (property PLL_USE_WB (string "DISABLED")) + (property CLKOS_TRIM_DELAY (integer 0)) + (property CLKOS_TRIM_POL (string "FALLING")) + (property CLKOP_TRIM_DELAY (integer 0)) + (property CLKOP_TRIM_POL (string "RISING")) + (property FRACN_DIV (integer 0)) + (property FRACN_ENABLE (string "DISABLED")) + (property FEEDBK_PATH (string "CLKOP")) + (property CLKOS3_FPHASE (integer 0)) + (property CLKOS2_FPHASE (integer 0)) + (property CLKOS_FPHASE (integer 0)) + (property CLKOP_FPHASE (integer 0)) + (property CLKOS3_CPHASE (integer 0)) + (property CLKOS2_CPHASE (integer 0)) + (property CLKOS_CPHASE (integer 0)) + (property CLKOP_CPHASE (integer 7)) + (property VCO_BYPASS_D0 (string "DISABLED")) + (property VCO_BYPASS_C0 (string "DISABLED")) + (property VCO_BYPASS_B0 (string "DISABLED")) + (property VCO_BYPASS_A0 (string "DISABLED")) + (property CLKOS3_ENABLE (string "DISABLED")) + (property CLKOS2_ENABLE (string "DISABLED")) + (property CLKOS_ENABLE (string "DISABLED")) + (property CLKOP_ENABLE (string "ENABLED")) + (property CLKOS3_DIV (integer 1)) + (property CLKOS2_DIV (integer 1)) + (property CLKOS_DIV (integer 1)) + (property CLKOP_DIV (integer 8)) + (property CLKFB_DIV (integer 6)) + (property CLKI_DIV (integer 13)) + (property orig_inst_of (string "EHXPLLJ")) + ) + ) + (cell REFB (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT)) + (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) + (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) + (port wb_ack (direction OUTPUT)) + (port wb_we (direction INPUT)) + (port wb_cyc_stb (direction INPUT)) + (port wb_rst (direction INPUT)) + (port PCLK (direction INPUT)) + ) + (contents + (instance EFBInst_0 (viewRef verilog (cellRef EFB)) + (property EFB_WB_CLK_FREQ (string "66.7")) + (property EFB_I2C1 (string "DISABLED")) + (property I2C1_ADDRESSING (string "7BIT")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property EFB_I2C2 (string "DISABLED")) + (property I2C2_ADDRESSING (string "7BIT")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C2_WAKEUP (string "DISABLED")) + (property EFB_SPI (string "DISABLED")) + (property SPI_MODE (string "MASTER")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_WAKEUP (string "DISABLED")) + (property EFB_TC (string "DISABLED")) + (property EFB_TC_PORTMODE (string "WB")) + (property TC_SCLK_SEL (string "PCLOCK")) + (property TC_MODE (string "CTCM")) + (property TC_CCLK_SEL (integer 1)) + (property GSR (string "ENABLED")) + (property TC_TOP_SET (integer 65535)) + (property TC_OCR_SET (integer 32767)) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_RESETN (string "ENABLED")) + (property TC_TOP_SEL (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_ICR_INT (string "OFF")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICAPTURE (string "DISABLED")) + (property EFB_UFM (string "ENABLED")) + (property DEV_DENSITY (string "1200L")) + (property UFM_INIT_PAGES (integer 321)) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_FILE_NAME (string "../RAM2GS-LCMXO2.mem")) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (net PCLK (joined + (portRef PCLK) + (portRef WBCLKI (instanceRef EFBInst_0)) + )) + (net wb_rst (joined + (portRef wb_rst) + (portRef WBRSTI (instanceRef EFBInst_0)) + )) + (net wb_cyc_stb (joined + (portRef wb_cyc_stb) + (portRef WBSTBI (instanceRef EFBInst_0)) + (portRef WBCYCI (instanceRef EFBInst_0)) + )) + (net wb_we (joined + (portRef wb_we) + (portRef WBWEI (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef (member wb_adr 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef (member wb_adr 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef (member wb_adr 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef (member wb_adr 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef (member wb_adr 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef (member wb_adr 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef (member wb_adr 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef (member wb_adr 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef (member wb_dati 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef (member wb_dati 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef (member wb_dati 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef (member wb_dati 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef (member wb_dati 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef (member wb_dati 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef (member wb_dati 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef (member wb_dati 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)) + )) + (net GND (joined + (portRef Z (instanceRef GND)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + )) + (net VCC (joined + (portRef Z (instanceRef VCC)) + (portRef UFMSN (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_7 "wb_dat_o_1[7]") (joined + (portRef WBDATO7 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_6 "wb_dat_o_1[6]") (joined + (portRef WBDATO6 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_5 "wb_dat_o_1[5]") (joined + (portRef WBDATO5 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_4 "wb_dat_o_1[4]") (joined + (portRef WBDATO4 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_3 "wb_dat_o_1[3]") (joined + (portRef WBDATO3 (instanceRef EFBInst_0)) + )) + (net (rename wb_dat_o_1_2 "wb_dat_o_1[2]") (joined + (portRef WBDATO2 (instanceRef EFBInst_0)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef WBDATO1 (instanceRef EFBInst_0)) + (portRef (member wb_dato 0)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef WBDATO0 (instanceRef EFBInst_0)) + (portRef (member wb_dato 1)) + )) + (net wb_ack (joined + (portRef WBACKO (instanceRef EFBInst_0)) + (portRef wb_ack) + )) + (net PLLCLKO (joined + (portRef PLLCLKO (instanceRef EFBInst_0)) + )) + (net PLLRSTO (joined + (portRef PLLRSTO (instanceRef EFBInst_0)) + )) + (net PLL0STBO (joined + (portRef PLL0STBO (instanceRef EFBInst_0)) + )) + (net PLL1STBO (joined + (portRef PLL1STBO (instanceRef EFBInst_0)) + )) + (net PLLWEO (joined + (portRef PLLWEO (instanceRef EFBInst_0)) + )) + (net PLLADRO4 (joined + (portRef PLLADRO4 (instanceRef EFBInst_0)) + )) + (net PLLADRO3 (joined + (portRef PLLADRO3 (instanceRef EFBInst_0)) + )) + (net PLLADRO2 (joined + (portRef PLLADRO2 (instanceRef EFBInst_0)) + )) + (net PLLADRO1 (joined + (portRef PLLADRO1 (instanceRef EFBInst_0)) + )) + (net PLLADRO0 (joined + (portRef PLLADRO0 (instanceRef EFBInst_0)) + )) + (net PLLDATO7_0 (joined + (portRef PLLDATO7 (instanceRef EFBInst_0)) + )) + (net PLLDATO6_0 (joined + (portRef PLLDATO6 (instanceRef EFBInst_0)) + )) + (net PLLDATO5_0 (joined + (portRef PLLDATO5 (instanceRef EFBInst_0)) + )) + (net PLLDATO4_0 (joined + (portRef PLLDATO4 (instanceRef EFBInst_0)) + )) + (net PLLDATO3_0 (joined + (portRef PLLDATO3 (instanceRef EFBInst_0)) + )) + (net PLLDATO2_0 (joined + (portRef PLLDATO2 (instanceRef EFBInst_0)) + )) + (net PLLDATO1_0 (joined + (portRef PLLDATO1 (instanceRef EFBInst_0)) + )) + (net PLLDATO0_0 (joined + (portRef PLLDATO0 (instanceRef EFBInst_0)) + )) + (net I2C1SCLO (joined + (portRef I2C1SCLO (instanceRef EFBInst_0)) + )) + (net I2C1SCLOEN (joined + (portRef I2C1SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C1SDAO (joined + (portRef I2C1SDAO (instanceRef EFBInst_0)) + )) + (net I2C1SDAOEN (joined + (portRef I2C1SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C2SCLO (joined + (portRef I2C2SCLO (instanceRef EFBInst_0)) + )) + (net I2C2SCLOEN (joined + (portRef I2C2SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C2SDAO (joined + (portRef I2C2SDAO (instanceRef EFBInst_0)) + )) + (net I2C2SDAOEN (joined + (portRef I2C2SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C1IRQO (joined + (portRef I2C1IRQO (instanceRef EFBInst_0)) + )) + (net I2C2IRQO (joined + (portRef I2C2IRQO (instanceRef EFBInst_0)) + )) + (net SPISCKO (joined + (portRef SPISCKO (instanceRef EFBInst_0)) + )) + (net SPISCKEN (joined + (portRef SPISCKEN (instanceRef EFBInst_0)) + )) + (net SPIMISOO (joined + (portRef SPIMISOO (instanceRef EFBInst_0)) + )) + (net SPIMISOEN (joined + (portRef SPIMISOEN (instanceRef EFBInst_0)) + )) + (net SPIMOSIO (joined + (portRef SPIMOSIO (instanceRef EFBInst_0)) + )) + (net SPIMOSIEN (joined + (portRef SPIMOSIEN (instanceRef EFBInst_0)) + )) + (net SPIMCSN0 (joined + (portRef SPIMCSN0 (instanceRef EFBInst_0)) + )) + (net SPIMCSN1 (joined + (portRef SPIMCSN1 (instanceRef EFBInst_0)) + )) + (net SPIMCSN2 (joined + (portRef SPIMCSN2 (instanceRef EFBInst_0)) + )) + (net SPIMCSN3 (joined + (portRef SPIMCSN3 (instanceRef EFBInst_0)) + )) + (net SPIMCSN4 (joined + (portRef SPIMCSN4 (instanceRef EFBInst_0)) + )) + (net SPIMCSN5 (joined + (portRef SPIMCSN5 (instanceRef EFBInst_0)) + )) + (net SPIMCSN6 (joined + (portRef SPIMCSN6 (instanceRef EFBInst_0)) + )) + (net SPIMCSN7 (joined + (portRef SPIMCSN7 (instanceRef EFBInst_0)) + )) + (net SPICSNEN (joined + (portRef SPICSNEN (instanceRef EFBInst_0)) + )) + (net SPIIRQO (joined + (portRef SPIIRQO (instanceRef EFBInst_0)) + )) + (net TCINT (joined + (portRef TCINT (instanceRef EFBInst_0)) + )) + (net TCOC (joined + (portRef TCOC (instanceRef EFBInst_0)) + )) + (net wbc_ufm_irq (joined + (portRef WBCUFMIRQ (instanceRef EFBInst_0)) + )) + (net CFGWAKE (joined + (portRef CFGWAKE (instanceRef EFBInst_0)) + )) + (net CFGSTDBY (joined + (portRef CFGSTDBY (instanceRef EFBInst_0)) + )) + ) + (property NGD_DRC_MASK (integer 1)) + (property orig_inst_of (string "REFB")) + ) + ) + (cell RPLL (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port ICLK (direction INPUT)) + (port PCLK (direction OUTPUT)) + ) + (contents + (instance PLLInst_0 (viewRef verilog (cellRef EHXPLLJ)) + (property FREQUENCY_PIN_CLKOP (string "61.384615")) + (property FREQUENCY_PIN_CLKI (string "133.000000")) + (property ICP_CURRENT (string "7")) + (property LPF_RESISTOR (string "8")) + (property FEEDBK_PATH (string "CLKOP")) + (property CLKI_DIV (integer 13)) + (property CLKFB_DIV (integer 6)) + (property CLKOP_DIV (integer 8)) + (property CLKOS_DIV (integer 1)) + (property CLKOS2_DIV (integer 1)) + (property CLKOS3_DIV (integer 1)) + (property CLKOP_ENABLE (string "ENABLED")) + (property VCO_BYPASS_A0 (string "DISABLED")) + (property PREDIVIDER_MUXA1 (integer 0)) + (property OUTDIVIDER_MUXA2 (string "DIVA")) + (property CLKOS_ENABLE (string "DISABLED")) + (property VCO_BYPASS_B0 (string "DISABLED")) + (property PREDIVIDER_MUXB1 (integer 0)) + (property OUTDIVIDER_MUXB2 (string "DIVB")) + (property CLKOS2_ENABLE (string "DISABLED")) + (property VCO_BYPASS_C0 (string "DISABLED")) + (property PREDIVIDER_MUXC1 (integer 0)) + (property OUTDIVIDER_MUXC2 (string "DIVC")) + (property CLKOS3_ENABLE (string "DISABLED")) + (property VCO_BYPASS_D0 (string "DISABLED")) + (property PREDIVIDER_MUXD1 (integer 0)) + (property OUTDIVIDER_MUXD2 (string "DIVD")) + (property FRACN_ENABLE (string "DISABLED")) + (property FRACN_DIV (integer 0)) + (property CLKOP_TRIM_POL (string "RISING")) + (property CLKOP_TRIM_DELAY (integer 0)) + (property CLKOS_TRIM_POL (string "FALLING")) + (property CLKOS_TRIM_DELAY (integer 0)) + (property PLL_LOCK_MODE (integer 0)) + (property CLKOP_CPHASE (integer 7)) + (property CLKOP_FPHASE (integer 0)) + (property CLKOS_CPHASE (integer 0)) + (property CLKOS_FPHASE (integer 0)) + (property CLKOS2_CPHASE (integer 0)) + (property CLKOS2_FPHASE (integer 0)) + (property CLKOS3_CPHASE (integer 0)) + (property CLKOS3_FPHASE (integer 0)) + (property PLL_USE_WB (string "DISABLED")) + (property DPHASE_SOURCE (string "DISABLED")) + (property STDBY_ENABLE (string "DISABLED")) + (property INTFB_WAKE (string "DISABLED")) + (property PLLRST_ENA (string "DISABLED")) + (property MRST_ENA (string "DISABLED")) + (property DCRST_ENA (string "DISABLED")) + (property DDRST_ENA (string "DISABLED")) + ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (net (rename CLKOP_inferred_clock "PCLK") (joined + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef PCLK) + (portRef CLKOP (instanceRef PLLInst_0)) + )) + (net ICLK (joined + (portRef ICLK) + (portRef CLKI (instanceRef PLLInst_0)) + )) + (net GND (joined + (portRef Z (instanceRef GND)) + (portRef PLLADDR0 (instanceRef PLLInst_0)) + (portRef PLLADDR1 (instanceRef PLLInst_0)) + (portRef PLLADDR2 (instanceRef PLLInst_0)) + (portRef PLLADDR3 (instanceRef PLLInst_0)) + (portRef PLLADDR4 (instanceRef PLLInst_0)) + (portRef PLLDATI0 (instanceRef PLLInst_0)) + (portRef PLLDATI1 (instanceRef PLLInst_0)) + (portRef PLLDATI2 (instanceRef PLLInst_0)) + (portRef PLLDATI3 (instanceRef PLLInst_0)) + (portRef PLLDATI4 (instanceRef PLLInst_0)) + (portRef PLLDATI5 (instanceRef PLLInst_0)) + (portRef PLLDATI6 (instanceRef PLLInst_0)) + (portRef PLLDATI7 (instanceRef PLLInst_0)) + (portRef PLLWE (instanceRef PLLInst_0)) + (portRef PLLSTB (instanceRef PLLInst_0)) + (portRef PLLRST (instanceRef PLLInst_0)) + (portRef PLLCLK (instanceRef PLLInst_0)) + (portRef ENCLKOS3 (instanceRef PLLInst_0)) + (portRef ENCLKOS2 (instanceRef PLLInst_0)) + (portRef ENCLKOS (instanceRef PLLInst_0)) + (portRef ENCLKOP (instanceRef PLLInst_0)) + (portRef RESETD (instanceRef PLLInst_0)) + (portRef RESETC (instanceRef PLLInst_0)) + (portRef RESETM (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)) + (portRef PLLWAKESYNC (instanceRef PLLInst_0)) + (portRef STDBY (instanceRef PLLInst_0)) + (portRef LOADREG (instanceRef PLLInst_0)) + (portRef PHASESTEP (instanceRef PLLInst_0)) + (portRef PHASEDIR (instanceRef PLLInst_0)) + (portRef PHASESEL0 (instanceRef PLLInst_0)) + (portRef PHASESEL1 (instanceRef PLLInst_0)) + )) + (net CLKOS (joined + (portRef CLKOS (instanceRef PLLInst_0)) + )) + (net CLKOS2 (joined + (portRef CLKOS2 (instanceRef PLLInst_0)) + )) + (net CLKOS3 (joined + (portRef CLKOS3 (instanceRef PLLInst_0)) + )) + (net LOCK (joined + (portRef LOCK (instanceRef PLLInst_0)) + )) + (net INTLOCK (joined + (portRef INTLOCK (instanceRef PLLInst_0)) + )) + (net REFCLK (joined + (portRef REFCLK (instanceRef PLLInst_0)) + )) + (net PLLDATO7 (joined + (portRef PLLDATO7 (instanceRef PLLInst_0)) + )) + (net PLLDATO6 (joined + (portRef PLLDATO6 (instanceRef PLLInst_0)) + )) + (net PLLDATO5 (joined + (portRef PLLDATO5 (instanceRef PLLInst_0)) + )) + (net PLLDATO4 (joined + (portRef PLLDATO4 (instanceRef PLLInst_0)) + )) + (net PLLDATO3 (joined + (portRef PLLDATO3 (instanceRef PLLInst_0)) + )) + (net PLLDATO2 (joined + (portRef PLLDATO2 (instanceRef PLLInst_0)) + )) + (net PLLDATO1 (joined + (portRef PLLDATO1 (instanceRef PLLInst_0)) + )) + (net PLLDATO0 (joined + (portRef PLLDATO0 (instanceRef PLLInst_0)) + )) + (net PLLACK (joined + (portRef PLLACK (instanceRef PLLInst_0)) + )) + (net DPHSRC (joined + (portRef DPHSRC (instanceRef PLLInst_0)) + )) + (net CLKINTFB (joined + (portRef CLKINTFB (instanceRef PLLInst_0)) + )) + ) + (property NGD_DRC_MASK (integer 1)) + (property orig_inst_of (string "RPLL")) + ) + ) + (cell ODDRXE (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port D0 (direction INPUT)) + (port D1 (direction INPUT)) + (port SCLK (direction INPUT)) + (port RST (direction INPUT)) + (port Q (direction OUTPUT)) + ) + (property GSR (string "ENABLED")) + (property orig_inst_of (string "ODDRXE")) + ) + ) + (cell RAM2GS (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port PHI2 (direction INPUT)) + (port (array (rename main "MAin[9:0]") 10) (direction INPUT)) + (port (array (rename crow "CROW[1:0]") 2) (direction INPUT)) + (port (array (rename din "Din[7:0]") 8) (direction INPUT)) + (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) + (port nCCAS (direction INPUT)) + (port nCRAS (direction INPUT)) + (port nFWE (direction INPUT)) + (port LED (direction OUTPUT)) + (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT)) + (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) + (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) + (port nRCS (direction OUTPUT)) + (port RCLK (direction INPUT)) + (port RCLKout (direction OUTPUT)) + (port RCKE (direction OUTPUT)) + (port nRWE (direction OUTPUT)) + (port nRRAS (direction OUTPUT)) + (port nRCAS (direction OUTPUT)) + (port RDQMH (direction OUTPUT)) + (port RDQML (direction OUTPUT)) + ) + (contents + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance Ready_RNILCP9 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename wb_dati_5_1_iv_RNO_0_3 "wb_dati_5_1_iv_RNO_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance un1_FS_36_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance (rename wb_adr_RNO_1_0 "wb_adr_RNO_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(B+A))+D (!C A+C (B+A)))")) + ) + (instance (rename wb_adr_5_i_a3_RNO_0 "wb_adr_5_i_a3_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!C B+C (!B !A)))")) + ) + (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B !A)+D (!C (!B !A+B A)+C (!B !A)))")) + ) + (instance (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance (rename FS_RNI3V8E_9 "FS_RNI3V8E[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) + ) + (instance wb_we_0_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))")) + ) + (instance (rename FS_RNI4OK11_14 "FS_RNI4OK11[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance un1_FS_36_1_0_a3_0_0_RNI0J061 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance wb_rst_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) + ) + (instance PHI2r3_RNIS5A51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !A+D (!C (B+!A)+C !A))")) + ) + (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !A+D (!C !A+C (!B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_RNO_3 "wb_dati_5_1_iv_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance CmdUFMData_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (B+A)+C A))")) + ) + (instance CmdEnable_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance CmdEnable_1_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance CmdEnable_1_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))")) + ) + (instance (rename wb_adr_5_1 "wb_adr_5[1]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance (rename wb_adr_5_bm_1 "wb_adr_5_bm[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (!C (B A)+C (!B+A)))")) + ) + (instance (rename wb_adr_5_am_1 "wb_adr_5_am[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)+C (B A))+D (B A))")) + ) + (instance (rename S_1__fb "S_1_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename C1Submitted_CN "C1Submitted.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_0 "RowA_0io[0]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_1 "RowA_0io[1]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_2 "RowA_0io[2]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_3 "RowA_0io[3]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_4 "RowA_0io[4]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_5 "RowA_0io[5]") (viewRef PRIM (cellRef IFS1P3JX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_6 "RowA_0io[6]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_7 "RowA_0io[7]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_8 "RowA_0io[8]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RowA_0io_9 "RowA_0io[9]") (viewRef PRIM (cellRef IFS1P3JX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef IFS1P3IX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + (property INIT (string "1")) + ) + (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + (property INIT (string "1")) + ) + (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + (property INIT (string "1")) + ) + (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + (property INIT (string "1")) + ) + (instance RA11_0io (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance wb_we (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance wb_rst (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance wb_req (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdValid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdUFMWrite (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdUFMShift (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdUFMData (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + (property INIT (string "0")) + ) + (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCLKout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename wb_dati_5_1_iv_5 "wb_dati_5_1_iv[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_2 "wb_dati_5_1_iv[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_7 "wb_dati_5_1_iv[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (!B+A)))")) + ) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !A)+D (!C (!B !A)))")) + ) + (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))")) + ) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (!C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_6 "wb_dati_5_1_iv[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename wb_dati_5_1_iv_4 "wb_dati_5_1_iv[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_3 "wb_dati_5_1_iv[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_dati_5_1_iv_1 "wb_dati_5_1_iv[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_1_2_2 "wb_dati_5_1_iv_1_2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance (rename FS_RNIFUUT2_9 "FS_RNIFUUT2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance XOR8MEG17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_ADWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C B+C (B+A)))")) + ) + (instance un1_FS_38_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B A)))")) + ) + (instance wb_cyc_stb_4_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (!C A+C (!B+A)))")) + ) + (instance nRWE_0_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D !A)")) + ) + (instance RA10_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance (rename wb_dati_5_0_iv_0 "wb_dati_5_0_iv[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance CmdEnable12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance CmdEnable13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_FS_36 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+!A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_6 "wb_dati_5_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_1_7 "wb_dati_5_1_iv_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_2_4 "wb_dati_5_1_iv_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance CmdUFMShift_3_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C !B))")) + ) + (instance CmdUFMWrite_3_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C B))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)))")) + ) + (instance CmdValid_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C !A)")) + ) + (instance un1_PHI2r3_RNIESG21 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C (!B+A))")) + ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance CmdLEDEN_4_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance Cmdn8MEGEN_4_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A)+C (B+A))")) + ) + (instance nRRAS_5_u_i_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A)+D (!C (!B+A)+C !B))")) + ) + (instance nRRAS_5_u_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) + ) + (instance un1_wb_we54_1_RNIH7RQ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance (rename FS_RNIVQ281_10 "FS_RNIVQ281[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_RNO_4 "wb_dati_5_1_iv_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance C1WR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance un1_FS_21_1_i_o3_RNIAU7A1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance un1_FS_26_1_0_a2_RNI761E1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance RCKEEN_8_u_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (C+(!B+A)))")) + ) + (instance un1_FS_36_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_1 "wb_dati_5_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename wb_adr_5_4 "wb_adr_5[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance (rename wb_adr_5_6 "wb_adr_5[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance (rename wb_adr_5_5 "wb_adr_5[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D (C B))")) + ) + (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance un1_wb_we54_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A+B !A)+C (B A)))")) + ) + (instance (rename FS_RNI7U6M_14 "FS_RNI7U6M[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance nRWE_0_i_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+A)))")) + ) + (instance (rename wb_dati_5_0_iv_RNO_0 "wb_dati_5_0_iv_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename wb_adr_5_i_a3_0 "wb_adr_5_i_a3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A+B !A)))")) + ) + (instance C1WR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance wb_cyc_stb_4_iv_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance ADWR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (C !A))")) + ) + (instance un1_FS_36_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D !A)")) + ) + (instance (rename wb_adr_5_i_1_0 "wb_adr_5_i_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) + ) + (instance CmdLEDEN_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C B)")) + ) + (instance Cmdn8MEGEN_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C !B)")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance ADSubmitted_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B A)))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (!C (B+A)+C A))")) + ) + (instance InitReady2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance XOR8MEG13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_Din_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance RCKEEN_8_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (C (B !A)))")) + ) + (instance ADWR_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance (rename wb_adr_5_i_0_0 "wb_adr_5_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B+!A))+D (C+(!B !A)))")) + ) + (instance CmdEnable13_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) + ) + (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance C1Submitted_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B A))")) + ) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance IS_0_sqmuxa_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance nRWE_0_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance RCKEEN_8_u_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance nRRAS_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A+B !A)+C B)")) + ) + (instance (rename FS_RNIQV0F_16 "FS_RNIQV0F[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename wb_adr_5_i_a3_1_0 "wb_adr_5_i_a3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A))")) + ) + (instance InitReady2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance un1_FS_36_1_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A)))")) + ) + (instance un1_PHI2r3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance XOR8MEG10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance RCKEEN_8_u_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+!A))")) + ) + (instance un1_FS_33_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance un1_Bank_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_Bank_1_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance wb_cyc_stb_4_iv_0_a3_0_4_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance wb_cyc_stb_4_iv_0_a3_0_4_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance un1_FS_36_2_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A))")) + ) + (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_RNO_6 "wb_dati_5_1_iv_0_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename wb_dati_5_1_iv_RNO_0_4 "wb_dati_5_1_iv_RNO_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance C1WR_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A))")) + ) + (instance (rename FS_RNIK7MA_14 "FS_RNIK7MA[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance (rename FS_RNI409E_9 "FS_RNI409E[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance CmdEnable13_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance CmdEnable12_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance CmdEnable12_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance LEDEN_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_4 "un9_RA[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_5 "un9_RA[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance un1_FS_21_1_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename FS_RNI8P57_11 "FS_RNI8P57[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance CmdUFMWrite_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance RA10_2_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_3 "wb_adr_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename FS_RNIVRDB_14 "FS_RNIVRDB[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance un1_FS_20_3_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance un1_FS_30_1_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance un1_FS_26_2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance un1_FS_26_1_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance CmdEnable13_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance InitReady2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance ADWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance ADWR_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_FS_38_i_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_am_RNO_1 "wb_adr_5_am_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)+C (B A))+D (!C (!B+!A)))")) + ) + (instance XOR8MEG_3_u_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (C (!B !A)))")) + ) + (instance XOR8MEG_3_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (C A))")) + ) + (instance wb_we_0_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !A+C (B !A))+D (!C+(B !A)))")) + ) + (instance wb_we_0_0_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A))")) + ) + (instance wb_we_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(B A))+D (B A))")) + ) + (instance (rename wb_adr_RNO_0_0 "wb_adr_RNO_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (!C !A+C (!B+!A)))")) + ) + (instance (rename wb_adr_RNO_0 "wb_adr_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)))")) + ) + (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(C+(B+!A)))")) + ) + (instance (rename wb_adr_cnst_sn_m2_i_o3 "wb_adr_cnst_sn.m2_i_o3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+!A)))")) + ) + (instance wb_rst10_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename FS_RNI3V8E_0_9 "FS_RNI3V8E_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename FS_RNI8OTF1_13 "FS_RNI8OTF1[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_3 "wb_dati_5_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B A))+D (B A))")) + ) + (instance un1_FS_36_1_0_a3_0_0_RNI60IN2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)+C A)+D A)")) + ) + (instance CmdValid_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x5002")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_15 "FS_cry_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance OSCH_inst (viewRef PRIM (cellRef OSCH (libraryRef LUCENT))) + (property NOM_FREQ (string "133.00")) + ) + (instance rclk_oddr (viewRef verilog (cellRef ODDRXE)) ) + (instance rpll (viewRef netlist (cellRef RPLL)) + ) + (instance ufmefb (viewRef netlist (cellRef REFB)) + ) + (net OSCH_inst_SEDSTDBY (joined + (portRef SEDSTDBY (instanceRef OSCH_inst)) + )) + (net un1_ADWR (joined + (portRef Z (instanceRef un1_ADWR)) + (portRef B (instanceRef C1Submitted_1)) + (portRef B (instanceRef ADSubmitted_2)) + (portRef B (instanceRef un1_CMDWR)) + )) + (net ICLK (joined + (portRef OSC (instanceRef OSCH_inst)) + (portRef ICLK (instanceRef rpll)) + )) + (net PCLK (joined + (portRef PCLK (instanceRef rpll)) + (portRef PCLK (instanceRef ufmefb)) + (portRef SCLK (instanceRef rclk_oddr)) + (portRef CK (instanceRef CASr)) + (portRef CK (instanceRef CASr2)) + (portRef CK (instanceRef CASr3)) + (portRef CK (instanceRef FS_17)) + (portRef CK (instanceRef FS_16)) + (portRef CK (instanceRef FS_15)) + (portRef CK (instanceRef FS_14)) + (portRef CK (instanceRef FS_13)) + (portRef CK (instanceRef FS_12)) + (portRef CK (instanceRef FS_11)) + (portRef CK (instanceRef FS_10)) + (portRef CK (instanceRef FS_9)) + (portRef CK (instanceRef FS_8)) + (portRef CK (instanceRef FS_7)) + (portRef CK (instanceRef FS_6)) + (portRef CK (instanceRef FS_5)) + (portRef CK (instanceRef FS_4)) + (portRef CK (instanceRef FS_3)) + (portRef CK (instanceRef FS_2)) + (portRef CK (instanceRef FS_1)) + (portRef CK (instanceRef FS_0)) + (portRef CK (instanceRef IS_3)) + (portRef CK (instanceRef IS_2)) + (portRef CK (instanceRef IS_1)) + (portRef CK (instanceRef IS_0)) + (portRef CK (instanceRef InitReady)) + (portRef CK (instanceRef LEDEN)) + (portRef CK (instanceRef PHI2r2)) + (portRef CK (instanceRef PHI2r3)) + (portRef CK (instanceRef RASr)) + (portRef CK (instanceRef RASr2)) + (portRef CK (instanceRef RASr3)) + (portRef CK (instanceRef RCKE)) + (portRef CK (instanceRef RCKEEN)) + (portRef CK (instanceRef Ready)) + (portRef CK (instanceRef S_1)) + (portRef CK (instanceRef S_0)) + (portRef CK (instanceRef n8MEGEN)) + (portRef CK (instanceRef nRowColSel)) + (portRef CK (instanceRef wb_adr_7)) + (portRef CK (instanceRef wb_adr_6)) + (portRef CK (instanceRef wb_adr_5)) + (portRef CK (instanceRef wb_adr_4)) + (portRef CK (instanceRef wb_adr_3)) + (portRef CK (instanceRef wb_adr_2)) + (portRef CK (instanceRef wb_adr_1)) + (portRef CK (instanceRef wb_adr_0)) + (portRef CK (instanceRef wb_cyc_stb)) + (portRef CK (instanceRef wb_dati_7)) + (portRef CK (instanceRef wb_dati_6)) + (portRef CK (instanceRef wb_dati_5)) + (portRef CK (instanceRef wb_dati_4)) + (portRef CK (instanceRef wb_dati_3)) + (portRef CK (instanceRef wb_dati_2)) + (portRef CK (instanceRef wb_dati_1)) + (portRef CK (instanceRef wb_dati_0)) + (portRef CK (instanceRef wb_req)) + (portRef CK (instanceRef wb_rst)) + (portRef CK (instanceRef wb_we)) + (portRef SCLK (instanceRef RA10_0io)) + (portRef SCLK (instanceRef nRCAS_0io)) + (portRef SCLK (instanceRef nRCS_0io)) + (portRef SCLK (instanceRef nRRAS_0io)) + (portRef SCLK (instanceRef nRWE_0io)) + (portRef SCLK (instanceRef PHI2r_0io)) + )) + (net wb_rst (joined + (portRef Q (instanceRef wb_rst)) + (portRef wb_rst (instanceRef ufmefb)) + )) + (net wb_cyc_stb (joined + (portRef Q (instanceRef wb_cyc_stb)) + (portRef wb_cyc_stb (instanceRef ufmefb)) + )) + (net wb_we (joined + (portRef Q (instanceRef wb_we)) + (portRef wb_we (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_0_iv_0)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef Q (instanceRef wb_adr_0)) + (portRef (member wb_adr 7) (instanceRef ufmefb)) + (portRef A (instanceRef wb_adr_5_am_1)) + (portRef A (instanceRef wb_adr_5_bm_1)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef Q (instanceRef wb_adr_1)) + (portRef (member wb_adr 6) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_2)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef Q (instanceRef wb_adr_2)) + (portRef (member wb_adr 5) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_3)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef Q (instanceRef wb_adr_3)) + (portRef (member wb_adr 4) (instanceRef ufmefb)) + (portRef C (instanceRef wb_adr_5_4)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef Q (instanceRef wb_adr_4)) + (portRef (member wb_adr 3) (instanceRef ufmefb)) + (portRef C (instanceRef wb_adr_5_5)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef Q (instanceRef wb_adr_5)) + (portRef (member wb_adr 2) (instanceRef ufmefb)) + (portRef C (instanceRef wb_adr_5_6)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef Q (instanceRef wb_adr_6)) + (portRef (member wb_adr 1) (instanceRef ufmefb)) + (portRef B (instanceRef wb_adr_5_7)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef Q (instanceRef wb_adr_7)) + (portRef (member wb_adr 0) (instanceRef ufmefb)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef Q (instanceRef wb_dati_0)) + (portRef (member wb_dati 7) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_0_1)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef Q (instanceRef wb_dati_1)) + (portRef (member wb_dati 6) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_2)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef Q (instanceRef wb_dati_2)) + (portRef (member wb_dati 5) (instanceRef ufmefb)) + (portRef A (instanceRef wb_dati_5_1_iv_0_3)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef Q (instanceRef wb_dati_3)) + (portRef (member wb_dati 4) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_2_4)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef Q (instanceRef wb_dati_4)) + (portRef (member wb_dati 3) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_5_1_iv_5)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef Q (instanceRef wb_dati_5)) + (portRef (member wb_dati 2) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_0_6)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef Q (instanceRef wb_dati_6)) + (portRef (member wb_dati 1) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_5_1_iv_1_7)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef Q (instanceRef wb_dati_7)) + (portRef (member wb_dati 0) (instanceRef ufmefb)) + (portRef D (instanceRef wb_adr_5_i_0_0)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef (member wb_dato 1) (instanceRef ufmefb)) + (portRef C (instanceRef n8MEGEN_6)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef (member wb_dato 0) (instanceRef ufmefb)) + (portRef C (instanceRef LEDEN_6)) + )) + (net wb_ack (joined + (portRef wb_ack (instanceRef ufmefb)) + (portRef B (instanceRef un1_FS_38_i_a3_0)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0)) + )) + (net (rename FS_9 "FS[9]") (joined + (portRef Q (instanceRef FS_9)) + (portRef A0 (instanceRef FS_cry_0_9)) + (portRef B (instanceRef FS_RNI3V8E_0_9)) + (portRef A (instanceRef un1_FS_26_1_0_a2)) + (portRef A (instanceRef un1_FS_21_1_i_o3)) + (portRef A (instanceRef FS_RNI409E_9)) + (portRef A (instanceRef FS_RNIK7MA_14)) + (portRef A (instanceRef wb_dati_5_1_iv_RNO_0_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_RNO_6)) + (portRef A (instanceRef un1_FS_36_2_0_a3_0_1)) + (portRef A (instanceRef un1_FS_33_0_a3_1)) + (portRef A (instanceRef un1_FS_36_1_0_a3_0_0)) + (portRef A (instanceRef wb_adr_5_i_a3_0)) + (portRef A (instanceRef wb_dati_5_0_iv_RNO_0)) + (portRef D (instanceRef wb_we_0_0_1_RNO)) + (portRef D (instanceRef FS_RNI3V8E_9)) + (portRef C (instanceRef wb_adr_RNO_1_0)) + (portRef B (instanceRef wb_dati_5_1_iv_RNO_0_3)) + )) + (net (rename FS_10 "FS[10]") (joined + (portRef Q (instanceRef FS_10)) + (portRef A1 (instanceRef FS_cry_0_9)) + (portRef A (instanceRef FS_RNI3V8E_0_9)) + (portRef B (instanceRef un1_FS_26_1_0_a2)) + (portRef B (instanceRef un1_FS_21_1_i_o3)) + (portRef B (instanceRef FS_RNI409E_9)) + (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_6)) + (portRef B (instanceRef un1_FS_36_2_0_a3_0_1)) + (portRef B (instanceRef un1_FS_33_0_a3_1)) + (portRef B (instanceRef un1_FS_36_1_0_a3_0_0)) + (portRef A (instanceRef InitReady2_5)) + (portRef B (instanceRef wb_adr_5_i_a3_0)) + (portRef A (instanceRef wb_dati_5_1_iv_RNO_4)) + (portRef A (instanceRef FS_RNIVQ281_10)) + (portRef C (instanceRef wb_we_0_0_1_RNO)) + (portRef C (instanceRef FS_RNI3V8E_9)) + (portRef D (instanceRef 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b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed @@ -0,0 +1,2778 @@ +* +NOTE Diamond (64-bit) 3.11.3.469 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Sun Jul 14 22:31:28 2024* +NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS RDQML : 48 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS RCLKout : 60 : out* +NOTE PINS nRCS : 57 : out* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS 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+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C5111* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +7BE9 diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp new file mode 100644 index 0000000..110ecb9 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp @@ -0,0 +1,600 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial + RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr + RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma + c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_ + impl1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c + 0 -gui -msgset + //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-1200HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469 +Mapped on: 07/14/24 22:31:15 + +Design Summary +-------------- + + Number of registers: 106 out of 1520 (7%) + PFU registers: 71 out of 1280 (6%) + PIO registers: 35 out of 240 (15%) + Number of SLICEs: 106 out of 640 (17%) + SLICEs as Logic/ROM: 106 out of 640 (17%) + SLICEs as RAM: 0 out of 480 (0%) + SLICEs as Carry: 10 out of 640 (2%) + Number of LUT4s: 210 out of 1280 (16%) + Number used as logic LUTs: 190 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%) + Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%) + Number of IDDR cells: 0 + Number of ODDR cells: 1 + Number of TDDR cells: 0 + Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential) + Number of PIO using IDDR only: 0 (0 differential) + Number of PIO using ODDR only: 1 (0 differential) + Number of PIO using TDDR only: 0 (0 differential) + Number of PIO using IDDR/ODDR: 0 (0 differential) + Number of PIO using IDDR/TDDR: 0 (0 differential) + Number of PIO using ODDR/TDDR: 0 (0 differential) + Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential) + Number of block RAMs: 0 out of 7 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : Yes + JTAG used : No + Readback used : No + Oscillator used : Yes + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + + Page 1 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +Design Summary (cont) +--------------------- + Number of PLLs: 1 out of 1 (100%) + Number of DQSDLLs: 0 out of 2 (0%) + Number of CLKDIVC: 0 out of 4 (0%) + Number of ECLKSYNCA: 0 out of 4 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 5 + Net ICLK: 1 loads, 1 rising, 0 falling (Driver: OSCH_inst ) + Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) + Net PCLK: 48 loads, 48 rising, 0 falling (Driver: rpll/PLLInst_0 ) + Net nCRAS_c: 14 loads, 0 rising, 14 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 7 + Net N_51: 1 loads, 1 LSLICEs + Net XOR8MEG17: 5 loads, 5 LSLICEs + Net N_94_i: 2 loads, 2 LSLICEs + Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs + Net N_239_i: 10 loads, 10 LSLICEs + Net N_63: 2 loads, 2 LSLICEs + Net N_258_i: 2 loads, 2 LSLICEs + Number of LSRs: 6 + Net RA10s_i: 1 loads, 0 LSLICEs + Net wb_rst7: 3 loads, 3 LSLICEs + Net wb_rst: 1 loads, 0 LSLICEs + Net Ready: 13 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net InitReady: 35 loads + Net Ready: 27 loads + Net FS[12]: 21 loads + Net FS[13]: 19 loads + Net FS[11]: 18 loads + Net N_242: 18 loads + Net FS[10]: 17 loads + Net FS[14]: 17 loads + Net FS[9]: 17 loads + Net S[0]: 12 loads + + + + + Number of warnings: 4 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + +WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_ + LCMXO2_1200HC_impl1_synplify.lpf(9): Semantic error in "FREQUENCY PORT + + Page 2 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +Design Errors/Warnings (cont) +----------------------------- + "RCLK" 62.500000 MHz ;": "RCLK" matches no ports in the design. This + preference has been disabled. +WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf(68): Semantic + error in "IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port "RCLK" + does not exist in the design. This preference has been disabled. +WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will + temporarily disable certain features of the device including Power + Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. + Functionality is restored after the Flash Memory (UFM/Configuration) + Interface is disabled using Disable Configuration Interface command 0x26 + followed by Bypass command 0xFF. +WARNING - map: IO buffer missing for top level port RCLK...logic will be + discarded. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nRCAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RCLKout | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[5] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS33 | OUT | + + Page 3 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nFWE | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[6] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS33 | IN | + + Page 4 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[3] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[1] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_c_i was merged into signal nCRAS_c +Signal RASr2_i was merged into signal RASr2 +Signal Ready_i was merged into signal Ready +Signal XOR8MEG.CN was merged into signal PHI2_c +Signal rpll/GND undriven or does not drive anything - clipped. +Signal ufmefb/VCC undriven or does not drive anything - clipped. +Signal ufmefb/GND undriven or does not drive anything - clipped. +Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. +Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. +Signal rpll/CLKINTFB undriven or does not drive anything - clipped. +Signal rpll/DPHSRC undriven or does not drive anything - clipped. +Signal rpll/PLLACK undriven or does not drive anything - clipped. +Signal rpll/PLLDATO0 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO1 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO2 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO3 undriven or does not drive anything - clipped. + + Page 5 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +Removed logic (cont) +-------------------- +Signal rpll/PLLDATO4 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO5 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO6 undriven or does not drive anything - clipped. +Signal rpll/PLLDATO7 undriven or does not drive anything - clipped. +Signal rpll/REFCLK undriven or does not drive anything - clipped. +Signal rpll/INTLOCK undriven or does not drive anything - clipped. +Signal rpll/LOCK undriven or does not drive anything - clipped. +Signal rpll/CLKOS3 undriven or does not drive anything - clipped. +Signal rpll/CLKOS2 undriven or does not drive anything - clipped. +Signal rpll/CLKOS undriven or does not drive anything - clipped. +Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped. +Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped. +Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped. +Signal ufmefb/TCOC undriven or does not drive anything - clipped. +Signal ufmefb/TCINT undriven or does not drive anything - clipped. +Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped. +Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO0_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO1_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO2_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO3_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO4_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO5_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO6_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO7_0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped. +Signal ufmefb/PLLWEO undriven or does not drive anything - clipped. +Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. + + Page 6 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +Removed logic (cont) +-------------------- +Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. +Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. +Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped. +Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped. +Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. +Signal N_1 undriven or does not drive anything - clipped. +Signal OSCH_inst_SEDSTDBY undriven or does not drive anything - clipped. +Block nCRAS_pad_RNIBPVB was optimized away. +Block RASr2_RNIAFR1 was optimized away. +Block Ready_RNILCP9 was optimized away. +Block C1Submitted.CN was optimized away. +Block rpll/GND was optimized away. +Block ufmefb/VCC was optimized away. +Block ufmefb/GND was optimized away. + + + +PLL/DLL Summary +--------------- + +PLL 1: Pin/Node Value + PLL Instance Name: rpll/PLLInst_0 + PLL Type: EHXPLLJ + Input Clock: NODE ICLK + Output Clock(P): NODE PCLK + Output Clock(S): NONE + Output Clock(S2): NONE + Output Clock(S3): NONE + Feedback Signal: NODE PCLK + Reset Signal: NONE + M Divider Reset Signal: NONE + C Divider Reset Signal: NONE + D Divider Reset Signal: NONE + Standby Signal: NONE + PLL LOCK signal: NONE + PLL Data bus CLK Signal: NONE + PLL Data bus Strobe Signal: NONE + PLL Data bus Reset Signal: NONE + PLL Data bus Write Enable Signal: NONE + PLL Data bus Address0: NONE + PLL Data bus Address1: NONE + PLL Data bus Address2: NONE + PLL Data bus Address3: NONE + PLL Data bus Address4: NONE + PLL Data In bus Data0: NONE + PLL Data In bus Data1: NONE + PLL Data In bus Data2: NONE + PLL Data In bus Data3: NONE + PLL Data In bus Data4: NONE + PLL Data In bus Data5: NONE + PLL Data In bus Data6: NONE + + Page 7 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +PLL/DLL Summary (cont) +---------------------- + PLL Data In bus Data7: NONE + PLL Data bus Acknowledge: NONE + PLL Data Out bus Data0: NONE + PLL Data Out bus Data1: NONE + PLL Data Out bus Data2: NONE + PLL Data Out bus Data3: NONE + PLL Data Out bus Data4: NONE + PLL Data Out bus Data5: NONE + PLL Data Out bus Data6: NONE + PLL Data Out bus Data7: NONE + Input Clock Frequency (MHz): 133.0000 + Output Clock(P) Frequency (MHz): 61.3846 + Output Clock(S) Frequency (MHz): NA + Output Clock(S2) Frequency (MHz): NA + Output Clock(S3) Frequency (MHz): NA + CLKOP Post Divider A Input: DIVA + CLKOS Post Divider B Input: DIVB + CLKOS2 Post Divider C Input: DIVC + CLKOS3 Post Divider D Input: DIVD + Pre Divider A Input: VCO_PHASE + Pre Divider B Input: VCO_PHASE + Pre Divider C Input: VCO_PHASE + Pre Divider D Input: VCO_PHASE + VCO Bypass A Input: VCO_PHASE + VCO Bypass B Input: VCO_PHASE + VCO Bypass C Input: VCO_PHASE + VCO Bypass D Input: VCO_PHASE + FB_MODE: CLKOP + CLKI Divider: 13 + CLKFB Divider: 6 + CLKOP Divider: 8 + CLKOS Divider: 1 + CLKOS2 Divider: 1 + CLKOS3 Divider: 1 + Fractional N Divider: 0 + CLKOP Desired Phase Shift(degree): 0 + CLKOP Trim Option Rising/Falling: RISING + CLKOP Trim Option Delay: 0 + CLKOS Desired Phase Shift(degree): 0 + CLKOS Trim Option Rising/Falling: FALLING + CLKOS Trim Option Delay: 0 + CLKOS2 Desired Phase Shift(degree): 0 + CLKOS3 Desired Phase Shift(degree): 0 + +OSC Summary +----------- + +OSC 1: Pin/Node Value + OSC Instance Name: OSCH_inst + OSC Type: OSCH + STDBY Input: NONE + OSC Output: NODE ICLK + OSC Nominal Frequency (MHz): 133.00 + + + + + Page 8 + + + + +Design: RAM2GS Date: 07/14/24 22:31:15 + +Embedded Functional Block Connection Summary +-------------------------------------------- + + Desired WISHBONE clock frequency: 66.7 MHz + Clock source: PCLK + Reset source: wb_rst + Functions mode: + I2C #1 (Primary) Function: DISABLED + I2C #2 (Secondary) Function: DISABLED + SPI Function: DISABLED + Timer/Counter Function: DISABLED + Timer/Counter Mode: WB + UFM Connection: ENABLED + PLL0 Connection: DISABLED + PLL1 Connection: DISABLED + I2C Function Summary: + -------------------- + None + SPI Function Summary: + -------------------- + None + Timer/Counter Function Summary: + ------------------------------ + None + UFM Function Summary: + -------------------- + UFM Utilization: General Purpose Flash Memory + Initialized UFM Pages: 321 Pages (321*128 Bits) + Available General + Purpose Flash Memory: 511 Pages (511*128 Bits) + + EBR Blocks with Unique + Initialization Data: 0 + + WID EBR Instance + --- ------------ + + +ASIC Components +--------------- + +Instance Name: OSCH_inst + Type: OSCH +Instance Name: ufmefb/EFBInst_0 + Type: EFB +Instance Name: rpll/PLLInst_0 + Type: EHXPLLJ + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 64 MB + + + + + + Page 9 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad new file mode 100644 index 0000000..ea91830 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad @@ -0,0 +1,303 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-1200HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.42 + +Sun Jul 14 22:31:22 2024 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS33_OUT | PT17D | | | DRIVE:4mA SLEW:FAST | +| Dout[1] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:4mA SLEW:FAST | +| Dout[2] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:4mA SLEW:FAST | +| Dout[3] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:4mA SLEW:FAST | +| Dout[4] | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:4mA SLEW:FAST | +| Dout[5] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:4mA SLEW:FAST | +| Dout[6] | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:4mA SLEW:FAST | +| Dout[7] | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:4mA SLEW:FAST | +| LED | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:24mA SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS33_IN | PL9B | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS33_IN | PL10C | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS33_IN | PL10D | | | CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS33_IN | PB6D | | | CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | +| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW | +| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW | +| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST | +| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW | +| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| nCCAS | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW | +| nRCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW | +| nRWE | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | 3.3V | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | | +| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | | +| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3C | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3D | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL4A | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL4B | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | +| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL8A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL8B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL8C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL8D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL9B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL10C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL10D | | | | +| 27/2 | unused, PULL:DOWN | | | PB4C | CSSPIN | | | +| 28/2 | unused, PULL:DOWN | | | PB4D | | | | +| 29/2 | unused, PULL:DOWN | | | PB6A | | | | +| 30/2 | unused, PULL:DOWN | | | PB6B | | | | +| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | | +| 45/2 | unused, PULL:DOWN | | | PB18C | | | | +| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | | +| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | | +| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | | +| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | | +| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | | +| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | | +| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | | +| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | +| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | +| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | | +| 63/1 | unused, PULL:DOWN | | | PR5C | PCLKT1_0/DQ0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | | +| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | | +| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | | +| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | | +| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | | +| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | | +| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | | +| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | | +| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | | +| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT17D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT16C | | | | +| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT15B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT15A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10B | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT10A | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT9A | | | | +| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | +| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | +| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | +| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | +| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | +| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | +| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | +| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | +| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | +| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | +| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | +| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | +| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | +| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | +| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | +| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | +| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | +| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | +| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | +| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | +| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | +| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | +| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | +| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | +| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | +| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | +| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "62"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "47"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLKout" SITE "60"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "15"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; + +#PLL +LOCATE COMP "rpll/PLLInst_0" SITE "LPLL" ; + + + + +PAR: Place And Route Diamond (64-bit) 3.11.3.469. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Sun Jul 14 22:31:25 2024 + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf new file mode 100644 index 0000000..c386b10 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf @@ -0,0 +1,115 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Sun Jul 14 22:31:16 2024 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLKout" SITE "60" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "62" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RBA[1]" SITE "47" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "nFWE" SITE "15" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +FREQUENCY NET "ICLK" 133.000000 MHz ; +FREQUENCY NET "PCLK" 61.384615 MHz ; +FREQUENCY PORT "PHI2" 2.900000 MHz ; +FREQUENCY PORT "nCCAS" 2.900000 MHz ; +FREQUENCY PORT "nCRAS" 2.900000 MHz ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ; +OUTPUT PORT "LED" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 5.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "RCKE" LOAD 5.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 5.000000 pF ; +OUTPUT PORT "RDQML" LOAD 5.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 5.000000 pF ; +OUTPUT PORT "nRCS" LOAD 5.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 5.000000 pF ; +OUTPUT PORT "nRWE" LOAD 5.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; +OUTPUT PORT "RCLKout" LOAD 5.000000 pF ; +COMMERCIAL ; diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr new file mode 100644 index 0000000..cb14625 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr @@ -0,0 +1,808 @@ +#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019 +#install: C:\lscc\diamond\3.11_x64\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEMACWIN11 + +# Sun Jul 14 22:31:08 2024 + +#Implementation: impl1 + + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43 + +@N|Running in 64-bit mode + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43 + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v" (library work) +@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v" (library work) +@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v" (library work) +Verilog syntax check successful! +Options changed - recompiling +Selecting top level module RAM2GS +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work. +Running optimization stage 1 on OSCH ....... +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. +Running optimization stage 1 on VLO ....... +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ in library work. +Running optimization stage 1 on EHXPLLJ ....... +@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v":8:7:8:10|Synthesizing module RPLL in library work. +Running optimization stage 1 on RPLL ....... +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work. +Running optimization stage 1 on ODDRXE ....... +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. +Running optimization stage 1 on VHI ....... +@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. +Running optimization stage 1 on EFB ....... +@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":8:7:8:10|Synthesizing module REFB in library work. +Running optimization stage 1 on REFB ....... +@W: CL318 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. +@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Running optimization stage 2 on RAM2GS ....... +@N: CL159 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":50:10:50:13|Input RCLK is unused. +Running optimization stage 2 on REFB ....... +Running optimization stage 2 on EFB ....... +Running optimization stage 2 on VHI ....... +Running optimization stage 2 on ODDRXE ....... +Running optimization stage 2 on RPLL ....... +Running optimization stage 2 on EHXPLLJ ....... +Running optimization stage 2 on VLO ....... +Running optimization stage 2 on OSCH ....... + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jul 14 22:31:08 2024 + +###########################################################] + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43 + +@N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jul 14 22:31:08 2024 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: A:\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jul 14 22:31:08 2024 + +###########################################################] + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Database state : \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\|impl1 +Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43 + +@N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Sun Jul 14 22:31:10 2024 + +###########################################################] +# Sun Jul 14 22:31:10 2024 + + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54 + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc +@N: MF284 |Setting synthesis effort to medium for the design +@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt +Printing clock summary report in "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt" file +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) + +@N: MF284 |Setting synthesis effort to medium for the design +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: MH105 |UMR3 is only supported for HAPS-80. +@N: MH105 |UMR3 is only supported for HAPS-80. +syn_allowed_resources : blockrams=7 set on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +-------------------------------------------------------------------------------------------------------------- +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10 + +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65 +============================================================================================================== + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +------------------------------------------------------------------------------------------------------------------------------ +PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) + +RCLK 0 RCLK(port) - - - + +System 0 - - - - + +RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - - +============================================================================================================================== + +@W: MT529 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":174:4:174:9|Found inferred clock RPLL|CLKOP_inferred_clock which controls 65 sequential elements including RCKE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +3 non-gated/non-generated clock tree(s) driving 41 clock pin(s) of sequential element(s) +1 gated/generated clock tree(s) driving 65 clock pin(s) of sequential element(s) +0 instances converted, 65 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= +====================================================== Gated/Generated Clocks ====================================================== +Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation +------------------------------------------------------------------------------------------------------------------------------------ +@KP:ckid0_0 rpll.PLLInst_0.CLKOP EHXPLLJ 65 RCKE Black box on clock path +==================================================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + +None +None + +Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Jul 14 22:31:10 2024 + +###########################################################] +# Sun Jul 14 22:31:11 2024 + + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54 + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +@N: MF284 |Setting synthesis effort to medium for the design +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +@N: MF284 |Setting synthesis effort to medium for the design + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":180:4:180:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":167:4:167:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 2.24ns 198 / 106 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 152MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 152MB) + +Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 153MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi +N-2018.03L-SP1-1 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB) + +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":57:11:57:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\rpll.v":64:12:64:20|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@N: MT615 |Found clock RCLK with period 16.00ns +@N: MT615 |Found clock PHI2 with period 350.00ns +@N: MT615 |Found clock nCRAS with period 350.00ns +@N: MT615 |Found clock nCCAS with period 350.00ns +@W: MT420 |Found inferred clock RPLL|CLKOP_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rpll.PCLK. + + +##### START OF TIMING REPORT #####[ +# Timing Report written on Sun Jul 14 22:31:13 2024 +# + + +Top view: RAM2GS +Requested Frequency: 2.9 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 3.291 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------------------- +PHI2 2.9 MHz 69.1 MHz 350.000 14.481 167.760 declared default_clkgroup +RCLK 62.5 MHz NA 16.000 NA NA declared default_clkgroup +RPLL|CLKOP_inferred_clock 100.0 MHz 149.0 MHz 10.000 6.709 3.291 inferred Inferred_clkgroup_0 +nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +nCRAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +System 100.0 MHz 388.0 MHz 10.000 2.577 7.423 system system_clkgroup +================================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +System RPLL|CLKOP_inferred_clock | 10.000 7.423 | No paths - | No paths - | No paths - +PHI2 PHI2 | No paths - | 350.000 347.124 | 175.000 167.760 | 175.000 173.428 +PHI2 RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp - +nCRAS RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp - +RPLL|CLKOP_inferred_clock System | 10.000 8.892 | No paths - | No paths - | No paths - +RPLL|CLKOP_inferred_clock PHI2 | Diff grp - | No paths - | Diff grp - | No paths - +RPLL|CLKOP_inferred_clock nCRAS | No paths - | No paths - | Diff grp - | No paths - +RPLL|CLKOP_inferred_clock RPLL|CLKOP_inferred_clock | 10.000 3.291 | No paths - | No paths - | No paths - +=================================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------ +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.760 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.760 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.760 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.760 +Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 167.760 +Bank_0io[5] PHI2 IFS1P3DX Q Bank[5] 0.972 167.760 +Bank_0io[6] PHI2 IFS1P3DX Q Bank[6] 0.972 167.760 +Bank_0io[7] PHI2 IFS1P3DX Q Bank[7] 0.972 167.760 +XOR8MEG PHI2 FD1P3AX Q XOR8MEG 1.044 173.428 +CmdEnable PHI2 FD1S3AX Q CmdEnable 1.180 347.124 +==================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------- +CmdEnable PHI2 FD1S3AX D CmdEnable_1 175.462 167.760 +CmdLEDEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897 +CmdUFMShift PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897 +CmdUFMWrite PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897 +Cmdn8MEGEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897 +XOR8MEG PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_2 175.089 169.017 +C1Submitted PHI2 FD1S3AX D C1Submitted_1 175.089 169.017 +CmdValid PHI2 FD1S3AX D CmdValid_0 175.089 169.049 +CmdUFMData PHI2 FD1P3AX SP CmdUFMData_1_sqmuxa 174.528 169.505 +============================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 175.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 175.462 + + - Propagation time: 7.703 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : 167.760 + + Number of logic level(s): 7 + Starting point: Bank_0io[0] / Q + Ending point: CmdEnable / D + The start point is clocked by PHI2 [rising] on pin SCLK + The end point is clocked by PHI2 [falling] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Bank_0io[0] IFS1P3DX Q Out 0.972 0.972 - +Bank[0] Net - - - - 1 +un1_Bank_1_4 ORCALUT4 A In 0.000 0.972 - +un1_Bank_1_4 ORCALUT4 Z Out 1.153 2.125 - +un1_Bank_1_4 Net - - - - 3 +C1WR_7 ORCALUT4 C In 0.000 2.125 - +C1WR_7 ORCALUT4 Z Out 1.089 3.213 - +C1WR_7 Net - - - - 2 +C1WR ORCALUT4 C In 0.000 3.213 - +C1WR ORCALUT4 Z Out 1.089 4.302 - +C1WR Net - - - - 2 +un1_ADWR ORCALUT4 B In 0.000 4.302 - +un1_ADWR ORCALUT4 Z Out 1.153 5.455 - +un1_ADWR Net - - - - 3 +un1_CMDWR ORCALUT4 B In 0.000 5.455 - +un1_CMDWR ORCALUT4 Z Out 1.017 6.472 - +un1_CMDWR Net - - - - 1 +CmdEnable_1_am ORCALUT4 C In 0.000 6.472 - +CmdEnable_1_am ORCALUT4 Z Out 1.017 7.489 - +CmdEnable_1_am Net - - - - 1 +CmdEnable_1 PFUMX BLUT In 0.000 7.489 - +CmdEnable_1 PFUMX Z Out 0.214 7.703 - +CmdEnable_1 Net - - - - 1 +CmdEnable FD1S3AX D In 0.000 7.703 - +================================================================================= + + + + +==================================== +Detailed Report for Clock: RPLL|CLKOP_inferred_clock +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------- +InitReady RPLL|CLKOP_inferred_clock FD1S3AX Q InitReady 1.326 3.291 +FS[15] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[15] 1.188 3.429 +FS[16] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[16] 1.188 3.429 +FS[17] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[17] 1.188 3.429 +FS[13] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[13] 1.276 3.777 +FS[9] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[9] 1.268 3.785 +FS[10] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[10] 1.268 3.785 +FS[14] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[14] 1.260 3.793 +FS[12] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[12] 1.284 4.049 +FS[11] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[11] 1.272 4.061 +=============================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------- +wb_dati[2] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[2] 10.089 3.291 +wb_dati[4] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[4] 10.089 3.291 +wb_dati[5] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[5] 10.089 3.291 +wb_dati[7] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[7] 10.089 3.291 +wb_dati[3] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[3] 10.089 3.395 +wb_dati[6] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[6] 10.089 3.395 +wb_dati[1] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[1] 10.089 4.483 +FS[17] RPLL|CLKOP_inferred_clock FD1S3AX D FS_s[17] 9.894 4.551 +LEDEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604 +n8MEGEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604 +==================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 10.089 + + - Propagation time: 6.798 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 3.291 + + Number of logic level(s): 5 + Starting point: InitReady / Q + Ending point: wb_dati[2] / D + The start point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK + The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +InitReady FD1S3AX Q Out 1.326 1.326 - +InitReady Net - - - - 35 +wb_adr_cnst_sn.m2_i_o3 ORCALUT4 B In 0.000 1.326 - +wb_adr_cnst_sn.m2_i_o3 ORCALUT4 Z Out 1.317 2.643 - +N_242 Net - - - - 18 +FS_RNI7U6M[14] ORCALUT4 B In 0.000 2.643 - +FS_RNI7U6M[14] ORCALUT4 Z Out 1.193 3.836 - +N_134 Net - - - - 4 +un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 C In 0.000 3.836 - +un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 Z Out 1.153 4.989 - +wb_adr_21_sqmuxa_s9 Net - - - - 3 +FS_RNIFUUT2[9] ORCALUT4 C In 0.000 4.989 - +FS_RNIFUUT2[9] ORCALUT4 Z Out 1.193 6.181 - +N_194 Net - - - - 4 +wb_dati_5_1_iv[2] ORCALUT4 B In 0.000 6.181 - +wb_dati_5_1_iv[2] ORCALUT4 Z Out 0.617 6.798 - +wb_dati_5[2] Net - - - - 1 +wb_dati[2] FD1P3AX D In 0.000 6.798 - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 7.423 +ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 9.472 +ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 9.472 +OSCH_inst System OSCH OSC ICLK 0.000 10.000 +========================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------- +LEDEN System FD1P3AX SP N_63 9.528 7.423 +n8MEGEN System FD1P3AX SP N_63 9.528 7.423 +wb_cyc_stb System FD1P3IX SP N_51 9.528 8.912 +LEDEN System FD1P3AX D LEDEN_6 10.089 9.472 +n8MEGEN System FD1P3AX D n8MEGEN_6 10.089 9.472 +rpll.PLLInst_0 System EHXPLLJ CLKI ICLK 10.000 10.000 +======================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 9.528 + + - Propagation time: 2.106 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 7.423 + + Number of logic level(s): 2 + Starting point: ufmefb.EFBInst_0 / WBACKO + Ending point: LEDEN / SP + The start point is clocked by System [rising] + The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 - +wb_ack Net - - - - 2 +un1_FS_38_i_a3_0 ORCALUT4 B In 0.000 0.000 - +un1_FS_38_i_a3_0 ORCALUT4 Z Out 1.017 1.017 - +un1_FS_38_i_a3_0 Net - - - - 1 +un1_FS_38_i_0 ORCALUT4 C In 0.000 1.017 - +un1_FS_38_i_0 ORCALUT4 Z Out 1.089 2.106 - +N_63 Net - - - - 2 +LEDEN FD1P3AX SP In 0.000 2.106 - +===================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied +None + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_1200hc-4 + +Register bits: 106 of 1280 (8%) +PIC Latch: 0 +I/O cells: 63 + + +Details: +BB: 8 +CCU2D: 10 +EFB: 1 +EHXPLLJ: 1 +FD1P3AX: 28 +FD1P3IX: 3 +FD1S3AX: 37 +FD1S3IX: 3 +GSR: 1 +IB: 24 +IFS1P3DX: 9 +IFS1P3IX: 10 +IFS1P3JX: 2 +INV: 7 +OB: 31 +ODDRXE: 1 +OFS1P3BX: 4 +OFS1P3DX: 8 +OFS1P3IX: 1 +OFS1P3JX: 1 +ORCALUT4: 186 +OSCH: 1 +PFUMX: 2 +PUR: 1 +VHI: 2 +VLO: 3 +true: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 157MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Sun Jul 14 22:31:13 2024 + +###########################################################] diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html new file mode 100644 index 0000000..c054c19 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html @@ -0,0 +1,152 @@ + +Bitgen Report + + +
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sun Jul 14 22:29:59 2024
+
+
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                   321 Pages (Page 190 to Page 510).
+ 
+Total CPU Time: 3 secs 
+Total REAL Time: 3 secs 
+Peak Memory Usage: 275 MB
+
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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt new file mode 100644 index 0000000..5a6449a --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt @@ -0,0 +1,148 @@ + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Sun Jul 14 22:31:10 2024 + +##### DESIGN INFO ####################################################### + +Top View: "RAM2GS" +Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" + + + + +##### SUMMARY ############################################################ + +Found 0 issues in 0 out of 4 constraints + + +##### DETAILS ############################################################ + + + +Clock Relationships +******************* + +Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +System System | 10.000 | No paths | No paths | No paths +System RPLL|CLKOP_inferred_clock | 10.000 | No paths | No paths | No paths +PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000 +PHI2 RPLL|CLKOP_inferred_clock | No paths | No paths | No paths | Diff grp +nCRAS RPLL|CLKOP_inferred_clock | No paths | No paths | No paths | Diff grp +RPLL|CLKOP_inferred_clock System | 10.000 | No paths | No paths | No paths +RPLL|CLKOP_inferred_clock PHI2 | Diff grp | No paths | Diff grp | No paths +RPLL|CLKOP_inferred_clock nCRAS | No paths | No paths | Diff grp | No paths +RPLL|CLKOP_inferred_clock RPLL|CLKOP_inferred_clock | 10.000 | No paths | No paths | No paths +======================================================================================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + +Unconstrained Start/End Points +****************************** + +p:CROW[0] +p:CROW[1] +p:Din[0] +p:Din[1] +p:Din[2] +p:Din[3] +p:Din[4] +p:Din[5] +p:Din[6] +p:Din[7] +p:Dout[0] +p:Dout[1] +p:Dout[2] +p:Dout[3] +p:Dout[4] +p:Dout[5] +p:Dout[6] +p:Dout[7] +p:MAin[0] +p:MAin[1] +p:MAin[2] +p:MAin[3] +p:MAin[4] +p:MAin[5] +p:MAin[6] +p:MAin[7] +p:MAin[8] +p:MAin[9] +p:RA[0] +p:RA[1] +p:RA[2] +p:RA[3] +p:RA[4] +p:RA[5] +p:RA[6] +p:RA[7] +p:RA[8] +p:RA[9] +p:RA[10] +p:RA[11] +p:RBA[0] +p:RBA[1] +p:RCKE +p:RCLKout +p:RDQMH +p:RDQML +p:RD[0] (bidir end point) +p:RD[0] (bidir start point) +p:RD[1] (bidir end point) +p:RD[1] (bidir start point) +p:RD[2] (bidir end point) +p:RD[2] (bidir start point) +p:RD[3] (bidir end point) +p:RD[3] (bidir start point) +p:RD[4] (bidir end point) +p:RD[4] (bidir start point) +p:RD[5] (bidir end point) +p:RD[5] (bidir start point) +p:RD[6] (bidir end point) +p:RD[6] (bidir start point) +p:RD[7] (bidir end point) +p:RD[7] (bidir start point) +p:nFWE +p:nRCAS +p:nRCS +p:nRRAS +p:nRWE + + +Inapplicable constraints +************************ + +(none) + + +Applicable constraints with issues +********************************** + +(none) + + +Constraints with matching wildcard expressions +********************************************** + +(none) + + +Library Report +************** + + +# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html new file mode 100644 index 0000000..eacd226 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html @@ -0,0 +1,603 @@ + +Project Summary + + +

+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
+     c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_
+     impl1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c
+     0 -gui -msgset
+     //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.11.3.469
+Mapped on:  07/14/24  22:31:15
+
+
+Design Summary
+   Number of registers:    106 out of  1520 (7%)
+      PFU registers:           71 out of  1280 (6%)
+      PIO registers:           35 out of   240 (15%)
+   Number of SLICEs:       106 out of   640 (17%)
+      SLICEs as Logic/ROM:    106 out of   640 (17%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         10 out of   640 (2%)
+   Number of LUT4s:        210 out of  1280 (16%)
+      Number used as logic LUTs:        190
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
+   Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
+      Number of IDDR cells:   0
+      Number of ODDR cells:   1
+      Number of TDDR cells:   0
+   Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
+      Number of PIO using IDDR only:        0 (0 differential)
+      Number of PIO using ODDR only:        1 (0 differential)
+      Number of PIO using TDDR only:        0 (0 differential)
+      Number of PIO using IDDR/ODDR:        0 (0 differential)
+      Number of PIO using IDDR/TDDR:        0 (0 differential)
+      Number of PIO using ODDR/TDDR:        0 (0 differential)
+      Number of PIO using IDDR/ODDR/TDDR:   0 (0 differential)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : Yes
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+
+   Number of PLLs:  1 out of 1 (100%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  5
+     Net ICLK: 1 loads, 1 rising, 0 falling (Driver: OSCH_inst )
+     Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
+     Net PCLK: 48 loads, 48 rising, 0 falling (Driver: rpll/PLLInst_0 )
+     Net nCRAS_c: 14 loads, 0 rising, 14 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  7
+     Net N_51: 1 loads, 1 LSLICEs
+     Net XOR8MEG17: 5 loads, 5 LSLICEs
+     Net N_94_i: 2 loads, 2 LSLICEs
+     Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
+     Net N_239_i: 10 loads, 10 LSLICEs
+     Net N_63: 2 loads, 2 LSLICEs
+     Net N_258_i: 2 loads, 2 LSLICEs
+   Number of LSRs:  6
+     Net RA10s_i: 1 loads, 0 LSLICEs
+     Net wb_rst7: 3 loads, 3 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net Ready: 13 loads, 0 LSLICEs
+     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
+     Net RASr2: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 35 loads
+     Net Ready: 27 loads
+     Net FS[12]: 21 loads
+     Net FS[13]: 19 loads
+     Net FS[11]: 18 loads
+     Net N_242: 18 loads
+     Net FS[10]: 17 loads
+     Net FS[14]: 17 loads
+     Net FS[9]: 17 loads
+     Net S[0]: 12 loads
+
+
+
+
+   Number of warnings:  4
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_
+     LCMXO2_1200HC_impl1_synplify.lpf(9): Semantic error in "FREQUENCY PORT
+
+     "RCLK" 62.500000 MHz ;": "RCLK" matches no ports in the design.  This
+     preference has been disabled.
+WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf(68): Semantic
+     error in "IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port "RCLK"
+     does not exist in the design. This preference has been disabled.
+WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+     temporarily disable certain features of the device including Power
+     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
+     Functionality is restored after the Flash Memory (UFM/Configuration)
+     Interface is disabled using Disable Configuration Interface command 0x26
+     followed by Bypass command 0xFF. 
+WARNING - map: IO buffer missing for top level port RCLK...logic will be
+     discarded.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCLKout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  | OUT        |
+
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS33  | IN         |
+
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_c_i was merged into signal nCRAS_c
+Signal RASr2_i was merged into signal RASr2
+Signal Ready_i was merged into signal Ready
+Signal XOR8MEG.CN was merged into signal PHI2_c
+Signal rpll/GND undriven or does not drive anything - clipped.
+Signal ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ufmefb/GND undriven or does not drive anything - clipped.
+Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
+Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
+Signal rpll/CLKINTFB undriven or does not drive anything - clipped.
+Signal rpll/DPHSRC undriven or does not drive anything - clipped.
+Signal rpll/PLLACK undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO0 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO1 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO2 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO3 undriven or does not drive anything - clipped.
+
+Signal rpll/PLLDATO4 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO5 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO6 undriven or does not drive anything - clipped.
+Signal rpll/PLLDATO7 undriven or does not drive anything - clipped.
+Signal rpll/REFCLK undriven or does not drive anything - clipped.
+Signal rpll/INTLOCK undriven or does not drive anything - clipped.
+Signal rpll/LOCK undriven or does not drive anything - clipped.
+Signal rpll/CLKOS3 undriven or does not drive anything - clipped.
+Signal rpll/CLKOS2 undriven or does not drive anything - clipped.
+Signal rpll/CLKOS undriven or does not drive anything - clipped.
+Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
+Signal ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO0_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO1_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO2_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO3_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO4_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO5_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO6_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO7_0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+
+Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
+Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
+Signal N_1 undriven or does not drive anything - clipped.
+Signal OSCH_inst_SEDSTDBY undriven or does not drive anything - clipped.
+Block nCRAS_pad_RNIBPVB was optimized away.
+Block RASr2_RNIAFR1 was optimized away.
+Block Ready_RNILCP9 was optimized away.
+Block C1Submitted.CN was optimized away.
+Block rpll/GND was optimized away.
+Block ufmefb/VCC was optimized away.
+Block ufmefb/GND was optimized away.
+
+     
+
+
+
+PLL/DLL Summary
+---------------
+
+PLL 1:                                     Pin/Node Value
+  PLL Instance Name:                                rpll/PLLInst_0
+  PLL Type:                                         EHXPLLJ
+  Input Clock:                             NODE     ICLK
+  Output Clock(P):                         NODE     PCLK
+  Output Clock(S):                                  NONE
+  Output Clock(S2):                                 NONE
+  Output Clock(S3):                                 NONE
+  Feedback Signal:                         NODE     PCLK
+  Reset Signal:                                     NONE
+  M Divider Reset Signal:                           NONE
+  C Divider Reset Signal:                           NONE
+  D Divider Reset Signal:                           NONE
+  Standby Signal:                                   NONE
+  PLL LOCK signal:                                  NONE
+  PLL Data bus CLK Signal:                          NONE
+  PLL Data bus Strobe Signal:                       NONE
+  PLL Data bus Reset Signal:                        NONE
+  PLL Data bus Write Enable Signal:                 NONE
+  PLL Data bus Address0:                            NONE
+  PLL Data bus Address1:                            NONE
+  PLL Data bus Address2:                            NONE
+  PLL Data bus Address3:                            NONE
+  PLL Data bus Address4:                            NONE
+  PLL Data In bus Data0:                            NONE
+  PLL Data In bus Data1:                            NONE
+  PLL Data In bus Data2:                            NONE
+  PLL Data In bus Data3:                            NONE
+  PLL Data In bus Data4:                            NONE
+  PLL Data In bus Data5:                            NONE
+  PLL Data In bus Data6:                            NONE
+
+  PLL Data In bus Data7:                            NONE
+  PLL Data bus Acknowledge:                         NONE
+  PLL Data Out bus Data0:                           NONE
+  PLL Data Out bus Data1:                           NONE
+  PLL Data Out bus Data2:                           NONE
+  PLL Data Out bus Data3:                           NONE
+  PLL Data Out bus Data4:                           NONE
+  PLL Data Out bus Data5:                           NONE
+  PLL Data Out bus Data6:                           NONE
+  PLL Data Out bus Data7:                           NONE
+  Input Clock Frequency (MHz):                      133.0000
+  Output Clock(P) Frequency (MHz):                  61.3846
+  Output Clock(S) Frequency (MHz):                  NA
+  Output Clock(S2) Frequency (MHz):                 NA
+  Output Clock(S3) Frequency (MHz):                 NA
+  CLKOP Post Divider A Input:                       DIVA
+  CLKOS Post Divider B Input:                       DIVB
+  CLKOS2 Post Divider C Input:                      DIVC
+  CLKOS3 Post Divider D Input:                      DIVD
+  Pre Divider A Input:                              VCO_PHASE
+  Pre Divider B Input:                              VCO_PHASE
+  Pre Divider C Input:                              VCO_PHASE
+  Pre Divider D Input:                              VCO_PHASE
+  VCO Bypass A Input:                               VCO_PHASE
+  VCO Bypass B Input:                               VCO_PHASE
+  VCO Bypass C Input:                               VCO_PHASE
+  VCO Bypass D Input:                               VCO_PHASE
+  FB_MODE:                                          CLKOP
+  CLKI Divider:                                     13
+  CLKFB Divider:                                    6
+  CLKOP Divider:                                    8
+  CLKOS Divider:                                    1
+  CLKOS2 Divider:                                   1
+  CLKOS3 Divider:                                   1
+  Fractional N Divider:                             0
+  CLKOP Desired Phase Shift(degree):                0
+  CLKOP Trim Option Rising/Falling:                 RISING
+  CLKOP Trim Option Delay:                          0
+  CLKOS Desired Phase Shift(degree):                0
+  CLKOS Trim Option Rising/Falling:                 FALLING
+  CLKOS Trim Option Delay:                          0
+  CLKOS2 Desired Phase Shift(degree):               0
+  CLKOS3 Desired Phase Shift(degree):               0
+
+OSC Summary
+-----------
+
+OSC 1:                                     Pin/Node Value
+  OSC Instance Name:                                OSCH_inst
+  OSC Type:                                         OSCH
+  STDBY Input:                                      NONE
+  OSC Output:                              NODE     ICLK
+  OSC Nominal Frequency (MHz):                      133.00
+
+
+
+
+
+
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 66.7 MHz
+   Clock source:                     PCLK
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            WB
+      UFM Connection:                ENABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Initialized UFM Pages:  321 Pages (321*128 Bits)
+      Available General
+      Purpose Flash Memory:   511 Pages (511*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: OSCH_inst
+         Type: OSCH
+Instance Name: ufmefb/EFBInst_0
+         Type: EFB
+Instance Name: rpll/PLLInst_0
+         Type: EHXPLLJ
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 64 MB
+        
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+

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+

+
+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html new file mode 100644 index 0000000..8687378 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html @@ -0,0 +1,368 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Sun Jul 14 22:31:22 2024
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVCMOS33_IN   | PL4B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVCMOS33_IN   | PL8A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVCMOS33_IN   | PT12A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVCMOS33_IN   | PT10A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVCMOS33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVCMOS33_OUT  | PT17D |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[1]   | 86/0     | LVCMOS33_OUT  | PT12C |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[2]   | 87/0     | LVCMOS33_OUT  | PT12B |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[3]   | 85/0     | LVCMOS33_OUT  | PT12D |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[4]   | 83/0     | LVCMOS33_OUT  | PT15B |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[5]   | 84/0     | LVCMOS33_OUT  | PT15A |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[6]   | 78/0     | LVCMOS33_OUT  | PT16C |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[7]   | 82/0     | LVCMOS33_OUT  | PT15C |           |           | DRIVE:4mA SLEW:FAST                                        |
+| LED       | 34/2     | LVCMOS33_OUT  | PB9A  |           |           | DRIVE:24mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVCMOS33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVCMOS33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVCMOS33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVCMOS33_IN   | PL9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVCMOS33_IN   | PL9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVCMOS33_IN   | PL8D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVCMOS33_IN   | PL10C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVCMOS33_IN   | PL8C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVCMOS33_IN   | PL10D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVCMOS33_IN   | PB6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVCMOS33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 47/2     | LVCMOS33_OUT  | PB18D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLKout   | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:24mA SLEW:FAST                                       |
+| RDQMH     | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS33_BIDI | PB15A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS33_BIDI | PB15B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS33_BIDI | PB18A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS33_BIDI | PB18B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVCMOS33_IN   | PL8B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVCMOS33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVCMOS33_IN   | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVCMOS33_IN   | PL4B  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVCMOS33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVCMOS33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVCMOS33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVCMOS33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVCMOS33_IN   | PL8A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVCMOS33_IN   | PL8B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVCMOS33_IN   | PL8C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVCMOS33_IN   | PL8D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVCMOS33_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVCMOS33_IN   | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVCMOS33_IN   | PL10C |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVCMOS33_IN   | PL10D |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |               | PB4C  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB6A  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |               | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |               | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVCMOS33_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |               | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PB15A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PB15B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PB18A |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | RBA[1]                | LOCATED    | LVCMOS33_OUT  | PB18D |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | RCLKout               | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     |     unused, PULL:DOWN |            |               | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVCMOS33_OUT  | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVCMOS33_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVCMOS33_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVCMOS33_OUT  | PT15B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVCMOS33_OUT  | PT15A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVCMOS33_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVCMOS33_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVCMOS33_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVCMOS33_IN   | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "47";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLKout"  SITE  "60";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+#PLL
+LOCATE  COMP  "rpll/PLLInst_0"  SITE  "LPLL" ;
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sun Jul 14 22:31:25 2024
+
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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html new file mode 100644 index 0000000..1988cbf --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html @@ -0,0 +1,326 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Sun Jul 14 22:31:16 2024
+
+C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
+RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
+RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            6.959        0            0.304        0            11           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 11 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
+Sun Jul 14 22:31:16 2024
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/108     62% used
+                  63+4(JTAG)/80      84% bonded
+   IOLOGIC           36/108          33% used
+
+   SLICE            106/640          16% used
+
+   OSC                1/1           100% used
+   PLL                1/1           100% used
+   EFB                1/1           100% used
+
+
+Number of Signals: 359
+Number of Connections: 970
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 3 signals are selected to use the primary clock routing resources:
+    PCLK (driver: rpll/PLLInst_0, clk load #: 47)
+    PHI2_c (driver: PHI2, clk load #: 19)
+    nCRAS_c (driver: nCRAS, clk load #: 14)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 3 signals are selected to use the secondary clock routing resources:
+    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
+    Ready (driver: SLICE_33, clk load #: 0, sr load #: 13, ce load #: 0)
+    N_239_i (driver: SLICE_75, clk load #: 0, sr load #: 0, ce load #: 10)
+
+WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+...................
+Placer score = 73583.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  73283
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 3 out of 108 (2%)
+  PLL        : 1 out of 1 (100%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "PCLK" from CLKOP on comp "rpll/PLLInst_0" on PLL site "LPLL", clk load = 47
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 19
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 14
+  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
+  SECONDARY "Ready" from Q0 on comp "SLICE_33" on site "R7C14A", clk load = 0, ce load = 0, sr load = 13
+  SECONDARY "N_239_i" from F0 on comp "SLICE_75" on site "R7C12D", clk load = 0, ce load = 10, sr load = 0
+
+  PRIMARY  : 3 out of 8 (37%)
+  SECONDARY: 3 out of 8 (37%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
+   63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 19 / 21 ( 90%) | 3.3V       | -         |
+| 2        | 13 / 20 ( 65%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 970 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=ICLK loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 9 secs 
+
+Start NBR router at 22:31:25 07/14/24
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 22:31:25 07/14/24
+
+Start NBR section for initial routing at 22:31:26 07/14/24
+Level 1, iteration 1
+0(0.00%) conflict; 743(76.60%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 7.385ns/0.000ns; real time: 10 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 735(75.77%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 7.429ns/0.000ns; real time: 10 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 734(75.67%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 7.556ns/0.000ns; real time: 10 secs 
+Level 4, iteration 1
+14(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 22:31:26 07/14/24
+Level 4, iteration 1
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 22:31:26 07/14/24
+
+Start NBR section for re-routing at 22:31:26 07/14/24
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs 
+
+Start NBR section for post-routing at 22:31:26 07/14/24
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 6.959ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=ICLK loads=1 clock_loads=1
+
+Total CPU time 10 secs 
+Total REAL time: 11 secs 
+Completely routed.
+End of route.  970 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 6.959
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 10 secs 
+Total REAL time to completion: 11 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt new file mode 100644 index 0000000..580caf1 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt @@ -0,0 +1,67 @@ + +Copyright (C) 1994-2018 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: N-2018.03L-SP1-1 +Install: C:\lscc\diamond\3.11_x64\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Sun Jul 14 22:31:10 2024 + +##### FILES SYNTAX CHECKED ############################################## +Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +-------------------------------------------------------------------------------------------------------------- +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10 + +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 + +0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65 +============================================================================================================== + + +Clock Load Summary +****************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +------------------------------------------------------------------------------------------------------------------------------ +PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) + +RCLK 0 RCLK(port) - - - + +System 0 - - - - + +RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - - +============================================================================================================================== diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html new file mode 100644 index 0000000..f3df900 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +

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RAM2GS_LCMXO2_1200HC project summary
Module Name:RAM2GS_LCMXO2_1200HCSynthesis:SynplifyPro
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2GS-LCMXO2.lpf
Physical Preference file:impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Product Version:3.11.3.469Patch Version:
Updated:2024/07/14 22:31:30
Implementation Location://Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1
Project File://Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf

+

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+

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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html new file mode 100644 index 0000000..6023296 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html @@ -0,0 +1,873 @@ + +Synthesis Report + + +
Synthesis Report
+#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
+#install: C:\lscc\diamond\3.11_x64\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Sun Jul 14 22:31:08 2024
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v" (library work)
+Verilog syntax check successful!
+Options changed - recompiling
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
+Running optimization stage 1 on OSCH .......
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ in library work.
+Running optimization stage 1 on EHXPLLJ .......
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v":8:7:8:10|Synthesizing module RPLL in library work.
+Running optimization stage 1 on RPLL .......
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+@W: CL318 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Running optimization stage 2 on RAM2GS .......
+@N: CL159 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":50:10:50:13|Input RCLK is unused.
+Running optimization stage 2 on REFB .......
+Running optimization stage 2 on EFB .......
+Running optimization stage 2 on VHI .......
+Running optimization stage 2 on ODDRXE .......
+Running optimization stage 2 on RPLL .......
+Running optimization stage 2 on EHXPLLJ .......
+Running optimization stage 2 on VLO .......
+Running optimization stage 2 on OSCH .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sun Jul 14 22:31:08 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sun Jul 14 22:31:08 2024
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sun Jul 14 22:31:08 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Database state : \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\|impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Sun Jul 14 22:31:10 2024
+
+###########################################################]
+# Sun Jul 14 22:31:10 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt 
+Printing clock  summary report in "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+syn_allowed_resources : blockrams=7  set on top level netlist RAM2GS
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start                         Requested     Requested     Clock        Clock                   Clock
+Level     Clock                         Frequency     Period        Type         Group                   Load 
+--------------------------------------------------------------------------------------------------------------
+0 -       PHI2                          2.9 MHz       350.000       declared     default_clkgroup        20   
+                                                                                                              
+0 -       nCRAS                         2.9 MHz       350.000       declared     default_clkgroup        15   
+                                                                                                              
+0 -       nCCAS                         2.9 MHz       350.000       declared     default_clkgroup        10   
+                                                                                                              
+0 -       RCLK                          62.5 MHz      16.000        declared     default_clkgroup        0    
+                                                                                                              
+0 -       System                        100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                              
+0 -       RPLL|CLKOP_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     65   
+==============================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                              Clock     Source                            Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock                         Load      Pin                               Seq Example     Seq Example       Comb Example      
+------------------------------------------------------------------------------------------------------------------------------
+PHI2                          20        PHI2(port)                        Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                                                              
+nCRAS                         15        nCRAS(port)                       CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                                                              
+nCCAS                         10        nCCAS(port)                       WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                                                              
+RCLK                          0         RCLK(port)                        -               -                 -                 
+                                                                                                                              
+System                        0         -                                 -               -                 -                 
+                                                                                                                              
+RPLL|CLKOP_inferred_clock     65        rpll.PLLInst_0.CLKOP(EHXPLLJ)     CASr2.C         -                 -                 
+==============================================================================================================================
+
+@W: MT529 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":174:4:174:9|Found inferred clock RPLL|CLKOP_inferred_clock which controls 65 sequential elements including RCKE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 41 clock pin(s) of sequential element(s)
+1 gated/generated clock tree(s) driving 65 clock pin(s) of sequential element(s)
+0 instances converted, 65 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+====================================================== Gated/Generated Clocks ======================================================
+Clock Tree ID     Driving Element          Drive Element Type     Unconverted Fanout     Sample Instance     Explanation            
+------------------------------------------------------------------------------------------------------------------------------------
+@KP:ckid0_0       rpll.PLLInst_0.CLKOP     EHXPLLJ                65                     RCKE                Black box on clock path
+====================================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Jul 14 22:31:10 2024
+
+###########################################################]
+# Sun Jul 14 22:31:11 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":180:4:180:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":167:4:167:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:00s		     2.24ns		 198 /       106
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 152MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 152MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 153MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
+N-2018.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
+
+@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":57:11:57:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\rpll.v":64:12:64:20|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+@W: MT420 |Found inferred clock RPLL|CLKOP_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rpll.PCLK.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Sun Jul 14 22:31:13 2024
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 3.291
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                              Requested     Estimated     Requested     Estimated                 Clock        Clock              
+Starting Clock                Frequency     Frequency     Period        Period        Slack       Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------
+PHI2                          2.9 MHz       69.1 MHz      350.000       14.481        167.760     declared     default_clkgroup   
+RCLK                          62.5 MHz      NA            16.000        NA            NA          declared     default_clkgroup   
+RPLL|CLKOP_inferred_clock     100.0 MHz     149.0 MHz     10.000        6.709         3.291       inferred     Inferred_clkgroup_0
+nCCAS                         2.9 MHz       NA            350.000       NA            NA          declared     default_clkgroup   
+nCRAS                         2.9 MHz       NA            350.000       NA            NA          declared     default_clkgroup   
+System                        100.0 MHz     388.0 MHz     10.000        2.577         7.423       system       system_clkgroup    
+==================================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                   Ending                     |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------------------------------------------
+System                     System                     |  10.000      10.000  |  No paths    -        |  No paths    -        |  No paths    -      
+System                     RPLL|CLKOP_inferred_clock  |  10.000      7.423   |  No paths    -        |  No paths    -        |  No paths    -      
+PHI2                       PHI2                       |  No paths    -       |  350.000     347.124  |  175.000     167.760  |  175.000     173.428
+PHI2                       RPLL|CLKOP_inferred_clock  |  No paths    -       |  No paths    -        |  No paths    -        |  Diff grp    -      
+nCRAS                      RPLL|CLKOP_inferred_clock  |  No paths    -       |  No paths    -        |  No paths    -        |  Diff grp    -      
+RPLL|CLKOP_inferred_clock  System                     |  10.000      8.892   |  No paths    -        |  No paths    -        |  No paths    -      
+RPLL|CLKOP_inferred_clock  PHI2                       |  Diff grp    -       |  No paths    -        |  Diff grp    -        |  No paths    -      
+RPLL|CLKOP_inferred_clock  nCRAS                      |  No paths    -       |  No paths    -        |  Diff grp    -        |  No paths    -      
+RPLL|CLKOP_inferred_clock  RPLL|CLKOP_inferred_clock  |  10.000      3.291   |  No paths    -        |  No paths    -        |  No paths    -      
+===================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                Starting                                         Arrival            
+Instance        Reference     Type         Pin     Net           Time        Slack  
+                Clock                                                               
+------------------------------------------------------------------------------------
+Bank_0io[0]     PHI2          IFS1P3DX     Q       Bank[0]       0.972       167.760
+Bank_0io[1]     PHI2          IFS1P3DX     Q       Bank[1]       0.972       167.760
+Bank_0io[2]     PHI2          IFS1P3DX     Q       Bank[2]       0.972       167.760
+Bank_0io[3]     PHI2          IFS1P3DX     Q       Bank[3]       0.972       167.760
+Bank_0io[4]     PHI2          IFS1P3DX     Q       Bank[4]       0.972       167.760
+Bank_0io[5]     PHI2          IFS1P3DX     Q       Bank[5]       0.972       167.760
+Bank_0io[6]     PHI2          IFS1P3DX     Q       Bank[6]       0.972       167.760
+Bank_0io[7]     PHI2          IFS1P3DX     Q       Bank[7]       0.972       167.760
+XOR8MEG         PHI2          FD1P3AX      Q       XOR8MEG       1.044       173.428
+CmdEnable       PHI2          FD1S3AX      Q       CmdEnable     1.180       347.124
+====================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                Starting                                                  Required            
+Instance        Reference     Type        Pin     Net                     Time         Slack  
+                Clock                                                                         
+----------------------------------------------------------------------------------------------
+CmdEnable       PHI2          FD1S3AX     D       CmdEnable_1             175.462      167.760
+CmdLEDEN        PHI2          FD1P3AX     SP      XOR8MEG17               174.528      168.897
+CmdUFMShift     PHI2          FD1P3AX     SP      XOR8MEG17               174.528      168.897
+CmdUFMWrite     PHI2          FD1P3AX     SP      XOR8MEG17               174.528      168.897
+Cmdn8MEGEN      PHI2          FD1P3AX     SP      XOR8MEG17               174.528      168.897
+XOR8MEG         PHI2          FD1P3AX     SP      XOR8MEG17               174.528      168.897
+ADSubmitted     PHI2          FD1S3AX     D       ADSubmitted_2           175.089      169.017
+C1Submitted     PHI2          FD1S3AX     D       C1Submitted_1           175.089      169.017
+CmdValid        PHI2          FD1S3AX     D       CmdValid_0              175.089      169.049
+CmdUFMData      PHI2          FD1P3AX     SP      CmdUFMData_1_sqmuxa     174.528      169.505
+==============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      175.000
+    - Setup time:                            -0.462
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         175.462
+
+    - Propagation time:                      7.703
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 167.760
+
+    Number of logic level(s):                7
+    Starting point:                          Bank_0io[0] / Q
+    Ending point:                            CmdEnable / D
+    The start point is clocked by            PHI2 [rising] on pin SCLK
+    The end   point is clocked by            PHI2 [falling] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Bank_0io[0]        IFS1P3DX     Q        Out     0.972     0.972       -         
+Bank[0]            Net          -        -       -         -           1         
+un1_Bank_1_4       ORCALUT4     A        In      0.000     0.972       -         
+un1_Bank_1_4       ORCALUT4     Z        Out     1.153     2.125       -         
+un1_Bank_1_4       Net          -        -       -         -           3         
+C1WR_7             ORCALUT4     C        In      0.000     2.125       -         
+C1WR_7             ORCALUT4     Z        Out     1.089     3.213       -         
+C1WR_7             Net          -        -       -         -           2         
+C1WR               ORCALUT4     C        In      0.000     3.213       -         
+C1WR               ORCALUT4     Z        Out     1.089     4.302       -         
+C1WR               Net          -        -       -         -           2         
+un1_ADWR           ORCALUT4     B        In      0.000     4.302       -         
+un1_ADWR           ORCALUT4     Z        Out     1.153     5.455       -         
+un1_ADWR           Net          -        -       -         -           3         
+un1_CMDWR          ORCALUT4     B        In      0.000     5.455       -         
+un1_CMDWR          ORCALUT4     Z        Out     1.017     6.472       -         
+un1_CMDWR          Net          -        -       -         -           1         
+CmdEnable_1_am     ORCALUT4     C        In      0.000     6.472       -         
+CmdEnable_1_am     ORCALUT4     Z        Out     1.017     7.489       -         
+CmdEnable_1_am     Net          -        -       -         -           1         
+CmdEnable_1        PFUMX        BLUT     In      0.000     7.489       -         
+CmdEnable_1        PFUMX        Z        Out     0.214     7.703       -         
+CmdEnable_1        Net          -        -       -         -           1         
+CmdEnable          FD1S3AX      D        In      0.000     7.703       -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RPLL|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                        Arrival          
+Instance      Reference                     Type        Pin     Net           Time        Slack
+              Clock                                                                            
+-----------------------------------------------------------------------------------------------
+InitReady     RPLL|CLKOP_inferred_clock     FD1S3AX     Q       InitReady     1.326       3.291
+FS[15]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[15]        1.188       3.429
+FS[16]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[16]        1.188       3.429
+FS[17]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[17]        1.188       3.429
+FS[13]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[13]        1.276       3.777
+FS[9]         RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[9]         1.268       3.785
+FS[10]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[10]        1.268       3.785
+FS[14]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[14]        1.260       3.793
+FS[12]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[12]        1.284       4.049
+FS[11]        RPLL|CLKOP_inferred_clock     FD1S3AX     Q       FS[11]        1.272       4.061
+===============================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                                           Required          
+Instance       Reference                     Type        Pin     Net              Time         Slack
+               Clock                                                                                
+----------------------------------------------------------------------------------------------------
+wb_dati[2]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[2]     10.089       3.291
+wb_dati[4]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[4]     10.089       3.291
+wb_dati[5]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[5]     10.089       3.291
+wb_dati[7]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[7]     10.089       3.291
+wb_dati[3]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[3]     10.089       3.395
+wb_dati[6]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[6]     10.089       3.395
+wb_dati[1]     RPLL|CLKOP_inferred_clock     FD1P3AX     D       wb_dati_5[1]     10.089       4.483
+FS[17]         RPLL|CLKOP_inferred_clock     FD1S3AX     D       FS_s[17]         9.894        4.551
+LEDEN          RPLL|CLKOP_inferred_clock     FD1P3AX     SP      N_63             9.528        4.604
+n8MEGEN        RPLL|CLKOP_inferred_clock     FD1P3AX     SP      N_63             9.528        4.604
+====================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         10.089
+
+    - Propagation time:                      6.798
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     3.291
+
+    Number of logic level(s):                5
+    Starting point:                          InitReady / Q
+    Ending point:                            wb_dati[2] / D
+    The start point is clocked by            RPLL|CLKOP_inferred_clock [rising] on pin CK
+    The end   point is clocked by            RPLL|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+InitReady                     FD1S3AX      Q        Out     1.326     1.326       -         
+InitReady                     Net          -        -       -         -           35        
+wb_adr_cnst_sn.m2_i_o3        ORCALUT4     B        In      0.000     1.326       -         
+wb_adr_cnst_sn.m2_i_o3        ORCALUT4     Z        Out     1.317     2.643       -         
+N_242                         Net          -        -       -         -           18        
+FS_RNI7U6M[14]                ORCALUT4     B        In      0.000     2.643       -         
+FS_RNI7U6M[14]                ORCALUT4     Z        Out     1.193     3.836       -         
+N_134                         Net          -        -       -         -           4         
+un1_FS_26_1_0_a2_RNI761E1     ORCALUT4     C        In      0.000     3.836       -         
+un1_FS_26_1_0_a2_RNI761E1     ORCALUT4     Z        Out     1.153     4.989       -         
+wb_adr_21_sqmuxa_s9           Net          -        -       -         -           3         
+FS_RNIFUUT2[9]                ORCALUT4     C        In      0.000     4.989       -         
+FS_RNIFUUT2[9]                ORCALUT4     Z        Out     1.193     6.181       -         
+N_194                         Net          -        -       -         -           4         
+wb_dati_5_1_iv[2]             ORCALUT4     B        In      0.000     6.181       -         
+wb_dati_5_1_iv[2]             ORCALUT4     Z        Out     0.617     6.798       -         
+wb_dati_5[2]                  Net          -        -       -         -           1         
+wb_dati[2]                    FD1P3AX      D        In      0.000     6.798       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       7.423 
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       9.472 
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       9.472 
+OSCH_inst            System        OSCH     OSC         ICLK           0.000       10.000
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                   Starting                                         Required           
+Instance           Reference     Type        Pin      Net           Time         Slack 
+                   Clock                                                               
+---------------------------------------------------------------------------------------
+LEDEN              System        FD1P3AX     SP       N_63          9.528        7.423 
+n8MEGEN            System        FD1P3AX     SP       N_63          9.528        7.423 
+wb_cyc_stb         System        FD1P3IX     SP       N_51          9.528        8.912 
+LEDEN              System        FD1P3AX     D        LEDEN_6       10.089       9.472 
+n8MEGEN            System        FD1P3AX     D        n8MEGEN_6     10.089       9.472 
+rpll.PLLInst_0     System        EHXPLLJ     CLKI     ICLK          10.000       10.000
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.528
+
+    - Propagation time:                      2.106
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 7.423
+
+    Number of logic level(s):                2
+    Starting point:                          ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            LEDEN / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RPLL|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net                    Pin        Pin               Arrival     No. of    
+Name                 Type         Name       Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBACKO     Out     0.000     0.000       -         
+wb_ack               Net          -          -       -         -           2         
+un1_FS_38_i_a3_0     ORCALUT4     B          In      0.000     0.000       -         
+un1_FS_38_i_a3_0     ORCALUT4     Z          Out     1.017     1.017       -         
+un1_FS_38_i_a3_0     Net          -          -       -         -           1         
+un1_FS_38_i_0        ORCALUT4     C          In      0.000     1.017       -         
+un1_FS_38_i_0        ORCALUT4     Z          Out     1.089     2.106       -         
+N_63                 Net          -          -       -         -           2         
+LEDEN                FD1P3AX      SP         In      0.000     2.106       -         
+=====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_1200hc-4
+
+Register bits: 106 of 1280 (8%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+EHXPLLJ:        1
+FD1P3AX:        28
+FD1P3IX:        3
+FD1S3AX:        37
+FD1S3IX:        3
+GSR:            1
+IB:             24
+IFS1P3DX:       9
+IFS1P3IX:       10
+IFS1P3JX:       2
+INV:            7
+OB:             31
+ODDRXE:         1
+OFS1P3BX:       4
+OFS1P3DX:       8
+OFS1P3IX:       1
+OFS1P3JX:       1
+ORCALUT4:       186
+OSCH:           1
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            3
+true:           1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 157MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Sun Jul 14 22:31:13 2024
+
+###########################################################]
+
+
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+ + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..8133d1e --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,21 @@ + 
Setting log file to '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
+(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/REFB.v
+(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2-IntOsc.v
+WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2-IntOsc.v(23,47-23,52) (VERI-1875) identifier Ready is used before its declaration
+(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v
+INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2-IntOsc.v(1,8-1,14) (VERI-1018) compiling module RAM2GS
+INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2-IntOsc.v(1,1-632,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
+INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v(8,1-93,10) (VERI-9000) elaborating module 'RPLL_uniq_1'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1'
+INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1730,1-1786,10) (VERI-9000) elaborating module 'EHXPLLJ_uniq_1'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
+Done: design load finished with (0) errors, and (1) warnings
+
+
\ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC-IntOsc/msg_file.log b/CPLD/LCMXO2-1200HC-IntOsc/msg_file.log new file mode 100644 index 0000000..f93e7cc --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/msg_file.log @@ -0,0 +1,29 @@ +SCUBA, Version Diamond (64-bit) 3.11.3.469 +Sun Jul 14 22:23:22 2024 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 + Circuit name : RPLL + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLKI + Outputs : CLKOP + I/O buffer : not inserted + EDIF output : RPLL.edn + Verilog output : RPLL.v + Verilog template : RPLL_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : RPLL.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/promote.xml b/CPLD/LCMXO2-1200HC-IntOsc/promote.xml new file mode 100644 index 0000000..b5a32a4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/promote.xml @@ -0,0 +1,3 @@ + + + diff --git a/CPLD/LCMXO2-1200HC-IntOsc/reportview.xml b/CPLD/LCMXO2-1200HC-IntOsc/reportview.xml new file mode 100644 index 0000000..abe56e8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC-IntOsc/reportview.xml @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/CPLD/RAM2GS-LCMXO2-IntOsc.v b/CPLD/RAM2GS-LCMXO2-IntOsc.v new file mode 100644 index 0000000..43555f7 --- /dev/null +++ b/CPLD/RAM2GS-LCMXO2-IntOsc.v @@ -0,0 +1,632 @@ +module RAM2GS(PHI2, MAin, CROW, Din, Dout, + nCCAS, nCRAS, nFWE, LED, + RBA, RA, RD, nRCS, RCLK, RCLKout, RCKE, + nRWE, nRRAS, nRCAS, RDQMH, RDQML); + + + /* 65816 Phase 2 Clock */ + input PHI2; + + /* Async. DRAM Control Inputs */ + input nCCAS, nCRAS; + + /* Synchronized PHI2 and DRAM signals */ + reg PHI2r, PHI2r2, PHI2r3; + reg RASr, RASr2, RASr3; + reg CASr, CASr2, CASr3; + reg FWEr; + reg CBR; + + /* Activity LED */ + reg LEDEN; + output LED; + assign LED = !(!nCRAS && !CBR && LEDEN && Ready); + + /* 65816 Data */ + input [7:0] Din; + output [7:0] Dout; + assign Dout[7:0] = RD[7:0]; + + /* Latched 65816 Bank Address */ + reg [7:0] Bank; + + /* Async. DRAM Address Bus */ + input [1:0] CROW; + input [9:0] MAin; + input nFWE; + reg n8MEGEN = 0; + reg XOR8MEG = 0; + + /* Internal clock */ + wire ICLK; + defparam OSCH_inst.NOM_FREQ = "133.00"; + OSCH OSCH_inst(.STDBY(1'b0), .OSC(ICLK), .SEDSTDBY()); + + /* PLL */ + wire PCLK; + RPLL rpll (.CLKI(ICLK), .CLKOP(PCLK)); + + /* SDRAM Clock in */ + input RCLK; + + /* Clock net tie */ + wire CLK = PCLK; + + /* SDRAM clock out */ + output RCLKout; + ODDRXE rclk_oddr(.D0(1'b0), .D1(1'b1), + .SCLK(CLK), .RST(1'b0), .Q(RCLKout)); + + /* SDRAM */ + reg RCKEEN; + output reg RCKE = 0; + output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1; + output reg [1:0] RBA; + reg nRowColSel; + reg RA11; + reg RA10; + reg [9:0] RowA; + output [11:0] RA; + assign RA[11] = RA11; + assign RA[10] = RA10; + assign RA[9:0] = !nRowColSel ? RowA[9:0] : MAin[9:0]; + output RDQML, RDQMH; + assign RDQML = !nRowColSel ? 1'b1 : !MAin[9]; + assign RDQMH = !nRowColSel ? 1'b1 : MAin[9]; + reg [7:0] WRD; + inout [7:0] RD; + assign RD[7:0] = (!nCCAS && !nFWE) ? WRD[7:0] : 8'bZ; + + /* UFM Interface */ + reg wb_rst; + reg wb_cyc_stb; + reg wb_req; + reg wb_we; + reg [7:0] wb_adr; + reg [7:0] wb_dati; + wire wb_ack; + wire [7:0] wb_dato; + wire ufm_irq; + REFB ufmefb ( + .wb_clk_i(CLK), + .wb_rst_i(wb_rst), + .wb_cyc_i(wb_cyc_stb), + .wb_stb_i(wb_cyc_stb), + .wb_we_i(wb_we), + .wb_adr_i(wb_adr), + .wb_dat_i(wb_dati), + .wb_dat_o(wb_dato), + .wb_ack_o(wb_ack), + .wbc_ufm_irq(ufm_irq)); + + /* UFM Command Interface */ + reg C1Submitted = 0; + reg ADSubmitted = 0; + reg CmdEnable = 0; + reg CmdValid = 0; + reg Cmdn8MEGEN = 0; + reg CmdLEDEN = 0; + reg CmdUFMWrite = 0; + reg CmdUFMShift = 0; + reg CmdUFMData = 0; + wire ADWR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFF && !nFWE; + wire C1WR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFE && !nFWE; + wire CMDWR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFD && !nFWE; + + /* State Counters */ + reg InitReady = 0; // 1 if ready for init sequence + reg Ready = 0; // 1 if done with init sequence + reg [1:0] S = 0; // post-RAS State counter + reg [17:0] FS = 0; // Fast init state counter + reg [3:0] IS = 0; // Init state counter + + /* Synchronize PHI2, RAS, CAS */ + always @(posedge CLK) begin + PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2; + RASr <= !nCRAS; RASr2 <= RASr; RASr3 <= RASr2; + CASr <= !nCCAS; CASr2 <= CASr; CASr3 <= CASr2; + end + + /* Latch 65816 bank when PHI2 rises */ + always @(posedge PHI2) begin + if (Ready) RA11 <= (Din[6] && !n8MEGEN) ^ XOR8MEG; // Set RA11 + else RA11 <= 1'b0; // Reserved in mode register + Bank[7:0] <= Din[7:0]; // Latch bank + end + + /* Latch bank address, row address, WE, and CAS when RAS falls */ + always @(negedge nCRAS) begin + if (Ready) begin + RBA[1:0] <= CROW[1:0]; + RowA[9:0] <= MAin[9:0]; + end else begin + RBA[1:0] <= 2'b00; // Reserved in mode register + RowA[9] <= 1'b1; // "1" for single write mode + RowA[8] <= 1'b0; // Reserved + RowA[7] <= 1'b0; // "0" for not test mode + RowA[6:4] <= 3'b010; // "2" for CAS latency 2 + RowA[3] <= 1'b0; // "0" for sequential burst (not used) + RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + end + FWEr <= !nFWE; + CBR <= !nCCAS; + end + + /* Latch write data when CAS falls */ + always @(negedge nCCAS) begin + WRD[7:0] <= Din[7:0]; + end + + /* State counter from RAS */ + always @(posedge CLK) begin + if (!RASr2) S <= 0; + else if (S==2'h3) S <= 2'h3; + else S <= S+2'h1; + end + /* Init state counter */ + always @(posedge CLK) begin + // Wait ~4.178ms (at 62.5 MHz) before starting init sequence + FS <= FS+18'h1; + if (FS[17:10]==8'hFF) InitReady <= 1'b1; + end + + /* SDRAM CKE */ + always @(posedge CLK) begin + // Only 1 LUT4 allowed for this function! + RCKE <= ((RASr || RASr2) && RCKEEN) || (!RASr2 && RASr3); + end + + /* SDRAM command */ + always @(posedge CLK) begin + if (Ready) begin + if (S==0) begin + if (RASr2) begin + if (CBR) begin + // AREF + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end else begin + // ACT + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // Bank RA10 consistently "1" + end + // Enable clock only for reads + RCKEEN <= !CBR && !FWEr; + end else if (RCKE) begin + // PCall + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b0; + RA10 <= 1'b1; // "all" + RCKEEN <= 1'b1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + RCKEEN <= 1'b1; + end + nRowColSel <= 1'b0; // Select registered row addres + end else if (S==1) begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + nRowColSel <= 1'b1; // Select asynchronous column address + RCKEEN <= !CBR; // Disable clock if refresh cycle + end else if (S==2) begin + if (!FWEr && !CBR) begin + // RD + nRCS <= 1'b0; + nRRAS <= 1'b1; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // Auto-precharge + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + nRowColSel <= 1'b1; // Select asynchronous column address + RCKEEN <= !CBR && FWEr; // Enable clock only for writes + end else if (S==3) begin + if (CASr2 && !CASr3 && !CBR && FWEr) begin + // WR + nRCS <= 1'b0; + nRRAS <= 1'b1; + nRCAS <= 1'b0; + nRWE <= 1'b0; + RA10 <= 1'b1; // Auto-precharge + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + nRowColSel <= !(!FWEr || CASr3 || CBR); + RCKEEN <= !(!FWEr || CASr2 || CBR); + end + end else if (InitReady) begin + if (S==0 && RASr2) begin + if (IS==0) begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end else if (IS==1) begin + // PC all + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b0; + RA10 <= 1'b1; // "all" + end else if (IS==9) begin + // Load mode register + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b0; + RA10 <= 1'b0; // Reserved in mode register + end else begin + // AREF + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + IS <= IS+4'h1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + if (S==3 && !RASr2 && IS==15) Ready <= 1'b1; + nRowColSel <= 1'b0; // Select registered row address + RCKEEN <= 1'b1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + nRowColSel <= 1'b0; // Select registered row address + RCKEEN <= 1'b0; + end + end + + /* Submit command when PHI2 falls */ + always @(negedge PHI2) begin + // Magic number check + if (C1WR && Din[7:0]==8'hC1) begin // "C1" magic number + if (ADSubmitted) begin + CmdEnable <= 1'b1; + end + C1Submitted <= 1'b1; + ADSubmitted <= 1'b0; + end else if (ADWR && Din[7:0]==8'hAD) begin // "AD" magic number + if (C1Submitted) begin + CmdEnable <= 1'b1; + end + ADSubmitted <= 1'b1; + C1Submitted <= 1'b0; + end else if (C1WR || ADWR) begin // wrong magic number submitted + CmdEnable <= 1'b0; + C1Submitted <= 1'b0; + ADSubmitted <= 1'b0; + end else if (CMDWR) CmdEnable <= 1'b0; + + // Submit command + if (CMDWR && CmdEnable) begin + // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED + // if (Din[7:4]==4'h0) begin // MAX w/o LED + // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM + if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2 + XOR8MEG <= Din[0] && !(LEDEN && Din[1]); + CmdValid <= 1'b0; + end else if (Din[7:4]==4'h0) begin // Unsupported type + XOR8MEG <= 0; + CmdValid <= 1'b0; + end else if (Din[7:4]==4'h1) begin + CmdLEDEN <= Din[1]; + Cmdn8MEGEN <= !Din[0]; + CmdUFMShift <= 1'b0; + CmdUFMWrite <= 1'b0; + CmdValid <= 1'b1; + end else if (Din[7:4]==4'h2) begin + // Reserved for MAX commands + CmdValid <= 1'b0; + end else if (Din[7:4]==4'h3 && !Din[3]) begin + // Reserved for SPI (LCMXO, iCE40) commands + // Din[2] - CS + // Din[1] - SCK + // Din[0] - SDI + CmdValid <= 1'b0; + end else if (Din[7:4]==4'h3 && Din[3]) begin + // LCMXO2 commands + // Din[1] - Shift when low, execute when high + // Din[0] - Shift data + CmdUFMShift <= !Din[1]; + CmdUFMWrite <= Din[1:0] == 2'b10; + CmdUFMData <= Din[0]; + CmdLEDEN <= LEDEN; + Cmdn8MEGEN <= n8MEGEN; + CmdValid <= 1'b1; + end else CmdValid <= 1'b0; + end else CmdValid <= 1'b0; + end + + /* UFM Control */ + always @(posedge CLK) begin + if (!InitReady && FS[17:15]==3'h0) begin + wb_rst <= !FS[14]; + wb_we <= 1'b0; + wb_cyc_stb <= 1'b0; + wb_req <= 1'b0; + wb_adr[7:0] <= 8'h00; + wb_dati[7:0] <= 8'h00; + end else if (!InitReady && FS[17:15]==3'h1) begin + wb_rst <= 1'b0; + + if (FS[8:0]==0) wb_cyc_stb <= 0; + else if (FS[8:0]==1 && wb_req) wb_cyc_stb <= 1; + else if (wb_ack) wb_cyc_stb <= 0; + case (FS[14:9]) + 0: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 1: begin // Enable configuration interface - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h74; + wb_req <= 1; + end 2: begin // Enable configuration interface - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h08; + wb_req <= 1; + end 3: begin // Enable configuration interface - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 4: begin // Enable configuration interface - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 5: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 6: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 7: begin // Poll status register - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h3C; + wb_req <= 1; + end 8: begin // Poll status register - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 9: begin // Poll status register - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 10: begin // Poll status register - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 11, 12, 13, 14: begin // Read status register 1-4 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h3C; + wb_req <= 1; + end 15: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 16: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 17: begin // Set UFM address - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hB4; + wb_req <= 1; + end 18: begin // Set UFM address - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 19: begin // Set UFM address - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 20: begin // Set UFM address - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 21: begin // Set UFM address - data 1/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h40; + wb_req <= 1; + end 22: begin // Set UFM address - data 2/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 23: begin // Set UFM address - data 3/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 24: begin // Set UFM address - data 4/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 190; + wb_req <= 1; + end 25: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 26: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 27: begin // Read UFM page - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hCA; + wb_req <= 1; + end 28: begin // Read UFM page - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h10; + wb_req <= 1; + end 29: begin // Read UFM page - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 30: begin // Read UFM page - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h01; + wb_req <= 1; + end 31: begin // Read UFM page - data 0 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + if (wb_ack) begin + LEDEN <= wb_dato[1]; + n8MEGEN <= wb_dato[0]; + end + end 32, 33, 34, + 35, 36, 37, 38, + 39, 40, 41, 42, + 43, 44, 45, 46: begin // Read UFM page - data 1-15 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 47: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 48: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 49: begin // Disable configuration interface - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h26; + wb_req <= 1; + end 50: begin // Disable configuration interface - operand 1/2 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 51: begin // Disable configuration interface - operand 2/2 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 52: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 53: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 54: begin // Bypass - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hFF; + wb_req <= 1; + end 55: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end default: begin + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 0; + end + endcase + end else if (!InitReady) begin + wb_rst <= 1'b0; + wb_cyc_stb <= 1'b0; + wb_req <= 1'b0; + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h00; + wb_dati[7:0] <= 8'h00; + end else if (!PHI2r2 && PHI2r3 && CmdValid) begin + wb_rst <= 1'b0; + wb_req <= 1'b0; + // Set user command signals after PHI2 falls + LEDEN <= CmdLEDEN; + n8MEGEN <= Cmdn8MEGEN; + if (CmdUFMShift) begin + wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] }; + wb_dati[7:0] <= { wb_dati[6:0], wb_we }; + wb_we <= CmdUFMData; + end + wb_cyc_stb <= CmdUFMWrite; + end else wb_cyc_stb <= 0; + end +endmodule