diff --git a/CPLD/LCMXO2-1200HC/RAM2GS-LCMXO2.ccl b/CPLD/LCMXO2-1200HC/RAM2GS-LCMXO2.ccl
new file mode 100644
index 0000000..43a374b
--- /dev/null
+++ b/CPLD/LCMXO2-1200HC/RAM2GS-LCMXO2.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
index 017cf1f..8d2aef6 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
@@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
-NOTE DATE CREATED: Thu Sep 21 05:40:22 2023 *
+NOTE DATE CREATED: Thu Oct 19 23:51:27 2023 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
@@ -13,6 +13,7 @@ NOTE PINS nRCAS : 52 : out *
NOTE PINS nRRAS : 54 : out *
NOTE PINS nRWE : 49 : out *
NOTE PINS RCKE : 53 : out *
+NOTE PINS RCLKout : 62 : out *
NOTE PINS RCLK : 63 : in *
NOTE PINS nRCS : 57 : out *
NOTE PINS RD[7] : 43 : inout *
@@ -24,7 +25,7 @@ NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS RA[11] : 59 : out *
NOTE PINS RA[10] : 64 : out *
-NOTE PINS RA[9] : 62 : out *
+NOTE PINS RA[9] : 47 : out *
NOTE PINS RA[8] : 65 : out *
NOTE PINS RA[7] : 75 : out *
NOTE PINS RA[6] : 68 : out *
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr
index 4b5ad23..b08bcc1 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr
@@ -1,9 +1,9 @@
----------------------------------------------------------------------
Report for cell RAM2GS.verilog
-Register bits: 109 of 1280 (9%)
+Register bits: 110 of 1280 (9%)
PIC Latch: 0
-I/O cells: 63
+I/O cells: 64
Cell usage:
cell count Res Usage(%)
BB 8 100.0
@@ -11,33 +11,33 @@ I/O cells: 63
EFB 1 100.0
FD1P3AX 25 100.0
FD1P3IX 2 100.0
- FD1S3AX 53 100.0
+ FD1S3AX 54 100.0
FD1S3IX 4 100.0
GSR 1 100.0
IB 25 100.0
IFS1P3DX 9 100.0
INV 7 100.0
- OB 30 100.0
+ OB 31 100.0
+ ODDRXE 1 100.0
OFS1P3BX 4 100.0
OFS1P3DX 11 100.0
OFS1P3JX 1 100.0
- ORCALUT4 213 100.0
- PFUMX 1 100.0
+ ORCALUT4 203 100.0
PUR 1 100.0
VHI 2 100.0
VLO 2 100.0
SUB MODULES
REFB 1 100.0
- TOTAL 411
+ TOTAL 403
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
- ORCALUT4 2 0.9
+ ORCALUT4 1 0.5
VHI 1 50.0
VLO 1 50.0
- TOTAL 5
+ TOTAL 4
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
index 52acd34..5381cd7 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
-Thu Sep 21 05:40:18 2023
+Thu Oct 19 23:51:23 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
@@ -83,4 +83,4 @@ Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
-Peak Memory Usage: 274 MB
+Peak Memory Usage: 275 MB
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit
index 2bad244..a212c27 100644
Binary files a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit differ
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
index 7ca1f94..61d257a 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
@@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
- (timeStamp 2023 9 21 5 39 42)
+ (timeStamp 2023 10 19 23 50 53)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
)
@@ -155,16 +155,6 @@
)
)
)
- (cell PFUMX (cellType GENERIC)
- (view PRIM (viewType NETLIST)
- (interface
- (port ALUT (direction INPUT))
- (port BLUT (direction INPUT))
- (port C0 (direction INPUT))
- (port Z (direction OUTPUT))
- )
- )
- )
(cell GSR (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
@@ -370,22 +360,17 @@
(port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT))
(port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT))
(port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT))
- (port (array (rename fs "FS[14:12]") 3) (direction INPUT))
+ (port (array (rename fs "FS[14:13]") 2) (direction INPUT))
(port wb_we (direction INPUT))
(port wb_cyc_stb (direction INPUT))
(port wb_rst (direction INPUT))
(port RCLK_c (direction INPUT))
+ (port g0_0_a3_1 (direction OUTPUT))
(port wb_ack (direction OUTPUT))
- (port N_4 (direction OUTPUT))
- (port N_226 (direction INPUT))
- (port N_214 (direction INPUT))
)
(contents
- (instance EFBInst_0_RNISI191 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (!B !A))"))
- )
- (instance EFBInst_0_RNISGNB (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (B A)))"))
+ (instance EFBInst_0_RNI8K48 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C (!B A))"))
)
(instance EFBInst_0 (viewRef verilog (cellRef EFB))
(property UFM_INIT_FILE_FORMAT (string "HEX"))
@@ -441,17 +426,18 @@
)
(instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
- (net N_214 (joined
- (portRef N_214)
- (portRef A (instanceRef EFBInst_0_RNISI191))
+ (net (rename FS_13 "FS[13]") (joined
+ (portRef (member fs 1))
+ (portRef A (instanceRef EFBInst_0_RNI8K48))
))
- (net N_226 (joined
- (portRef N_226)
- (portRef B (instanceRef EFBInst_0_RNISI191))
+ (net (rename FS_14 "FS[14]") (joined
+ (portRef (member fs 0))
+ (portRef B (instanceRef EFBInst_0_RNI8K48))
))
- (net g0_0_a3_2 (joined
- (portRef Z (instanceRef EFBInst_0_RNISGNB))
- (portRef C (instanceRef EFBInst_0_RNISI191))
+ (net wb_ack (joined
+ (portRef WBACKO (instanceRef EFBInst_0))
+ (portRef C (instanceRef EFBInst_0_RNI8K48))
+ (portRef wb_ack)
))
(net GND (joined
(portRef Z (instanceRef GND))
@@ -485,26 +471,9 @@
(portRef PLL0DATI6 (instanceRef EFBInst_0))
(portRef PLL0DATI7 (instanceRef EFBInst_0))
))
- (net N_4 (joined
- (portRef Z (instanceRef EFBInst_0_RNISI191))
- (portRef N_4)
- ))
- (net (rename FS_12 "FS[12]") (joined
- (portRef (member fs 2))
- (portRef A (instanceRef EFBInst_0_RNISGNB))
- ))
- (net (rename FS_13 "FS[13]") (joined
- (portRef (member fs 1))
- (portRef B (instanceRef EFBInst_0_RNISGNB))
- ))
- (net (rename FS_14 "FS[14]") (joined
- (portRef (member fs 0))
- (portRef C (instanceRef EFBInst_0_RNISGNB))
- ))
- (net wb_ack (joined
- (portRef WBACKO (instanceRef EFBInst_0))
- (portRef D (instanceRef EFBInst_0_RNISGNB))
- (portRef wb_ack)
+ (net g0_0_a3_1 (joined
+ (portRef Z (instanceRef EFBInst_0_RNI8K48))
+ (portRef g0_0_a3_1)
))
(net RCLK_c (joined
(portRef RCLK_c)
@@ -769,6 +738,19 @@
(property orig_inst_of (string "REFB"))
)
)
+ (cell ODDRXE (cellType GENERIC)
+ (view verilog (viewType NETLIST)
+ (interface
+ (port D0 (direction INPUT))
+ (port D1 (direction INPUT))
+ (port SCLK (direction INPUT))
+ (port RST (direction INPUT))
+ (port Q (direction OUTPUT))
+ )
+ (property GSR (string "ENABLED"))
+ (property orig_inst_of (string "ODDRXE"))
+ )
+ )
(cell RAM2GS (cellType GENERIC)
(view verilog (viewType NETLIST)
(interface
@@ -786,6 +768,7 @@
(port (array (rename rd "RD[7:0]") 8) (direction INOUT))
(port nRCS (direction OUTPUT))
(port RCLK (direction INPUT))
+ (port RCLKout (direction OUTPUT))
(port RCKE (direction OUTPUT))
(port nRWE (direction OUTPUT))
(port nRRAS (direction OUTPUT))
@@ -802,83 +785,37 @@
(instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
(instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
- (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
- (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B+!A)+C B)+D B)"))
- )
- (instance (rename wb_dati_5_1_iv_0_a3_0_RNO_1 "wb_dati_5_1_iv_0_a3_0_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (!B A)))"))
- )
- (instance wb_we_0_i_0_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (!B !A))"))
- )
- (instance (rename FS_RNIHVJI_0_16 "FS_RNIHVJI_0[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B !A)))"))
- )
- (instance (rename FS_RNIJO0F_14 "FS_RNIJO0F[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A))"))
+ (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) )
+ (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
)
(instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (B+A)+D (!C A+C (B+A)))"))
)
- (instance (rename wb_dati_5_1_iv_i_i_1_RNO_3 "wb_dati_5_1_iv_i_i_1_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C A+C (!B A))"))
+ (instance (rename wb_dati_5_1_iv_0_1_RNO_7 "wb_dati_5_1_iv_0_1_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B+A)+C (!B !A+B A))"))
)
- (instance Ready_RNICVV51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B A))"))
- )
- (instance (rename wb_dati_5_1_iv_i_i_0_RNO_3 "wb_dati_5_1_iv_i_i_0_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (!B A)))"))
- )
- (instance nRCAS_r_i_0_o2_0_2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A)+C !A)"))
- )
- (instance un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D+(!C+(!B+A)))"))
- )
- (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D A+D (!C (B A)))"))
- )
- (instance RCKEEN_8_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
- )
- (instance (rename wb_adr_RNO_0_0 "wb_adr_RNO_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_0_RNO_7 "wb_dati_5_1_iv_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C (!B A))"))
)
- (instance wb_we_0_i_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C A+C (!B+A))"))
+ (instance (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)))"))
+ )
+ (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
+ )
+ (instance wb_we_0_0_0_a2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_RNO_4 "wb_dati_5_1_iv_0_a2_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (B A)+D (!C (B A)+C (!B A+B !A)))"))
)
(instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
)
- (instance wb_reqe_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B !A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_RNO_0_7 "wb_dati_5_1_iv_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_RNO_7 "wb_dati_5_1_iv_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!B A)+D (C (!B A)))"))
- )
- (instance un1_CmdEnable20_0_0_a2_0_RNI00E51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (B A)))"))
- )
(instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D A+D (!C (B+A)+C A))"))
)
- (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B+!A)+C !A))"))
- )
- (instance nRCS_9_u_i_0_o2_1_RNIL2K71_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B !A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_o3_5 "wb_dati_5_1_iv_0_o3[5]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) )
- (instance (rename wb_dati_5_1_iv_0_o3_bm_5 "wb_dati_5_1_iv_0_o3_bm[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C A+C (!B+A))+D A)"))
- )
- (instance (rename wb_dati_5_1_iv_0_o3_am_5 "wb_dati_5_1_iv_0_o3_am[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D A+D (!C A+C (!B+A)))"))
- )
(instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B+A)"))
)
@@ -1054,6 +991,8 @@
)
(instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
)
+ (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+ )
(instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
)
(instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
@@ -1128,6 +1067,7 @@
(instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
+ (instance RCLKout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) )
@@ -1194,46 +1134,49 @@
(instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
)
- (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(!C A+C B))"))
- )
- (instance CmdEnable_0_sqmuxa_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance (rename wb_dati_5_1_iv_0_2 "wb_dati_5_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C (B+A))"))
- )
- (instance (rename wb_dati_5_1_iv_0_5 "wb_dati_5_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C (B+A))"))
- )
(instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C !B)+D (!C (!B A)))"))
)
- (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C+(!B+A))+D A)"))
+ (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C A+C B))"))
)
- (instance CmdUFMData_1_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B+A)+C (B A)))"))
- )
- (instance (rename wb_adr_RNO_0 "wb_adr_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A)))"))
- )
- (instance un1_ADWR_i_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance ADSubmitted_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B A)"))
)
- (instance CmdUFMData_1_sqmuxa_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B A)))"))
+ (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
)
- (instance (rename wb_dati_5_1_iv_i_i_3 "wb_dati_5_1_iv_i_i[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+ (instance CmdUFMData_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
+ )
+ (instance (rename wb_adr_5_i_i_0 "wb_adr_5_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C B+C (B+A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_2 "wb_dati_5_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C B+C (B+A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_5 "wb_dati_5_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C B+C (B+A)))"))
+ )
+ (instance XOR8MEG18_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B A)"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_4 "wb_dati_5_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C+(B+A))"))
+ )
+ (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
+ )
+ (instance (rename wb_adr_5_i_i_1 "wb_adr_5_i_i[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C+(B !A))"))
)
(instance (rename wb_dati_5_1_iv_0_6 "wb_dati_5_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C (!B !A)))"))
+ (property lut_function (string "(D+(!C A+C (B+A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_3 "wb_dati_5_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C B+C (B+A)))"))
+ )
+ (instance (rename wb_adr_5_i_i_5_0 "wb_adr_5_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D+(C+(B+A)))"))
)
(instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
@@ -1242,239 +1185,227 @@
(instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C !A+C (B !A))"))
)
- (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A)))"))
- )
- (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C !A+C (!B !A))+D (!C !A))"))
- )
- (instance (rename wb_dati_5_1_iv_0_1 "wb_dati_5_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C (!B !A)))"))
- )
- (instance un1_CmdEnable20_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C+(!B+!A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_1_6 "wb_dati_5_1_iv_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_1_4 "wb_dati_5_1_iv_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
- )
- (instance (rename wb_dati_5_1_iv_0_a3_3_7 "wb_dati_5_1_iv_0_a3_3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (!B !A)))"))
- )
(instance (rename wb_dati_5_0_iv_0_0 "wb_dati_5_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
)
- (instance wb_cyc_stb_4_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D C+D (C+(B A)))"))
- )
(instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D+(!C+(B+A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_a3_6 "wb_dati_5_1_iv_0_a3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (!B !A+B A)))"))
+ (instance un1_ADWR_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C+(!B+!A)))"))
)
- (instance wb_we_0_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C (B A)))"))
+ (instance (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C+(B+A)))"))
)
- (instance nRWE_s_i_0_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C (B !A)))"))
+ (instance wb_we_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C+(B A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+ (instance un1_CmdEnable20_0_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
)
- (instance (rename wb_dati_5_1_iv_i_i_0_3 "wb_dati_5_1_iv_i_i_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
- )
- (instance (rename wb_dati_5_1_iv_i_i_1_3 "wb_dati_5_1_iv_i_i_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
- )
- (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B !A+B A)"))
- )
- (instance XOR8MEG_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D C+D (C+(!B+!A)))"))
- )
- (instance un1_nRCAS_6_sqmuxa_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (B+A)+D !C)"))
- )
- (instance CmdUFMShift_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
- )
- (instance CmdUFMWrite_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_1_3 "wb_dati_5_1_iv_0_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D C+D (C+(B !A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B !A+B A)+C (!B !A))+D (C (!B !A)))"))
+ (instance (rename wb_dati_5_1_iv_0_2_4 "wb_dati_5_1_iv_0_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
)
- (instance nRCS_9_u_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D A+D (C+(B+A)))"))
+ (instance (rename wb_adr_5_i_i_0_1 "wb_adr_5_i_i_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C !B)+D (!C A+C (!B+A)))"))
)
- (instance nRWE_s_i_0_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A)))"))
+ (instance wb_cyc_stb_4_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D C+D (C+(B A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_a3_4 "wb_dati_5_1_iv_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance CmdUFMWrite_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D C+D (C+(B !A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_0_1 "wb_dati_5_1_iv_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B !A)))"))
+ )
+ (instance nRCS_9_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C (!B A)+C !B))"))
+ )
+ (instance (rename wb_adr_5_i_i_a2_5_0 "wb_adr_5_i_i_a2_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C (B !A))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_0_7 "wb_dati_5_1_iv_0_a2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (C (!B !A+B A)))"))
)
- (instance wb_cyc_stb_2_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C+A)+D (C+(B+A)))"))
+ (instance (rename wb_dati_5_1_iv_0_o2_0_5 "wb_dati_5_1_iv_0_o2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D C+D (C+(B !A)))"))
)
- (instance wb_cyc_stb_4_iv_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (B !A)))"))
+ (instance (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_a3_0_6 "wb_dati_5_1_iv_0_a3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (B A)))"))
+ (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
)
- (instance Cmdn8MEGEN_4_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_adr_5_i_i_1_0 "wb_adr_5_i_i_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+ )
+ (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_1_3 "wb_dati_5_1_iv_0_a2_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B !A)))"))
+ )
+ (instance CmdUFMShift_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
)
- (instance CmdLEDEN_4_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D C+D (C+(!B+!A)))"))
+ )
+ (instance (rename wb_adr_5_i_i_1_0_0 "wb_adr_5_i_i_1_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A))+D !B)"))
+ )
+ (instance wb_cyc_stb_4_iv_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
+ )
+ (instance wb_cyc_stb_2_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C A+C (B+A)))"))
+ )
+ (instance wb_we_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C (!B !A))"))
+ )
+ (instance (rename wb_adr_5_i_i_a2_7_0 "wb_adr_5_i_i_a2_7[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B !A)))"))
+ )
+ (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
+ )
+ (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))"))
)
- (instance un1_CmdEnable20_0_0_a3_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (B A))"))
+ (instance wb_we_0_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C (!B !A)))"))
)
- (instance wb_we_0_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D C+D (C+(B+!A)))"))
- )
- (instance un1_CmdEnable20_0_0_o3_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance un1_ADWR_i_o2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D+(C+(B+!A)))"))
)
- (instance nRCAS_r_i_0_o2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C !A+C (!B !A)))"))
- )
- (instance un1_CmdEnable20_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance un1_CmdEnable20_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!B !A)+D (C+(!B !A)))"))
)
- (instance (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C (B !A)))"))
- )
(instance (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
)
- (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
+ (instance (rename wb_adr_5_i_i_0_RNO_1 "wb_adr_5_i_i_0_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C+(B !A))"))
+ )
+ (instance wb_reqe_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C+(!B+!A)))"))
)
(instance CmdValid_RNIS5A51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
)
- (instance CmdUFMWrite_3_u_0_0_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_o2_3 "wb_dati_5_1_iv_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (B !A)+C (B A))+D (C (!B+!A)))"))
+ )
+ (instance (rename wb_adr_5_i_m2_0_6 "wb_adr_5_i_m2_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C !B+C (!B+A))"))
+ )
+ (instance (rename wb_adr_5_i_m2_0_5 "wb_adr_5_i_m2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C !B+C (!B+A))"))
+ )
+ (instance (rename wb_adr_5_i_m2_0_4 "wb_adr_5_i_m2_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C !B+C (!B+A))"))
+ )
+ (instance CmdEnable_0_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance (rename wb_dati_5_1_iv_i_i_a2_3_3 "wb_dati_5_1_iv_i_i_a2_3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_a2_7_1 "wb_dati_5_1_iv_0_a2_7[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B !A)"))
)
- (instance (rename wb_adr_5_i_0_a3_1 "wb_adr_5_i_0_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C !B+C A))"))
+ (instance CmdUFMWrite_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B A)"))
)
- (instance wb_we_0_i_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (!B !A)+C (!B A)))"))
+ (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B+A)"))
)
- (instance (rename wb_adr_5_i_0_a3_0_1 "wb_adr_5_i_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B A))+D (!C A))"))
+ (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
)
- (instance nRCS_9_u_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C !B))"))
+ (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B !A)"))
)
- (instance Ready_0_sqmuxa_0_a2_4_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (!B A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_a3_0_1 "wb_dati_5_1_iv_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (B !A))"))
+ (instance (rename wb_dati_5_1_iv_0_a2_2_1 "wb_dati_5_1_iv_0_a2_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B A)))"))
)
- (instance InitReady3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (B A)))"))
+ (instance (rename wb_adr_5_i_i_a2_0 "wb_adr_5_i_i_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)+C (!B A)))"))
)
- (instance (rename wb_adr_5_i_0_0_0 "wb_adr_5_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (B A)+C B))"))
+ (instance wb_we_0_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)))"))
)
- (instance (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D C+D (C+(!B A+B !A)))"))
+ (instance nRCS_9_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B !A)+C !A))"))
)
- (instance (rename wb_adr_5_i_m2_i_m2_6 "wb_adr_5_i_m2_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))"))
- )
- (instance (rename wb_adr_5_i_m2_i_m2_5 "wb_adr_5_i_m2_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))"))
- )
- (instance (rename wb_adr_5_i_m2_i_m2_4 "wb_adr_5_i_m2_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))"))
- )
- (instance (rename wb_adr_5_i_0_m2_0 "wb_adr_5_i_0_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))"))
- )
- (instance (rename wb_adr_5_i_0_m2_1 "wb_adr_5_i_0_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))"))
+ (instance (rename wb_adr_5_i_i_a2_0_1_1 "wb_adr_5_i_i_a2_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (B !A))+D (!C (B A)))"))
)
(instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C (B A)+C (!B+!A))"))
)
- (instance XOR8MEG_3_u_0_0_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C+(B+A)))"))
- )
- (instance nRowColSel_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C+(B !A)))"))
- )
- (instance (rename wb_adr_5_i_0_o2_0 "wb_adr_5_i_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A+B A)+C (!B !A))"))
- )
- (instance (rename wb_dati_5_1_iv_i_i_o2_3 "wb_dati_5_1_iv_i_i_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))"))
- )
- (instance CmdValid_2_i_o2_1_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance CmdValid_2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D+(!C !B+C (!B+!A)))"))
)
- (instance ADSubmitted_r_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_0_o2_1 "wb_dati_5_1_iv_0_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))"))
+ )
+ (instance CmdUFMData_1_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C (B A)))"))
+ )
+ (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C+(B+A)))"))
+ )
+ (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
+ )
+ (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (C+(!B A)))"))
)
(instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C+(!B+A))"))
)
- (instance (rename wb_adr_5_i_0_a3_4_0 "wb_adr_5_i_0_a3_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (!B A)))"))
- )
- (instance wb_cyc_stb_4_iv_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (!B !A)))"))
- )
- (instance un1_CmdEnable20_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance CmdEnable_0_sqmuxa_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (B !A)))"))
)
- (instance un1_CmdEnable20_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C (B A)))"))
+ )
+ (instance wb_cyc_stb_2_sqmuxa_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B !A)))"))
+ )
+ (instance nRWE_s_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (C (!B A)))"))
)
- (instance nRWE_s_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (C (!B A)))"))
)
- (instance XOR8MEG_3_u_0_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (!B A)))"))
+ (instance (rename wb_adr_5_i_i_1_0_tz_0_0 "wb_adr_5_i_i_1_0_tz_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C (!B A)))"))
)
- (instance wb_cyc_stb_2_sqmuxa_i_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (B !A)+C B)"))
+ (instance (rename wb_dati_5_1_iv_0_a2_1_1_7 "wb_dati_5_1_iv_0_a2_1_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (!B !A)))"))
)
- (instance (rename wb_dati_5_1_iv_0_a3_0_1_7 "wb_dati_5_1_iv_0_a3_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (!B A+B !A)))"))
+ (instance (rename wb_dati_5_1_iv_0_a2_1_0_6 "wb_dati_5_1_iv_0_a2_1_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)+C (!B A)))"))
)
- (instance (rename wb_dati_5_0_iv_0_a3_1_0 "wb_dati_5_0_iv_0_a3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (B A)+C (!B A)))"))
- )
- (instance RCKE_2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
)
(instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B+!A)"))
)
- (instance un1_nRCAS_6_sqmuxa_i_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C+(B+A))"))
- )
- (instance Ready_0_sqmuxa_0_a2_4_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C+(!B+!A))"))
)
- (instance (rename wb_adr_5_i_0_o2_0_0 "wb_adr_5_i_0_o2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A)+C (!B+A))"))
+ (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C+(B+A))"))
)
- (instance (rename FS_RNIVOOA_14 "FS_RNIVOOA[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (B A))"))
+ (instance (rename wb_adr_5_i_i_a2_3_0_0 "wb_adr_5_i_i_a2_3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
)
(instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B+A)"))
@@ -1482,222 +1413,252 @@
(instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B+A)"))
)
- (instance wb_cyc_stb_4_iv_0_a3_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A))"))
+ (instance (rename wb_adr_5_i_i_a2_6_0_0 "wb_adr_5_i_i_a2_6_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C (!B !A))"))
)
- (instance RCKEEN_8_u_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename FS_RNIQV0F_16 "FS_RNIQV0F[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C+(B+A))"))
+ )
+ (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B !A)))"))
+ )
+ (instance RCKEEN_8_u_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C (B !A))"))
)
- (instance (rename wb_adr_5_i_0_a3_0_2_0 "wb_adr_5_i_0_a3_0_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C (B !A)))"))
+ (instance wb_cyc_stb_2_sqmuxa_i_a2_3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)))"))
)
- (instance Ready_0_sqmuxa_0_a2_4_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance InitReady3_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (B A)))"))
+ )
+ (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (B A)))"))
)
- (instance InitReady3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (B A))"))
- )
- (instance un1_CmdEnable20_0_0_o3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance un1_ADWR_i_o2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(C+(!B+!A))"))
)
- (instance un1_CmdEnable20_0_0_o3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance un1_ADWR_i_o2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D+(!C+(!B+!A)))"))
)
- (instance un1_CmdEnable20_0_0_o3_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance un1_ADWR_i_o2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D+(!C+(!B+!A)))"))
)
- (instance (rename wb_dati_5_1_iv_i_i_a3_1_1_3 "wb_dati_5_1_iv_i_i_a3_1_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B !A)+C (B A)))"))
+ (instance (rename wb_dati_5_0_iv_0_a2_0_0_0 "wb_dati_5_0_iv_0_a2_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C (B A))+D (C (!B A)))"))
+ )
+ (instance (rename un9_RA_i_m2_9 "un9_RA_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_7 "un9_RA_i_m2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_6 "un9_RA_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_5 "un9_RA_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_4 "un9_RA_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_3 "un9_RA_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_2 "un9_RA_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_1 "un9_RA_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance (rename un9_RA_i_m2_0 "un9_RA_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C B+C A)"))
+ )
+ (instance LEDEN_6_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (B A)+C (!B+A))"))
)
(instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C B+C A)"))
)
- (instance (rename un9_RA_i_m2_i_m2_0 "un9_RA_i_m2_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_1 "un9_RA_i_m2_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_2 "un9_RA_i_m2_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_3 "un9_RA_i_m2_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_4 "un9_RA_i_m2_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_5 "un9_RA_i_m2_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_6 "un9_RA_i_m2_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_7 "un9_RA_i_m2_i_m2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance (rename un9_RA_i_m2_i_m2_9 "un9_RA_i_m2_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C B+C A)"))
- )
- (instance LEDEN_6_i_m2_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (B A)+C (!B+A))"))
- )
- (instance nRCAS_r_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B !A)"))
- )
- (instance CmdLEDEN_4_u_i_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance XOR8MEG_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
- )
- (instance (rename wb_dati_5_0_iv_0_a2_0 "wb_dati_5_0_iv_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance (rename wb_dati_5_1_iv_0_a2_6 "wb_dati_5_1_iv_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B !A)"))
- )
- (instance XOR8MEG_3_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B !A)"))
- )
- (instance nRowColSel_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B !A)"))
- )
- (instance RDQML_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B+!A)"))
- )
- (instance (rename wb_adr_5_i_0_o2_1 "wb_adr_5_i_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B+!A)"))
- )
- (instance XOR8MEG_3_u_0_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B+A)"))
- )
- (instance (rename S_0_i_o2_i_o2_1 "S_0_i_o2_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B+A)"))
- )
- (instance nRCS_9_u_i_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B+!A)"))
- )
- (instance (rename wb_dati_5_1_iv_0_o2_0_7 "wb_dati_5_1_iv_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B+!A)"))
- )
- (instance RCKEEN_8_u_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B+!A)"))
- )
- (instance IS_n1_0_x2_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A+B !A)"))
- )
- (instance nRowColSel_0_0_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A+B !A)"))
- )
- (instance (rename FS_RNIH267_16 "FS_RNIH267[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B+A)"))
- )
- (instance (rename wb_dati_5_1_iv_i_i_a2_2_3 "wb_dati_5_1_iv_i_i_a2_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
- )
- (instance (rename wb_adr_5_i_0_a2_0_1 "wb_adr_5_i_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B !A)"))
- )
- (instance (rename wb_adr_5_i_0_a2_1_0 "wb_adr_5_i_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
- )
- (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
(instance (rename wb_adr_5_3 "wb_adr_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance wb_cyc_stb_4_iv_0_a3_0_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_a2_2_6 "wb_dati_5_1_iv_0_a2_2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B A)"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B+A)"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_o2_0_6 "wb_dati_5_1_iv_0_o2_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B+!A)"))
+ )
+ (instance wb_cyc_stb_2_sqmuxa_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B+!A)"))
+ )
+ (instance XOR8MEG_3_u_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B+A)"))
+ )
+ (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B+!A)"))
+ )
+ (instance XOR8MEG_3_u_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B !A)"))
)
- (instance wb_cyc_stb_4_iv_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance XOR8MEG_3_u_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B A)"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_1_1 "wb_dati_5_1_iv_0_a2_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B !A)))"))
+ (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B A+B !A)"))
)
- (instance (rename wb_dati_5_1_iv_0_4 "wb_dati_5_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(!C A+C (B !A)))"))
+ (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B+A)"))
)
- (instance RCKEEN_8_u_0_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance wb_cyc_stb_2_sqmuxa_i_a2_3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B !A)"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C+(!B+A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C+A)+D (!C+(B+A)))"))
+ )
+ (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
)
- (instance RCKEEN_8_u_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
)
(instance LEDENe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C (!B A)+C (B+A))"))
)
(instance wb_rste (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (C !A)+D (!C (B A)+C (B+!A)))"))
+ (property lut_function (string "(!D (C !B)+D (!C (B !A)+C (!B+!A)))"))
)
(instance wb_reqe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!C (B A)+C (!B+A))"))
)
+ (instance n8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (B+A)+C (B !A))"))
+ )
+ (instance CmdValid_RNITBH02 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D C+D (C+(B A)))"))
+ )
+ (instance wb_cyc_stb_2_sqmuxa_i_o2_RNI167R (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (!B !A)))"))
+ )
+ (instance (rename FS_RNITL2J_14 "FS_RNITL2J[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B A)))"))
+ )
+ (instance wb_cyc_stb_4_iv_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(C (!B A))"))
+ )
+ (instance (rename FS_RNI1FVB_14 "FS_RNI1FVB[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
+ )
+ (instance n8MEGEN_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B+!A)+C (B !A))"))
+ )
+ (instance (rename FS_RNI7O57_11 "FS_RNI7O57[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B+!A)"))
+ )
+ (instance (rename FS_RNIS637_9 "FS_RNIS637[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B+!A)"))
+ )
+ (instance (rename FS_RNICHC8_14 "FS_RNICHC8[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B !A)"))
+ )
+ (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B !A)"))
+ )
(instance CmdValid_fast_RNI3K0H1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D+(C (B A)))"))
)
(instance PHI2r3_RNIFT0I_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B !A)"))
)
- (instance n8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (B+A)+C (B !A))"))
- )
- (instance CmdValid_RNIOOBE2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D C+D (C+(B A)))"))
- )
- (instance (rename FS_RNI7U6M_14 "FS_RNI7U6M[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B !A)"))
)
- (instance (rename FS_RNIGOCT_14 "FS_RNIGOCT[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B A)))"))
+ (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!B A)+D (!C !B+C (!B A)))"))
)
- (instance wb_cyc_stb_4_iv_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(C (!B A))"))
+ (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))"))
)
- (instance n8MEGEN_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B+!A)+C (B !A))"))
+ (instance nRCAS_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B A)"))
)
- (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B+!A)+C !A))"))
+ )
+ (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B !A)"))
+ )
+ (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C (!B+!A)))"))
+ )
+ (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (C+!A)+D (!C (!B !A)+C !B))"))
+ )
+ (instance nRWE_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B !A)"))
)
- (instance CBR_fast_RNIQ31K1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (!B A)))"))
- )
- (instance RASr2_RNI6PUF (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
- )
- (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B A)"))
- )
- (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (!B+!A)+C !A))"))
+ (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
)
(instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))"))
)
- (instance CmdLEDEN_4_u_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (B !A)))"))
+ (instance wb_cyc_stb_2_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C+(B+!A)))"))
)
- (instance un1_CmdEnable20_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_a2_3_2_7 "wb_dati_5_1_iv_0_a2_3_2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B A)))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_9_1 "wb_dati_5_1_iv_0_a2_9[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (!B !A)))"))
+ )
+ (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (B !A)))"))
+ )
+ (instance un1_CmdEnable20_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(D (!C (!B A)))"))
)
+ (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(C+(!B+!A)))"))
+ )
(instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
+ (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B A)"))
+ )
+ (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B+A)"))
+ )
+ (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B A)"))
+ )
+ (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B A)"))
+ )
+ (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(B A)"))
+ )
(instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
(instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
(instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
@@ -1707,44 +1668,41 @@
(instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(B A)"))
)
- (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
- (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!B+A)"))
- )
- (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(B A)"))
- )
(instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!B+A)"))
)
- (instance (rename FS_RNIF2MA_9 "FS_RNIF2MA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C+(!B+!A))"))
+ (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
)
- (instance CmdLEDEN_4_u_i_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!D (!C (B !A)))"))
+ (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (!B A)))"))
)
- (instance nRCS_9_u_i_0_o2_1_RNIL2K71 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C+(B+A)))"))
+ (instance un1_CmdEnable20_0_a2_3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (C (B A)))"))
)
- (instance (rename FS_RNIHVJI_16 "FS_RNIHVJI[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D+(C+(!B+A)))"))
- )
- (instance (rename wb_adr_5_i_0_a2_1_1 "wb_adr_5_i_0_a2_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (C (B !A)))"))
- )
- (instance (rename wb_dati_5_1_iv_i_i_a3_0_3 "wb_dati_5_1_iv_i_i_a3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (instance (rename wb_dati_5_1_iv_0_0_a2_1 "wb_dati_5_1_iv_0_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
(property lut_function (string "(!D (!C (B A)))"))
)
- (instance (rename wb_dati_5_1_iv_i_i_a2_4_3 "wb_dati_5_1_iv_i_i_a2_4[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(!C (!B !A))"))
+ (instance (rename wb_adr_5_i_i_a2_11_0 "wb_adr_5_i_i_a2_11[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
)
- (instance CmdEnable16_0_a2_1_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
- (property lut_function (string "(D (!C (B A)))"))
+ (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!B !A)"))
+ )
+ (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B !A+B A)+C A)"))
+ )
+ (instance (rename wb_adr_5_i_i_a2_6_0 "wb_adr_5_i_i_a2_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!C (!B A))"))
+ )
+ (instance (rename wb_dati_5_1_iv_0_a2_4 "wb_dati_5_1_iv_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(!D (!C (!B A)))"))
+ )
+ (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D (!C (B !A)))"))
+ )
+ (instance CmdEnable_RNI7PMB1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+ (property lut_function (string "(D+(!C+(B+!A)))"))
)
(instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
(property INIT0 (string "0x5002"))
@@ -1806,6 +1764,7 @@
(property INJECT1_0 (string "NO"))
(property INIT1 (string "0x300A"))
)
+ (instance rck (viewRef verilog (cellRef ODDRXE)) )
(instance ufmefb (viewRef netlist (cellRef REFB))
)
(net wb_rst (joined
@@ -1825,7 +1784,7 @@
(net (rename wb_adr_0 "wb_adr[0]") (joined
(portRef Q (instanceRef wb_adr_0))
(portRef (member wb_adr 7) (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_0_m2_1))
+ (portRef D (instanceRef wb_adr_5_i_i_0_1))
))
(net (rename wb_adr_1 "wb_adr[1]") (joined
(portRef Q (instanceRef wb_adr_1))
@@ -1840,17 +1799,17 @@
(net (rename wb_adr_3 "wb_adr[3]") (joined
(portRef Q (instanceRef wb_adr_3))
(portRef (member wb_adr 4) (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_m2_i_m2_4))
+ (portRef C (instanceRef wb_adr_5_i_m2_0_4))
))
(net (rename wb_adr_4 "wb_adr[4]") (joined
(portRef Q (instanceRef wb_adr_4))
(portRef (member wb_adr 3) (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_m2_i_m2_5))
+ (portRef C (instanceRef wb_adr_5_i_m2_0_5))
))
(net (rename wb_adr_5 "wb_adr[5]") (joined
(portRef Q (instanceRef wb_adr_5))
(portRef (member wb_adr 2) (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_m2_i_m2_6))
+ (portRef C (instanceRef wb_adr_5_i_m2_0_6))
))
(net (rename wb_adr_6 "wb_adr[6]") (joined
(portRef Q (instanceRef wb_adr_6))
@@ -1864,7 +1823,7 @@
(net (rename wb_dati_0 "wb_dati[0]") (joined
(portRef Q (instanceRef wb_dati_0))
(portRef (member wb_dati 7) (instanceRef ufmefb))
- (portRef D (instanceRef wb_dati_5_1_iv_0_1_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_1))
))
(net (rename wb_dati_1 "wb_dati[1]") (joined
(portRef Q (instanceRef wb_dati_1))
@@ -1874,12 +1833,12 @@
(net (rename wb_dati_2 "wb_dati[2]") (joined
(portRef Q (instanceRef wb_dati_2))
(portRef (member wb_dati 5) (instanceRef ufmefb))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_0_3))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_3))
))
(net (rename wb_dati_3 "wb_dati[3]") (joined
(portRef Q (instanceRef wb_dati_3))
(portRef (member wb_dati 4) (instanceRef ufmefb))
- (portRef D (instanceRef wb_dati_5_1_iv_0_1_4))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_0_4))
))
(net (rename wb_dati_4 "wb_dati[4]") (joined
(portRef Q (instanceRef wb_dati_4))
@@ -1889,7 +1848,7 @@
(net (rename wb_dati_5 "wb_dati[5]") (joined
(portRef Q (instanceRef wb_dati_5))
(portRef (member wb_dati 2) (instanceRef ufmefb))
- (portRef D (instanceRef wb_dati_5_1_iv_0_1_6))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_0_6))
))
(net (rename wb_dati_6 "wb_dati[6]") (joined
(portRef Q (instanceRef wb_dati_6))
@@ -1899,7 +1858,7 @@
(net (rename wb_dati_7 "wb_dati[7]") (joined
(portRef Q (instanceRef wb_dati_7))
(portRef (member wb_dati 0) (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_0_m2_0))
+ (portRef D (instanceRef wb_adr_5_i_i_1_0))
))
(net (rename wb_dato_0 "wb_dato[0]") (joined
(portRef (member wb_dato 1) (instanceRef ufmefb))
@@ -1907,63 +1866,52 @@
))
(net (rename wb_dato_1 "wb_dato[1]") (joined
(portRef (member wb_dato 0) (instanceRef ufmefb))
- (portRef C (instanceRef LEDEN_6_i_m2_i_m2))
+ (portRef C (instanceRef LEDEN_6_i_m2))
))
(net wb_ack (joined
(portRef wb_ack (instanceRef ufmefb))
- (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
+ (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
))
(net CBR (joined
(portRef Q (instanceRef CBR))
- (portRef A (instanceRef RCKEEN_8_u_0))
- (portRef A (instanceRef RCKEEN_8_u_0_0_a2_2))
+ (portRef A (instanceRef nRCAS_0io_RNO_0))
+ (portRef A (instanceRef RCKEEN_8_u))
+ (portRef B (instanceRef nRowColSel_0_0_a3_0))
(portRef A (instanceRef LED_pad_RNO))
- (portRef A (instanceRef nRowColSel_0_0_0))
- (portRef A (instanceRef nRCAS_r_i_0_o2_0_2))
))
(net InitReady (joined
(portRef Q (instanceRef InitReady))
- (portRef A (instanceRef wb_adr_5_i_0_a2_1_1))
- (portRef A (instanceRef FS_RNIHVJI_16))
- (portRef B (instanceRef n8MEGEN_RNO_0))
- (portRef B (instanceRef CmdValid_RNIOOBE2))
+ (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_o2))
(portRef D (instanceRef CmdValid_fast_RNI3K0H1))
- (portRef A (instanceRef wb_adr_5_2))
- (portRef A (instanceRef wb_adr_5_3))
+ (portRef B (instanceRef n8MEGEN_RNO_0))
+ (portRef B (instanceRef CmdValid_RNITBH02))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_1))
(portRef A (instanceRef wb_adr_5_7))
- (portRef B (instanceRef wb_adr_5_i_0_a2_1_0))
- (portRef B (instanceRef wb_adr_5_i_0_a2_0_1))
- (portRef A (instanceRef nRCS_9_u_i_0_o2_1))
- (portRef B (instanceRef LEDEN_6_i_m2_i_m2))
- (portRef D (instanceRef wb_adr_5_i_0_a3_0_2_0))
- (portRef B (instanceRef wb_adr_5_i_0_m2_1))
- (portRef B (instanceRef wb_adr_5_i_0_m2_0))
- (portRef B (instanceRef wb_adr_5_i_m2_i_m2_4))
- (portRef B (instanceRef wb_adr_5_i_m2_i_m2_5))
- (portRef B (instanceRef wb_adr_5_i_m2_i_m2_6))
- (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_a3))
- (portRef C (instanceRef wb_adr_5_i_0_a3_0_1))
- (portRef B (instanceRef wb_we_0_i_0_a3_1))
+ (portRef A (instanceRef wb_adr_5_3))
+ (portRef A (instanceRef wb_adr_5_2))
+ (portRef B (instanceRef LEDEN_6_i_m2))
+ (portRef C (instanceRef FS_RNIQV0F_16))
+ (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
+ (portRef A (instanceRef wb_adr_5_i_m2_0_4))
+ (portRef A (instanceRef wb_adr_5_i_m2_0_5))
+ (portRef A (instanceRef wb_adr_5_i_m2_0_6))
(portRef B (instanceRef CmdValid_RNIS5A51))
(portRef A (instanceRef wb_dati_5_1_iv_0_0_7))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_0_3))
- (portRef A (instanceRef wb_dati_5_1_iv_0_1_1))
+ (portRef A (instanceRef wb_adr_5_i_i_1_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_4))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_6))
(portRef B (instanceRef wb_cyc_stb_4_iv_0))
+ (portRef A (instanceRef wb_adr_5_i_i_0_1))
+ (portRef B (instanceRef wb_we_0_0_0))
(portRef A (instanceRef wb_dati_5_0_iv_0_0))
- (portRef A (instanceRef wb_dati_5_1_iv_0_1_4))
- (portRef A (instanceRef wb_dati_5_1_iv_0_1_6))
- (portRef B (instanceRef wb_we_RNO))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_3))
(portRef A (instanceRef wb_dati_5_1_iv_0_5))
(portRef A (instanceRef wb_dati_5_1_iv_0_2))
(portRef B (instanceRef InitReady_RNO))
(portRef D (instanceRef Ready_RNO))
- (portRef B (instanceRef wb_reqe_RNO))
- (portRef B (instanceRef wb_we_0_i_0_1_RNO))
- (portRef C (instanceRef RCKEEN_8_u_0_0_0))
- (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER))
- (portRef B (instanceRef FS_RNIJO0F_14))
- (portRef A (instanceRef FS_RNIHVJI_0_16))
- (portRef B (instanceRef wb_we_0_i_0_0_RNO))
+ (portRef C (instanceRef RCKEEN_8_u_RNO))
+ (portRef B (instanceRef FS_RNIHVJI_15))
))
(net C1Submitted (joined
(portRef Q (instanceRef C1Submitted))
@@ -1973,26 +1921,28 @@
(net CmdUFMShift (joined
(portRef Q (instanceRef CmdUFMShift))
(portRef A (instanceRef CmdValid_fast_RNI3K0H1))
- (portRef A (instanceRef CmdUFMShift_3_u_0_0_0))
+ (portRef A (instanceRef CmdUFMShift_3_u_0_0))
))
(net (rename Bank_2 "Bank[2]") (joined
(portRef Q (instanceRef Bank_0io_2))
- (portRef B (instanceRef un1_CmdEnable20_0_0_o3_10))
+ (portRef B (instanceRef un1_ADWR_i_o2_10))
))
(net Ready (joined
(portRef Q (instanceRef Ready))
- (portRef A (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71))
- (portRef C (instanceRef CBR_fast_RNIQ31K1))
- (portRef D (instanceRef RCKEEN_8_u_0))
- (portRef B (instanceRef RCKEEN_8_u_0_0_a2_2))
- (portRef D (instanceRef nRowColSel_0_0_0))
- (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_a3))
- (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0))
- (portRef D (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0))
+ (portRef B (instanceRef IS_RNO_0))
+ (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+ (portRef D (instanceRef RCKEEN_8_u))
+ (portRef B (instanceRef RCKEEN_8_u_0_a2_1))
+ (portRef D (instanceRef nRowColSel_0_0_a3_0))
+ (portRef C (instanceRef nRowColSel_0_0))
+ (portRef D (instanceRef nRCS_9_u_i_0_0))
+ (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
+ (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+ (portRef B (instanceRef IS_0_sqmuxa_0_o2))
+ (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
(portRef A (instanceRef Ready_RNO))
- (portRef A (instanceRef RCKEEN_8_u_0_0_0))
- (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER))
- (portRef A (instanceRef Ready_RNICVV51))
+ (portRef A (instanceRef RCKEEN_8_u_RNO))
+ (portRef A (instanceRef S_RNICVV51_0))
))
(net n8MEGEN (joined
(portRef Q (instanceRef n8MEGEN))
@@ -2002,333 +1952,305 @@
))
(net CO0 (joined
(portRef Q (instanceRef S_0))
- (portRef D (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71))
- (portRef B (instanceRef CBR_fast_RNIQ31K1))
- (portRef B (instanceRef RCKEEN_8_u_0_1_0))
- (portRef A (instanceRef nRowColSel_0_0_0_x2))
- (portRef B (instanceRef RCKEEN_8_u_0_0_o2))
- (portRef A (instanceRef S_0_i_o2_i_o2_1))
- (portRef A (instanceRef nRCAS_r_i_0_a2))
- (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2))
+ (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
+ (portRef A (instanceRef nRCS_0io_RNO_0))
+ (portRef B (instanceRef nRCAS_0io_RNO_0))
+ (portRef B (instanceRef RCKEEN_8_u_1_0))
+ (portRef A (instanceRef S_0_i_o2_1))
+ (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
(portRef A (instanceRef S_RNO_0))
- (portRef C (instanceRef nRWE_s_i_0_a2))
- (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0))
- (portRef A (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0))
- (portRef B (instanceRef nRCAS_r_i_0_o2_0_2_RNO))
- (portRef C (instanceRef Ready_RNICVV51))
- (portRef D (instanceRef nRCAS_0io_RNO_0))
+ (portRef C (instanceRef nRWE_s_i_a2_0))
+ (portRef A (instanceRef nRowColSel_0_0))
+ (portRef C (instanceRef S_RNICVV51_0))
))
(net (rename S_1 "S[1]") (joined
(portRef Q (instanceRef S_1))
- (portRef C (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71))
- (portRef B (instanceRef RASr2_RNI6PUF))
- (portRef D (instanceRef RCKEEN_8_u_0_1_0))
- (portRef B (instanceRef nRowColSel_0_0_0_x2))
- (portRef B (instanceRef S_0_i_o2_i_o2_1))
- (portRef D (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2))
- (portRef C (instanceRef RCKEEN_8_u_0_0_a2_2))
+ (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
+ (portRef D (instanceRef nRCAS_0io_RNO))
+ (portRef D (instanceRef RCKEEN_8_u_1_0))
+ (portRef B (instanceRef S_0_i_o2_1))
+ (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
+ (portRef C (instanceRef RCKEEN_8_u_0_a2_1))
(portRef B (instanceRef S_RNO_0))
- (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0_0))
- (portRef B (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0))
- (portRef B (instanceRef Ready_RNICVV51))
- (portRef A (instanceRef nRCAS_0io_RNO_0))
+ (portRef D (instanceRef nRowColSel_0_0))
+ (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+ (portRef B (instanceRef S_RNICVV51_0))
))
(net RASr2 (joined
(portRef Q (instanceRef RASr2))
- (portRef A (instanceRef RASr2_RNI6PUF))
- (portRef B (instanceRef nRCS_9_u_i_0_o2_1))
- (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2))
- (portRef B (instanceRef RCKE_2_0_0))
- (portRef B (instanceRef nRCS_9_u_i_0_o3))
- (portRef A (instanceRef nRWE_s_i_0_tz_0))
+ (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
+ (portRef A (instanceRef nRWE_0io_RNO_2))
+ (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
+ (portRef B (instanceRef RCKE_2_0))
+ (portRef B (instanceRef nRCS_9_u_i_0_0))
+ (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
(portRef D (instanceRef RASr3))
- (portRef C (instanceRef nRRAS_0io_RNO))
- (portRef B (instanceRef RCKEEN_8_u_0_0_0))
- (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER))
+ (portRef B (instanceRef RCKEEN_8_u_RNO))
(portRef A (instanceRef RASr2_RNIAFR1))
))
(net (rename FS_14 "FS[14]") (joined
(portRef Q (instanceRef FS_14))
(portRef (member fs 0) (instanceRef ufmefb))
(portRef A1 (instanceRef FS_cry_0_13))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_a2_4_3))
- (portRef C (instanceRef FS_RNIGOCT_14))
- (portRef A (instanceRef FS_RNI7U6M_14))
- (portRef A (instanceRef wb_adr_5_i_0_a2_1_0))
- (portRef A (instanceRef wb_adr_5_i_0_a2_0_1))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a2_6))
- (portRef C (instanceRef FS_RNIVOOA_14))
- (portRef C (instanceRef wb_dati_5_0_iv_0_a3_1_0))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_o2_3))
- (portRef B (instanceRef wb_adr_5_i_0_a3_0_1))
- (portRef C (instanceRef wb_adr_5_i_0_a3_1))
- (portRef D (instanceRef wb_dati_5_1_iv_0_o2_7))
- (portRef C (instanceRef wb_we_0_i_0_1_RNO))
- (portRef C (instanceRef FS_RNIJO0F_14))
- (portRef C (instanceRef wb_we_0_i_0_0_RNO))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_4))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_6_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_3_2_7))
+ (portRef A (instanceRef FS_RNICHC8_14))
+ (portRef B (instanceRef FS_RNI1FVB_14))
+ (portRef B (instanceRef FS_RNITL2J_14))
+ (portRef A (instanceRef wb_rste))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_o2_7))
+ (portRef D (instanceRef wb_dati_5_0_iv_0_a2_0_0_0))
+ (portRef B (instanceRef InitReady3_0_a2))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_2_1))
+ (portRef C (instanceRef wb_reqe_RNO))
+ (portRef A (instanceRef wb_we_0_0_0_a2))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_7))
))
(net FWEr (joined
(portRef Q (instanceRef FWEr))
- (portRef C (instanceRef RCKEEN_8_u_0_1_0))
- (portRef B (instanceRef nRowColSel_0_0_0_a2))
- (portRef B (instanceRef nRCAS_r_i_0_a2))
- (portRef D (instanceRef nRWE_s_i_0_a2))
- (portRef B (instanceRef nRCAS_r_i_0_o2_0_2))
+ (portRef B (instanceRef nRCS_0io_RNO_0))
+ (portRef C (instanceRef nRCAS_0io_RNO_0))
+ (portRef C (instanceRef RCKEEN_8_u_1_0))
+ (portRef C (instanceRef nRowColSel_0_0_a3_0))
))
(net CASr3 (joined
(portRef Q (instanceRef CASr3))
- (portRef A (instanceRef nRowColSel_0_0_0_a2))
- (portRef B (instanceRef nRWE_s_i_0_a2))
+ (portRef B (instanceRef nRCAS_0io_RNO_1))
+ (portRef A (instanceRef nRowColSel_0_0_a3_0))
+ (portRef B (instanceRef nRWE_s_i_a2_0))
))
(net (rename IS_0 "IS[0]") (joined
(portRef Q (instanceRef IS_0))
- (portRef A (instanceRef IS_n1_0_x2_0_x2))
- (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_o2))
- (portRef A (instanceRef IS_RNO_2))
- (portRef A (instanceRef nRCS_9_u_i_0_a2))
- (portRef A (instanceRef nRWE_s_i_0_a3_1_0))
(portRef A (instanceRef IS_RNO_0))
+ (portRef D (instanceRef nRRAS_0io_RNO))
+ (portRef A (instanceRef nRWE_0io_RNO_1))
+ (portRef A (instanceRef IS_n1_0_x2))
+ (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
+ (portRef A (instanceRef IS_RNO_2))
+ (portRef A (instanceRef nRCS_9_u_i_0))
(portRef D (instanceRef IS_RNO_3))
(portRef A (instanceRef RA10_0io_RNO))
))
(net (rename IS_3 "IS[3]") (joined
(portRef Q (instanceRef IS_3))
- (portRef B (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2))
- (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0))
+ (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
+ (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
(portRef C (instanceRef RA10_0io_RNO_0))
(portRef A (instanceRef IS_RNO_3))
))
(net (rename IS_1 "IS[1]") (joined
(portRef Q (instanceRef IS_1))
- (portRef B (instanceRef IS_n1_0_x2_0_x2))
- (portRef B (instanceRef Ready_0_sqmuxa_0_a2_4_o2))
- (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0))
+ (portRef B (instanceRef nRWE_0io_RNO_1))
+ (portRef B (instanceRef IS_n1_0_x2))
+ (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+ (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
(portRef B (instanceRef IS_RNO_2))
- (portRef B (instanceRef nRWE_s_i_0_a3_1_0))
(portRef A (instanceRef RA10_0io_RNO_0))
(portRef C (instanceRef IS_RNO_3))
))
(net (rename IS_2 "IS[2]") (joined
(portRef Q (instanceRef IS_2))
- (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_o2))
- (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0))
+ (portRef C (instanceRef nRWE_0io_RNO_1))
+ (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+ (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
(portRef C (instanceRef IS_RNO_2))
- (portRef C (instanceRef nRWE_s_i_0_a3_1_0))
(portRef B (instanceRef RA10_0io_RNO_0))
(portRef B (instanceRef IS_RNO_3))
))
(net (rename FS_15 "FS[15]") (joined
(portRef Q (instanceRef FS_15))
(portRef A0 (instanceRef FS_cry_0_15))
- (portRef B (instanceRef FS_RNIHVJI_16))
- (portRef A (instanceRef InitReady3_0_a3_1))
- (portRef A (instanceRef wb_adr_5_i_0_m2_1))
- (portRef A (instanceRef wb_adr_5_i_0_m2_0))
- (portRef A (instanceRef wb_adr_5_i_m2_i_m2_4))
- (portRef A (instanceRef wb_adr_5_i_m2_i_m2_5))
- (portRef A (instanceRef wb_adr_5_i_m2_i_m2_6))
- (portRef B (instanceRef FS_RNIHVJI_0_16))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_o2))
+ (portRef B (instanceRef InitReady3_0_a2_2))
+ (portRef A (instanceRef FS_RNIHVJI_15))
))
(net (rename FS_16 "FS[16]") (joined
(portRef Q (instanceRef FS_16))
(portRef A1 (instanceRef FS_cry_0_15))
- (portRef D (instanceRef FS_RNIHVJI_16))
- (portRef A (instanceRef FS_RNIH267_16))
- (portRef B (instanceRef InitReady3_0_a3_1))
- (portRef D (instanceRef wb_reqe_RNO))
- (portRef D (instanceRef FS_RNIHVJI_0_16))
+ (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_o2))
+ (portRef C (instanceRef InitReady3_0_a2_2))
+ (portRef A (instanceRef FS_RNIQV0F_16))
+ (portRef D (instanceRef FS_RNIHVJI_15))
))
(net (rename FS_17 "FS[17]") (joined
(portRef Q (instanceRef FS_17))
(portRef A0 (instanceRef FS_s_0_17))
- (portRef C (instanceRef FS_RNIHVJI_16))
- (portRef B (instanceRef FS_RNIH267_16))
- (portRef C (instanceRef InitReady3_0_a3_1))
- (portRef C (instanceRef wb_reqe_RNO))
- (portRef C (instanceRef FS_RNIHVJI_0_16))
+ (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_o2))
+ (portRef D (instanceRef InitReady3_0_a2_2))
+ (portRef B (instanceRef FS_RNIQV0F_16))
+ (portRef C (instanceRef FS_RNIHVJI_15))
))
(net (rename FS_0 "FS[0]") (joined
(portRef Q (instanceRef FS_0))
(portRef A1 (instanceRef FS_cry_0_0))
- (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_0))
- (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0))
- ))
- (net (rename FS_1 "FS[1]") (joined
- (portRef Q (instanceRef FS_1))
- (portRef A0 (instanceRef FS_cry_0_1))
- (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_3))
- ))
- (net (rename FS_5 "FS[5]") (joined
- (portRef Q (instanceRef FS_5))
- (portRef A0 (instanceRef FS_cry_0_5))
- (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_3))
- ))
- (net (rename FS_8 "FS[8]") (joined
- (portRef Q (instanceRef FS_8))
- (portRef A1 (instanceRef FS_cry_0_7))
- (portRef C (instanceRef wb_cyc_stb_4_iv_0_a3_0_3))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_0))
+ (portRef A (instanceRef wb_cyc_stb_4_iv_0_a2_0))
))
(net (rename FS_7 "FS[7]") (joined
(portRef Q (instanceRef FS_7))
(portRef A0 (instanceRef FS_cry_0_7))
- (portRef C (instanceRef wb_cyc_stb_4_iv_0_a3_0_2))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3))
))
- (net (rename FS_4 "FS[4]") (joined
- (portRef Q (instanceRef FS_4))
- (portRef A1 (instanceRef FS_cry_0_3))
- (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0))
- ))
- (net (rename FS_2 "FS[2]") (joined
- (portRef Q (instanceRef FS_2))
- (portRef A1 (instanceRef FS_cry_0_1))
- (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_2))
+ (net (rename FS_8 "FS[8]") (joined
+ (portRef Q (instanceRef FS_8))
+ (portRef A1 (instanceRef FS_cry_0_7))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3))
))
(net (rename FS_6 "FS[6]") (joined
(portRef Q (instanceRef FS_6))
(portRef A1 (instanceRef FS_cry_0_5))
- (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_2))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3))
+ ))
+ (net (rename FS_2 "FS[2]") (joined
+ (portRef Q (instanceRef FS_2))
+ (portRef A1 (instanceRef FS_cry_0_1))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4))
+ ))
+ (net (rename FS_1 "FS[1]") (joined
+ (portRef Q (instanceRef FS_1))
+ (portRef A0 (instanceRef FS_cry_0_1))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4))
+ ))
+ (net (rename FS_4 "FS[4]") (joined
+ (portRef Q (instanceRef FS_4))
+ (portRef A1 (instanceRef FS_cry_0_3))
+ (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4))
+ ))
+ (net (rename FS_5 "FS[5]") (joined
+ (portRef Q (instanceRef FS_5))
+ (portRef A0 (instanceRef FS_cry_0_5))
+ (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4))
))
(net (rename FS_3 "FS[3]") (joined
(portRef Q (instanceRef FS_3))
(portRef A0 (instanceRef FS_cry_0_3))
- (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3))
))
(net PHI2r2 (joined
(portRef Q (instanceRef PHI2r2))
+ (portRef A (instanceRef PHI2r3_RNIFT0I_0))
(portRef A (instanceRef PHI2r3_RNIFT0I))
(portRef B (instanceRef wb_cyc_stb_4_iv_0_RNO))
- (portRef A (instanceRef PHI2r3_RNIFT0I_0))
(portRef C (instanceRef CmdValid_RNIS5A51))
(portRef D (instanceRef PHI2r3))
))
(net (rename FS_9 "FS[9]") (joined
(portRef Q (instanceRef FS_9))
(portRef A0 (instanceRef FS_cry_0_9))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_a3_0_3))
- (portRef B (instanceRef wb_adr_5_i_0_a2_1_1))
- (portRef C (instanceRef FS_RNIF2MA_9))
- (portRef A (instanceRef wb_dati_5_1_iv_0_4))
- (portRef A (instanceRef wb_dati_5_1_iv_0_0_4))
- (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_7))
- (portRef A (instanceRef wb_adr_5_i_0_o2_1))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3))
- (portRef A (instanceRef wb_adr_5_i_0_o2_0_0))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_1_7))
- (portRef A (instanceRef wb_adr_5_i_0_1_0))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_3_3))
- (portRef A (instanceRef wb_adr_5_i_0_3_0))
- (portRef C0 (instanceRef wb_dati_5_1_iv_0_o3_5))
- (portRef D (instanceRef wb_dati_5_1_iv_0_RNO_7))
- (portRef D (instanceRef wb_dati_5_1_iv_0_RNO_0_7))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3))
- (portRef D (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_11_0))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_0_a2_1))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_9_1))
+ (portRef A (instanceRef FS_RNIS637_9))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_6))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_6_0_0))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_3_0_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_1))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_o2_3))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_RNO_4))
+ (portRef D (instanceRef wb_we_0_0_0_a2_RNO))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_0_RNO_7))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_1_RNO_7))
))
(net (rename FS_10 "FS[10]") (joined
(portRef Q (instanceRef FS_10))
(portRef A1 (instanceRef FS_cry_0_9))
- (portRef C (instanceRef wb_adr_5_i_0_a2_1_1))
- (portRef B (instanceRef FS_RNIF2MA_9))
- (portRef B (instanceRef wb_dati_5_1_iv_0_0_4))
- (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_7))
- (portRef B (instanceRef wb_adr_5_i_0_o2_1))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3))
- (portRef B (instanceRef wb_adr_5_i_0_o2_0_0))
- (portRef A (instanceRef wb_dati_5_0_iv_0_a3_1_0))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a3_0_1_7))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_o2_3))
- (portRef A (instanceRef wb_adr_5_i_0_o2_0))
- (portRef B (instanceRef wb_adr_5_i_0_1_0))
- (portRef A (instanceRef InitReady3_0_a3))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_6))
- (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_3_7))
- (portRef C (instanceRef wb_dati_5_1_iv_0_RNO_7))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3))
- (portRef C (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_11_0))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_9_1))
+ (portRef B (instanceRef FS_RNIS637_9))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_6))
+ (portRef A (instanceRef InitReady3_0_a2_2))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_6_0_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_1_7))
+ (portRef A (instanceRef wb_adr_5_i_i_1_0_tz_0_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_o2_3))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_7_0))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_RNO_4))
+ (portRef C (instanceRef wb_we_0_0_0_a2_RNO))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_RNO_7))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_1_RNO_7))
))
(net (rename FS_11 "FS[11]") (joined
(portRef Q (instanceRef FS_11))
(portRef A0 (instanceRef FS_cry_0_11))
- (portRef D (instanceRef wb_adr_5_i_0_a2_1_1))
- (portRef A (instanceRef FS_RNIF2MA_9))
- (portRef A (instanceRef wb_dati_5_0_iv_0_a2_0))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3))
- (portRef A (instanceRef wb_adr_5_i_0_a3_0_2_0))
- (portRef C (instanceRef wb_adr_5_i_0_o2_0_0))
- (portRef A (instanceRef wb_adr_5_i_0_a3_4_0))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_o2_3))
- (portRef B (instanceRef wb_adr_5_i_0_o2_0))
- (portRef B (instanceRef InitReady3_0_a3))
- (portRef A (instanceRef wb_we_0_i_0_a3_1))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_4))
- (portRef B (instanceRef wb_dati_5_1_iv_0_o2_7))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_6))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a3_3_7))
- (portRef A (instanceRef wb_dati_5_1_iv_0_1))
- (portRef A (instanceRef wb_dati_5_1_iv_0_6))
- (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_7))
- (portRef C (instanceRef wb_adr_RNO_0_1))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_9_1))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_3_2_7))
+ (portRef A (instanceRef FS_RNI7O57_11))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_1_7))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_6))
+ (portRef A (instanceRef wb_dati_5_0_iv_0_a2_0_0_0))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_3_0_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_0_6))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_1_7))
+ (portRef B (instanceRef wb_adr_5_i_i_1_0_tz_0_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_1))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_0_1_1))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_o2_3))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_7_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_3))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_1))
+ (portRef A (instanceRef wb_adr_5_i_i_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_RNO_4))
+ (portRef B (instanceRef wb_we_0_0_0_a2_RNO))
))
(net (rename FS_12 "FS[12]") (joined
(portRef Q (instanceRef FS_12))
- (portRef (member fs 2) (instanceRef ufmefb))
(portRef A1 (instanceRef FS_cry_0_11))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_4_3))
- (portRef A (instanceRef FS_RNIGOCT_14))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_2_3))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a2_6))
- (portRef B (instanceRef wb_adr_5_i_0_a3_0_2_0))
- (portRef A (instanceRef FS_RNIVOOA_14))
- (portRef B (instanceRef wb_dati_5_0_iv_0_a3_1_0))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_o2_3))
- (portRef A (instanceRef wb_adr_5_i_0_0_0))
- (portRef A (instanceRef wb_adr_5_i_0_a3_1))
- (portRef A (instanceRef wb_we_0_i_0_0))
- (portRef A (instanceRef wb_we_0_i_0_1))
- (portRef D (instanceRef wb_dati_5_1_iv_0_o3_bm_5))
- (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_0_7))
- (portRef C (instanceRef wb_adr_RNO_0_0))
- (portRef D (instanceRef wb_adr_RNO_0_1))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3))
- (portRef A (instanceRef FS_RNIJO0F_14))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_9_1))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_3_2_7))
+ (portRef B (instanceRef FS_RNI7O57_11))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_2_6))
+ (portRef B (instanceRef wb_dati_5_0_iv_0_a2_0_0_0))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_6_0_0))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_3_0_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_0_6))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_1_1_7))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_1))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_0_1_1))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_0))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_o2_3))
+ (portRef A (instanceRef wb_reqe_RNO))
+ (portRef A (instanceRef wb_we_0_0_0_0))
+ (portRef A (instanceRef wb_adr_5_i_i_1_0_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_3))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_5_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_1))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_RNO_4))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_1_RNO_7))
))
(net (rename FS_13 "FS[13]") (joined
(portRef Q (instanceRef FS_13))
(portRef (member fs 1) (instanceRef ufmefb))
(portRef A0 (instanceRef FS_cry_0_13))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_a3_0_3))
- (portRef B (instanceRef FS_RNIGOCT_14))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_a2_2_3))
- (portRef B (instanceRef wb_dati_5_0_iv_0_a2_0))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3))
- (portRef C (instanceRef wb_adr_5_i_0_a3_0_2_0))
- (portRef B (instanceRef FS_RNIVOOA_14))
- (portRef B (instanceRef wb_adr_5_i_0_a3_4_0))
- (portRef C (instanceRef wb_adr_5_i_0_o2_0))
- (portRef B (instanceRef wb_adr_5_i_0_0_0))
- (portRef A (instanceRef wb_adr_5_i_0_a3_0_1))
- (portRef B (instanceRef wb_adr_5_i_0_a3_1))
- (portRef C (instanceRef wb_dati_5_1_iv_0_o2_7))
- (portRef B (instanceRef wb_we_0_i_0_1))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a3_6))
- (portRef C (instanceRef wb_dati_5_1_iv_0_a3_3_7))
- (portRef D (instanceRef wb_dati_5_1_iv_0_o3_am_5))
- (portRef B (instanceRef wb_adr_RNO_0_0))
- (portRef A (instanceRef wb_we_0_i_0_0_RNO))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_4))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_3_2_7))
+ (portRef A (instanceRef FS_RNI1FVB_14))
+ (portRef A (instanceRef FS_RNITL2J_14))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7))
+ (portRef C (instanceRef wb_dati_5_0_iv_0_a2_0_0_0))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_1_0_6))
+ (portRef C (instanceRef wb_adr_5_i_i_1_0_tz_0_0))
+ (portRef A (instanceRef InitReady3_0_a2))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_0_1_1))
+ (portRef A (instanceRef wb_we_0_0_0_a2_2))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_1))
+ (portRef B (instanceRef wb_reqe_RNO))
+ (portRef C (instanceRef wb_adr_5_i_i_a2_7_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_7))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_5_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_1_3))
+ (portRef A (instanceRef wb_we_0_0_0_a2_RNO))
))
(net CASr2 (joined
(portRef Q (instanceRef CASr2))
- (portRef A (instanceRef RCKEEN_8_u_0_1_0))
- (portRef A (instanceRef RCKEEN_8_u_0_0_o2))
- (portRef A (instanceRef nRWE_s_i_0_a2))
+ (portRef A (instanceRef nRCAS_0io_RNO_1))
+ (portRef A (instanceRef RCKEEN_8_u_1_0))
+ (portRef A (instanceRef nRWE_s_i_a2_0))
(portRef D (instanceRef CASr3))
- (portRef C (instanceRef nRCAS_r_i_0_o2_0_2_RNO))
))
(net CASr (joined
(portRef Q (instanceRef CASr))
@@ -2340,68 +2262,68 @@
))
(net RASr (joined
(portRef Q (instanceRef RASr))
- (portRef A (instanceRef RCKE_2_0_0))
+ (portRef A (instanceRef RCKE_2_0))
(portRef D (instanceRef RASr2))
))
(net (rename Bank_0 "Bank[0]") (joined
(portRef Q (instanceRef Bank_0io_0))
- (portRef A (instanceRef un1_CmdEnable20_0_0_o3_10))
+ (portRef A (instanceRef un1_ADWR_i_o2_10))
))
(net (rename Bank_1 "Bank[1]") (joined
(portRef Q (instanceRef Bank_0io_1))
- (portRef A (instanceRef un1_CmdEnable20_0_0_o3_11))
+ (portRef A (instanceRef un1_ADWR_i_o2))
))
(net (rename Bank_3 "Bank[3]") (joined
(portRef Q (instanceRef Bank_0io_3))
- (portRef B (instanceRef un1_CmdEnable20_0_0_o3_11))
+ (portRef B (instanceRef un1_ADWR_i_o2))
))
(net (rename Bank_4 "Bank[4]") (joined
(portRef Q (instanceRef Bank_0io_4))
- (portRef C (instanceRef un1_CmdEnable20_0_0_o3_11))
+ (portRef A (instanceRef un1_ADWR_i_o2_11))
))
(net (rename Bank_5 "Bank[5]") (joined
(portRef Q (instanceRef Bank_0io_5))
- (portRef D (instanceRef un1_CmdEnable20_0_0_o3_11))
+ (portRef B (instanceRef un1_ADWR_i_o2_11))
))
(net (rename Bank_6 "Bank[6]") (joined
(portRef Q (instanceRef Bank_0io_6))
- (portRef A (instanceRef un1_CmdEnable20_0_0_o3))
+ (portRef C (instanceRef un1_ADWR_i_o2_11))
))
(net (rename Bank_7 "Bank[7]") (joined
(portRef Q (instanceRef Bank_0io_7))
- (portRef B (instanceRef un1_CmdEnable20_0_0_o3))
+ (portRef D (instanceRef un1_ADWR_i_o2_11))
))
(net (rename RowA_0 "RowA[0]") (joined
(portRef Q (instanceRef RowA_0))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_0))
+ (portRef B (instanceRef un9_RA_i_m2_0))
))
(net (rename RowA_1 "RowA[1]") (joined
(portRef Q (instanceRef RowA_1))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_1))
+ (portRef B (instanceRef un9_RA_i_m2_1))
))
(net (rename RowA_2 "RowA[2]") (joined
(portRef Q (instanceRef RowA_2))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_2))
+ (portRef B (instanceRef un9_RA_i_m2_2))
))
(net (rename RowA_3 "RowA[3]") (joined
(portRef Q (instanceRef RowA_3))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_3))
+ (portRef B (instanceRef un9_RA_i_m2_3))
))
(net (rename RowA_4 "RowA[4]") (joined
(portRef Q (instanceRef RowA_4))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_4))
+ (portRef B (instanceRef un9_RA_i_m2_4))
))
(net (rename RowA_5 "RowA[5]") (joined
(portRef Q (instanceRef RowA_5))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_5))
+ (portRef B (instanceRef un9_RA_i_m2_5))
))
(net (rename RowA_6 "RowA[6]") (joined
(portRef Q (instanceRef RowA_6))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_6))
+ (portRef B (instanceRef un9_RA_i_m2_6))
))
(net (rename RowA_7 "RowA[7]") (joined
(portRef Q (instanceRef RowA_7))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_7))
+ (portRef B (instanceRef un9_RA_i_m2_7))
))
(net (rename RowA_8 "RowA[8]") (joined
(portRef Q (instanceRef RowA_8))
@@ -2409,7 +2331,7 @@
))
(net (rename RowA_9 "RowA[9]") (joined
(portRef Q (instanceRef RowA_9))
- (portRef B (instanceRef un9_RA_i_m2_i_m2_9))
+ (portRef B (instanceRef un9_RA_i_m2_9))
))
(net (rename WRD_0 "WRD[0]") (joined
(portRef Q (instanceRef WRD_0io_0))
@@ -2445,135 +2367,142 @@
))
(net nRowColSel (joined
(portRef Q (instanceRef nRowColSel))
- (portRef B (instanceRef RDQML_0_0))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_9))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_7))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_6))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_5))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_4))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_3))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_2))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_1))
- (portRef C (instanceRef un9_RA_i_m2_i_m2_0))
+ (portRef B (instanceRef RDQML_0))
(portRef C (instanceRef un9_RA_8))
+ (portRef C (instanceRef un9_RA_i_m2_0))
+ (portRef C (instanceRef un9_RA_i_m2_1))
+ (portRef C (instanceRef un9_RA_i_m2_2))
+ (portRef C (instanceRef un9_RA_i_m2_3))
+ (portRef C (instanceRef un9_RA_i_m2_4))
+ (portRef C (instanceRef un9_RA_i_m2_5))
+ (portRef C (instanceRef un9_RA_i_m2_6))
+ (portRef C (instanceRef un9_RA_i_m2_7))
+ (portRef C (instanceRef un9_RA_i_m2_9))
(portRef B (instanceRef RDQMH_pad_RNO))
))
(net RASr3 (joined
(portRef Q (instanceRef RASr3))
- (portRef C (instanceRef RCKE_2_0_0))
+ (portRef C (instanceRef RCKE_2_0))
))
(net LEDEN (joined
(portRef Q (instanceRef LEDEN))
(portRef A (instanceRef LEDENe))
(portRef B (instanceRef LED_pad_RNO))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_0))
+ (portRef B (instanceRef XOR8MEG_3_u_0_0))
(portRef B (instanceRef CmdLEDEN_RNO))
))
(net CmdLEDEN (joined
(portRef Q (instanceRef CmdLEDEN))
- (portRef A (instanceRef LEDEN_6_i_m2_i_m2))
- (portRef A (instanceRef CmdLEDEN_4_u_i_0_0))
+ (portRef A (instanceRef LEDEN_6_i_m2))
+ (portRef A (instanceRef CmdLEDEN_4_u_i_0))
))
(net Cmdn8MEGEN (joined
(portRef Q (instanceRef Cmdn8MEGEN))
(portRef A (instanceRef n8MEGEN_RNO_0))
- (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0_0))
+ (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
))
(net PHI2r3 (joined
(portRef Q (instanceRef PHI2r3))
+ (portRef B (instanceRef PHI2r3_RNIFT0I_0))
(portRef B (instanceRef PHI2r3_RNIFT0I))
(portRef C (instanceRef wb_cyc_stb_4_iv_0_RNO))
- (portRef B (instanceRef PHI2r3_RNIFT0I_0))
(portRef D (instanceRef CmdValid_RNIS5A51))
))
(net CmdValid (joined
(portRef Q (instanceRef CmdValid))
(portRef A (instanceRef wb_cyc_stb_4_iv_0_RNO))
- (portRef A (instanceRef CmdValid_RNIOOBE2))
+ (portRef A (instanceRef CmdValid_RNITBH02))
(portRef A (instanceRef CmdValid_RNIS5A51))
))
(net CmdUFMData (joined
(portRef Q (instanceRef CmdUFMData))
- (portRef A (instanceRef wb_we_RNO))
+ (portRef A (instanceRef wb_we_0_0_0))
))
(net wb_rst10 (joined
- (portRef Z (instanceRef FS_RNIHVJI_0_16))
+ (portRef Z (instanceRef FS_RNIHVJI_15))
(portRef D (instanceRef wb_rste))
(portRef CD (instanceRef wb_cyc_stb))
(portRef CD (instanceRef wb_req))
(portRef CD (instanceRef wb_we))
))
(net InitReady3 (joined
- (portRef Z (instanceRef InitReady3_0_a3))
+ (portRef Z (instanceRef InitReady3_0_a2))
(portRef A (instanceRef InitReady_RNO))
))
(net RCKEEN (joined
(portRef Q (instanceRef RCKEEN))
- (portRef D (instanceRef RCKE_2_0_0))
+ (portRef D (instanceRef RCKE_2_0))
))
(net XOR8MEG (joined
(portRef Q (instanceRef XOR8MEG))
(portRef C (instanceRef RA11d))
- (portRef D (instanceRef XOR8MEG_3_u_0_0_0_a3))
+ (portRef D (instanceRef XOR8MEG_3_u_0_a2))
))
(net nRRAS_0_sqmuxa (joined
- (portRef Z (instanceRef Ready_RNICVV51))
- (portRef D (instanceRef nRCS_9_u_i_0_o3))
- (portRef C (instanceRef nRWE_s_i_0_tz_0))
+ (portRef Z (instanceRef S_RNICVV51_0))
+ (portRef D (instanceRef nRWE_0io_RNO_0))
(portRef CD (instanceRef nRowColSel))
- (portRef A (instanceRef nRRAS_0io_RNO))
))
(net wb_req (joined
(portRef Q (instanceRef wb_req))
(portRef C (instanceRef wb_reqe))
- (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_0))
- (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_0))
+ (portRef D (instanceRef wb_cyc_stb_4_iv_0_a2_0))
))
(net Ready_0_sqmuxa (joined
- (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_4_a3))
+ (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
(portRef A (instanceRef Ready_fast_RNO))
))
(net RCKE_2 (joined
- (portRef Z (instanceRef RCKE_2_0_0))
+ (portRef Z (instanceRef RCKE_2_0))
(portRef D (instanceRef RCKE))
))
(net nRCAS_0_sqmuxa_1 (joined
- (portRef Z (instanceRef CBR_fast_RNIQ31K1))
- (portRef A (instanceRef nRWE_0io_RNO))
- (portRef B (instanceRef nRCAS_0io_RNO_0))
+ (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+ (portRef D (instanceRef nRWE_0io_RNO))
+ (portRef B (instanceRef nRCAS_0io_RNO))
+ ))
+ (net XOR8MEG18 (joined
+ (portRef Z (instanceRef XOR8MEG18_0_a2))
+ (portRef SP (instanceRef CmdLEDEN))
+ (portRef SP (instanceRef CmdUFMShift))
+ (portRef SP (instanceRef CmdUFMWrite))
+ (portRef SP (instanceRef Cmdn8MEGEN))
+ (portRef SP (instanceRef XOR8MEG))
))
(net CmdEnable (joined
(portRef Q (instanceRef CmdEnable))
- (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a3_3))
+ (portRef C (instanceRef CmdEnable_RNI7PMB1))
+ (portRef B (instanceRef XOR8MEG18_0_a2))
+ (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2))
(portRef A (instanceRef CmdEnable_s))
))
(net CmdUFMWrite (joined
(portRef Q (instanceRef CmdUFMWrite))
- (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0_a3))
+ (portRef A (instanceRef CmdUFMWrite_3_u_0_a2))
(portRef A (instanceRef wb_cyc_stb_4_iv_0))
))
(net CmdEnable16 (joined
- (portRef Z (instanceRef CmdEnable16_0_a2_1_a2))
- (portRef D (instanceRef ADSubmitted_r_0_0))
- (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3))
+ (portRef Z (instanceRef CmdEnable16_0_a2))
+ (portRef D (instanceRef ADSubmitted_r_0))
(portRef A (instanceRef C1Submitted_RNO))
))
(net CmdEnable17 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_0_RNI00E51))
- (portRef C (instanceRef ADSubmitted_r_0_0))
+ (portRef Z (instanceRef CmdEnable17_0_a2))
+ (portRef C (instanceRef ADSubmitted_r_0))
(portRef B (instanceRef CmdEnable_s))
))
(net CmdUFMData_1_sqmuxa (joined
- (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a3))
+ (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a2))
(portRef SP (instanceRef CmdUFMData))
))
(net ADSubmitted (joined
(portRef Q (instanceRef ADSubmitted))
- (portRef A (instanceRef ADSubmitted_r_0_0))
- (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3))
+ (portRef A (instanceRef ADSubmitted_r_0))
+ (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2))
))
(net CmdEnable_0_sqmuxa (joined
- (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3))
+ (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2))
(portRef D (instanceRef CmdEnable_s))
))
(net wb_cyc_stb_4 (joined
@@ -2585,20 +2514,20 @@
(portRef D (instanceRef wb_dati_0))
))
(net (rename wb_dati_5_1 "wb_dati_5[1]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_1))
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1))
(portRef D (instanceRef wb_dati_1))
))
+ (net (rename wb_dati_5_2 "wb_dati_5[2]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_2))
+ (portRef D (instanceRef wb_dati_2))
+ ))
(net (rename wb_dati_5_4 "wb_dati_5[4]") (joined
(portRef Z (instanceRef wb_dati_5_1_iv_0_4))
(portRef D (instanceRef wb_dati_4))
))
- (net (rename wb_dati_5_6 "wb_dati_5[6]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_6))
- (portRef D (instanceRef wb_dati_6))
- ))
- (net (rename wb_dati_5_7 "wb_dati_5[7]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_7))
- (portRef D (instanceRef wb_dati_7))
+ (net (rename wb_dati_5_5 "wb_dati_5[5]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_5))
+ (portRef D (instanceRef wb_dati_5))
))
(net CmdValid_r (joined
(portRef Z (instanceRef CmdValid_r))
@@ -2608,15 +2537,80 @@
(portRef Z (instanceRef C1Submitted_RNO))
(portRef D (instanceRef C1Submitted))
))
- (net ADSubmitted_r_0_0 (joined
- (portRef Z (instanceRef ADSubmitted_r_0_0))
+ (net ADSubmitted_r_0 (joined
+ (portRef Z (instanceRef ADSubmitted_r_0))
(portRef D (instanceRef ADSubmitted))
))
(net CmdEnable_s (joined
(portRef Z (instanceRef CmdEnable_s))
(portRef D (instanceRef CmdEnable))
))
- (net un1_wb_rst14_i_0 (joined
+ (net wb_we_0_0_0 (joined
+ (portRef Z (instanceRef wb_we_0_0_0))
+ (portRef D (instanceRef wb_we))
+ ))
+ (net nRowColSel_0_0 (joined
+ (portRef Z (instanceRef nRowColSel_0_0))
+ (portRef D (instanceRef nRowColSel))
+ ))
+ (net XOR8MEG_3 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_0))
+ (portRef D (instanceRef XOR8MEG))
+ ))
+ (net CmdUFMShift_3 (joined
+ (portRef Z (instanceRef CmdUFMShift_3_u_0_0))
+ (portRef D (instanceRef CmdUFMShift))
+ ))
+ (net CmdUFMWrite_3 (joined
+ (portRef Z (instanceRef CmdUFMWrite_3_u_0_0))
+ (portRef D (instanceRef CmdUFMWrite))
+ ))
+ (net RCKEEN_8 (joined
+ (portRef Z (instanceRef RCKEEN_8_u))
+ (portRef D (instanceRef RCKEEN))
+ ))
+ (net (rename wb_adr_5_i_m2_0_6 "wb_adr_5_i_m2_0[6]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_m2_0_6))
+ (portRef D (instanceRef wb_adr_6))
+ ))
+ (net N_80 (joined
+ (portRef Z (instanceRef wb_adr_5_i_m2_0_5))
+ (portRef D (instanceRef wb_adr_5))
+ ))
+ (net N_81 (joined
+ (portRef Z (instanceRef wb_adr_5_i_m2_0_4))
+ (portRef D (instanceRef wb_adr_4))
+ ))
+ (net N_39 (joined
+ (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+ (portRef A (instanceRef nRCAS_0io_RNO))
+ ))
+ (net N_41 (joined
+ (portRef Z (instanceRef S_0_i_o2_1))
+ (portRef A (instanceRef nRCS_9_u_i_0_0))
+ (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+ (portRef D (instanceRef S_1))
+ (portRef D (instanceRef RCKEEN_8_u_RNO))
+ ))
+ (net IS_0_sqmuxa_0_o2 (joined
+ (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
+ (portRef C (instanceRef nRWE_0io_RNO_0))
+ (portRef D (instanceRef RA10_0io_RNO_0))
+ ))
+ (net N_53_i (joined
+ (portRef Z (instanceRef IS_n1_0_x2))
+ (portRef D (instanceRef IS_1))
+ ))
+ (net CmdValid_RNITBH02 (joined
+ (portRef Z (instanceRef CmdValid_RNITBH02))
+ (portRef A (instanceRef n8MEGEN_RNO))
+ (portRef B (instanceRef LEDENe))
+ ))
+ (net N_103 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
+ (portRef SP (instanceRef wb_cyc_stb))
+ ))
+ (net N_122 (joined
(portRef Z (instanceRef CmdValid_fast_RNI3K0H1))
(portRef SP (instanceRef wb_adr_7))
(portRef SP (instanceRef wb_adr_6))
@@ -2636,452 +2630,29 @@
(portRef SP (instanceRef wb_dati_0))
(portRef SP (instanceRef wb_we))
))
- (net nRowColSel_0_0_0 (joined
- (portRef Z (instanceRef nRowColSel_0_0_0))
- (portRef D (instanceRef nRowColSel))
- ))
- (net CmdUFMShift_3 (joined
- (portRef Z (instanceRef CmdUFMShift_3_u_0_0_0))
- (portRef D (instanceRef CmdUFMShift))
- ))
- (net CmdUFMWrite_3 (joined
- (portRef Z (instanceRef CmdUFMWrite_3_u_0_0_0))
- (portRef D (instanceRef CmdUFMWrite))
- ))
- (net RCKEEN_8 (joined
- (portRef Z (instanceRef RCKEEN_8_u_0))
- (portRef D (instanceRef RCKEEN))
- ))
- (net XOR8MEG_3 (joined
- (portRef Z (instanceRef XOR8MEG_3_u_0_0_0))
- (portRef D (instanceRef XOR8MEG))
- ))
- (net nRCS_9_u_i_0_o3 (joined
- (portRef Z (instanceRef nRCS_9_u_i_0_o3))
- (portRef A (instanceRef nRCS_0io_RNO))
- ))
- (net un1_nRCAS_6_sqmuxa_i_0_0 (joined
- (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0_0))
- (portRef A (instanceRef nRCAS_r_i_0_o2_0_2_RNO))
- ))
- (net CmdValid_2_i_o2_1_o3 (joined
- (portRef Z (instanceRef CmdValid_2_i_o2_1_o3))
- (portRef B (instanceRef CmdValid_r_fast))
- (portRef B (instanceRef CmdUFMWrite_3_u_0_0_0_a3))
- (portRef B (instanceRef CmdValid_r))
- (portRef D (instanceRef CmdLEDEN_4_u_i_0_0))
- (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0_0))
- (portRef C (instanceRef CmdUFMShift_3_u_0_0_0))
- ))
- (net (rename wb_dati_5_1_iv_i_i_3 "wb_dati_5_1_iv_i_i[3]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_3))
- (portRef D (instanceRef wb_dati_3))
- ))
- (net CmdValid_RNIOOBE2 (joined
- (portRef Z (instanceRef CmdValid_RNIOOBE2))
- (portRef A (instanceRef n8MEGEN_RNO))
- (portRef B (instanceRef LEDENe))
- ))
- (net N_178 (joined
- (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
- (portRef SP (instanceRef wb_cyc_stb))
- ))
- (net N_207 (joined
- (portRef Z (instanceRef wb_adr_5_i_0_o2_1))
- (portRef C (instanceRef wb_we_0_i_0_a3_1))
- (portRef B (instanceRef wb_we_0_i_0_0))
- (portRef B (instanceRef wb_dati_5_1_iv_0_a3_4))
- (portRef B (instanceRef wb_dati_5_1_iv_0_1))
- (portRef B (instanceRef wb_dati_5_1_iv_0_6))
- (portRef B (instanceRef wb_adr_RNO_0_1))
- ))
- (net N_208 (joined
- (portRef Z (instanceRef wb_adr_5_i_0_o2_0))
- (portRef C (instanceRef wb_dati_5_1_iv_0_0_4))
- (portRef B (instanceRef wb_adr_5_i_0_3_0))
- ))
- (net N_209 (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_o2_3))
- (portRef A (instanceRef wb_dati_5_1_iv_i_i_a3_0_3))
- (portRef C (instanceRef wb_dati_5_1_iv_0_o3_am_5))
- ))
- (net N_213 (joined
- (portRef Z (instanceRef XOR8MEG_3_u_0_0_o2_1))
- (portRef A (instanceRef CmdLEDEN_4_u_i_0_a2))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_a3_0_2))
- (portRef D (instanceRef CmdValid_2_i_o2_1_o3))
- (portRef C (instanceRef XOR8MEG_3_u_0_0_0_a3))
- ))
- (net N_214 (joined
- (portRef Z (instanceRef FS_RNIHVJI_16))
- (portRef N_214 (instanceRef ufmefb))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_a2_4_3))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_a3_0_3))
- (portRef D (instanceRef FS_RNIGOCT_14))
- (portRef B (instanceRef FS_RNI7U6M_14))
- (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_1))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_a2_3_3))
- (portRef B (instanceRef wb_dati_5_1_iv_0_0_7))
- (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0))
- (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
- (portRef B (instanceRef wb_dati_5_1_iv_0_o3_am_5))
- (portRef B (instanceRef wb_dati_5_1_iv_0_o3_bm_5))
- (portRef C (instanceRef wb_dati_5_1_iv_0_RNO_0_7))
- ))
- (net N_216 (joined
- (portRef Z (instanceRef S_0_i_o2_i_o2_1))
- (portRef B (instanceRef nRCS_9_u_i_0_a2))
- (portRef D (instanceRef S_1))
- (portRef D (instanceRef RCKEEN_8_u_0_0_0))
- ))
- (net N_217 (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_7))
- (portRef C (instanceRef wb_dati_5_1_iv_0_o3_bm_5))
- (portRef A (instanceRef wb_dati_5_1_iv_0_RNO_0_7))
- ))
- (net N_221 (joined
- (portRef Z (instanceRef nRCS_9_u_i_0_o2_1))
- (portRef B (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71))
- (portRef C (instanceRef nRCS_9_u_i_0_a2))
- (portRef C (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0))
- ))
- (net N_226 (joined
- (portRef Z (instanceRef FS_RNIF2MA_9))
- (portRef N_226 (instanceRef ufmefb))
- (portRef D (instanceRef wb_adr_5_i_0_a3_0_1))
- ))
- (net N_236 (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_0_7))
- (portRef C (instanceRef wb_adr_5_i_0_a3_4_0))
- (portRef C (instanceRef wb_dati_5_1_iv_0_a3_6))
- ))
- (net un1_nRCAS_6_sqmuxa_i_0_0_o2_0 (joined
- (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0))
- (portRef D (instanceRef nRCS_9_u_i_0_a2))
- (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER))
- ))
- (net N_267 (joined
- (portRef Z (instanceRef RCKEEN_8_u_0_0_o2))
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- ))
- (net LEDEN_6_i_m2_i_m2 (joined
- (portRef Z (instanceRef LEDEN_6_i_m2_i_m2))
+ (net LEDEN_6_i_m2 (joined
+ (portRef Z (instanceRef LEDEN_6_i_m2))
(portRef C (instanceRef LEDENe))
))
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))
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))
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+ (portRef D (instanceRef wb_dati_3))
))
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- (net N_385 (joined
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- (net N_384 (joined
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- ))
- (net N_361 (joined
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- (portRef B (instanceRef wb_dati_5_1_iv_0_5))
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- ))
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- (portRef Z (instanceRef wb_dati_5_1_iv_0_2))
- (portRef D (instanceRef wb_dati_2))
- ))
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- (portRef Z (instanceRef wb_dati_5_1_iv_0_5))
- (portRef D (instanceRef wb_dati_5))
- ))
- (net un1_PHI2r3 (joined
- (portRef Z (instanceRef wb_cyc_stb_4_iv_0_RNO))
- (portRef D (instanceRef wb_cyc_stb_4_iv_0))
+ (net (rename wb_dati_5_7 "wb_dati_5[7]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_7))
+ (portRef D (instanceRef wb_dati_7))
))
(net (rename wb_adr_5_2 "wb_adr_5[2]") (joined
(portRef Z (instanceRef wb_adr_5_2))
@@ -3095,24 +2666,351 @@
(portRef Z (instanceRef wb_adr_5_7))
(portRef D (instanceRef wb_adr_7))
))
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- (portRef Z (instanceRef nRWE_s_i_0_a3_1_0))
- (portRef D (instanceRef nRWE_s_i_0_tz_0))
+ (net N_367 (joined
+ (portRef Z (instanceRef FS_RNI1FVB_14))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_1_7))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_0_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_2_4))
+ (portRef C (instanceRef wb_adr_5_i_i_0))
))
- (net RCKEEN_8_u_0_0_0 (joined
- (portRef Z (instanceRef RCKEEN_8_u_0_0_0))
- (portRef B (instanceRef RCKEEN_8_u_0))
+ (net N_341 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_3))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_3))
))
- (net CmdLEDEN_4_u_i_0_a3_0_0 (joined
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- (portRef B (instanceRef CmdLEDEN_4_u_i_0_0))
- (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0_0))
+ (net N_362 (joined
+ (portRef Z (instanceRef FS_RNICHC8_14))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_1_3))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_4))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_6))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_1_3))
+ ))
+ (net N_125 (joined
+ (portRef Z (instanceRef FS_RNIS637_9))
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+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_0_1))
+ ))
+ (net N_376 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_2_6))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_0_7))
+ ))
+ (net N_383 (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_11_0))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_0_7))
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+ ))
+ (net N_375 (joined
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+ (portRef B (instanceRef wb_dati_5_1_iv_0_7))
+ (portRef D (instanceRef wb_adr_5_i_i_a2_7_0))
+ ))
+ (net N_384 (joined
+ (portRef Z (instanceRef FS_RNITL2J_14))
+ (portRef C (instanceRef wb_adr_5_i_i_5_0))
+ (portRef B (instanceRef wb_adr_5_i_i_1))
+ ))
+ (net N_394 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_9_1))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_2_1))
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+ (portRef D (instanceRef wb_dati_5_1_iv_0_o2_0_5))
+ ))
+ (net N_141 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_0_6))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_1_0_6))
+ ))
+ (net N_131 (joined
+ (portRef Z (instanceRef FS_RNIQV0F_16))
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+ ))
+ (net N_142 (joined
+ (portRef Z (instanceRef FS_RNI7O57_11))
+ (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R))
+ (portRef D (instanceRef InitReady3_0_a2))
+ (portRef D (instanceRef wb_we_0_0_0_a2_2))
+ (portRef B (instanceRef wb_adr_5_i_i_0_RNO_1))
+ (portRef A (instanceRef wb_adr_5_i_i_1))
+ ))
+ (net N_132 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_o2))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_4))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_6_0))
+ (portRef B (instanceRef wb_adr_5_i_i_a2_11_0))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_0_a2_1))
+ (portRef B (instanceRef FS_RNICHC8_14))
+ (portRef C (instanceRef FS_RNI1FVB_14))
+ (portRef D (instanceRef FS_RNITL2J_14))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R))
+ (portRef D (instanceRef wb_adr_5_i_i_a2_0))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_a2_2_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_a2_7_1))
+ (portRef B (instanceRef wb_adr_5_i_m2_0_4))
+ (portRef B (instanceRef wb_adr_5_i_m2_0_5))
+ (portRef B (instanceRef wb_adr_5_i_m2_0_6))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_7))
+ (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
+ (portRef B (instanceRef wb_cyc_stb_4_iv_0_a2_0))
+ (portRef B (instanceRef wb_adr_5_i_i_1_0_0))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_5))
+ (portRef B (instanceRef wb_adr_5_i_i_0_1))
+ ))
+ (net N_133 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_7))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_a2_1_1_7))
+ (portRef A (instanceRef wb_adr_5_i_i_0_RNO_1))
+ (portRef C (instanceRef wb_we_0_0_0_0))
+ (portRef C (instanceRef wb_adr_5_i_i_1_0_0))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_5))
+ ))
+ (net N_137 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_RNO_4))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_a2_4))
+ ))
+ (net N_220 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_1_RNO_7))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_1_7))
+ ))
+ (net N_223 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_3))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_1_3))
+ ))
+ (net N_353 (joined
+ (portRef Z (instanceRef wb_we_0_0_0_a2))
+ (portRef C (instanceRef wb_we_0_0_0))
+ ))
+ (net N_356 (joined
+ (portRef Z (instanceRef wb_we_0_0_0_a2_2))
+ (portRef D (instanceRef wb_we_0_0_0_0))
+ ))
+ (net N_345 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_7))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_7))
+ ))
+ (net N_226 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_a2_1))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_o2_0_5))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_1_3))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_1))
+ ))
+ (net N_233 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_1))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_0_1))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_6))
+ ))
+ (net N_307 (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_0))
+ (portRef B (instanceRef wb_adr_5_i_i_1_0))
+ ))
+ (net N_313 (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_5_0))
+ (portRef B (instanceRef wb_adr_5_i_i_0))
+ ))
+ (net N_315 (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_7_0))
+ (portRef B (instanceRef wb_adr_5_i_i_5_0))
+ ))
+ (net N_314 (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_6_0))
+ (portRef A (instanceRef wb_adr_5_i_i_5_0))
+ ))
+ (net N_348_2 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_3_2_7))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_2_4))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_6))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_RNO_7))
+ ))
+ (net N_143 (joined
+ (portRef Z (instanceRef wb_we_0_0_0_a2_RNO))
+ (portRef C (instanceRef wb_we_0_0_0_a2))
+ ))
+ (net N_335 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_4))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_4))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_5))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_2))
+ ))
+ (net N_28_i_1 (joined
+ (portRef Z (instanceRef RCKEEN_8_u_0_a2_1))
+ (portRef A (instanceRef nRWE_0io_RNO))
+ (portRef A (instanceRef nRCS_0io_RNO))
+ ))
+ (net N_37_i_1 (joined
+ (portRef Z (instanceRef nRWE_s_i_a2_0))
+ (portRef B (instanceRef nRWE_0io_RNO))
+ (portRef C (instanceRef nRCS_0io_RNO))
+ ))
+ (net N_129 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_1))
+ (portRef A (instanceRef wb_dati_5_1_iv_0_0_a2_1))
+ ))
+ (net N_303 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_2_1))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_0_1))
+ ))
+ (net N_382 (joined
+ (portRef Z (instanceRef XOR8MEG18_0_a2_0))
+ (portRef D (instanceRef CmdUFMData_1_sqmuxa_0_a2))
+ (portRef C (instanceRef CmdEnable17_0_a2))
+ ))
+ (net N_393 (joined
+ (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2_1))
+ (portRef A (instanceRef CmdEnable16_0_a2))
+ (portRef D (instanceRef un1_CmdEnable20_0_0))
+ (portRef D (instanceRef CmdEnable_0_sqmuxa_0_a2))
+ ))
+ (net N_294 (joined
+ (portRef Z (instanceRef un1_ADWR_i_o2))
+ (portRef B (instanceRef CmdEnable_RNI7PMB1))
+ (portRef C (instanceRef XOR8MEG18_0_a2))
+ (portRef B (instanceRef CmdEnable16_0_a2))
+ (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2))
+ (portRef B (instanceRef XOR8MEG18_0_a2_0))
+ (portRef B (instanceRef ADSubmitted_r_0_RNO))
+ (portRef B (instanceRef CmdEnable_s_RNO))
+ (portRef C (instanceRef C1Submitted_RNO))
+ ))
+ (net N_378 (joined
+ (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+ (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2))
+ ))
+ (net N_380 (joined
+ (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a2_0))
+ (portRef D (instanceRef CmdUFMShift_3_u_0_0))
+ (portRef D (instanceRef CmdUFMWrite_3_u_0_0))
+ (portRef C (instanceRef CmdLEDEN_RNO))
+ (portRef B (instanceRef Cmdn8MEGEN_RNO))
+ (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a2))
+ ))
+ (net N_381 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_a2_2))
+ (portRef D (instanceRef XOR8MEG_3_u_0_a2_0_2))
+ (portRef D (instanceRef CmdEnable_0_sqmuxa_0_a2_1))
+ ))
+ (net N_371 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_a2_1))
+ (portRef C (instanceRef XOR8MEG_3_u_0_a2_0_2))
+ ))
+ (net N_134 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_o2_1))
+ (portRef B (instanceRef XOR8MEG_3_u_0_a2_0_2))
+ (portRef C (instanceRef XOR8MEG_3_u_0_a2))
+ (portRef D (instanceRef CmdUFMData_1_sqmuxa_0_a2_0))
+ (portRef D (instanceRef CmdValid_2_i_o2))
+ ))
+ (net N_330 (joined
+ (portRef Z (instanceRef wb_cyc_stb_4_iv_0_a2_0))
+ (portRef C (instanceRef wb_cyc_stb_4_iv_0))
+ ))
+ (net N_330_4 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3))
+ (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
+ (portRef C (instanceRef wb_cyc_stb_4_iv_0_a2_0))
+ ))
+ (net N_295 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_0))
+ (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
+ ))
+ (net N_302 (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_1))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_0_1))
+ ))
+ (net N_140 (joined
+ (portRef Z (instanceRef CmdValid_2_i_o2))
+ (portRef B (instanceRef CmdValid_r_fast))
+ (portRef B (instanceRef CmdValid_r))
+ (portRef B (instanceRef CmdUFMWrite_3_u_0_a2))
+ (portRef D (instanceRef CmdLEDEN_4_u_i_0))
+ (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
+ (portRef C (instanceRef CmdUFMShift_3_u_0_0))
+ ))
+ (net N_279 (joined
+ (portRef Z (instanceRef CmdUFMWrite_3_u_0_a2))
+ (portRef C (instanceRef CmdUFMWrite_3_u_0_0))
+ ))
+ (net N_274 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_a2))
+ (portRef C (instanceRef XOR8MEG_3_u_0_0))
+ ))
+ (net un1_PHI2r3 (joined
+ (portRef Z (instanceRef wb_cyc_stb_4_iv_0_RNO))
+ (portRef D (instanceRef wb_cyc_stb_4_iv_0))
+ ))
+ (net N_374 (joined
+ (portRef Z (instanceRef un1_CmdEnable20_0_a2_2))
+ (portRef C (instanceRef un1_CmdEnable20_0_a2_3_0))
+ (portRef C (instanceRef CmdEnable16_0_a2))
+ (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+ (portRef C (instanceRef un1_CmdEnable20_0_0))
+ ))
+ (net N_248 (joined
+ (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
+ (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
+ (portRef C (instanceRef Ready_RNO))
+ ))
+ (net N_43 (joined
+ (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
+ (portRef C (instanceRef IS_RNO_0))
+ (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+ (portRef C (instanceRef nRRAS_0io_RNO))
+ (portRef A (instanceRef IS_0_sqmuxa_0_o2))
+ (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+ (portRef B (instanceRef nRCS_9_u_i_0))
+ ))
+ (net N_49 (joined
+ (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+ (portRef B (instanceRef nRRAS_0io_RNO))
+ (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+ (portRef C (instanceRef nRCS_9_u_i_0))
+ ))
+ (net N_255 (joined
+ (portRef Z (instanceRef nRowColSel_0_0_a3_0))
+ (portRef B (instanceRef nRowColSel_0_0))
+ ))
+ (net (rename wb_adr_5_i_i_a2_0_1 "wb_adr_5_i_i_a2_0[1]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_0_1_1))
+ (portRef C (instanceRef wb_adr_5_i_i_0_RNO_1))
+ ))
+ (net N_428_tz (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_0_RNO_1))
+ (portRef C (instanceRef wb_adr_5_i_i_0_1))
+ ))
+ (net (rename wb_adr_5_i_i_a2_3_0_0 "wb_adr_5_i_i_a2_3_0[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_3_0_0))
+ (portRef D (instanceRef wb_adr_5_i_i_1_0_tz_0_0))
+ ))
+ (net RCKEEN_8_u_0_0 (joined
+ (portRef Z (instanceRef RCKEEN_8_u_RNO))
+ (portRef B (instanceRef RCKEEN_8_u))
+ ))
+ (net (rename wb_adr_5_i_i_1_0_0 "wb_adr_5_i_i_1_0[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_1_0_0))
+ (portRef C (instanceRef wb_adr_5_i_i_1_0))
+ ))
+ (net nRCS_9_u_i_0 (joined
+ (portRef Z (instanceRef nRCS_9_u_i_0))
+ (portRef D (instanceRef nRCS_0io_RNO))
+ ))
+ (net (rename wb_adr_5_i_i_a2_6_0_0 "wb_adr_5_i_i_a2_6_0[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_a2_6_0_0))
+ (portRef A (instanceRef wb_adr_5_i_i_a2_6_0))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_2_4))
))
(net nCRAS_c_i (joined
(portRef Z (instanceRef nCRAS_pad_RNIBPVB))
(portRef CK (instanceRef CBR))
(portRef CK (instanceRef CBR_fast))
(portRef CK (instanceRef FWEr))
+ (portRef CK (instanceRef FWEr_fast))
(portRef CK (instanceRef RowA_9))
(portRef CK (instanceRef RowA_8))
(portRef CK (instanceRef RowA_7))
@@ -3126,6 +3024,12 @@
(portRef SCLK (instanceRef RBA_0io_1))
(portRef SCLK (instanceRef RBA_0io_0))
))
+ (net N_244_i (joined
+ (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+ (portRef SP (instanceRef IS_3))
+ (portRef SP (instanceRef IS_2))
+ (portRef SP (instanceRef IS_1))
+ ))
(net RD_1_i (joined
(portRef Z (instanceRef nCCAS_pad_RNI01SJ))
(portRef T (instanceRef RD_pad_0))
@@ -3137,60 +3041,52 @@
(portRef T (instanceRef RD_pad_6))
(portRef T (instanceRef RD_pad_7))
))
- (net N_248_i (joined
+ (net N_242_i (joined
(portRef Z (instanceRef nRCAS_0io_RNO))
(portRef D (instanceRef nRCAS_0io))
))
- (net N_247_i (joined
+ (net N_25_i (joined
+ (portRef Z (instanceRef nRRAS_0io_RNO))
+ (portRef D (instanceRef nRRAS_0io))
+ ))
+ (net N_28_i (joined
(portRef Z (instanceRef nRCS_0io_RNO))
(portRef D (instanceRef nRCS_0io))
))
- (net N_49_i (joined
+ (net N_37_i (joined
(portRef Z (instanceRef nRWE_0io_RNO))
(portRef D (instanceRef nRWE_0io))
))
- (net N_351_i_i (joined
+ (net N_60_i_i (joined
(portRef Z (instanceRef IS_RNO_0))
(portRef D (instanceRef IS_0))
))
- (net N_350_i_i (joined
+ (net N_58_i_i (joined
(portRef Z (instanceRef IS_RNO_3))
(portRef D (instanceRef IS_3))
))
- (net N_348_i_i (joined
+ (net N_57_i_i (joined
(portRef Z (instanceRef IS_RNO_2))
(portRef D (instanceRef IS_2))
))
- (net N_123_i (joined
+ (net N_253_i (joined
(portRef Z (instanceRef S_RNO_0))
(portRef D (instanceRef S_0))
))
- (net N_92_i (joined
+ (net N_94_i (joined
(portRef Z (instanceRef CmdValid_RNIS5A51))
(portRef B (instanceRef wb_reqe))
- (portRef A (instanceRef wb_rste))
+ (portRef B (instanceRef wb_rste))
))
- (net N_229_i (joined
- (portRef Z (instanceRef wb_adr_RNO_1))
- (portRef D (instanceRef wb_adr_1))
- ))
- (net N_230_i (joined
- (portRef Z (instanceRef wb_adr_RNO_0))
- (portRef D (instanceRef wb_adr_0))
- ))
- (net N_40_i (joined
+ (net N_284_i (joined
(portRef Z (instanceRef CmdLEDEN_RNO))
(portRef D (instanceRef CmdLEDEN))
))
- (net N_38_i (joined
+ (net N_285_i (joined
(portRef Z (instanceRef Cmdn8MEGEN_RNO))
(portRef D (instanceRef Cmdn8MEGEN))
))
- (net N_231_i (joined
- (portRef Z (instanceRef wb_we_RNO))
- (portRef D (instanceRef wb_we))
- ))
- (net N_31_i (joined
+ (net N_34_i (joined
(portRef Z (instanceRef wb_reqe_RNO))
(portRef A (instanceRef wb_reqe))
))
@@ -3198,6 +3094,15 @@
(portRef Z (instanceRef CmdEnable_s_RNO))
(portRef C (instanceRef CmdEnable_s))
))
+ (net N_22_i (joined
+ (portRef Z (instanceRef ADSubmitted_r_0_RNO))
+ (portRef B (instanceRef ADSubmitted_r_0))
+ ))
+ (net XOR8MEG18_i (joined
+ (portRef Z (instanceRef CmdEnable_RNI7PMB1))
+ (portRef A (instanceRef CmdValid_r_fast))
+ (portRef A (instanceRef CmdValid_r))
+ ))
(net (rename FS_cry_0 "FS_cry[0]") (joined
(portRef COUT (instanceRef FS_cry_0_0))
(portRef CIN (instanceRef FS_cry_0_1))
@@ -3310,150 +3215,134 @@
(portRef Z (instanceRef RA10_0io_RNO_0))
(portRef PD (instanceRef RA10_0io))
))
- (net Cmdn8MEGEN_4_u_i_0_0 (joined
- (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0_0))
- (portRef A (instanceRef Cmdn8MEGEN_RNO))
+ (net un1_CmdEnable20_0_a2_3_0 (joined
+ (portRef Z (instanceRef un1_CmdEnable20_0_a2_3_0))
+ (portRef D (instanceRef un1_CmdEnable20_0_a2_1_0))
+ (portRef D (instanceRef CmdEnable17_0_a2))
))
- (net CmdLEDEN_4_u_i_0_0 (joined
- (portRef Z (instanceRef CmdLEDEN_4_u_i_0_0))
- (portRef A (instanceRef CmdLEDEN_RNO))
+ (net CmdLEDEN_4_u_i_a2_0_0 (joined
+ (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+ (portRef B (instanceRef CmdLEDEN_4_u_i_0))
+ (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
))
- (net un1_CmdEnable20_0_0_a3_1_1 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_a3_1_1))
+ (net un1_CmdEnable20_0_a2_1_0 (joined
+ (portRef Z (instanceRef un1_CmdEnable20_0_a2_1_0))
(portRef D (instanceRef CmdEnable_s_RNO))
))
- (net wb_cyc_stb_4_iv_0_a3_0_2_0 (joined
- (portRef Z (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0))
- (portRef D (instanceRef wb_cyc_stb_4_iv_0_a3_0_2))
+ (net Cmdn8MEGEN_4_u_i_0 (joined
+ (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
+ (portRef A (instanceRef Cmdn8MEGEN_RNO))
))
- (net wb_we_0_i_0_0 (joined
- (portRef Z (instanceRef wb_we_0_i_0_0))
- (portRef D (instanceRef wb_we_0_i_0_1))
+ (net CmdLEDEN_4_u_i_0 (joined
+ (portRef Z (instanceRef CmdLEDEN_4_u_i_0))
+ (portRef A (instanceRef CmdLEDEN_RNO))
))
- (net wb_we_0_i_0_1 (joined
- (portRef Z (instanceRef wb_we_0_i_0_1))
- (portRef D (instanceRef wb_we_RNO))
+ (net wb_we_0_0_0_0 (joined
+ (portRef Z (instanceRef wb_we_0_0_0_0))
+ (portRef D (instanceRef wb_we_0_0_0))
))
- (net (rename wb_adr_5_i_0_a3_0_1_0 "wb_adr_5_i_0_a3_0_1[0]") (joined
- (portRef Z (instanceRef wb_adr_5_i_0_a3_0_2_0))
- (portRef D (instanceRef wb_adr_5_i_0_1_0))
+ (net wb_cyc_stb_2_sqmuxa_i_a2_3_3 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3))
+ (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3))
))
- (net wb_we_0_i_0_a3_0_0 (joined
- (portRef Z (instanceRef wb_we_0_i_0_0_RNO))
- (portRef D (instanceRef wb_we_0_i_0_0))
+ (net wb_cyc_stb_2_sqmuxa_i_a2_3_4 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4))
+ (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3))
))
- (net XOR8MEG_3_u_0_0_a3_0_2 (joined
- (portRef Z (instanceRef XOR8MEG_3_u_0_0_a3_0_2))
- (portRef D (instanceRef XOR8MEG_3_u_0_0_0))
+ (net InitReady3_0_a2_2 (joined
+ (portRef Z (instanceRef InitReady3_0_a2_2))
+ (portRef C (instanceRef InitReady3_0_a2))
))
- (net Ready_0_sqmuxa_0_a2_4_a3_2 (joined
- (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2))
- (portRef D (instanceRef Ready_0_sqmuxa_0_a2_4_a3))
+ (net XOR8MEG_3_u_0_a2_0_2 (joined
+ (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0_2))
+ (portRef D (instanceRef XOR8MEG_3_u_0_0))
+ ))
+ (net (rename wb_adr_5_i_i_1_0_tz_0_0 "wb_adr_5_i_i_1_0_tz_0[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_1_0_tz_0_0))
+ (portRef D (instanceRef wb_adr_5_i_i_1_0_0))
+ ))
+ (net Ready_0_sqmuxa_0_a3_2 (joined
+ (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
+ (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
(portRef B (instanceRef Ready_RNO))
))
- (net InitReady3_0_a3_1 (joined
- (portRef Z (instanceRef InitReady3_0_a3_1))
- (portRef C (instanceRef InitReady3_0_a3))
- ))
- (net wb_cyc_stb_2_sqmuxa_i_a3_0 (joined
- (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0))
- (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0))
- ))
- (net nRWE_s_i_0_tz_0 (joined
- (portRef Z (instanceRef nRWE_s_i_0_tz_0))
- (portRef D (instanceRef nRWE_0io_RNO))
- ))
- (net (rename wb_dati_5_1_iv_0_a3_0_1_7 "wb_dati_5_1_iv_0_a3_0_1[7]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_a3_0_1_7))
+ (net (rename wb_dati_5_1_iv_0_a2_3_0_7 "wb_dati_5_1_iv_0_a2_3_0[7]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_RNO_7))
(portRef D (instanceRef wb_dati_5_1_iv_0_0_7))
))
- (net un1_CmdEnable20_0_0_o3_3 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_3))
- (portRef C (instanceRef un1_CmdEnable20_0_0_o3_10))
+ (net un1_ADWR_i_o2_3 (joined
+ (portRef Z (instanceRef un1_ADWR_i_o2_3))
+ (portRef C (instanceRef un1_ADWR_i_o2_10))
))
- (net un1_CmdEnable20_0_0_o3_4 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_4))
- (portRef D (instanceRef un1_CmdEnable20_0_0_o3_10))
+ (net un1_ADWR_i_o2_4 (joined
+ (portRef Z (instanceRef un1_ADWR_i_o2_4))
+ (portRef D (instanceRef un1_ADWR_i_o2_10))
))
- (net un1_CmdEnable20_0_0_o3_10 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_10))
- (portRef C (instanceRef un1_CmdEnable20_0_0_o3))
+ (net un1_ADWR_i_o2_10 (joined
+ (portRef Z (instanceRef un1_ADWR_i_o2_10))
+ (portRef C (instanceRef un1_ADWR_i_o2))
))
- (net un1_CmdEnable20_0_0_o3_11 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_11))
- (portRef D (instanceRef un1_CmdEnable20_0_0_o3))
+ (net un1_ADWR_i_o2_11 (joined
+ (portRef Z (instanceRef un1_ADWR_i_o2_11))
+ (portRef D (instanceRef un1_ADWR_i_o2))
))
- (net nRCAS_r_i_0_o2_0_0 (joined
- (portRef Z (instanceRef nRCAS_r_i_0_o2_0_2_RNO))
- (portRef D (instanceRef nRCAS_r_i_0_o2_0_2))
+ (net (rename wb_dati_5_1_iv_0_a2_1_1_7 "wb_dati_5_1_iv_0_a2_1_1[7]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_1_7))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_7))
))
- (net N_248_i_1 (joined
- (portRef Z (instanceRef nRCAS_r_i_0_o2_0_2))
- (portRef A (instanceRef nRCAS_0io_RNO))
+ (net (rename wb_dati_5_1_iv_0_a2_1_6 "wb_dati_5_1_iv_0_a2_1[6]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_0_6))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_0_6))
))
- (net (rename wb_dati_5_1_iv_0_a3_0_1_1 "wb_dati_5_1_iv_0_a3_0_1[1]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1))
- (portRef C (instanceRef wb_dati_5_1_iv_0_a3_0_1))
+ (net nRCS_9_u_i_0_0 (joined
+ (portRef Z (instanceRef nRCS_9_u_i_0_0))
+ (portRef A (instanceRef nRRAS_0io_RNO))
+ (portRef D (instanceRef nRCS_9_u_i_0))
))
- (net wb_cyc_stb_4_iv_0_a3_0_0 (joined
- (portRef Z (instanceRef wb_cyc_stb_4_iv_0_a3_0_0))
- (portRef D (instanceRef wb_cyc_stb_4_iv_0_a3_0))
- ))
- (net (rename wb_dati_5_0_iv_0_a3_1_0 "wb_dati_5_0_iv_0_a3_1[0]") (joined
- (portRef Z (instanceRef wb_dati_5_0_iv_0_a3_1_0))
- (portRef C (instanceRef wb_dati_5_0_iv_0_0))
- ))
- (net (rename wb_dati_5_1_iv_i_i_a3_3_0_3 "wb_dati_5_1_iv_i_i_a3_3_0[3]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_0_3))
- ))
- (net un1_CmdEnable20_0_0_0 (joined
- (portRef Z (instanceRef un1_CmdEnable20_0_0_0))
+ (net un1_CmdEnable20_0_0 (joined
+ (portRef Z (instanceRef un1_CmdEnable20_0_0))
(portRef C (instanceRef CmdEnable_s_RNO))
))
- (net (rename wb_adr_5_i_0_0_1 "wb_adr_5_i_0_0[1]") (joined
- (portRef Z (instanceRef wb_adr_RNO_0_1))
- (portRef D (instanceRef wb_adr_RNO_1))
+ (net (rename wb_dati_5_0_iv_0_a2_0_0 "wb_dati_5_0_iv_0_a2_0[0]") (joined
+ (portRef Z (instanceRef wb_dati_5_0_iv_0_a2_0_0_0))
+ (portRef C (instanceRef wb_dati_5_0_iv_0_0))
))
- (net (rename wb_dati_5_1_iv_i_i_a3_1_3 "wb_dati_5_1_iv_i_i_a3_1[3]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3))
- (portRef D (instanceRef wb_dati_5_1_iv_i_i_3))
+ (net (rename wb_dati_5_1_iv_0_1_3 "wb_dati_5_1_iv_0_1[3]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_1_3))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_3))
))
- (net (rename wb_adr_5_i_0_0_0 "wb_adr_5_i_0_0[0]") (joined
- (portRef Z (instanceRef wb_adr_5_i_0_0_0))
- (portRef C (instanceRef wb_adr_RNO_0))
+ (net (rename wb_dati_5_1_iv_0_o2_0_5 "wb_dati_5_1_iv_0_o2_0[5]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_0_5))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_5))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_2))
))
- (net (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (joined
- (portRef Z (instanceRef wb_adr_5_i_0_1_0))
- (portRef D (instanceRef wb_adr_5_i_0_3_0))
- ))
- (net (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (joined
- (portRef Z (instanceRef wb_adr_5_i_0_3_0))
- (portRef D (instanceRef wb_adr_RNO_0))
- ))
- (net (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_1_1))
- (portRef D (instanceRef wb_dati_5_1_iv_0_1))
- ))
- (net (rename wb_dati_5_1_iv_0_1_6 "wb_dati_5_1_iv_0_1[6]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_1_6))
+ (net (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_6))
(portRef D (instanceRef wb_dati_5_1_iv_0_6))
))
- (net (rename wb_dati_5_1_iv_i_i_0_3 "wb_dati_5_1_iv_i_i_0[3]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_0_3))
- (portRef B (instanceRef wb_dati_5_1_iv_i_i_3))
+ (net (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4))
+ (portRef B (instanceRef wb_dati_5_1_iv_0_4))
))
- (net (rename wb_dati_5_1_iv_i_i_1_3 "wb_dati_5_1_iv_i_i_1[3]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_i_i_1_3))
- (portRef C (instanceRef wb_dati_5_1_iv_i_i_3))
+ (net (rename wb_dati_5_1_iv_0_2_4 "wb_dati_5_1_iv_0_2[4]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_2_4))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_4))
+ ))
+ (net (rename wb_adr_5_i_i_0_1 "wb_adr_5_i_i_0[1]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_0_1))
+ (portRef C (instanceRef wb_adr_5_i_i_1))
))
(net (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (joined
(portRef Z (instanceRef wb_dati_5_1_iv_0_0_7))
- (portRef D (instanceRef wb_dati_5_1_iv_0_7))
+ (portRef D (instanceRef wb_dati_5_1_iv_0_1_7))
))
- (net (rename wb_dati_5_1_iv_0_1_4 "wb_dati_5_1_iv_0_1[4]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_1_4))
- (portRef D (instanceRef wb_dati_5_1_iv_0_4))
+ (net (rename wb_adr_5_i_i_1_0 "wb_adr_5_i_i_1[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_1_0))
+ (portRef D (instanceRef wb_adr_5_i_i_5_0))
+ ))
+ (net (rename wb_adr_5_i_i_5_0 "wb_adr_5_i_i_5[0]") (joined
+ (portRef Z (instanceRef wb_adr_5_i_i_5_0))
+ (portRef D (instanceRef wb_adr_5_i_i_0))
))
(net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined
(portRef S0 (instanceRef FS_cry_0_0))
@@ -3464,13 +3353,13 @@
(net (rename FS_s_0_COUT_17 "FS_s_0_COUT[17]") (joined
(portRef COUT (instanceRef FS_s_0_17))
))
- (net (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4))
- (portRef C (instanceRef wb_dati_5_1_iv_0_4))
+ (net (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (joined
+ (portRef Z (instanceRef wb_dati_5_1_iv_0_1_7))
+ (portRef C (instanceRef wb_dati_5_1_iv_0_7))
))
- (net RCKEEN_8_u_0_1_0 (joined
- (portRef Z (instanceRef RCKEEN_8_u_0_1_0))
- (portRef C (instanceRef RCKEEN_8_u_0))
+ (net RCKEEN_8_u_1 (joined
+ (portRef Z (instanceRef RCKEEN_8_u_1_0))
+ (portRef C (instanceRef RCKEEN_8_u))
))
(net LEDENe_0 (joined
(portRef Z (instanceRef LEDENe))
@@ -3484,6 +3373,26 @@
(portRef Z (instanceRef RowAd_7))
(portRef D (instanceRef RowA_7))
))
+ (net (rename RowAd_0_8 "RowAd_0[8]") (joined
+ (portRef Z (instanceRef RowAd_8))
+ (portRef D (instanceRef RowA_8))
+ ))
+ (net (rename RowAd_0_5 "RowAd_0[5]") (joined
+ (portRef Z (instanceRef RowAd_5))
+ (portRef D (instanceRef RowA_5))
+ ))
+ (net (rename RBAd_0_1 "RBAd_0[1]") (joined
+ (portRef Z (instanceRef RBAd_1))
+ (portRef D (instanceRef RBA_0io_1))
+ ))
+ (net (rename RowAd_0_3 "RowAd_0[3]") (joined
+ (portRef Z (instanceRef RowAd_3))
+ (portRef D (instanceRef RowA_3))
+ ))
+ (net (rename RowAd_0_0 "RowAd_0[0]") (joined
+ (portRef Z (instanceRef RowAd_0))
+ (portRef D (instanceRef RowA_0))
+ ))
(net (rename RowAd_0_6 "RowAd_0[6]") (joined
(portRef Z (instanceRef RowAd_6))
(portRef D (instanceRef RowA_6))
@@ -3492,10 +3401,6 @@
(portRef Z (instanceRef RowAd_2))
(portRef D (instanceRef RowA_2))
))
- (net (rename RowAd_0_3 "RowAd_0[3]") (joined
- (portRef Z (instanceRef RowAd_3))
- (portRef D (instanceRef RowA_3))
- ))
(net (rename RowAd_0_4 "RowAd_0[4]") (joined
(portRef Z (instanceRef RowAd_4))
(portRef D (instanceRef RowA_4))
@@ -3508,22 +3413,6 @@
(portRef Z (instanceRef RBAd_0))
(portRef D (instanceRef RBA_0io_0))
))
- (net (rename RBAd_0_1 "RBAd_0[1]") (joined
- (portRef Z (instanceRef RBAd_1))
- (portRef D (instanceRef RBA_0io_1))
- ))
- (net (rename RowAd_0_8 "RowAd_0[8]") (joined
- (portRef Z (instanceRef RowAd_8))
- (portRef D (instanceRef RowA_8))
- ))
- (net (rename RowAd_0_5 "RowAd_0[5]") (joined
- (portRef Z (instanceRef RowAd_5))
- (portRef D (instanceRef RowA_5))
- ))
- (net (rename RowAd_0_0 "RowAd_0[0]") (joined
- (portRef Z (instanceRef RowAd_0))
- (portRef D (instanceRef RowA_0))
- ))
(net (rename RowAd_0_9 "RowAd_0[9]") (joined
(portRef Z (instanceRef RowAd_9))
(portRef D (instanceRef RowA_9))
@@ -3540,29 +3429,25 @@
(portRef Z (instanceRef RA11d))
(portRef D (instanceRef RA11_0io))
))
- (net G_4_0_a3_0 (joined
- (portRef Z (instanceRef PHI2r3_RNIFT0I_0))
- (portRef C (instanceRef CmdValid_fast_RNI3K0H1))
+ (net N_4 (joined
+ (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R))
+ (portRef C (instanceRef CmdValid_RNITBH02))
))
(net n8MEGENe_1_0 (joined
(portRef Z (instanceRef n8MEGEN_RNO_0))
(portRef C (instanceRef n8MEGEN_RNO))
))
- (net N_4 (joined
- (portRef N_4 (instanceRef ufmefb))
- (portRef C (instanceRef CmdValid_RNIOOBE2))
- ))
(net g1_0 (joined
(portRef Z (instanceRef PHI2r3_RNIFT0I))
- (portRef D (instanceRef CmdValid_RNIOOBE2))
+ (portRef D (instanceRef CmdValid_RNITBH02))
))
- (net m3_0_a2_0 (joined
- (portRef Z (instanceRef RASr2_RNI6PUF))
- (portRef D (instanceRef CBR_fast_RNIQ31K1))
+ (net g0_0_a3_1 (joined
+ (portRef g0_0_a3_1 (instanceRef ufmefb))
+ (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R))
))
- (net CBR_fast (joined
- (portRef Q (instanceRef CBR_fast))
- (portRef A (instanceRef CBR_fast_RNIQ31K1))
+ (net G_8_0_a3_0_0 (joined
+ (portRef Z (instanceRef PHI2r3_RNIFT0I_0))
+ (portRef C (instanceRef CmdValid_fast_RNI3K0H1))
))
(net CmdValid_fast (joined
(portRef Q (instanceRef CmdValid_fast))
@@ -3575,23 +3460,52 @@
(net Ready_fast (joined
(portRef Q (instanceRef Ready_fast))
(portRef B (instanceRef RowAd_9))
- (portRef B (instanceRef RowAd_0))
- (portRef B (instanceRef RowAd_5))
- (portRef B (instanceRef RowAd_8))
- (portRef B (instanceRef RBAd_1))
(portRef B (instanceRef RBAd_0))
(portRef B (instanceRef RowAd_1))
(portRef B (instanceRef RowAd_4))
- (portRef B (instanceRef RowAd_3))
(portRef B (instanceRef RowAd_2))
(portRef B (instanceRef RowAd_6))
+ (portRef B (instanceRef RowAd_0))
+ (portRef B (instanceRef RowAd_3))
+ (portRef B (instanceRef RBAd_1))
+ (portRef B (instanceRef RowAd_5))
+ (portRef B (instanceRef RowAd_8))
(portRef B (instanceRef RowAd_7))
(portRef B (instanceRef RA11d))
(portRef B (instanceRef Ready_fast_RNO))
))
- (net N_248_i_sx (joined
+ (net CBR_fast (joined
+ (portRef Q (instanceRef CBR_fast))
+ (portRef A (instanceRef RCKEEN_8_u_0_a2_1))
+ (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+ ))
+ (net FWEr_fast (joined
+ (portRef Q (instanceRef FWEr_fast))
+ (portRef D (instanceRef nRWE_s_i_a2_0))
+ ))
+ (net nRCAS_0io_RNO_1 (joined
+ (portRef Z (instanceRef nRCAS_0io_RNO_1))
+ (portRef D (instanceRef nRCAS_0io_RNO_0))
+ ))
+ (net N_242_i_1 (joined
(portRef Z (instanceRef nRCAS_0io_RNO_0))
- (portRef D (instanceRef nRCAS_0io_RNO))
+ (portRef C (instanceRef nRCAS_0io_RNO))
+ ))
+ (net nRCS_0io_RNO_0 (joined
+ (portRef Z (instanceRef nRCS_0io_RNO_0))
+ (portRef B (instanceRef nRCS_0io_RNO))
+ ))
+ (net nRWE_0io_RNO_1 (joined
+ (portRef Z (instanceRef nRWE_0io_RNO_1))
+ (portRef A (instanceRef nRWE_0io_RNO_0))
+ ))
+ (net nRWE_0io_RNO_2 (joined
+ (portRef Z (instanceRef nRWE_0io_RNO_2))
+ (portRef B (instanceRef nRWE_0io_RNO_0))
+ ))
+ (net nRWE_0io_RNO_0 (joined
+ (portRef Z (instanceRef nRWE_0io_RNO_0))
+ (portRef C (instanceRef nRWE_0io_RNO))
))
(net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
(portRef Z (instanceRef XOR8MEG_CN))
@@ -3609,6 +3523,7 @@
))
(net VCC (joined
(portRef Z (instanceRef VCC))
+ (portRef D1 (instanceRef rck))
(portRef B0 (instanceRef FS_cry_0_0))
(portRef SP (instanceRef RA10_0io))
(portRef SP (instanceRef RA11_0io))
@@ -3639,6 +3554,8 @@
))
(net GND (joined
(portRef Z (instanceRef GND))
+ (portRef RST (instanceRef rck))
+ (portRef D0 (instanceRef rck))
(portRef D1 (instanceRef FS_cry_0_0))
(portRef C1 (instanceRef FS_cry_0_0))
(portRef B1 (instanceRef FS_cry_0_0))
@@ -3745,12 +3662,14 @@
))
(net (rename MAin_c_0 "MAin_c[0]") (joined
(portRef O (instanceRef MAin_pad_0))
+ (portRef A (instanceRef CmdEnable_RNI7PMB1))
+ (portRef D (instanceRef XOR8MEG18_0_a2))
(portRef A (instanceRef RowAd_0))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_0))
- (portRef C (instanceRef un1_CmdEnable20_0_0_a2_0))
- (portRef C (instanceRef un1_CmdEnable20_0_0_a2_1))
- (portRef A (instanceRef un1_CmdEnable20_0_0_0))
- (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a3_3))
+ (portRef A (instanceRef un9_RA_i_m2_0))
+ (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2_1))
+ (portRef A (instanceRef un1_CmdEnable20_0_0))
+ (portRef C (instanceRef un1_CmdEnable20_0_a2_1_0))
+ (portRef A (instanceRef XOR8MEG18_0_a2_0))
))
(net (rename MAin_0 "MAin[0]") (joined
(portRef (member main 9))
@@ -3758,14 +3677,16 @@
))
(net (rename MAin_c_1 "MAin_c[1]") (joined
(portRef O (instanceRef MAin_pad_1))
- (portRef D (instanceRef CmdEnable16_0_a2_1_a2))
+ (portRef D (instanceRef CmdEnable_RNI7PMB1))
+ (portRef A (instanceRef XOR8MEG18_0_a2))
+ (portRef D (instanceRef un1_CmdEnable20_0_a2_3_0))
+ (portRef D (instanceRef CmdEnable16_0_a2))
(portRef A (instanceRef RowAd_1))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_1))
- (portRef B (instanceRef un1_CmdEnable20_0_0_0))
- (portRef A (instanceRef un1_CmdEnable20_0_0_a3_1_1))
- (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a3_3))
- (portRef A (instanceRef un1_ADWR_i_i_a2))
- (portRef D (instanceRef un1_CmdEnable20_0_0_a2_0_RNI00E51))
+ (portRef A (instanceRef un9_RA_i_m2_1))
+ (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+ (portRef B (instanceRef un1_CmdEnable20_0_0))
+ (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2))
+ (portRef A (instanceRef ADSubmitted_r_0_RNO))
(portRef D (instanceRef C1Submitted_RNO))
))
(net (rename MAin_1 "MAin[1]") (joined
@@ -3775,8 +3696,8 @@
(net (rename MAin_c_2 "MAin_c[2]") (joined
(portRef O (instanceRef MAin_pad_2))
(portRef A (instanceRef RowAd_2))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_2))
- (portRef A (instanceRef un1_CmdEnable20_0_0_o3_4))
+ (portRef A (instanceRef un9_RA_i_m2_2))
+ (portRef A (instanceRef un1_ADWR_i_o2_4))
))
(net (rename MAin_2 "MAin[2]") (joined
(portRef (member main 7))
@@ -3785,8 +3706,8 @@
(net (rename MAin_c_3 "MAin_c[3]") (joined
(portRef O (instanceRef MAin_pad_3))
(portRef A (instanceRef RowAd_3))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_3))
- (portRef B (instanceRef un1_CmdEnable20_0_0_o3_4))
+ (portRef A (instanceRef un9_RA_i_m2_3))
+ (portRef A (instanceRef un1_ADWR_i_o2_3))
))
(net (rename MAin_3 "MAin[3]") (joined
(portRef (member main 6))
@@ -3795,8 +3716,8 @@
(net (rename MAin_c_4 "MAin_c[4]") (joined
(portRef O (instanceRef MAin_pad_4))
(portRef A (instanceRef RowAd_4))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_4))
- (portRef A (instanceRef un1_CmdEnable20_0_0_o3_3))
+ (portRef A (instanceRef un9_RA_i_m2_4))
+ (portRef B (instanceRef un1_ADWR_i_o2_4))
))
(net (rename MAin_4 "MAin[4]") (joined
(portRef (member main 5))
@@ -3805,8 +3726,8 @@
(net (rename MAin_c_5 "MAin_c[5]") (joined
(portRef O (instanceRef MAin_pad_5))
(portRef A (instanceRef RowAd_5))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_5))
- (portRef C (instanceRef un1_CmdEnable20_0_0_o3_4))
+ (portRef A (instanceRef un9_RA_i_m2_5))
+ (portRef C (instanceRef un1_ADWR_i_o2_4))
))
(net (rename MAin_5 "MAin[5]") (joined
(portRef (member main 4))
@@ -3815,8 +3736,8 @@
(net (rename MAin_c_6 "MAin_c[6]") (joined
(portRef O (instanceRef MAin_pad_6))
(portRef A (instanceRef RowAd_6))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_6))
- (portRef B (instanceRef un1_CmdEnable20_0_0_o3_3))
+ (portRef A (instanceRef un9_RA_i_m2_6))
+ (portRef B (instanceRef un1_ADWR_i_o2_3))
))
(net (rename MAin_6 "MAin[6]") (joined
(portRef (member main 3))
@@ -3825,8 +3746,8 @@
(net (rename MAin_c_7 "MAin_c[7]") (joined
(portRef O (instanceRef MAin_pad_7))
(portRef A (instanceRef RowAd_7))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_7))
- (portRef D (instanceRef un1_CmdEnable20_0_0_o3_4))
+ (portRef A (instanceRef un9_RA_i_m2_7))
+ (portRef D (instanceRef un1_ADWR_i_o2_4))
))
(net (rename MAin_7 "MAin[7]") (joined
(portRef (member main 2))
@@ -3844,8 +3765,8 @@
(net (rename MAin_c_9 "MAin_c[9]") (joined
(portRef O (instanceRef MAin_pad_9))
(portRef A (instanceRef RowAd_9))
- (portRef A (instanceRef RDQML_0_0))
- (portRef A (instanceRef un9_RA_i_m2_i_m2_9))
+ (portRef A (instanceRef RDQML_0))
+ (portRef A (instanceRef un9_RA_i_m2_9))
(portRef A (instanceRef RDQMH_pad_RNO))
))
(net (rename MAin_9 "MAin[9]") (joined
@@ -3870,10 +3791,10 @@
))
(net (rename Din_c_0 "Din_c[0]") (joined
(portRef O (instanceRef Din_pad_0))
- (portRef D (instanceRef un1_CmdEnable20_0_0_a2))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a2))
- (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0_0))
- (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0))
+ (portRef D (instanceRef un1_CmdEnable20_0_a2_2))
+ (portRef A (instanceRef XOR8MEG_3_u_0_a2_1))
+ (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
+ (portRef A (instanceRef CmdUFMWrite_3_u_0_0))
(portRef D (instanceRef CmdUFMData))
(portRef D (instanceRef Bank_0io_0))
(portRef D (instanceRef WRD_0io_0))
@@ -3884,11 +3805,11 @@
))
(net (rename Din_c_1 "Din_c[1]") (joined
(portRef O (instanceRef Din_pad_1))
- (portRef B (instanceRef un1_CmdEnable20_0_0_a2))
- (portRef C (instanceRef CmdLEDEN_4_u_i_0_0))
- (portRef B (instanceRef CmdUFMWrite_3_u_0_0_0))
- (portRef B (instanceRef CmdUFMShift_3_u_0_0_0))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_0))
+ (portRef B (instanceRef un1_CmdEnable20_0_a2_2))
+ (portRef C (instanceRef CmdLEDEN_4_u_i_0))
+ (portRef A (instanceRef XOR8MEG_3_u_0_0))
+ (portRef B (instanceRef CmdUFMShift_3_u_0_0))
+ (portRef B (instanceRef CmdUFMWrite_3_u_0_0))
(portRef D (instanceRef Bank_0io_1))
(portRef D (instanceRef WRD_0io_1))
))
@@ -3898,8 +3819,9 @@
))
(net (rename Din_c_2 "Din_c[2]") (joined
(portRef O (instanceRef Din_pad_2))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_0))
- (portRef A (instanceRef un1_CmdEnable20_0_0_a2_0))
+ (portRef A (instanceRef XOR8MEG_3_u_0_a2_2))
+ (portRef A (instanceRef un1_CmdEnable20_0_a2_1_0))
+ (portRef A (instanceRef CmdEnable17_0_a2))
(portRef D (instanceRef Bank_0io_2))
(portRef D (instanceRef WRD_0io_2))
))
@@ -3909,11 +3831,11 @@
))
(net (rename Din_c_3 "Din_c[3]") (joined
(portRef O (instanceRef Din_pad_3))
- (portRef D (instanceRef CmdLEDEN_4_u_i_0_a2))
- (portRef A (instanceRef CmdLEDEN_4_u_i_0_a2_0))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_a3_0_2))
- (portRef A (instanceRef un1_CmdEnable20_0_0_a2_1))
- (portRef A (instanceRef CmdValid_2_i_o2_1_o3))
+ (portRef B (instanceRef un1_CmdEnable20_0_a2_3_0))
+ (portRef A (instanceRef XOR8MEG_3_u_0_a2_0_2))
+ (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_1))
+ (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2_0))
+ (portRef A (instanceRef CmdValid_2_i_o2))
(portRef D (instanceRef Bank_0io_3))
(portRef D (instanceRef WRD_0io_3))
))
@@ -3923,12 +3845,12 @@
))
(net (rename Din_c_4 "Din_c[4]") (joined
(portRef O (instanceRef Din_pad_4))
- (portRef B (instanceRef CmdLEDEN_4_u_i_0_a3_0_0))
- (portRef C (instanceRef un1_CmdEnable20_0_0_a2))
- (portRef B (instanceRef CmdLEDEN_4_u_i_0_a2))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a2))
- (portRef B (instanceRef CmdValid_2_i_o2_1_o3))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a3))
+ (portRef C (instanceRef un1_CmdEnable20_0_a2_2))
+ (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+ (portRef B (instanceRef XOR8MEG_3_u_0_a2_1))
+ (portRef A (instanceRef XOR8MEG_3_u_0_a2))
+ (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2_0))
+ (portRef B (instanceRef CmdValid_2_i_o2))
(portRef D (instanceRef Bank_0io_4))
(portRef D (instanceRef WRD_0io_4))
))
@@ -3938,12 +3860,12 @@
))
(net (rename Din_c_5 "Din_c[5]") (joined
(portRef O (instanceRef Din_pad_5))
- (portRef A (instanceRef CmdLEDEN_4_u_i_0_a3_0_0))
- (portRef C (instanceRef CmdLEDEN_4_u_i_0_a2))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_0))
- (portRef B (instanceRef CmdLEDEN_4_u_i_0_a2_0))
- (portRef C (instanceRef CmdValid_2_i_o2_1_o3))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a3))
+ (portRef A (instanceRef un1_CmdEnable20_0_a2_3_0))
+ (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+ (portRef B (instanceRef XOR8MEG_3_u_0_a2_2))
+ (portRef B (instanceRef XOR8MEG_3_u_0_a2))
+ (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a2_0))
+ (portRef C (instanceRef CmdValid_2_i_o2))
(portRef D (instanceRef Bank_0io_5))
(portRef D (instanceRef WRD_0io_5))
))
@@ -3953,11 +3875,12 @@
))
(net (rename Din_c_6 "Din_c[6]") (joined
(portRef O (instanceRef Din_pad_6))
- (portRef D (instanceRef CmdLEDEN_4_u_i_0_a3_0_0))
+ (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0))
(portRef A (instanceRef RA11d))
- (portRef A (instanceRef XOR8MEG_3_u_0_0_o2_1))
- (portRef B (instanceRef un1_CmdEnable20_0_0_a2_0))
- (portRef B (instanceRef un1_CmdEnable20_0_0_a2_1))
+ (portRef A (instanceRef XOR8MEG_3_u_0_o2_1))
+ (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_1))
+ (portRef B (instanceRef un1_CmdEnable20_0_a2_1_0))
+ (portRef B (instanceRef CmdEnable17_0_a2))
(portRef D (instanceRef Bank_0io_6))
(portRef D (instanceRef WRD_0io_6))
))
@@ -3967,9 +3890,9 @@
))
(net (rename Din_c_7 "Din_c[7]") (joined
(portRef O (instanceRef Din_pad_7))
- (portRef C (instanceRef CmdLEDEN_4_u_i_0_a3_0_0))
- (portRef A (instanceRef un1_CmdEnable20_0_0_a2))
- (portRef B (instanceRef XOR8MEG_3_u_0_0_o2_1))
+ (portRef A (instanceRef un1_CmdEnable20_0_a2_2))
+ (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+ (portRef B (instanceRef XOR8MEG_3_u_0_o2_1))
(portRef D (instanceRef Bank_0io_7))
(portRef D (instanceRef WRD_0io_7))
))
@@ -4030,9 +3953,9 @@
))
(net nFWE_c (joined
(portRef O (instanceRef nFWE_pad))
- (portRef C (instanceRef un1_CmdEnable20_0_0_o3_3))
+ (portRef C (instanceRef un1_ADWR_i_o2_3))
(portRef B (instanceRef nCCAS_pad_RNI01SJ))
- (portRef A (instanceRef FWEr_RNO))
+ (portRef A (instanceRef nFWE_pad_RNI420B))
))
(net nFWE (joined
(portRef nFWE)
@@ -4063,7 +3986,7 @@
(portRef (member rba 0))
))
(net (rename RA_c_0 "RA_c[0]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_0))
+ (portRef Z (instanceRef un9_RA_i_m2_0))
(portRef I (instanceRef RA_pad_0))
))
(net (rename RA_0 "RA[0]") (joined
@@ -4071,7 +3994,7 @@
(portRef (member ra 11))
))
(net (rename RA_c_1 "RA_c[1]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_1))
+ (portRef Z (instanceRef un9_RA_i_m2_1))
(portRef I (instanceRef RA_pad_1))
))
(net (rename RA_1 "RA[1]") (joined
@@ -4079,7 +4002,7 @@
(portRef (member ra 10))
))
(net (rename RA_c_2 "RA_c[2]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_2))
+ (portRef Z (instanceRef un9_RA_i_m2_2))
(portRef I (instanceRef RA_pad_2))
))
(net (rename RA_2 "RA[2]") (joined
@@ -4087,7 +4010,7 @@
(portRef (member ra 9))
))
(net (rename RA_c_3 "RA_c[3]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_3))
+ (portRef Z (instanceRef un9_RA_i_m2_3))
(portRef I (instanceRef RA_pad_3))
))
(net (rename RA_3 "RA[3]") (joined
@@ -4095,7 +4018,7 @@
(portRef (member ra 8))
))
(net (rename RA_c_4 "RA_c[4]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_4))
+ (portRef Z (instanceRef un9_RA_i_m2_4))
(portRef I (instanceRef RA_pad_4))
))
(net (rename RA_4 "RA[4]") (joined
@@ -4103,7 +4026,7 @@
(portRef (member ra 7))
))
(net (rename RA_c_5 "RA_c[5]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_5))
+ (portRef Z (instanceRef un9_RA_i_m2_5))
(portRef I (instanceRef RA_pad_5))
))
(net (rename RA_5 "RA[5]") (joined
@@ -4111,7 +4034,7 @@
(portRef (member ra 6))
))
(net (rename RA_c_6 "RA_c[6]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_6))
+ (portRef Z (instanceRef un9_RA_i_m2_6))
(portRef I (instanceRef RA_pad_6))
))
(net (rename RA_6 "RA[6]") (joined
@@ -4119,7 +4042,7 @@
(portRef (member ra 5))
))
(net (rename RA_c_7 "RA_c[7]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_7))
+ (portRef Z (instanceRef un9_RA_i_m2_7))
(portRef I (instanceRef RA_pad_7))
))
(net (rename RA_7 "RA[7]") (joined
@@ -4135,7 +4058,7 @@
(portRef (member ra 3))
))
(net (rename RA_c_9 "RA_c[9]") (joined
- (portRef Z (instanceRef un9_RA_i_m2_i_m2_9))
+ (portRef Z (instanceRef un9_RA_i_m2_9))
(portRef I (instanceRef RA_pad_9))
))
(net (rename RA_9 "RA[9]") (joined
@@ -4233,6 +4156,7 @@
(net RCLK_c (joined
(portRef O (instanceRef RCLK_pad))
(portRef RCLK_c (instanceRef ufmefb))
+ (portRef SCLK (instanceRef rck))
(portRef CK (instanceRef CASr))
(portRef CK (instanceRef CASr2))
(portRef CK (instanceRef CASr3))
@@ -4304,12 +4228,19 @@
(portRef RCLK)
(portRef I (instanceRef RCLK_pad))
))
+ (net RCLKout_c (joined
+ (portRef Q (instanceRef rck))
+ (portRef I (instanceRef RCLKout_pad))
+ ))
+ (net RCLKout (joined
+ (portRef O (instanceRef RCLKout_pad))
+ (portRef RCLKout)
+ ))
(net RCKE_c (joined
(portRef Q (instanceRef RCKE))
- (portRef C (instanceRef nRCS_9_u_i_0_o3))
- (portRef B (instanceRef nRWE_s_i_0_tz_0))
+ (portRef B (instanceRef nRWE_0io_RNO_2))
+ (portRef C (instanceRef nRCS_9_u_i_0_0))
(portRef I (instanceRef RCKE_pad))
- (portRef B (instanceRef nRRAS_0io_RNO))
))
(net RCKE (joined
(portRef O (instanceRef RCKE_pad))
@@ -4348,28 +4279,29 @@
(portRef RDQMH)
))
(net RDQML_c (joined
- (portRef Z (instanceRef RDQML_0_0))
+ (portRef Z (instanceRef RDQML_0))
(portRef I (instanceRef RDQML_pad))
))
(net RDQML (joined
(portRef O (instanceRef RDQML_pad))
(portRef RDQML)
))
- (net N_757_0 (joined
+ (net N_586_0 (joined
(portRef Z (instanceRef InitReady_RNO))
(portRef D (instanceRef InitReady))
))
- (net N_758_0 (joined
+ (net N_587_0 (joined
(portRef Z (instanceRef Ready_RNO))
(portRef D (instanceRef Ready))
))
- (net N_759_0 (joined
+ (net N_588_0 (joined
(portRef Z (instanceRef Ready_fast_RNO))
(portRef D (instanceRef Ready_fast))
))
(net nFWE_c_i (joined
- (portRef Z (instanceRef FWEr_RNO))
+ (portRef Z (instanceRef nFWE_pad_RNI420B))
(portRef D (instanceRef FWEr))
+ (portRef D (instanceRef FWEr_fast))
))
(net nCRAS_c_i_0 (joined
(portRef Z (instanceRef RASr_RNO))
@@ -4389,16 +4321,6 @@
(portRef SCLK (instanceRef WRD_0io_1))
(portRef SCLK (instanceRef WRD_0io_0))
))
- (net N_360_i (joined
- (portRef Z (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0))
- (portRef SP (instanceRef IS_3))
- (portRef SP (instanceRef IS_2))
- (portRef SP (instanceRef IS_1))
- ))
- (net N_246_i (joined
- (portRef Z (instanceRef nRRAS_0io_RNO))
- (portRef D (instanceRef nRRAS_0io))
- ))
(net (rename IS_i_0 "IS_i[0]") (joined
(portRef Z (instanceRef RA10_0io_RNO))
(portRef D (instanceRef RA10_0io))
@@ -4408,14 +4330,6 @@
(portRef CD (instanceRef S_1))
(portRef CD (instanceRef S_0))
))
- (net (rename wb_dati_5_1_iv_0_o3_am_5 "wb_dati_5_1_iv_0_o3_am[5]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_o3_am_5))
- (portRef BLUT (instanceRef wb_dati_5_1_iv_0_o3_5))
- ))
- (net (rename wb_dati_5_1_iv_0_o3_bm_5 "wb_dati_5_1_iv_0_o3_bm[5]") (joined
- (portRef Z (instanceRef wb_dati_5_1_iv_0_o3_bm_5))
- (portRef ALUT (instanceRef wb_dati_5_1_iv_0_o3_5))
- ))
(net N_1 (joined
(portRef CIN (instanceRef FS_cry_0_0))
))
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
index 29629f9..9a2c0f9 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
@@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
-NOTE DATE CREATED: Thu Sep 21 05:40:18 2023*
+NOTE DATE CREATED: Thu Oct 19 23:51:24 2023*
NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@@ -16,6 +16,7 @@ NOTE PINS nRCAS : 52 : out*
NOTE PINS nRRAS : 54 : out*
NOTE PINS nRWE : 49 : out*
NOTE PINS RCKE : 53 : out*
+NOTE PINS RCLKout : 62 : out*
NOTE PINS RCLK : 63 : in*
NOTE PINS nRCS : 57 : out*
NOTE PINS RD[7] : 43 : inout*
@@ -27,7 +28,7 @@ NOTE PINS RD[2] : 38 : inout*
NOTE PINS RD[1] : 37 : inout*
NOTE PINS RA[11] : 59 : out*
NOTE PINS RA[10] : 64 : out*
-NOTE PINS RA[9] : 62 : out*
+NOTE PINS RA[9] : 47 : out*
NOTE PINS RA[8] : 65 : out*
NOTE PINS RA[7] : 75 : out*
NOTE PINS RA[6] : 68 : out*
@@ -75,556 +76,556 @@ QF343936*
G0*
F0*
L000000
-11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000010100101000
-00000011000011000101000000110000010010001111111101000110000000000000000000000000101110001110000000000001010011010000000000000000
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*
NOTE END CONFIG DATA*
-L70016
+L69504
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
@@ -2769,10 +2770,10 @@ L302720
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
*
-C651E*
+C3886*
NOTE FEATURE_ROW*
E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
-7B11
+8207
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
index dc364d2..fea8aaf 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
@@ -15,24 +15,36 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
-Mapped on: 09/21/23 05:39:45
+Mapped on: 10/19/23 23:50:56
Design Summary
--------------
- Number of registers: 109 out of 1520 (7%)
- PFU registers: 84 out of 1280 (7%)
+ Number of registers: 110 out of 1520 (7%)
+ PFU registers: 85 out of 1280 (7%)
PIO registers: 25 out of 240 (10%)
- Number of SLICEs: 120 out of 640 (19%)
- SLICEs as Logic/ROM: 120 out of 640 (19%)
+ Number of SLICEs: 115 out of 640 (18%)
+ SLICEs as Logic/ROM: 115 out of 640 (18%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 10 out of 640 (2%)
- Number of LUT4s: 237 out of 1280 (19%)
- Number used as logic LUTs: 217
+ Number of LUT4s: 229 out of 1280 (18%)
+ Number used as logic LUTs: 209
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
- Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
+ Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
+ Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
+ Number of IDDR cells: 0
+ Number of ODDR cells: 1
+ Number of TDDR cells: 0
+ Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
+ Number of PIO using IDDR only: 0 (0 differential)
+ Number of PIO using ODDR only: 1 (0 differential)
+ Number of PIO using TDDR only: 0 (0 differential)
+ Number of PIO using IDDR/ODDR: 0 (0 differential)
+ Number of PIO using IDDR/TDDR: 0 (0 differential)
+ Number of PIO using ODDR/TDDR: 0 (0 differential)
+ Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
@@ -48,6 +60,16 @@ Design Summary
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
+
+ Page 1
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
+Design Summary (cont)
+---------------------
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
@@ -59,24 +81,14 @@ Design Summary
ripple logic.
Number of clocks: 4
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
- Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
-
- Page 1
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-Design Summary (cont)
----------------------
- Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
+ Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
+ Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 5
- Net N_178: 1 loads, 1 LSLICEs
+ Net N_103: 1 loads, 1 LSLICEs
Net XOR8MEG18: 5 loads, 5 LSLICEs
- Net N_360_i: 2 loads, 2 LSLICEs
- Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
+ Net N_122: 9 loads, 9 LSLICEs
+ Net N_244_i: 2 loads, 2 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
@@ -86,16 +98,16 @@ Design Summary (cont)
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
- Net InitReady: 41 loads
- Net FS[11]: 23 loads
- Net FS[13]: 22 loads
- Net FS[10]: 21 loads
- Net FS[12]: 21 loads
- Net FS[9]: 20 loads
+ Net InitReady: 31 loads
+ Net FS[12]: 23 loads
+ Net FS[13]: 23 loads
+ Net FS[11]: 21 loads
+ Net N_132: 20 loads
Net FS[14]: 18 loads
- Net CO0: 15 loads
+ Net FS[10]: 16 loads
+ Net FS[9]: 14 loads
+ Net Ready: 14 loads
Net Ready_fast: 14 loads
- Net N_214: 13 loads
@@ -114,6 +126,14 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
+
+ Page 2
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
IO (PIO) Attributes
-------------------
@@ -126,16 +146,6 @@ IO (PIO) Attributes
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN |
-
- Page 2
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-IO (PIO) Attributes (cont)
---------------------------
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -149,6 +159,8 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
+| RCLKout | OUTPUT | LVCMOS33 | |
++---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
@@ -180,6 +192,16 @@ IO (PIO) Attributes (cont)
| RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | |
+
+ Page 3
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
+IO (PIO) Attributes (cont)
+--------------------------
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -192,16 +214,6 @@ IO (PIO) Attributes (cont)
| RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
-
- Page 3
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-IO (PIO) Attributes (cont)
---------------------------
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
@@ -246,6 +258,16 @@ IO (PIO) Attributes (cont)
| CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | |
+
+ Page 4
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
+IO (PIO) Attributes (cont)
+--------------------------
+---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -258,16 +280,6 @@ IO (PIO) Attributes (cont)
| MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | |
-
- Page 4
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-IO (PIO) Attributes (cont)
---------------------------
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -285,7 +297,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
-Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
@@ -313,6 +324,16 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+
+ Page 5
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
+Removed logic (cont)
+--------------------
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
@@ -324,16 +345,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-
- Page 5
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-Removed logic (cont)
---------------------
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
@@ -360,7 +371,6 @@ Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
-Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@@ -380,6 +390,16 @@ Embedded Functional Block Connection Summary
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
+
+ Page 6
+
+
+
+
+Design: RAM2GS Date: 10/19/23 23:50:56
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
@@ -390,16 +410,6 @@ Embedded Functional Block Connection Summary
Timer/Counter Function Summary:
------------------------------
None
-
- Page 6
-
-
-
-
-Design: RAM2GS Date: 09/21/23 05:39:45
-
-Embedded Functional Block Connection Summary (cont)
----------------------------------------------------
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
@@ -436,16 +446,6 @@ Run Time and Memory Usage
-
-
-
-
-
-
-
-
-
-
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
index 9c5f8e8..3c05c43 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
-Thu Sep 21 05:39:56 2023
+Thu Oct 19 23:51:05 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -53,11 +53,12 @@ Pinout by Port Name:
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
-| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
+| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
+| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST |
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
@@ -134,7 +135,7 @@ Pinout by Pin Number:
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
-| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
+| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
@@ -146,7 +147,7 @@ Pinout by Pin Number:
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
-| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
+| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
@@ -264,11 +265,12 @@ LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65";
-LOCATE COMP "RA[9]" SITE "62";
+LOCATE COMP "RA[9]" SITE "47";
LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "63";
+LOCATE COMP "RCLKout" SITE "62";
LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36";
@@ -297,5 +299,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
-Thu Sep 21 05:39:59 2023
+Thu Oct 19 23:51:08 2023
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
index 4ed3d7d..a31ef81 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
@@ -1,5 +1,5 @@
SCHEMATIC START ;
-# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:45 2023
+# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Oct 19 23:50:57 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
@@ -11,6 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "RCLKout" SITE "62" ;
LOCATE COMP "RCLK" SITE "63" ;
LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "RD[7]" SITE "43" ;
@@ -22,7 +23,7 @@ LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[10]" SITE "64" ;
-LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[9]" SITE "47" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[6]" SITE "68" ;
@@ -110,4 +111,5 @@ OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
+OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;
COMMERCIAL ;
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
index 086d334..21fb607 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
@@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
-# Thu Sep 21 05:39:34 2023
+# Thu Oct 19 23:50:47 2023
#Implementation: impl1
@@ -51,10 +51,16 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
+
+Compiler output is up to date. No re-compile necessary
+
Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@@ -65,6 +71,9 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2GS .......
@@ -77,13 +86,15 @@ Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on ODDRXE .......
+Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:47 2023
###########################################################]
###########################################################[
@@ -110,7 +121,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:48 2023
###########################################################]
@@ -125,7 +136,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:48 2023
###########################################################]
###########################################################[
@@ -146,18 +157,17 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:36 2023
+# Thu Oct 19 23:50:49 2023
###########################################################]
-Premap Report
-
-# Thu Sep 21 05:39:37 2023
+# Thu Oct 19 23:50:49 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -179,7 +189,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
@@ -223,17 +233,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -317,12 +327,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:39:38 2023
+# Thu Oct 19 23:50:50 2023
###########################################################]
-Map & Optimize Report
-
-# Thu Sep 21 05:39:39 2023
+# Thu Oct 19 23:50:50 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -341,42 +349,42 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
-@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].
-Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Available hyper_sources - for debug and ip models
@@ -398,50 +406,63 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
- 1 0h:00m:01s -2.98ns 201 / 106
- 2 0h:00m:01s -2.98ns 217 / 106
- 3 0h:00m:01s -2.76ns 215 / 106
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
+ 1 0h:00m:01s -2.76ns 193 / 106
+ 2 0h:00m:01s -2.76ns 209 / 106
+ 3 0h:00m:01s -2.76ns 208 / 106
+ 4 0h:00m:01s -2.76ns 206 / 106
+ 5 0h:00m:01s -2.76ns 206 / 106
+ 6 0h:00m:01s -2.76ns 205 / 106
+ 7 0h:00m:01s -2.76ns 205 / 106
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 2 LUTs via timing driven replication
- 4 0h:00m:02s -1.97ns 220 / 109
+ 8 0h:00m:01s -1.83ns 209 / 110
+ 9 0h:00m:01s -1.83ns 209 / 110
+ 10 0h:00m:01s -1.83ns 209 / 110
+ 11 0h:00m:01s -1.83ns 209 / 110
+ 12 0h:00m:01s -1.83ns 209 / 110
- 5 0h:00m:02s -1.97ns 220 / 109
+ 13 0h:00m:01s -1.83ns 208 / 110
+ 14 0h:00m:01s -1.83ns 209 / 110
+ 15 0h:00m:01s -1.83ns 209 / 110
+ 16 0h:00m:01s -1.83ns 209 / 110
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB)
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
-Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
+@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock RCLK with period 16.00ns
@N: MT615 |Found clock PHI2 with period 350.00ns
@@ -450,7 +471,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:39:43 2023
+# Timing report written on Thu Oct 19 23:50:54 2023
#
@@ -470,15 +491,15 @@ Performance Summary
*******************
-Worst slack in design: -2.605
+Worst slack in design: -1.828
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup
-RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup
+RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
-nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup
+nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -501,12 +522,12 @@ Starting Ending | constraint slack | constraint slack | constraint
---------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
-RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
+RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
-PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428
-nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605
+PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428
+nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693
===============================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -540,30 +561,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
-Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
-Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
-Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
+Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041
+Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041
+Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041
==========================================================================================
Ending Points with Worst Slack
******************************
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------
-wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-=========================================================================================
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------
+wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
+==============================================================================
@@ -579,7 +600,7 @@ Path information for path number 1:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -594,7 +615,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -607,7 +628,7 @@ Path information for path number 2:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -622,7 +643,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -635,7 +656,7 @@ Path information for path number 3:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -650,7 +671,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -663,7 +684,7 @@ Path information for path number 4:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -678,7 +699,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -691,7 +712,7 @@ Path information for path number 5:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -706,7 +727,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -729,13 +750,13 @@ Instance Reference Type Pin Net Time Slac
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
-IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
-IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
-IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
-InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
-FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
-FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
-FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
+FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100
+FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108
+FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132
+InitReady RCLK FD1S3AX Q InitReady 1.317 9.708
+FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845
+FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845
+FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877
==================================================================================
@@ -832,7 +853,7 @@ Path information for path number 3:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[0] / D
+ Ending point: RowA[1] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -841,10 +862,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[0] ORCALUT4 B In 0.000 1.256 r -
-RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
-RowAd_0[0] Net - - - - 1
-RowA[0] FD1S3AX D In 0.000 1.873 r -
+RowAd[1] ORCALUT4 B In 0.000 1.256 r -
+RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[1] Net - - - - 1
+RowA[1] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -860,7 +881,7 @@ Path information for path number 4:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[5] / D
+ Ending point: RowA[4] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -869,10 +890,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[5] ORCALUT4 B In 0.000 1.256 r -
-RowAd[5] ORCALUT4 Z Out 0.617 1.873 f -
-RowAd_0[5] Net - - - - 1
-RowA[5] FD1S3AX D In 0.000 1.873 f -
+RowAd[4] ORCALUT4 B In 0.000 1.256 r -
+RowAd[4] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[4] Net - - - - 1
+RowA[4] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -888,7 +909,7 @@ Path information for path number 5:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[8] / D
+ Ending point: RowA[2] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -897,10 +918,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[8] ORCALUT4 B In 0.000 1.256 r -
-RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
-RowAd_0[8] Net - - - - 1
-RowA[8] FD1S3AX D In 0.000 1.873 r -
+RowAd[2] ORCALUT4 B In 0.000 1.256 r -
+RowAd[2] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[2] Net - - - - 1
+RowA[2] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -915,29 +936,30 @@ Detailed Report for Clock: nCRAS
Starting Points with Worst Slack
********************************
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605
-CBR nCRAS FD1S3AX Q CBR 1.180 -1.797
-FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
-==============================================================================
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------
+CBR nCRAS FD1S3AX Q CBR 1.148 -1.693
+FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693
+CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661
+FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589
+================================================================================
Ending Points with Worst Slack
******************************
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------
-nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
-nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
-nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
-nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
-RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
-==========================================================================================
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------
+RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693
+nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693
+nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693
+nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693
+nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661
+========================================================================================
@@ -951,32 +973,29 @@ Path information for path number 1:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 3.694
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : -2.605
+ = Slack (non-critical) : -1.693
- Number of logic level(s): 3
- Starting point: CBR_fast / Q
+ Number of logic level(s): 2
+ Starting point: CBR / Q
Ending point: nRCAS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-CBR_fast FD1S3AX Q Out 0.972 0.972 r -
-CBR_fast Net - - - - 1
-CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r -
-CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
-nRCAS_0_sqmuxa_1 Net - - - - 2
-nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
-nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
-N_248_i_sx Net - - - - 1
-nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
-====================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+----------------------------------------------------------------------------------
+CBR FD1S3AX Q Out 1.148 1.148 r -
+CBR Net - - - - 4
+nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r -
+nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
+N_242_i_1 Net - - - - 1
+nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f -
+nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
+N_242_i Net - - - - 1
+nRCAS_0io OFS1P3BX D In 0.000 2.781 r -
+==================================================================================
Path information for path number 2:
@@ -985,29 +1004,29 @@ Path information for path number 2:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: CBR / Q
- Ending point: nRCS_0io / D
+ Starting point: FWEr / Q
+ Ending point: RCKEEN / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
- The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+ The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-CBR FD1S3AX Q Out 1.180 1.180 r -
-CBR Net - - - - 5
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
-N_590 Net - - - - 2
-nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
-nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_247_i Net - - - - 1
-nRCS_0io OFS1P3BX D In 0.000 2.885 r -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r -
+RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r -
+RCKEEN_8_u_1 Net - - - - 1
+RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r -
+RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r -
+RCKEEN_8 Net - - - - 1
+RCKEEN FD1S3AX D In 0.000 2.781 r -
+=================================================================================
Path information for path number 3:
@@ -1016,29 +1035,29 @@ Path information for path number 3:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: FWEr / Q
- Ending point: nRCAS_0io / D
+ Starting point: CBR / Q
+ Ending point: nRowColSel / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
- The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+ The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-FWEr FD1S3AX Q Out 1.180 1.180 r -
-FWEr Net - - - - 5
-nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
-nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
-N_248_i_1_0 Net - - - - 2
-nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
-=================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR FD1S3AX Q Out 1.148 1.148 r -
+CBR Net - - - - 4
+nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r -
+nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f -
+N_255 Net - - - - 1
+nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f -
+nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f -
+nRowColSel_0_0 Net - - - - 1
+nRowColSel FD1S3IX D In 0.000 2.781 f -
+======================================================================================
Path information for path number 4:
@@ -1047,29 +1066,29 @@ Path information for path number 4:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: CBR / Q
- Ending point: nRWE_0io / D
+ Starting point: FWEr / Q
+ Ending point: nRCS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-CBR FD1S3AX Q Out 1.180 1.180 r -
-CBR Net - - - - 5
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
-N_590 Net - - - - 2
-nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
-nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_49_i Net - - - - 1
-nRWE_0io OFS1P3BX D In 0.000 2.885 r -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r -
+nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
+nRCS_0io_RNO_0 Net - - - - 1
+nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f -
+nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
+N_28_i Net - - - - 1
+nRCS_0io OFS1P3BX D In 0.000 2.781 r -
+=================================================================================
Path information for path number 5:
@@ -1078,9 +1097,9 @@ Path information for path number 5:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
@@ -1088,19 +1107,19 @@ Path information for path number 5:
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr FD1S3AX Q Out 1.180 1.180 r -
-FWEr Net - - - - 5
-nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
-nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
-N_248_i_1_1 Net - - - - 2
-nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+----------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r -
+nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r -
+N_242_i_1 Net - - - - 1
+nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r -
+nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f -
+N_242_i Net - - - - 1
+nRCAS_0io OFS1P3BX D In 0.000 2.781 f -
+==================================================================================
@@ -1133,7 +1152,7 @@ Instance Reference Type Pin Net Time Sla
-----------------------------------------------------------------------------------
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
-wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
+wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912
===================================================================================
@@ -1159,25 +1178,25 @@ Path information for path number 1:
The start point is clocked by System [rising]
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
-wb_ack Net - - - - 2
-ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r -
-ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r -
-g0_0_a3_2 Net - - - - 1
-ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r -
-ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r -
-N_4 Net - - - - 1
-CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
-CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
-CmdValid_RNIOOBE2 Net - - - - 2
-LEDENe ORCALUT4 B In 0.000 2.554 r -
-LEDENe ORCALUT4 Z Out 0.617 3.171 r -
-LEDENe_0 Net - - - - 1
-LEDEN FD1S3AX D In 0.000 3.171 r -
-==============================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+-----------------------------------------------------------------------------------------------------
+ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
+wb_ack Net - - - - 2
+ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r -
+ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r -
+g0_0_a3_1 Net - - - - 1
+wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r -
+wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r -
+N_4 Net - - - - 1
+CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r -
+CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r -
+CmdValid_RNITBH02 Net - - - - 2
+LEDENe ORCALUT4 B In 0.000 2.554 r -
+LEDENe ORCALUT4 Z Out 0.617 3.171 r -
+LEDENe_0 Net - - - - 1
+LEDEN FD1S3AX D In 0.000 3.171 r -
+=====================================================================================================
@@ -1185,18 +1204,18 @@ LEDEN FD1S3AX D In 0.000 3.171 r
Timing exceptions that could not be applied
-Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
-Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
-Register bits: 109 of 1280 (9%)
+Register bits: 110 of 1280 (9%)
PIC Latch: 0
-I/O cells: 63
+I/O cells: 64
Details:
@@ -1205,26 +1224,26 @@ CCU2D: 10
EFB: 1
FD1P3AX: 25
FD1P3IX: 2
-FD1S3AX: 53
+FD1S3AX: 54
FD1S3IX: 4
GSR: 1
IB: 25
IFS1P3DX: 9
INV: 7
-OB: 30
+OB: 31
+ODDRXE: 1
OFS1P3BX: 4
OFS1P3DX: 11
OFS1P3JX: 1
-ORCALUT4: 213
-PFUMX: 1
+ORCALUT4: 203
PUR: 1
VHI: 2
VLO: 2
Mapper successful!
-At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:39:43 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Thu Oct 19 23:50:54 2023
###########################################################]
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
index bd9feea..f7135e6 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:39:46 2023
+Thu Oct 19 23:50:57 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -42,42 +42,42 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
+Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
- Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
+ Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels.
Constraint Details:
- 9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
+ 8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
- 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
+ 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns
Physical Path Details:
- Data path Din[0]_MGIOL to SLICE_17:
+ Data path Din[0]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
-CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
-ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
-ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
-ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
-CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
-ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
-ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
+ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0]
+CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89
+ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75
+ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294
+CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75
+ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382
+CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73
+ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17
+CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10
+ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
- 9.223 (33.1% logic, 66.9% route), 6 logic levels.
+ 8.469 (36.0% logic, 64.0% route), 6 logic levels.
-Report: 53.254MHz is the maximum frequency for this preference.
+Report: 57.904MHz is the maximum frequency for this preference.
================================================================================
@@ -118,48 +118,48 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 6.049ns
+Passed: The following path meets requirements by 5.761ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q IS[1] (from RCLK_c +)
- Destination: FF Data in nRCAS_0io (to RCLK_c +)
+ Source: FF Q FS[11] (from RCLK_c +)
+ Destination: FF Data in wb_adr[0] (to RCLK_c +)
- Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
+ Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels.
Constraint Details:
- 9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
+ 10.073ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
- 0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns
Physical Path Details:
- Data path SLICE_27 to nRCAS_MGIOL:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
-ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
-CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
-ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
-CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
-ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
-CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
-ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
-CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
-ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
-CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
-ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
-CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
-ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
+REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c)
+ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11]
+CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66
+ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0]
+CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66
+ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0]
+CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86
+ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0]
+CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85
+ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0]
+CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
+ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0]
+CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48
+ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c)
--------
- 9.798 (34.9% logic, 65.1% route), 7 logic levels.
+ 10.073 (34.0% logic, 66.0% route), 7 logic levels.
-Report: 100.492MHz is the maximum frequency for this preference.
+Report: 97.666MHz is the maximum frequency for this preference.
Report Summary
--------------
@@ -167,13 +167,13 @@ Report Summary
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
-FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
+FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
-FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
+FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7
| | |
----------------------------------------------------------------------------
@@ -186,7 +186,7 @@ Clock Domains Analysis
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -198,7 +198,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -228,11 +228,11 @@ Timing summary (Setup):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
+Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:39:46 2023
+Thu Oct 19 23:50:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -284,7 +284,7 @@ Passed: The following path meets requirements by 0.447ns
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
-ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
@@ -303,7 +303,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@@ -357,7 +357,7 @@ Clock Domains Analysis
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -369,7 +369,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -399,7 +399,7 @@ Timing summary (Hold):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
+Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
index 8496830..2912982 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:40:03 2023
+Thu Oct 19 23:51:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -42,21 +42,21 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 160.229ns (weighted slack = 320.458ns)
+Passed: The following path meets requirements by 162.455ns (weighted slack = 324.910ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 11.846ns (25.8% logic, 74.2% route), 6 logic levels.
+ Delay: 9.620ns (31.7% logic, 68.3% route), 6 logic levels.
Constraint Details:
- 11.846ns physical path delay Din[0]_MGIOL to SLICE_17 meets
+ 9.620ns physical path delay Din[0]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 160.229ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.455ns
Physical Path Details:
@@ -65,18 +65,18 @@ Passed: The following path meets requirements by 160.229ns (weighted slack = 320
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 11.846 (25.8% logic, 74.2% route), 6 logic levels.
+ 9.620 (31.7% logic, 68.3% route), 6 logic levels.
Clock Skew Details:
@@ -90,287 +90,26 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 161.365ns (weighted slack = 322.730ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdUFMData (to PHI2_c -)
-
- Delay: 10.569ns (24.2% logic, 75.8% route), 5 logic levels.
-
- Constraint Details:
-
- 10.569ns physical path delay Din[0]_MGIOL to SLICE_82 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.307ns CE_SET requirement (totaling 171.934ns) by 161.365ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_82:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.718 R5C10A.F1 to R5C10C.B0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10C.B0 to R5C10C.F0 SLICE_82
-ROUTE 1 0.653 R5C10C.F0 to R5C10C.CE CmdUFMData_1_sqmuxa (to PHI2_c)
- --------
- 10.569 (24.2% logic, 75.8% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_82:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.468ns (weighted slack = 322.936ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[2] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.607ns (28.8% logic, 71.2% route), 6 logic levels.
-
- Constraint Details:
-
- 10.607ns physical path delay Din[2]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.468ns
-
- Physical Path Details:
-
- Data path Din[2]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c)
-ROUTE 1 1.512 IOL_T12A.IN to R4C11A.C0 Bank[2]
-CTOF_DEL --- 0.495 R4C11A.C0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.607 (28.8% logic, 71.2% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[2]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.870ns (weighted slack = 323.740ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdValid (to PHI2_c -)
-
- Delay: 10.205ns (25.1% logic, 74.9% route), 5 logic levels.
-
- Constraint Details:
-
- 10.205ns physical path delay Din[0]_MGIOL to SLICE_22 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.870ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_22:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 1.007 R5C10A.F1 to R5C10D.A0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10D.A0 to R5C10D.F0 SLICE_22
-ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 CmdValid_r (to PHI2_c)
- --------
- 10.205 (25.1% logic, 74.9% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_22:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10D.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.985ns (weighted slack = 323.970ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[1] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.090ns (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
- 10.090ns physical path delay Din[1]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.985ns
-
- Physical Path Details:
-
- Data path Din[1]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c)
-ROUTE 1 1.601 IOL_T10B.IN to R2C10A.A1 Bank[1]
-CTOF_DEL --- 0.495 R2C10A.A1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.090 (30.2% logic, 69.8% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[1]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.032ns (weighted slack = 324.064ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[5] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.043ns (30.4% logic, 69.6% route), 6 logic levels.
-
- Constraint Details:
-
- 10.043ns physical path delay Din[5]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.032ns
-
- Physical Path Details:
-
- Data path Din[5]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c)
-ROUTE 1 1.554 IOL_T9B.IN to R2C10A.B1 Bank[5]
-CTOF_DEL --- 0.495 R2C10A.B1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.043 (30.4% logic, 69.6% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[5]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns)
+Passed: The following path meets requirements by 162.715ns (weighted slack = 325.430ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
- Delay: 9.978ns (25.6% logic, 74.4% route), 5 logic levels.
+ Delay: 9.360ns (32.6% logic, 67.4% route), 6 logic levels.
Constraint Details:
- 9.978ns physical path delay Din[0]_MGIOL to SLICE_10 meets
+ 9.360ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.097ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.715ns
Physical Path Details:
@@ -379,16 +118,18 @@ Passed: The following path meets requirements by 162.097ns (weighted slack = 324
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 0.987 R5C12C.F1 to R5C13B.A0 CmdEnable16
-CTOF_DEL --- 0.495 R5C13B.A0 to R5C13B.F0 SLICE_10
-ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17
+CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
- 9.978 (25.6% logic, 74.4% route), 5 logic levels.
+ 9.360 (32.6% logic, 67.4% route), 6 logic levels.
Clock Skew Details:
@@ -402,130 +143,132 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13B.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 162.159ns (weighted slack = 324.318ns)
+Passed: The following path meets requirements by 162.913ns (weighted slack = 325.826ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdValid_fast (to PHI2_c -)
-
- Delay: 9.916ns (25.8% logic, 74.2% route), 5 logic levels.
-
- Constraint Details:
-
- 9.916ns physical path delay Din[0]_MGIOL to SLICE_23 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.159ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_23:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.718 R5C10A.F1 to R5C10A.B0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10A.B0 to R5C10A.F0 SLICE_23
-ROUTE 1 0.000 R5C10A.F0 to R5C10A.DI0 N_36_fast (to PHI2_c)
- --------
- 9.916 (25.8% logic, 74.2% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_23:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10A.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.410ns (weighted slack = 324.820ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[4] (from PHI2_c +)
+ Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 9.665ns (31.6% logic, 68.4% route), 6 logic levels.
+ Delay: 9.162ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
- 9.665ns physical path delay Din[4]_MGIOL to SLICE_17 meets
+ 9.162ns physical path delay Din[7]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.410ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.913ns
Physical Path Details:
- Data path Din[4]_MGIOL to SLICE_17:
+ Data path Din[7]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE 1 1.176 IOL_T9A.IN to R2C10A.D1 Bank[4]
-CTOF_DEL --- 0.495 R2C10A.D1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
+ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7]
+CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 9.665 (31.6% logic, 68.4% route), 6 logic levels.
+ 9.162 (33.3% logic, 66.7% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path PHI2 to Din[4]_MGIOL:
+ Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T9A.CLK PHI2_c
+ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 162.515ns (weighted slack = 325.030ns)
+Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[7] (from PHI2_c +)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
+
+ Delay: 8.902ns (34.3% logic, 65.7% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.902ns physical path delay Din[7]_MGIOL to SLICE_10 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.173ns
+
+ Physical Path Details:
+
+ Data path Din[7]_MGIOL to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
+ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7]
+CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17
+CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
+ --------
+ 8.902 (34.3% logic, 65.7% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[7]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
- Delay: 9.419ns (21.9% logic, 78.1% route), 4 logic levels.
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
Constraint Details:
- 9.419ns physical path delay Din[0]_MGIOL to SLICE_18 meets
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
- 0.307ns CE_SET requirement (totaling 171.934ns) by 162.515ns
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
Physical Path Details:
@@ -534,14 +277,14 @@ Passed: The following path meets requirements by 162.515ns (weighted slack = 325
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.716 R5C10A.F1 to R5C9B.CE XOR8MEG18 (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R3C10B.CE XOR8MEG18 (to PHI2_c)
--------
- 9.419 (21.9% logic, 78.1% route), 4 logic levels.
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
Clock Skew Details:
@@ -555,11 +298,262 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R3C10B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Report: 41.034MHz is the maximum frequency for this preference.
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in CmdUFMShift (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_20 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_20:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R4C10B.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_20:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R4C10B.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in CmdUFMWrite (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_21 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R4C10D.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_24 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R3C10C.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.326ns (weighted slack = 326.652ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[6] (from PHI2_c +)
+ Destination: FF Data in CmdEnable (to PHI2_c -)
+
+ Delay: 8.749ns (34.9% logic, 65.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.749ns physical path delay Din[6]_MGIOL to SLICE_17 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.326ns
+
+ Physical Path Details:
+
+ Data path Din[6]_MGIOL to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE 1 1.802 IOL_L2D.IN to R3C9D.D0 Bank[6]
+CTOF_DEL --- 0.495 R3C9D.D0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
+ --------
+ 8.749 (34.9% logic, 65.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[6]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.343ns (weighted slack = 326.686ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
+
+ Delay: 8.732ns (29.3% logic, 70.7% route), 5 logic levels.
+
+ Constraint Details:
+
+ 8.732ns physical path delay Din[0]_MGIOL to SLICE_10 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.343ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.456 R4C10A.F1 to R5C12C.A1 N_294
+CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_10
+ROUTE 1 0.967 R5C12C.F1 to R5C12C.A0 N_22_i
+CTOF_DEL --- 0.495 R5C12C.A0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
+ --------
+ 8.732 (29.3% logic, 70.7% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+Report: 50.206MHz is the maximum frequency for this preference.
================================================================================
@@ -600,540 +594,528 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 5.578ns
+Passed: The following path meets requirements by 5.798ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels.
+ Delay: 10.036ns (24.2% logic, 75.8% route), 5 logic levels.
Constraint Details:
- 10.256ns physical path delay SLICE_2 to SLICE_54 meets
+ 10.036ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.798ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 2.663 R5C5C.Q1 to R2C7A.A1 FS[12]
+CTOF_DEL --- 0.495 R2C7A.A1 to R2C7A.F1 SLICE_101
+ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142
+CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 10.256 (30.7% logic, 69.3% route), 6 logic levels.
+ 10.036 (24.2% logic, 75.8% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.578ns
+Passed: The following path meets requirements by 6.138ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
+ Destination: FF Data in n8MEGEN (to RCLK_c +)
- Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels.
+ Delay: 9.523ns (76.3% logic, 23.7% route), 3 logic levels.
Constraint Details:
- 10.256ns physical path delay SLICE_2 to SLICE_54 meets
+ 9.523ns physical path delay ufmefb/EFBInst_0 to SLICE_46 meets
16.000ns delay constraint less
- 0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.138ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path ufmefb/EFBInst_0 to SLICE_46:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
+ROUTE 1 1.297 EFB.WBDATO0 to R3C5B.C1 wb_dato[0]
+CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_108
+ROUTE 1 0.958 R3C5B.F1 to R3C8B.D0 n8MEGENe_1_0
+CTOF_DEL --- 0.495 R3C8B.D0 to R3C8B.F0 SLICE_46
+ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n8MEGENe_0 (to RCLK_c)
--------
- 10.256 (30.7% logic, 69.3% route), 6 logic levels.
+ 9.523 (76.3% logic, 23.7% route), 3 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c
--------
- 2.264 (0.0% logic, 100.0% route), 0 logic levels.
+ 2.437 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_46:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C8B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.743ns
+Passed: The following path meets requirements by 6.414ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[4] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_adr[0] (to RCLK_c +)
- Delay: 10.091ns (29.0% logic, 71.0% route), 6 logic levels.
+ Delay: 9.420ns (36.3% logic, 63.7% route), 7 logic levels.
Constraint Details:
- 10.091ns physical path delay SLICE_2 to SLICE_54 meets
+ 9.420ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.743ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.414ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473
-CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86
-ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4]
-CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54
-ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 2.237 R5C5C.Q1 to R2C7D.A1 FS[12]
+CTOF_DEL --- 0.495 R2C7D.A1 to R2C7D.F1 SLICE_66
+ROUTE 1 0.436 R2C7D.F1 to R2C7D.C0 wb_adr_5_i_i_a2_3_0[0]
+CTOF_DEL --- 0.495 R2C7D.C0 to R2C7D.F0 SLICE_66
+ROUTE 1 0.967 R2C7D.F0 to R2C7B.A0 wb_adr_5_i_i_1_0_tz_0[0]
+CTOF_DEL --- 0.495 R2C7B.A0 to R2C7B.F0 SLICE_86
+ROUTE 1 1.001 R2C7B.F0 to R2C6A.B0 wb_adr_5_i_i_1_0[0]
+CTOF_DEL --- 0.495 R2C6A.B0 to R2C6A.F0 SLICE_85
+ROUTE 1 1.042 R2C6A.F0 to R4C6D.D0 wb_adr_5_i_i_1[0]
+CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_77
+ROUTE 1 0.315 R4C6D.F0 to R4C6C.D0 wb_adr_5_i_i_5[0]
+CTOF_DEL --- 0.495 R4C6C.D0 to R4C6C.F0 SLICE_48
+ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 N_283 (to RCLK_c)
--------
- 10.091 (29.0% logic, 71.0% route), 6 logic levels.
+ 9.420 (36.3% logic, 63.7% route), 7 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.835ns
+Passed: The following path meets requirements by 6.769ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[9] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels.
+ Delay: 9.065ns (32.3% logic, 67.7% route), 6 logic levels.
Constraint Details:
- 9.999ns physical path delay SLICE_1 to SLICE_54 meets
+ 9.065ns physical path delay SLICE_5 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.769ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_5 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q0 SLICE_5 (from RCLK_c)
+ROUTE 14 1.803 R5C5B.Q0 to R3C6D.B1 FS[9]
+CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_80
+ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125
+CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.999 (31.5% logic, 68.5% route), 6 logic levels.
+ 9.065 (32.3% logic, 67.7% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.835ns
+Passed: The following path meets requirements by 7.019ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[13] (from RCLK_c +)
+ Destination: FF Data in wb_dati[7] (to RCLK_c +)
- Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels.
+ Delay: 8.815ns (33.2% logic, 66.8% route), 6 logic levels.
Constraint Details:
- 9.999ns physical path delay SLICE_1 to SLICE_54 meets
+ 8.815ns physical path delay SLICE_3 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.019ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_3 to SLICE_56:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c)
+ROUTE 23 1.929 R5C5D.Q0 to R3C5D.A1 FS[13]
+CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 SLICE_70
+ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2
+CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70
+ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
+CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108
+ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7]
+CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69
+ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56
+ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
--------
- 9.999 (31.5% logic, 68.5% route), 6 logic levels.
+ 8.815 (33.2% logic, 66.8% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.851ns
+Passed: The following path meets requirements by 7.040ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[6] (to RCLK_c +)
+ Source: FF Q FS[13] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.983ns (29.3% logic, 70.7% route), 6 logic levels.
+ Delay: 8.794ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
- 9.983ns physical path delay SLICE_2 to SLICE_55 meets
+ 8.794ns physical path delay SLICE_3 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.851ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.040ns
Physical Path Details:
- Data path SLICE_2 to SLICE_55:
+ Data path SLICE_3 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 0.976 R3C4C.F1 to R3C4C.A0 N_473
-CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_85
-ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6]
-CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55
-ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c)
+REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c)
+ROUTE 23 3.158 R5C5D.Q0 to R4C7C.A0 FS[13]
+CTOF_DEL --- 0.495 R4C7C.A0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.983 (29.3% logic, 70.7% route), 6 logic levels.
+ 8.794 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_55:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.867ns
+Passed: The following path meets requirements by 7.108ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[6] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_dati[7] (to RCLK_c +)
- Delay: 9.967ns (29.4% logic, 70.6% route), 6 logic levels.
+ Delay: 8.726ns (33.5% logic, 66.5% route), 6 logic levels.
Constraint Details:
- 9.967ns physical path delay SLICE_2 to SLICE_55 meets
+ 8.726ns physical path delay SLICE_4 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.867ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.108ns
Physical Path Details:
- Data path SLICE_2 to SLICE_55:
+ Data path SLICE_4 to SLICE_56:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.559 R2C5D.F1 to R3C5A.B1 N_214
-CTOF_DEL --- 0.495 R3C5A.B1 to R3C5A.F1 SLICE_87
-ROUTE 4 1.323 R3C5A.F1 to R5C4B.A0 N_579
-CTOF_DEL --- 0.495 R5C4B.A0 to R5C4B.F0 SLICE_89
-ROUTE 1 1.023 R5C4B.F0 to R3C4C.B0 N_472
-CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_85
-ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6]
-CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55
-ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 1.840 R5C5C.Q1 to R3C5D.B1 FS[12]
+CTOF_DEL --- 0.495 R3C5D.B1 to R3C5D.F1 SLICE_70
+ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2
+CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70
+ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
+CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108
+ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7]
+CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69
+ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56
+ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
--------
- 9.967 (29.4% logic, 70.6% route), 6 logic levels.
+ 8.726 (33.5% logic, 66.5% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_55:
+ Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.956ns
+Passed: The following path meets requirements by 7.132ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[2] (to RCLK_c +)
+ Source: FF Q FS[10] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels.
+ Delay: 8.702ns (33.6% logic, 66.4% route), 6 logic levels.
Constraint Details:
- 9.878ns physical path delay SLICE_2 to SLICE_53 meets
+ 8.702ns physical path delay SLICE_5 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.132ns
Physical Path Details:
- Data path SLICE_2 to SLICE_53:
+ Data path SLICE_5 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361
-CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53
-ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c)
+REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q1 SLICE_5 (from RCLK_c)
+ROUTE 16 1.440 R5C5B.Q1 to R3C6D.A1 FS[10]
+CTOF_DEL --- 0.495 R3C6D.A1 to R3C6D.F1 SLICE_80
+ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125
+CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.878 (31.9% logic, 68.1% route), 6 logic levels.
+ 8.702 (33.6% logic, 66.4% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_53:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.956ns
+Passed: The following path meets requirements by 7.246ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[2] (to RCLK_c +)
+ Source: FF Q FS[11] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels.
+ Delay: 8.588ns (28.3% logic, 71.7% route), 5 logic levels.
Constraint Details:
- 9.878ns physical path delay SLICE_2 to SLICE_53 meets
+ 8.588ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.246ns
Physical Path Details:
- Data path SLICE_2 to SLICE_53:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361
-CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53
-ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q0 SLICE_4 (from RCLK_c)
+ROUTE 21 1.215 R5C5C.Q0 to R2C7A.D1 FS[11]
+CTOF_DEL --- 0.495 R2C7A.D1 to R2C7A.F1 SLICE_101
+ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142
+CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.878 (31.9% logic, 68.1% route), 6 logic levels.
+ 8.588 (28.3% logic, 71.7% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_53:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 6.000ns
+Passed: The following path meets requirements by 7.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[4] (to RCLK_c +)
+ Source: FF Q InitReady (from RCLK_c +)
+ Destination: FF Data in nRWE_0io (to RCLK_c +)
- Delay: 9.834ns (29.8% logic, 70.2% route), 6 logic levels.
+ Delay: 8.771ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
- 9.834ns physical path delay SLICE_1 to SLICE_54 meets
+ 8.771ns physical path delay SLICE_30 to nRWE_MGIOL meets
16.000ns delay constraint less
- 0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.000ns
+ -0.173ns skew and
+ 0.153ns DO_SET requirement (totaling 16.020ns) by 7.249ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_30 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473
-CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86
-ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4]
-CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54
-ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c)
+REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_30 (from RCLK_c)
+ROUTE 31 1.714 R4C8D.Q0 to R7C15A.D1 InitReady
+CTOF_DEL --- 0.495 R7C15A.D1 to R7C15A.F1 SLICE_62
+ROUTE 6 1.032 R7C15A.F1 to R7C16A.B1 N_43
+CTOF_DEL --- 0.495 R7C16A.B1 to R7C16A.F1 SLICE_78
+ROUTE 2 0.775 R7C16A.F1 to R7C14B.C1 IS_0_sqmuxa_0_o2
+CTOF_DEL --- 0.495 R7C14B.C1 to R7C14B.F1 SLICE_68
+ROUTE 1 1.023 R7C14B.F1 to R8C14C.B1 nRWE_0io_RNO_0
+CTOF_DEL --- 0.495 R8C14C.B1 to R8C14C.F1 SLICE_92
+ROUTE 1 1.795 R8C14C.F1 to IOL_B20D.OPOS N_37_i (to RCLK_c)
--------
- 9.834 (29.8% logic, 70.2% route), 6 logic levels.
+ 8.771 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c
--------
- 2.264 (0.0% logic, 100.0% route), 0 logic levels.
+ 2.437 (0.0% logic, 100.0% route), 0 logic levels.
-Report: 95.951MHz is the maximum frequency for this preference.
+Report: 98.020MHz is the maximum frequency for this preference.
Report Summary
--------------
@@ -1141,13 +1123,13 @@ Report Summary
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
-FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 41.034 MHz| 6
+FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 50.206 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
-FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.951 MHz| 6
+FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 98.020 MHz| 5
| | |
----------------------------------------------------------------------------
@@ -1160,7 +1142,7 @@ Clock Domains Analysis
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -1172,7 +1154,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -1202,11 +1184,11 @@ Timing summary (Setup):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage)
+Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:40:03 2023
+Thu Oct 19 23:51:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -1235,6 +1217,51 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
--------------------------------------------------------------------------------
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q C1Submitted (from PHI2_c -)
+ Destination: FF Data in C1Submitted (to PHI2_c -)
+
+ Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.366ns physical path delay SLICE_11 to SLICE_11 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+ Data path SLICE_11 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C12A.CLK to R5C12A.Q0 SLICE_11 (from PHI2_c)
+ROUTE 2 0.132 R5C12A.Q0 to R5C12A.A0 C1Submitted
+CTOF_DEL --- 0.101 R5C12A.A0 to R5C12A.F0 SLICE_11
+ROUTE 1 0.000 R5C12A.F0 to R5C12A.DI0 C1Submitted_RNO (to PHI2_c)
+ --------
+ 0.366 (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
@@ -1256,10 +1283,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_20 (from PHI2_c)
-ROUTE 2 0.132 R5C9D.Q0 to R5C9D.A0 CmdUFMShift
-CTOF_DEL --- 0.101 R5C9D.A0 to R5C9D.F0 SLICE_20
-ROUTE 1 0.000 R5C9D.F0 to R5C9D.DI0 CmdUFMShift_3 (to PHI2_c)
+REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_20 (from PHI2_c)
+ROUTE 2 0.132 R4C10B.Q0 to R4C10B.A0 CmdUFMShift
+CTOF_DEL --- 0.101 R4C10B.A0 to R4C10B.F0 SLICE_20
+ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1268,14 +1295,14 @@ ROUTE 1 0.000 R5C9D.F0 to R5C9D.DI0 CmdUFMShift_3 (to PHI
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1301,10 +1328,10 @@ Passed: The following path meets requirements by 0.382ns
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c)
-ROUTE 2 0.135 R5C13B.Q0 to R5C13B.D0 ADSubmitted
-CTOF_DEL --- 0.101 R5C13B.D0 to R5C13B.F0 SLICE_10
-ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_10 (from PHI2_c)
+ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 ADSubmitted
+CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.369 (63.4% logic, 36.6% route), 2 logic levels.
@@ -1313,104 +1340,200 @@ ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.382ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q C1Submitted (from PHI2_c -)
- Destination: FF Data in C1Submitted (to PHI2_c -)
-
- Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels.
-
- Constraint Details:
-
- 0.369ns physical path delay SLICE_11 to SLICE_11 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.382ns
-
- Physical Path Details:
-
- Data path SLICE_11 to SLICE_11:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_11 (from PHI2_c)
-ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 C1Submitted
-CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_11
-ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 C1Submitted_RNO (to PHI2_c)
- --------
- 0.369 (63.4% logic, 36.6% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_11:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_11:
-
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 0.382ns
+Passed: The following path meets requirements by 0.387ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels.
+ Delay: 0.374ns (62.6% logic, 37.4% route), 2 logic levels.
Constraint Details:
- 0.369ns physical path delay SLICE_17 to SLICE_17 meets
+ 0.374ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.382ns
+ 0.000ns skew requirement (totaling -0.013ns) by 0.387ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c)
-ROUTE 2 0.135 R5C13C.Q0 to R5C13C.D0 CmdEnable
-CTOF_DEL --- 0.101 R5C13C.D0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.140 R5C11D.Q0 to R5C11D.D0 CmdEnable
+CTOF_DEL --- 0.101 R5C11D.D0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 0.369 (63.4% logic, 36.6% route), 2 logic levels.
+ 0.374 (62.6% logic, 37.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CmdUFMWrite (from PHI2_c -)
+ Destination: FF Data in CmdUFMWrite (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_21 to SLICE_21 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_21 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_21 (from PHI2_c)
+ROUTE 2 0.212 R4C10D.Q0 to R4C10D.A1 CmdUFMWrite
+CTOF_DEL --- 0.101 R4C10D.A1 to R4C10D.F1 SLICE_21
+ROUTE 1 0.056 R4C10D.F1 to R4C10D.C0 N_279
+CTOF_DEL --- 0.101 R4C10D.C0 to R4C10D.F0 SLICE_21
+ROUTE 1 0.000 R4C10D.F0 to R4C10D.DI0 CmdUFMWrite_3 (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Cmdn8MEGEN (from PHI2_c -)
+ Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_24 to SLICE_24 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_24 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_24 (from PHI2_c)
+ROUTE 2 0.212 R3C10C.Q0 to R3C10C.A1 Cmdn8MEGEN
+CTOF_DEL --- 0.101 R3C10C.A1 to R3C10C.F1 SLICE_24
+ROUTE 1 0.056 R3C10C.F1 to R3C10C.C0 Cmdn8MEGEN_4_u_i_0
+CTOF_DEL --- 0.101 R3C10C.C0 to R3C10C.F0 SLICE_24
+ROUTE 1 0.000 R3C10C.F0 to R3C10C.DI0 N_285_i (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q XOR8MEG (from PHI2_c -)
+ Destination: FF Data in XOR8MEG (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_45 to SLICE_45 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_45 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C10D.CLK to R5C10D.Q0 SLICE_45 (from PHI2_c)
+ROUTE 2 0.212 R5C10D.Q0 to R5C10D.A1 XOR8MEG
+CTOF_DEL --- 0.101 R5C10D.A1 to R5C10D.F1 SLICE_45
+ROUTE 1 0.056 R5C10D.F1 to R5C10D.C0 N_274
+CTOF_DEL --- 0.101 R5C10D.C0 to R5C10D.F0 SLICE_45
+ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 XOR8MEG_3 (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1436,12 +1559,12 @@ Passed: The following path meets requirements by 0.628ns
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_18 (from PHI2_c)
-ROUTE 2 0.224 R5C9B.Q0 to R5C9B.B1 CmdLEDEN
-CTOF_DEL --- 0.101 R5C9B.B1 to R5C9B.F1 SLICE_18
-ROUTE 1 0.056 R5C9B.F1 to R5C9B.C0 CmdLEDEN_4_u_i_0_0
-CTOF_DEL --- 0.101 R5C9B.C0 to R5C9B.F0 SLICE_18
-ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_40_i (to PHI2_c)
+REG_DEL --- 0.133 R3C10B.CLK to R3C10B.Q0 SLICE_18 (from PHI2_c)
+ROUTE 2 0.224 R3C10B.Q0 to R3C10B.B1 CmdLEDEN
+CTOF_DEL --- 0.101 R3C10B.B1 to R3C10B.F1 SLICE_18
+ROUTE 1 0.056 R3C10B.F1 to R3C10B.C0 CmdLEDEN_4_u_i_0
+CTOF_DEL --- 0.101 R3C10B.C0 to R3C10B.F0 SLICE_18
+ROUTE 1 0.000 R3C10B.F0 to R3C10B.DI0 N_284_i (to PHI2_c)
--------
0.615 (54.5% logic, 45.5% route), 3 logic levels.
@@ -1450,247 +1573,106 @@ ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_40_i (to PHI2_c)
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 0.628ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q XOR8MEG (from PHI2_c -)
- Destination: FF Data in XOR8MEG (to PHI2_c -)
-
- Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels.
-
- Constraint Details:
-
- 0.615ns physical path delay SLICE_44 to SLICE_44 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.628ns
-
- Physical Path Details:
-
- Data path SLICE_44 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_44 (from PHI2_c)
-ROUTE 2 0.224 R5C10B.Q0 to R5C10B.B1 XOR8MEG
-CTOF_DEL --- 0.101 R5C10B.B1 to R5C10B.F1 SLICE_44
-ROUTE 1 0.056 R5C10B.F1 to R5C10B.C0 N_441
-CTOF_DEL --- 0.101 R5C10B.C0 to R5C10B.F0 SLICE_44
-ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 XOR8MEG_3 (to PHI2_c)
- --------
- 0.615 (54.5% logic, 45.5% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.693ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Cmdn8MEGEN (from PHI2_c -)
- Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
-
- Delay: 0.680ns (49.3% logic, 50.7% route), 3 logic levels.
-
- Constraint Details:
-
- 0.680ns physical path delay SLICE_24 to SLICE_24 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.693ns
-
- Physical Path Details:
-
- Data path SLICE_24 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_24 (from PHI2_c)
-ROUTE 2 0.135 R5C9C.Q0 to R5C9C.D1 Cmdn8MEGEN
-CTOF_DEL --- 0.101 R5C9C.D1 to R5C9C.F1 SLICE_24
-ROUTE 1 0.210 R5C9C.F1 to R5C9C.A0 Cmdn8MEGEN_4_u_i_0_0
-CTOF_DEL --- 0.101 R5C9C.A0 to R5C9C.F0 SLICE_24
-ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 N_38_i (to PHI2_c)
- --------
- 0.680 (49.3% logic, 50.7% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.702ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q CmdUFMWrite (from PHI2_c -)
- Destination: FF Data in CmdUFMWrite (to PHI2_c -)
-
- Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels.
-
- Constraint Details:
-
- 0.689ns physical path delay SLICE_21 to SLICE_21 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.702ns
-
- Physical Path Details:
-
- Data path SLICE_21 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_21 (from PHI2_c)
-ROUTE 2 0.212 R5C9A.Q0 to R5C9A.A1 CmdUFMWrite
-CTOF_DEL --- 0.101 R5C9A.A1 to R5C9A.F1 SLICE_21
-ROUTE 1 0.142 R5C9A.F1 to R5C9A.B0 N_462
-CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_21
-ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 CmdUFMWrite_3 (to PHI2_c)
- --------
- 0.689 (48.6% logic, 51.4% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.710ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q ADSubmitted (from PHI2_c -)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 0.697ns (48.1% logic, 51.9% route), 3 logic levels.
-
- Constraint Details:
-
- 0.697ns physical path delay SLICE_10 to SLICE_17 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.710ns
-
- Physical Path Details:
-
- Data path SLICE_10 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c)
-ROUTE 2 0.139 R5C13B.Q0 to R5C14C.C0 ADSubmitted
-CTOF_DEL --- 0.101 R5C14C.C0 to R5C14C.F0 SLICE_33
-ROUTE 1 0.223 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.101 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 0.697 (48.1% logic, 51.9% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_10:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.723ns
+Passed: The following path meets requirements by 0.632ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
- Destination: FF Data in XOR8MEG (to PHI2_c -)
+ Destination: FF Data in CmdValid_fast (to PHI2_c -)
- Delay: 0.695ns (33.7% logic, 66.3% route), 2 logic levels.
+ Delay: 0.619ns (54.1% logic, 45.9% route), 3 logic levels.
Constraint Details:
- 0.695ns physical path delay SLICE_17 to SLICE_44 meets
- -0.028ns CE_HLD and
+ 0.619ns physical path delay SLICE_17 to SLICE_23 meets
+ -0.013ns DIN_HLD and
0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.028ns) by 0.723ns
+ 0.000ns skew requirement (totaling -0.013ns) by 0.632ns
Physical Path Details:
- Data path SLICE_17 to SLICE_44:
+ Data path SLICE_17 to SLICE_23:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c)
-ROUTE 2 0.309 R5C13C.Q0 to R5C10A.B1 CmdEnable
-CTOF_DEL --- 0.101 R5C10A.B1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.152 R5C10A.F1 to R5C10B.CE XOR8MEG18 (to PHI2_c)
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.226 R5C11D.Q0 to R4C10C.C1 CmdEnable
+CTOF_DEL --- 0.101 R4C10C.C1 to R4C10C.F1 SLICE_23
+ROUTE 2 0.058 R4C10C.F1 to R4C10C.C0 XOR8MEG18_i
+CTOF_DEL --- 0.101 R4C10C.C0 to R4C10C.F0 SLICE_23
+ROUTE 1 0.000 R4C10C.F0 to R4C10C.DI0 N_36_fast (to PHI2_c)
--------
- 0.695 (33.7% logic, 66.3% route), 2 logic levels.
+ 0.619 (54.1% logic, 45.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path PHI2 to SLICE_44:
+ Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.661ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CmdEnable (from PHI2_c -)
+ Destination: FF Data in XOR8MEG (to PHI2_c -)
+
+ Delay: 0.633ns (37.0% logic, 63.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.633ns physical path delay SLICE_17 to SLICE_45 meets
+ -0.028ns CE_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.028ns) by 0.661ns
+
+ Physical Path Details:
+
+ Data path SLICE_17 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.140 R5C11D.Q0 to R5C11C.D1 CmdEnable
+CTOF_DEL --- 0.101 R5C11C.D1 to R5C11C.F1 SLICE_106
+ROUTE 5 0.259 R5C11C.F1 to R5C10D.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 0.633 (37.0% logic, 63.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1709,7 +1691,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@@ -1734,8 +1716,8 @@ Passed: The following path meets requirements by 0.304ns
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13D.CLK to R5C13D.Q0 SLICE_12 (from RCLK_c)
-ROUTE 1 0.152 R5C13D.Q0 to R5C13D.M1 CASr (to RCLK_c)
+REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q0 SLICE_12 (from RCLK_c)
+ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
@@ -1744,14 +1726,57 @@ ROUTE 1 0.152 R5C13D.Q0 to R5C13D.M1 CASr (to RCLK_c)
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CASr2 (from RCLK_c +)
+ Destination: FF Data in CASr3 (to RCLK_c +)
+
+ Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.287ns physical path delay SLICE_12 to SLICE_76 meets
+ -0.019ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+ Data path SLICE_12 to SLICE_76:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q1 SLICE_12 (from RCLK_c)
+ROUTE 4 0.154 R5C12B.Q1 to R5C12D.M0 CASr2 (to RCLK_c)
+ --------
+ 0.287 (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path RCLK to SLICE_12:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path RCLK to SLICE_76:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R5C12D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1767,34 +1792,34 @@ Passed: The following path meets requirements by 0.306ns
Constraint Details:
- 0.287ns physical path delay SLICE_32 to SLICE_32 meets
+ 0.287ns physical path delay SLICE_33 to SLICE_33 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
- Data path SLICE_32 to SLICE_32:
+ Data path SLICE_33 to SLICE_33:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C14C.CLK to R7C14C.Q0 SLICE_32 (from RCLK_c)
-ROUTE 2 0.154 R7C14C.Q0 to R7C14C.M1 RASr (to RCLK_c)
+REG_DEL --- 0.133 R7C10D.CLK to R7C10D.Q0 SLICE_33 (from RCLK_c)
+ROUTE 2 0.154 R7C10D.Q0 to R7C10D.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_32:
+ Source Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_32:
+ Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1810,38 +1835,81 @@ Passed: The following path meets requirements by 0.311ns
Constraint Details:
- 0.292ns physical path delay SLICE_31 to SLICE_31 meets
+ 0.292ns physical path delay SLICE_32 to SLICE_32 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.311ns
Physical Path Details:
- Data path SLICE_31 to SLICE_31:
+ Data path SLICE_32 to SLICE_32:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R4C8A.CLK to R4C8A.Q0 SLICE_31 (from RCLK_c)
-ROUTE 5 0.159 R4C8A.Q0 to R4C8A.M1 PHI2r2 (to RCLK_c)
+REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_32 (from RCLK_c)
+ROUTE 5 0.159 R3C9D.Q0 to R3C9D.M1 PHI2r2 (to RCLK_c)
--------
0.292 (45.5% logic, 54.5% route), 1 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_31:
+ Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_31:
+ Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
+Passed: The following path meets requirements by 0.347ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q wb_dati[3] (from RCLK_c +)
+ Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
+
+ Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.306ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets
+ -0.095ns WBDATI_HLD and
+ 0.000ns delay constraint less
+ -0.054ns skew requirement (totaling -0.041ns) by 0.347ns
+
+ Physical Path Details:
+
+ Data path SLICE_54 to ufmefb/EFBInst_0:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R2C6D.CLK to R2C6D.Q1 SLICE_54 (from RCLK_c)
+ROUTE 2 0.173 R2C6D.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c)
+ --------
+ 0.306 (43.5% logic, 56.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path RCLK to SLICE_54:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R2C6D.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.842 63.PADDI to EFB.WBCLKI RCLK_c
+ --------
+ 0.842 (0.0% logic, 100.0% route), 0 logic levels.
+
+
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
@@ -1863,10 +1931,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C6A.CLK to R7C6A.Q1 SLICE_0 (from RCLK_c)
-ROUTE 3 0.132 R7C6A.Q1 to R7C6A.A1 FS[0]
-CTOF_DEL --- 0.101 R7C6A.A1 to R7C6A.F1 SLICE_0
-ROUTE 1 0.000 R7C6A.F1 to R7C6A.DI1 FS_s[0] (to RCLK_c)
+REG_DEL --- 0.133 R5C4A.CLK to R5C4A.Q1 SLICE_0 (from RCLK_c)
+ROUTE 3 0.132 R5C4A.Q1 to R5C4A.A1 FS[0]
+CTOF_DEL --- 0.101 R5C4A.A1 to R5C4A.F1 SLICE_0
+ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1875,14 +1943,14 @@ ROUTE 1 0.000 R7C6A.F1 to R7C6A.DI1 FS_s[0] (to RCLK_c)
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1908,10 +1976,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 0.132 R7C8B.Q0 to R7C8B.A0 FS[17]
-CTOF_DEL --- 0.101 R7C8B.A0 to R7C8B.F0 SLICE_1
-ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 FS_s[17] (to RCLK_c)
+REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_1 (from RCLK_c)
+ROUTE 5 0.132 R5C6B.Q0 to R5C6B.A0 FS[17]
+CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_1
+ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1920,14 +1988,14 @@ ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 FS_s[17] (to RCLK_c)
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1953,10 +2021,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q0 SLICE_2 (from RCLK_c)
-ROUTE 9 0.132 R7C8A.Q0 to R7C8A.A0 FS[15]
-CTOF_DEL --- 0.101 R7C8A.A0 to R7C8A.F0 SLICE_2
-ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 FS_s[15] (to RCLK_c)
+REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_2 (from RCLK_c)
+ROUTE 4 0.132 R5C6A.Q0 to R5C6A.A0 FS[15]
+CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_2
+ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1965,14 +2033,14 @@ ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 FS_s[15] (to RCLK_c)
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1998,10 +2066,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 0.132 R7C8A.Q1 to R7C8A.A1 FS[16]
-CTOF_DEL --- 0.101 R7C8A.A1 to R7C8A.F1 SLICE_2
-ROUTE 1 0.000 R7C8A.F1 to R7C8A.DI1 FS_s[16] (to RCLK_c)
+REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q1 SLICE_2 (from RCLK_c)
+ROUTE 5 0.132 R5C6A.Q1 to R5C6A.A1 FS[16]
+CTOF_DEL --- 0.101 R5C6A.A1 to R5C6A.F1 SLICE_2
+ROUTE 1 0.000 R5C6A.F1 to R5C6A.DI1 FS_s[16] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -2010,104 +2078,14 @@ ROUTE 1 0.000 R7C8A.F1 to R7C8A.DI1 FS_s[16] (to RCLK_c)
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q FS[14] (from RCLK_c +)
- Destination: FF Data in FS[14] (to RCLK_c +)
-
- Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
- 0.366ns physical path delay SLICE_3 to SLICE_3 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
- Data path SLICE_3 to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q1 SLICE_3 (from RCLK_c)
-ROUTE 18 0.132 R7C7D.Q1 to R7C7D.A1 FS[14]
-CTOF_DEL --- 0.101 R7C7D.A1 to R7C7D.F1 SLICE_3
-ROUTE 1 0.000 R7C7D.F1 to R7C7D.DI1 FS_s[14] (to RCLK_c)
- --------
- 0.366 (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q FS[13] (from RCLK_c +)
- Destination: FF Data in FS[13] (to RCLK_c +)
-
- Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
- 0.366ns physical path delay SLICE_3 to SLICE_3 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
- Data path SLICE_3 to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q0 SLICE_3 (from RCLK_c)
-ROUTE 22 0.132 R7C7D.Q0 to R7C7D.A0 FS[13]
-CTOF_DEL --- 0.101 R7C7D.A0 to R7C7D.F0 SLICE_3
-ROUTE 1 0.000 R7C7D.F0 to R7C7D.DI0 FS_s[13] (to RCLK_c)
- --------
- 0.366 (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -2133,10 +2111,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7C.CLK to R7C7C.Q1 SLICE_4 (from RCLK_c)
-ROUTE 21 0.132 R7C7C.Q1 to R7C7C.A1 FS[12]
-CTOF_DEL --- 0.101 R7C7C.A1 to R7C7C.F1 SLICE_4
-ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 FS_s[12] (to RCLK_c)
+REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 0.132 R5C5C.Q1 to R5C5C.A1 FS[12]
+CTOF_DEL --- 0.101 R5C5C.A1 to R5C5C.F1 SLICE_4
+ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 FS_s[12] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -2145,14 +2123,14 @@ ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 FS_s[12] (to RCLK_c)
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -2181,7 +2159,7 @@ Clock Domains Analysis
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -2193,7 +2171,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -2223,7 +2201,7 @@ Timing summary (Hold):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage)
+Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
index af730a2..965acf4 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
@@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
-Thu Sep 21 05:40:13 2023
+Thu Oct 19 23:51:23 2023
-Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2GS
@@ -80,10 +80,20 @@ Creating bit map...
Bitstream Status: Final Version 1.95.
-Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.bit".
-Total CPU Time: 4 secs
+Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
+
+===========
+UFM Summary.
+===========
+UFM Size: 511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+
+Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
+Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
+
+Total CPU Time: 3 secs
Total REAL Time: 4 secs
-Peak Memory Usage: 274 MB
+Peak Memory Usage: 275 MB
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt
index 5dcf9c3..31621ea 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
-# Written on Thu Sep 21 05:39:38 2023
+# Written on Thu Oct 19 23:50:50 2023
##### DESIGN INFO #######################################################
@@ -103,6 +103,7 @@ p:RA[11]
p:RBA[0]
p:RBA[1]
p:RCKE
+p:RCLKout
p:RDQMH
p:RDQML
p:RD[0] (bidir end point)
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
index 8c1a01d..6488645 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
@@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Sep 21 05:40:06 2023
+// Written on Thu Oct 19 23:51:14 2023
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
@@ -50,96 +50,99 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
-CROW[0] nCRAS F 2.913 4 -0.274 M
-CROW[1] nCRAS F 2.475 4 -0.161 M
-Din[0] PHI2 F 5.366 4 4.293 4
-Din[0] nCCAS F 1.448 4 -0.034 M
-Din[1] PHI2 F 4.971 4 4.173 4
-Din[1] nCCAS F 0.519 4 0.708 4
-Din[2] PHI2 F 5.192 4 4.173 4
-Din[2] nCCAS F 1.948 4 -0.142 M
-Din[3] PHI2 F 5.298 4 4.173 4
-Din[3] nCCAS F 1.974 4 -0.157 M
-Din[4] PHI2 F 4.281 4 4.173 4
-Din[4] nCCAS F 1.060 4 0.217 4
-Din[5] PHI2 F 5.059 4 4.173 4
-Din[5] nCCAS F 1.956 4 -0.150 M
-Din[6] PHI2 F 4.644 4 4.293 4
-Din[6] nCCAS F 2.886 4 -0.382 M
-Din[7] PHI2 F 5.316 4 4.293 4
-Din[7] nCCAS F 2.381 4 -0.244 M
-MAin[0] PHI2 F 4.362 4 1.145 4
-MAin[0] nCRAS F 1.189 4 0.362 4
-MAin[1] PHI2 F 4.386 4 0.999 4
-MAin[1] nCRAS F 1.884 4 -0.024 M
-MAin[2] PHI2 F 9.426 4 -0.750 M
-MAin[2] nCRAS F 1.136 4 0.453 4
-MAin[3] PHI2 F 10.458 4 -0.997 M
-MAin[3] nCRAS F 1.564 4 0.067 4
-MAin[4] PHI2 F 11.109 4 -1.209 M
-MAin[4] nCRAS F 1.390 4 0.207 4
-MAin[5] PHI2 F 9.884 4 -0.896 M
-MAin[5] nCRAS F 1.269 4 0.218 4
-MAin[6] PHI2 F 9.859 4 -0.845 M
-MAin[6] nCRAS F 0.889 4 0.653 4
-MAin[7] PHI2 F 10.678 4 -1.070 M
-MAin[7] nCRAS F 1.186 4 0.309 4
-MAin[8] nCRAS F 1.639 4 0.014 M
-MAin[9] nCRAS F 1.097 4 0.457 4
+CROW[0] nCRAS F 1.569 4 0.268 6
+CROW[1] nCRAS F 1.013 4 0.820 4
+Din[0] PHI2 F 5.478 4 4.293 4
+Din[0] nCCAS F 2.010 4 -0.119 M
+Din[1] PHI2 F 4.088 4 4.173 4
+Din[1] nCCAS F 0.601 4 0.796 4
+Din[2] PHI2 F 4.967 4 4.173 4
+Din[2] nCCAS F 0.811 4 0.583 4
+Din[3] PHI2 F 3.810 4 4.173 4
+Din[3] nCCAS F 1.136 4 0.322 4
+Din[4] PHI2 F 4.400 4 4.173 4
+Din[4] nCCAS F 0.762 4 0.590 4
+Din[5] PHI2 F 5.595 4 4.173 4
+Din[5] nCCAS F 0.779 4 0.576 4
+Din[6] PHI2 F 5.120 4 4.293 4
+Din[6] nCCAS F 2.036 4 -0.117 M
+Din[7] PHI2 F 5.630 4 4.293 4
+Din[7] nCCAS F 2.301 4 -0.192 M
+MAin[0] PHI2 F 4.196 4 1.086 4
+MAin[0] nCRAS F 0.152 6 1.567 4
+MAin[1] PHI2 F 3.875 4 1.164 4
+MAin[1] nCRAS F -0.177 M 2.102 4
+MAin[2] PHI2 F 8.381 4 -0.693 M
+MAin[2] nCRAS F -0.315 M 2.358 4
+MAin[3] PHI2 F 7.199 4 -0.405 M
+MAin[3] nCRAS F -0.173 M 1.962 4
+MAin[4] PHI2 F 8.710 4 -0.769 M
+MAin[4] nCRAS F 0.292 4 1.419 4
+MAin[5] PHI2 F 8.562 4 -0.730 M
+MAin[5] nCRAS F -0.055 M 1.752 4
+MAin[6] PHI2 F 7.862 4 -0.604 M
+MAin[6] nCRAS F -0.126 M 1.965 4
+MAin[7] PHI2 F 8.829 4 -0.836 M
+MAin[7] nCRAS F -0.122 M 1.960 4
+MAin[8] nCRAS F -0.288 M 2.424 4
+MAin[9] nCRAS F -0.212 M 2.196 4
PHI2 RCLK R -0.133 M 2.360 4
-nCCAS RCLK R 2.943 4 -0.337 M
-nCCAS nCRAS F 2.967 4 -0.214 M
-nCRAS RCLK R 3.047 4 -0.402 M
-nFWE PHI2 F 11.116 4 -1.189 M
-nFWE nCRAS F 1.394 4 0.225 4
+nCCAS RCLK R 3.627 4 -0.577 M
+nCCAS nCRAS F 3.154 4 -0.145 M
+nCRAS RCLK R 1.461 4 -0.017 M
+nFWE PHI2 F 6.933 4 -0.318 M
+nFWE nCRAS F 0.403 4 1.860 4
// Clock to Output Delay
-Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
+Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
-LED RCLK R 11.046 4 3.298 M
-LED nCRAS F 11.710 4 3.359 M
-RA[0] RCLK R 11.397 4 3.516 M
-RA[0] nCRAS F 11.476 4 3.432 M
-RA[10] RCLK R 7.888 4 2.711 M
-RA[11] PHI2 R 9.755 4 3.200 M
-RA[1] RCLK R 11.272 4 3.469 M
-RA[1] nCRAS F 11.238 4 3.348 M
-RA[2] RCLK R 11.235 4 3.468 M
-RA[2] nCRAS F 11.665 4 3.453 M
-RA[3] RCLK R 11.390 4 3.512 M
-RA[3] nCRAS F 11.922 4 3.539 M
-RA[4] RCLK R 11.662 4 3.573 M
-RA[4] nCRAS F 11.818 4 3.505 M
-RA[5] RCLK R 11.744 4 3.584 M
-RA[5] nCRAS F 11.779 4 3.513 M
-RA[6] RCLK R 11.738 4 3.607 M
-RA[6] nCRAS F 11.836 4 3.531 M
-RA[7] RCLK R 12.475 4 3.797 M
-RA[7] nCRAS F 11.420 4 3.426 M
-RA[8] RCLK R 11.122 4 3.431 M
-RA[8] nCRAS F 11.667 4 3.471 M
-RA[9] RCLK R 11.935 4 3.649 M
-RA[9] nCRAS F 11.401 4 3.424 M
-RBA[0] nCRAS F 8.903 4 2.891 M
-RBA[1] nCRAS F 8.903 4 2.891 M
-RCKE RCLK R 10.011 4 3.215 M
-RDQMH RCLK R 10.790 4 3.354 M
-RDQML RCLK R 11.053 4 3.450 M
-RD[0] nCCAS F 8.977 4 3.012 M
-RD[1] nCCAS F 8.977 4 3.012 M
-RD[2] nCCAS F 8.977 4 3.012 M
-RD[3] nCCAS F 8.977 4 3.012 M
-RD[4] nCCAS F 8.977 4 3.012 M
-RD[5] nCCAS F 8.977 4 3.012 M
-RD[6] nCCAS F 8.977 4 3.012 M
-RD[7] nCCAS F 8.977 4 3.012 M
-nRCAS RCLK R 7.822 4 2.706 M
-nRCS RCLK R 7.822 4 2.706 M
-nRRAS RCLK R 7.822 4 2.706 M
-nRWE RCLK R 7.803 4 2.713 M
+LED RCLK R 10.948 4 3.270 M
+LED nCRAS F 12.507 4 3.690 M
+RA[0] RCLK R 13.208 4 4.000 M
+RA[0] nCRAS F 13.040 4 3.935 M
+RA[10] RCLK R 7.888 4 2.711 M
+RA[11] PHI2 R 9.755 4 3.200 M
+RA[1] RCLK R 13.332 4 4.024 M
+RA[1] nCRAS F 12.944 4 3.885 M
+RA[2] RCLK R 13.624 4 4.099 M
+RA[2] nCRAS F 13.220 4 3.993 M
+RA[3] RCLK R 13.506 4 4.055 M
+RA[3] nCRAS F 13.322 4 4.022 M
+RA[4] RCLK R 12.512 4 3.834 M
+RA[4] nCRAS F 14.534 4 4.331 M
+RA[5] RCLK R 13.530 4 4.069 M
+RA[5] nCRAS F 13.126 4 3.963 M
+RA[6] RCLK R 14.238 4 4.245 M
+RA[6] nCRAS F 13.589 4 4.077 M
+RA[7] RCLK R 13.759 4 4.129 M
+RA[7] nCRAS F 13.371 4 3.990 M
+RA[8] RCLK R 11.858 4 3.632 M
+RA[8] nCRAS F 13.338 4 4.026 M
+RA[9] RCLK R 11.007 4 3.423 M
+RA[9] nCRAS F 12.651 4 3.856 M
+RBA[0] nCRAS F 10.201 4 3.325 M
+RBA[1] nCRAS F 10.201 4 3.325 M
+RCKE RCLK R 9.754 4 3.167 M
+RCLKout RCLK R 7.971 4 2.504 M
+RDQMH RCLK R 11.153 4 3.458 M
+RDQML RCLK R 11.133 4 3.466 M
+RD[0] nCCAS F 9.354 4 3.132 M
+RD[1] nCCAS F 9.354 4 3.132 M
+RD[2] nCCAS F 9.354 4 3.132 M
+RD[3] nCCAS F 9.354 4 3.132 M
+RD[4] nCCAS F 9.354 4 3.132 M
+RD[5] nCCAS F 9.354 4 3.132 M
+RD[6] nCCAS F 9.354 4 3.132 M
+RD[7] nCCAS F 9.354 4 3.132 M
+nRCAS RCLK R 7.822 4 2.706 M
+nRCS RCLK R 7.822 4 2.706 M
+nRRAS RCLK R 7.822 4 2.706 M
+nRWE RCLK R 7.803 4 2.713 M
WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: 6
+WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
index 7e4d955..45d3fd0 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2GS")
- (DATE "Thu Sep 21 05:39:48 2023")
+ (DATE "Thu Oct 19 23:50:59 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")
@@ -324,6 +324,8 @@
(INSTANCE SLICE_16)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -390,11 +392,32 @@
(SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
)
)
+ (CELL
+ (CELLTYPE "SLICE_19")
+ (INSTANCE SLICE_19)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
+ )
+ )
(CELL
(CELLTYPE "SLICE_20")
(INSTANCE SLICE_20)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -533,6 +556,27 @@
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_27")
+ (INSTANCE SLICE_27)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
(TIMINGCHECK
(SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
)
@@ -542,8 +586,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_27")
- (INSTANCE SLICE_27)
+ (CELLTYPE "SLICE_28")
+ (INSTANCE SLICE_28)
(DELAY
(ABSOLUTE
(IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -566,10 +610,12 @@
)
)
(CELL
- (CELLTYPE "SLICE_28")
- (INSTANCE SLICE_28)
+ (CELLTYPE "SLICE_29")
+ (INSTANCE SLICE_29)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -588,8 +634,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_29")
- (INSTANCE SLICE_29)
+ (CELLTYPE "SLICE_30")
+ (INSTANCE SLICE_30)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -610,8 +656,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_30")
- (INSTANCE SLICE_30)
+ (CELLTYPE "SLICE_31")
+ (INSTANCE SLICE_31)
(DELAY
(ABSOLUTE
(IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -632,10 +678,15 @@
)
)
(CELL
- (CELLTYPE "SLICE_31")
- (INSTANCE SLICE_31)
+ (CELLTYPE "SLICE_32")
+ (INSTANCE SLICE_32)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -651,28 +702,6 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_32")
- (INSTANCE SLICE_32)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_33")
(INSTANCE SLICE_33)
@@ -681,13 +710,14 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
(TIMINGCHECK
- (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -711,7 +741,7 @@
)
)
(TIMINGCHECK
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -723,6 +753,8 @@
(INSTANCE SLICE_35)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -745,7 +777,6 @@
(INSTANCE SLICE_36)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -768,10 +799,11 @@
(INSTANCE SLICE_37)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -790,22 +822,22 @@
(INSTANCE SLICE_38)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
+ (TIMINGCHECK
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ )
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
(WIDTH (negedge CLK) (1250:1250:1250))
)
- (TIMINGCHECK
- (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
- )
)
(CELL
(CELLTYPE "SLICE_39")
@@ -898,6 +930,28 @@
(CELL
(CELLTYPE "SLICE_43")
(INSTANCE SLICE_43)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_44")
+ (INSTANCE SLICE_44)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -921,8 +975,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_44")
- (INSTANCE SLICE_44)
+ (CELLTYPE "SLICE_45")
+ (INSTANCE SLICE_45)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -946,8 +1000,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_45")
- (INSTANCE SLICE_45)
+ (CELLTYPE "SLICE_46")
+ (INSTANCE SLICE_46)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -969,10 +1023,12 @@
)
)
(CELL
- (CELLTYPE "SLICE_46")
- (INSTANCE SLICE_46)
+ (CELLTYPE "SLICE_47")
+ (INSTANCE SLICE_47)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -994,8 +1050,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_47")
- (INSTANCE SLICE_47)
+ (CELLTYPE "SLICE_48")
+ (INSTANCE SLICE_48)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1020,40 +1076,13 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_48")
- (INSTANCE SLICE_48)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_49")
(INSTANCE SLICE_49)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -1075,9 +1104,9 @@
(INSTANCE SLICE_50)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1098,6 +1127,30 @@
(CELL
(CELLTYPE "SLICE_51")
(INSTANCE SLICE_51)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_52")
+ (INSTANCE SLICE_52)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1124,8 +1177,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_52")
- (INSTANCE SLICE_52)
+ (CELLTYPE "SLICE_53")
+ (INSTANCE SLICE_53)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1150,37 +1203,12 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_53")
- (INSTANCE SLICE_53)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_54")
(INSTANCE SLICE_54)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1211,7 +1239,6 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1232,6 +1259,33 @@
(CELL
(CELLTYPE "SLICE_56")
(INSTANCE SLICE_56)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_57")
+ (INSTANCE SLICE_57)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1256,8 +1310,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_57")
- (INSTANCE SLICE_57)
+ (CELLTYPE "SLICE_58")
+ (INSTANCE SLICE_58)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1280,8 +1334,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_58")
- (INSTANCE SLICE_58)
+ (CELLTYPE "SLICE_59")
+ (INSTANCE SLICE_59)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1307,23 +1361,6 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "wb_dati_5_1_iv_0_o3_5__SLICE_59")
- (INSTANCE wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 OFX0 (457:589:721)(457:589:721))
- (IOPATH C1 OFX0 (457:589:721)(457:589:721))
- (IOPATH B1 OFX0 (457:589:721)(457:589:721))
- (IOPATH A1 OFX0 (457:589:721)(457:589:721))
- (IOPATH D0 OFX0 (457:589:721)(457:589:721))
- (IOPATH C0 OFX0 (457:589:721)(457:589:721))
- (IOPATH B0 OFX0 (457:589:721)(457:589:721))
- (IOPATH A0 OFX0 (457:589:721)(457:589:721))
- (IOPATH M0 OFX0 (322:349:376)(322:349:376))
- )
- )
- )
(CELL
(CELLTYPE "SLICE_60")
(INSTANCE SLICE_60)
@@ -1349,6 +1386,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1364,6 +1402,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1423,7 +1462,6 @@
(INSTANCE SLICE_66)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1454,6 +1492,7 @@
(INSTANCE SLICE_68)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1472,7 +1511,6 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1499,10 +1537,10 @@
(INSTANCE SLICE_71)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1518,6 +1556,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1537,112 +1576,6 @@
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_74")
- (INSTANCE SLICE_74)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_75")
- (INSTANCE SLICE_75)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_76")
- (INSTANCE SLICE_76)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_77")
- (INSTANCE SLICE_77)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_78")
- (INSTANCE SLICE_78)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_79")
- (INSTANCE SLICE_79)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_80")
- (INSTANCE SLICE_80)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
@@ -1656,11 +1589,122 @@
(SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
)
)
+ (CELL
+ (CELLTYPE "SLICE_74")
+ (INSTANCE SLICE_74)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_75")
+ (INSTANCE SLICE_75)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_76")
+ (INSTANCE SLICE_76)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_77")
+ (INSTANCE SLICE_77)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_78")
+ (INSTANCE SLICE_78)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_79")
+ (INSTANCE SLICE_79)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_80")
+ (INSTANCE SLICE_80)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
(CELL
(CELLTYPE "SLICE_81")
(INSTANCE SLICE_81)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1676,29 +1720,22 @@
(INSTANCE SLICE_82)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- (TIMINGCHECK
- (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
- (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
- )
)
(CELL
(CELLTYPE "SLICE_83")
(INSTANCE SLICE_83)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1713,8 +1750,6 @@
(INSTANCE SLICE_84)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1745,8 +1780,6 @@
(INSTANCE SLICE_86)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1761,7 +1794,6 @@
(INSTANCE SLICE_87)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1776,8 +1808,6 @@
(INSTANCE SLICE_88)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1792,6 +1822,8 @@
(INSTANCE SLICE_89)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1822,8 +1854,6 @@
(INSTANCE SLICE_91)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1838,6 +1868,7 @@
(INSTANCE SLICE_92)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1853,8 +1884,6 @@
(INSTANCE SLICE_93)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1869,8 +1898,6 @@
(INSTANCE SLICE_94)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1899,6 +1926,8 @@
(INSTANCE SLICE_96)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1913,6 +1942,7 @@
(INSTANCE SLICE_97)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1927,6 +1957,7 @@
(INSTANCE SLICE_98)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1941,6 +1972,7 @@
(INSTANCE SLICE_99)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1955,6 +1987,8 @@
(INSTANCE SLICE_100)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1985,8 +2019,6 @@
(ABSOLUTE
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -1997,9 +2029,10 @@
(INSTANCE SLICE_103)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2011,11 +2044,10 @@
(INSTANCE SLICE_104)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2026,10 +2058,9 @@
(INSTANCE SLICE_105)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2045,6 +2076,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2056,30 +2088,21 @@
(INSTANCE SLICE_107)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
- (TIMINGCHECK
- (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
)
(CELL
(CELLTYPE "SLICE_108")
(INSTANCE SLICE_108)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -2095,7 +2118,6 @@
(INSTANCE SLICE_109)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -2110,11 +2132,9 @@
(INSTANCE SLICE_110)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2126,8 +2146,10 @@
(INSTANCE SLICE_111)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2138,10 +2160,10 @@
(INSTANCE SLICE_112)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2152,8 +2174,10 @@
(INSTANCE SLICE_113)
(DELAY
(ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2164,8 +2188,6 @@
(INSTANCE SLICE_114)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -2178,9 +2200,9 @@
(INSTANCE SLICE_115)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2192,10 +2214,8 @@
(INSTANCE SLICE_116)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2209,88 +2229,6 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_118")
- (INSTANCE SLICE_118)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_119")
- (INSTANCE SLICE_119)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_120")
- (INSTANCE SLICE_120)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_121")
- (INSTANCE SLICE_121)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_122")
- (INSTANCE SLICE_122)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_123")
- (INSTANCE SLICE_123)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2468,6 +2406,32 @@
)
)
)
+ (CELL
+ (CELLTYPE "RCLKout")
+ (INSTANCE RCLKout_I)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH IOLDO RCLKout (2293:2420:2548)(2293:2420:2548))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "RCLKout_MGIOL")
+ (INSTANCE RCLKout_MGIOL)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH CLK IOLDO (1172:1208:1244)(1172:1208:1244))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD ONEG (posedge CLK) (72:72:72)(-52:-52:-52))
+ (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (4807:4807:4807))
+ (WIDTH (negedge CLK) (4807:4807:4807))
+ )
+ )
(CELL
(CELLTYPE "RCLK")
(INSTANCE RCLK_I)
@@ -3463,8 +3427,8 @@
(DELAY
(ABSOLUTE
(INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_0/Q1 SLICE_92/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_0/Q1 SLICE_121/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_0/Q1 SLICE_87/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
@@ -3478,7 +3442,6 @@
(INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0))
- (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
@@ -3490,8 +3453,8 @@
(INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0))
- (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
- (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (0:0:0)(0:0:0))
@@ -3505,238 +3468,226 @@
(INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0))
- (INTERCONNECT RCLK_I/PADDI SLICE_107/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT RCLK_I/PADDI RCLKout_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI
ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0))
(INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_1/Q0 SLICE_56/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_1/Q0 SLICE_66/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_1/Q0 SLICE_97/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_1/Q0 SLICE_123/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_1/Q0 SLICE_58/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_1/Q0 SLICE_61/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_1/Q0 SLICE_103/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_1/Q0 SLICE_103/B0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q1 SLICE_56/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q1 SLICE_57/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q1 SLICE_66/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q1 SLICE_97/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q1 SLICE_123/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q1 SLICE_58/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q1 SLICE_61/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q1 SLICE_103/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q1 SLICE_103/A0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_49/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_49/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_50/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_57/B1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_66/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_2/Q0 SLICE_123/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q0 SLICE_61/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_2/Q0 SLICE_103/B1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_62/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_69/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_70/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_75/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_76/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_30/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_57/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_58/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_65/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_67/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_70/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_71/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_3/Q1 SLICE_72/D1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_3/Q1 SLICE_77/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_87/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_96/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_101/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_102/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_104/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_104/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_105/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_106/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_110/D0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_113/A1 (0:0:0)(0:0:0))
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+ (INTERCONNECT SLICE_8/Q0 SLICE_91/A0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_9/Q1 SLICE_98/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_9/Q1 SLICE_34/B1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_9/Q0 SLICE_121/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_9/Q0 SLICE_34/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_10/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_11/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_11/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_17/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_23/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_80/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_10/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_11/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_11/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_17/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_23/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_76/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_75/F1 SLICE_106/C1 (0:0:0)(0:0:0))
(INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/A1 (0:0:0)(0:0:0))
(INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D1 (0:0:0)(0:0:0))
(INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D0 (0:0:0)(0:0:0))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_17/D1 (0:0:0)(0:0:0))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/C1 (0:0:0)(0:0:0))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_38/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_39/A1 (0:0:0)(0:0:0))
(INTERCONNECT MAin\[1\]_I/PADDI SLICE_64/B0 (0:0:0)(0:0:0))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_80/A1 (0:0:0)(0:0:0))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_117/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_112/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_11/F1 SLICE_10/D0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_11/F1 SLICE_11/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_11/F1 SLICE_33/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_17/F1 SLICE_10/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_17/F1 SLICE_17/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_73/F0 SLICE_10/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_73/F0 SLICE_17/B0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_10/F1 SLICE_10/B0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_10/Q0 SLICE_33/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_10/Q0 SLICE_76/A0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0))
- (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
- (INTERCONNECT PHI2_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0))
+ (INTERCONNECT PHI2_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
@@ -3747,14 +3698,15 @@
(INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_112/F1 SLICE_11/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_112/F1 SLICE_17/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_112/F1 SLICE_64/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_112/F1 SLICE_80/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_20/F1 SLICE_11/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_20/F1 SLICE_64/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_20/F1 SLICE_73/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_20/F1 SLICE_76/B1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_64/F1 SLICE_11/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_64/F1 SLICE_64/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_64/F1 SLICE_76/D0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_11/Q0 SLICE_80/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_11/Q0 SLICE_17/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0))
(INTERCONNECT nCCAS_I/PADDI SLICE_12/A0 (0:0:0)(0:0:0))
(INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0))
@@ -3767,61 +3719,58 @@
(INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
(INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/F0 SLICE_80/M0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/F0 SLICE_80/M1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/F0 SLICE_73/M0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/F0 SLICE_73/M1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/Q1 SLICE_26/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/Q1 SLICE_61/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/Q1 SLICE_107/M0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/Q1 SLICE_108/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_12/Q1 SLICE_108/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_16/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_16/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_35/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_43/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_43/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_60/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_61/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_72/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_79/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_81/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_88/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_43/Q0 SLICE_108/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/Q1 SLICE_76/M0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/Q1 SLICE_92/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/Q1 SLICE_105/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_12/Q1 SLICE_117/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_16/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_16/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_44/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_47/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_62/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_62/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_68/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_96/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_105/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_44/Q0 SLICE_117/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_16/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_16/LSR (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_34/M0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_35/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_36/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_36/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_44/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_44/LSR (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_62/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q1 SLICE_90/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_29/Q0 SLICE_16/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_29/Q0 SLICE_78/C0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_16/Q0 SLICE_16/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_16/Q0 SLICE_16/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_26/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_43/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_43/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_60/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_60/D0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_61/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_61/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_72/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_79/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_83/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_88/D1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_108/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/Q0 SLICE_108/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_44/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_47/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_62/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_68/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_92/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_96/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_105/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/Q0 SLICE_105/B0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_16/LSR (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_33/M0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_34/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_35/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_35/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_43/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_43/LSR (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_72/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_74/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_78/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_79/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_90/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_16/F1 SLICE_46/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_99/F0 SLICE_17/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_99/F0 SLICE_80/C1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_33/F0 SLICE_17/D0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_80/F0 SLICE_17/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/F1 SLICE_37/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_16/F1 SLICE_38/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_106/F0 SLICE_17/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_64/F0 SLICE_17/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_76/F0 SLICE_17/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_17/Q0 SLICE_23/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_17/Q0 SLICE_23/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_17/Q0 SLICE_74/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_17/Q0 SLICE_106/B1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_22/F1 SLICE_18/D1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_22/F1 SLICE_20/C0 (0:0:0)(0:0:0))
@@ -3830,115 +3779,126 @@
(INTERCONNECT SLICE_22/F1 SLICE_23/B0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_22/F1 SLICE_24/D1 (0:0:0)(0:0:0))
(INTERCONNECT Din\[1\]_I/PADDI SLICE_18/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/B1 (0:0:0)(0:0:0))
(INTERCONNECT Din\[1\]_I/PADDI SLICE_20/B0 (0:0:0)(0:0:0))
(INTERCONNECT Din\[1\]_I/PADDI SLICE_21/B0 (0:0:0)(0:0:0))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_44/A0 (0:0:0)(0:0:0))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_112/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_45/A0 (0:0:0)(0:0:0))
(INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
(INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_119/F1 SLICE_18/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_119/F1 SLICE_24/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_104/F1 SLICE_18/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_104/F1 SLICE_24/A1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_18/Q0 SLICE_18/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_18/Q0 SLICE_30/A1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/F1 SLICE_18/C0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/F1 SLICE_20/D0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/F1 SLICE_21/D0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/F1 SLICE_24/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/F1 SLICE_82/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_30/Q0 SLICE_18/B0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_30/Q0 SLICE_32/B1 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_30/Q0 SLICE_44/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_18/Q0 SLICE_31/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_74/F1 SLICE_18/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_74/F1 SLICE_20/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_74/F1 SLICE_21/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_74/F1 SLICE_24/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_31/Q0 SLICE_18/B0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_31/Q0 SLICE_33/B1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_31/Q0 SLICE_45/B0 (0:0:0)(0:0:0))
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+ (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_89/A0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_90/F1 nRRAS_MGIOL/OPOS (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_92/F1 nRWE_MGIOL/OPOS (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_93/F1 SLICE_93/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_94/F1 SLICE_94/D0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_117/F0 SLICE_96/D1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_96/F1 SLICE_96/C0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_96/F0 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_102/F0 RDQMH_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_102/F1 RDQML_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_108/C1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_109/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_110/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_110/F1 RA\[8\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_111/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_111/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_112/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_112/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_113/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_113/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_114/F1 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0))
+ (INTERCONNECT CROW\[0\]_I/PADDI SLICE_115/A1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_115/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_115/F1 RBA\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
(INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
(INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0))
(INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0))
(INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (0:0:0)(0:0:0))
(INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0))
+ (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (0:0:0)(0:0:0))
(INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (0:0:0)(0:0:0))
(INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
(INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (0:0:0)(0:0:0))
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
index bf34131..0e72972 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd
-// Netlist created on Thu Sep 21 05:39:45 2023
-// Netlist written on Thu Sep 21 05:39:48 2023
+// Netlist created on Thu Oct 19 23:50:56 2023
+// Netlist written on Thu Oct 19 23:50:59 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4
@@ -11,7 +11,8 @@
`timescale 1 ns / 1 ps
module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
- RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML );
+ RD, nRCS, RCLK, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH,
+ RDQML );
input PHI2;
input [9:0] MAin;
input [1:0] CROW;
@@ -21,7 +22,7 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
output LED;
output [1:0] RBA;
output [11:0] RA;
- output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
+ output nRCS, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
inout [7:0] RD;
wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] ,
\FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] ,
@@ -30,73 +31,70 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
\FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] ,
\FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] ,
\FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] ,
- \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] ,
- un1_CmdEnable20_0_0_o3, \MAin_c[1] , CmdEnable16, CmdEnable17, N_524,
- ADSubmitted, ADSubmitted_r_0_0, PHI2_c, N_518, N_594, C1Submitted,
- C1Submitted_RNO, nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , CO0,
- N_123_i, RASr2, N_345_i, N_593, CmdEnable_0_sqmuxa, un1_CmdEnable20_i,
- CmdEnable, CmdEnable_s, CmdValid_2_i_o2_1_o3, \Din_c[1] ,
- CmdLEDEN_4_u_i_0_a3_0_0, CmdLEDEN, N_531, LEDEN, CmdLEDEN_4_u_i_0_0,
- N_40_i, XOR8MEG18, CmdUFMShift, CmdUFMShift_3, CmdUFMWrite, N_462,
- \Din_c[0] , CmdUFMWrite_3, N_213, \Din_c[5] , \Din_c[4] , \Din_c[3] ,
- CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast, CmdValid_fast,
- Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0_0, N_38_i, nFWE_c, nFWE_c_i,
- nCRAS_c, FWEr, RD_1_i, nRCS_9_u_i_0_o2_1_RNIL2K71, \IS[0] , N_351_i_i,
- N_267, \IS[2] , \IS[1] , N_348_i_i, N_344_i, N_360_i, \IS[3] ,
- N_350_i_i, \IS_i[0] , N_581, InitReady3_0_a3_1, InitReady, InitReady3,
- N_757_0, \wb_dato[1] , LEDEN_6_i_m2_i_m2, CmdValid_RNIOOBE2, LEDENe_0,
- Ready_fast, \CROW_c[0] , PHI2r2, PHI2r, \RBAd_0[0] , PHI2r3, CBR,
- nCRAS_c_i_0, RASr, LED_c, nRowColSel, \RowA[3] , \MAin_c[3] , RASr3,
- \RA_c[3] , N_216, Ready, RCKEEN_8_u_0_1_0, RCKEEN_8_u_0_0_0, RCKEEN_8,
- RCKEEN, RCKE_2, RCKE_c, m3_0_a2_0, N_347, Ready_0_sqmuxa_0_a2_4_a3_2,
- N_758_0, Ready_0_sqmuxa, N_759_0, \RowAd_0[1] , \RowAd_0[0] ,
- \RowA[0] , \RowA[1] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] ,
- \RowA[2] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] ,
- \RowA[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] ,
- \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] ,
- \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , XOR8MEG,
- XOR8MEG_3_u_0_0_a3_0_2, N_441, XOR8MEG_3, g1_0, N_4, n8MEGENe_1_0,
- n8MEGENe_0, CASr3, N_248_i_1_1, nRowColSel_0_0_0, nRRAS_0_sqmuxa,
- \wb_adr_5_i_0_0[1] , N_417, N_416, N_382, \wb_adr_5_i_0_3[0] ,
- \wb_adr_5_i_0_0[0] , N_423, N_383, N_229_i, N_230_i, un1_wb_rst14_i_0,
- \wb_adr[0] , \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] ,
- \wb_adr[3] , \wb_adr[4] , N_210, N_385, N_384, \wb_adr[5] ,
- \wb_adr[6] , \wb_adr_5[7] , N_386, \wb_adr[7] ,
- wb_cyc_stb_4_iv_0_a3_0_0, N_471_3, N_471_2, N_214, un1_PHI2r3, N_471,
- wb_cyc_stb_4, N_178, wb_rst10, wb_cyc_stb, \wb_dati_5_1_iv_0_1[1] ,
- N_578, N_207, wb_we, \wb_dati_5_0_iv_0_a3_1[0] , N_576,
- \wb_dati_5[1] , \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] ,
- \wb_dati_5_1_iv_i_i_a3_1[3] , \wb_dati_5_1_iv_i_i_1[3] ,
- \wb_dati_5_1_iv_i_i_0[3] , N_579, N_361, \wb_dati_5_1_iv_i_i[3] ,
- \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] ,
- \wb_dati_5_1_iv_0_1[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] ,
- \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_0[7] , N_488, N_486,
- N_484, \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] ,
- \wb_dati[6] , \wb_dati[7] , wb_req, N_92_i, N_31_i, wb_reqe_0, wb_rst,
- N_515, wb_rste_0, wb_we_0_i_0_1, CmdUFMData, N_231_i, N_217, N_479,
- N_209, CBR_fast, N_408, nRCAS_0_sqmuxa_1, N_248_i_sx,
- un1_nRCAS_6_sqmuxa_i_0_0, nRCAS_r_i_0_o2_0_0, N_599, N_407,
- wb_we_0_i_0_a3_0_0, N_427, wb_we_0_i_0_0, N_539, \Din_c[6] ,
- un1_CmdEnable20_0_0_0, \wb_adr_5_i_0_a3_0_1[0] , N_424,
- \wb_adr_5_i_0_1[0] , N_542, N_208, \wb_dati_5_1_iv_0_a3_0_1[7] ,
- \ufmefb/g0_0_a3_2 , N_226, \wb_dati_5_1_iv_0_a3_0_1[1] , N_477, N_236,
- N_596, N_536, N_502, N_412, N_522, nRCS_9_u_i_0_o3,
- \wb_dati_5_1_iv_i_i_a3_3_0[3] , un1_nRCAS_6_sqmuxa_i_0_0_o2_0, N_221,
- N_246_i, un1_CmdEnable20_0_0_a3_1_1, nRWE_s_i_0_tz_0, N_595, N_590,
- N_49_i, CmdUFMData_1_sqmuxa, N_248_i_1_0, N_247_i, \Bank[5] ,
- \Bank[4] , \Bank[3] , \Bank[1] , un1_CmdEnable20_0_0_o3_11,
- un1_CmdEnable20_0_0_o3_10, \Bank[7] , \Bank[6] , N_537, N_514, N_473,
- N_472, RA10s_i, nRWE_s_i_0_a3_1_0, wb_cyc_stb_2_sqmuxa_i_a3_0, wb_ack,
- un1_CmdEnable20_0_0_o3_4, un1_CmdEnable20_0_0_o3_3, \Bank[2] ,
- \Bank[0] , N_248_i_1, N_248_i, N_511, N_404,
- wb_cyc_stb_4_iv_0_a3_0_2_0, N_505, \Din_c[2] , \Din_c[7] ,
- XOR8MEG_3_u_0_0_0_a2, G_4_0_a3_0, RDQMH_c, RDQML_c, \RA_c[6] ,
- \RA_c[8] , \RA_c[9] , \RA_c[0] , \RA_c[7] , \RA_c[1] , \RA_c[5] ,
- \RA_c[2] , \RA_c[4] , \CROW_c[1] , RA11d_0, \RBAd_0[1] , \wb_dato[0] ,
- \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] ,
- \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] ,
- \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] ,
- \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI;
+ \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_294,
+ \MAin_c[1] , CmdEnable16, CmdEnable17, N_22_i, ADSubmitted,
+ ADSubmitted_r_0, PHI2_c, N_374, N_393, C1Submitted, C1Submitted_RNO,
+ nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_253_i,
+ Ready_0_sqmuxa_0_a3_2, un1_CmdEnable20_0_a2_1_0, un1_CmdEnable20_0_0,
+ CmdEnable_0_sqmuxa, un1_CmdEnable20_i, CmdEnable, CmdEnable_s, N_140,
+ \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, CmdLEDEN, N_380, LEDEN,
+ CmdLEDEN_4_u_i_0, N_284_i, XOR8MEG18, \Din_c[0] , CmdUFMData_1_sqmuxa,
+ VCC, CmdUFMData, GND, \Din_c[4] , \Din_c[7] , CmdUFMShift,
+ CmdUFMShift_3, CmdUFMWrite, N_279, CmdUFMWrite_3, N_134, \Din_c[5] ,
+ \Din_c[3] , XOR8MEG18_i, CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast,
+ CmdValid_fast, Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_285_i,
+ nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, Ready_fast, \CROW_c[1] ,
+ \Din_c[2] , N_381, FWEr_fast, \RBAd_0[1] , N_43, Ready, \IS[0] ,
+ N_60_i_i, N_244_i, \IS[2] , \IS[1] , N_57_i_i, N_53_i, N_58_i_i, N_49,
+ N_142, InitReady3_0_a2_2, InitReady, InitReady3, N_586_0,
+ \wb_dato[1] , LEDEN_6_i_m2, CmdValid_RNITBH02, LEDENe_0, nRowColSel,
+ \RowA[4] , \MAin_c[4] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[4] ,
+ PHI2r2, PHI2r, un1_ADWR_i_o2_11, \RA_c[4] , PHI2r3, CBR, nCRAS_c_i_0,
+ RASr, LED_c, N_133, \wb_dati_5_1_iv_0_a2_1_1[7] , RASr3,
+ wb_cyc_stb_2_sqmuxa_i_a2_3_4, N_41, RCKEEN_8_u_1, RCKEEN_8_u_0_0,
+ RCKEEN_8, RCKEEN, RCKE_c, RCKE_2, nRWE_0io_RNO_2, N_248, N_587_0,
+ Ready_0_sqmuxa, N_588_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] ,
+ \RowA[1] , \MAin_c[3] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] ,
+ \RowA[2] , \RowA[3] , \MAin_c[5] , \RowAd_0[5] , \RowAd_0[4] ,
+ \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] ,
+ \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] ,
+ \RowAd_0[8] , \RowA[8] , \RowA[9] , CBR_fast, nRCAS_0_sqmuxa_1,
+ XOR8MEG, XOR8MEG_3_u_0_a2_0_2, N_274, XOR8MEG_3, g1_0, N_4,
+ n8MEGENe_1_0, n8MEGENe_0, CASr3, N_255, nRowColSel_0_0,
+ nRRAS_0_sqmuxa, \wb_adr_5_i_i_0[1] , N_384, \wb_adr_5_i_i_5[0] ,
+ N_367, N_313, N_282, N_283, N_122, \wb_adr[0] , \wb_adr[1] ,
+ \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] ,
+ N_132, N_80, N_81, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] ,
+ \wb_adr_5_i_m2_0[6] , \wb_adr[7] , wb_req, N_330_4, un1_PHI2r3, N_330,
+ wb_cyc_stb_4, N_103, wb_rst10, wb_cyc_stb, N_303, N_302, N_233, N_226,
+ wb_we, \wb_dati_5_0_iv_0_a2_0[0] , N_383, \wb_dati_5[1] ,
+ \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_1[3] ,
+ \wb_dati[2] , N_341, \wb_dati_5_1_iv_0_o2_0[5] , N_335,
+ \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[3] , \wb_dati[4] ,
+ \wb_dati_5_1_iv_0_2[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] ,
+ \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_1[7] , N_375, N_345,
+ \wb_dati_5_1_iv_0_0[6] , N_348_2, \wb_dati_5[7] , \wb_dati_5[6] ,
+ \wb_dati[6] , \wb_dati[7] , N_131, N_94_i, N_34_i, wb_reqe_0, wb_rst,
+ wb_rste_0, N_394, N_362, wb_we_0_0_0_0, N_353, wb_we_0_0_0, N_129,
+ N_223, N_428_tz, N_39, N_125, N_356, \Din_c[6] ,
+ \wb_adr_5_i_i_a2_0[1] , \wb_adr_5_i_i_a2_3_0[0] ,
+ \wb_adr_5_i_i_1_0_tz_0[0] , g0_0_a3_1, wb_ack, IS_0_sqmuxa_0_o2,
+ nRWE_0io_RNO_1, nRWE_0io_RNO_0, \wb_dati_5_1_iv_0_0[7] , N_220,
+ \wb_dati_5_1_iv_0_a2_3_0[7] , N_143, N_137, un1_CmdEnable20_0_a2_3_0,
+ N_382, un1_ADWR_i_o2_10, \Bank[3] , \Bank[1] , N_378,
+ \wb_adr_5_i_i_a2_6_0[0] , \wb_adr_5_i_i_1[0] , N_315, N_314, RA10s_i,
+ nRCS_9_u_i_0, N_37_i_1, nRCS_0io_RNO_0, N_28_i_1, nRCS_9_u_i_0_0,
+ N_28_i, N_376, \wb_dati_5_1_iv_0_a2_1[6] , \wb_adr_5_i_i_1_0[0] ,
+ N_307, N_295, un1_ADWR_i_o2_4, un1_ADWR_i_o2_3, \Bank[2] , \Bank[0] ,
+ N_25_i, wb_cyc_stb_2_sqmuxa_i_a2_3_3, N_37_i, N_371, N_141,
+ G_8_0_a3_0_0, nRCAS_0io_RNO_1, N_242_i_1, N_242_i, RDQMH_c, RDQML_c,
+ \wb_dato[0] , \RA_c[3] , \RA_c[9] , \RA_c[8] , \RA_c[7] , \RA_c[0] ,
+ \RA_c[6] , \RA_c[1] , \RA_c[5] , \RA_c[2] , \IS_i[0] , \CROW_c[0] ,
+ RA11d_0, \RBAd_0[0] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c,
+ RCLKout_c, nRCS_c, \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] ,
+ \RD_in[5] , \WRD[5] , \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] ,
+ \RD_in[2] , \WRD[2] , \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] ,
+ \RBA_c[1] , \RBA_c[0] , VCCI;
SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ),
.Q1(\FS[0] ), .FCO(\FS_cry[0] ));
@@ -126,345 +124,332 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ),
.DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ),
.Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
- SLICE_10 SLICE_10( .B1(un1_CmdEnable20_0_0_o3), .A1(\MAin_c[1] ),
- .D0(CmdEnable16), .C0(CmdEnable17), .B0(N_524), .A0(ADSubmitted),
- .DI0(ADSubmitted_r_0_0), .CLK(PHI2_c), .F0(ADSubmitted_r_0_0),
- .Q0(ADSubmitted), .F1(N_524));
- SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), .B1(N_518),
- .A1(N_594), .D0(\MAin_c[1] ), .C0(un1_CmdEnable20_0_0_o3),
- .B0(C1Submitted), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c),
- .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
+ SLICE_10 SLICE_10( .B1(N_294), .A1(\MAin_c[1] ), .D0(CmdEnable16),
+ .C0(CmdEnable17), .B0(N_22_i), .A0(ADSubmitted), .DI0(ADSubmitted_r_0),
+ .CLK(PHI2_c), .F0(ADSubmitted_r_0), .Q0(ADSubmitted), .F1(N_22_i));
+ SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_374), .B1(N_294), .A1(N_393),
+ .D0(\MAin_c[1] ), .C0(N_294), .B0(C1Submitted), .A0(CmdEnable16),
+ .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO),
+ .Q0(C1Submitted), .F1(CmdEnable16));
SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c),
.F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2));
- SLICE_16 SLICE_16( .B1(\S[1] ), .A1(CO0), .B0(\S[1] ), .A0(CO0),
- .DI0(N_123_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_123_i), .Q0(CO0),
- .F1(N_345_i));
- SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), .B1(N_518),
- .A1(N_593), .D0(CmdEnable_0_sqmuxa), .C0(un1_CmdEnable20_i),
- .B0(CmdEnable17), .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c),
- .F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable17));
- SLICE_18 SLICE_18( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[1] ),
- .B1(CmdLEDEN_4_u_i_0_a3_0_0), .A1(CmdLEDEN), .C0(N_531), .B0(LEDEN),
- .A0(CmdLEDEN_4_u_i_0_0), .DI0(N_40_i), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(N_40_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_0_0));
- SLICE_20 SLICE_20( .D0(N_531), .C0(CmdValid_2_i_o2_1_o3), .B0(\Din_c[1] ),
- .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(CmdUFMShift_3), .Q0(CmdUFMShift));
- SLICE_21 SLICE_21( .B1(CmdValid_2_i_o2_1_o3), .A1(CmdUFMWrite), .D0(N_531),
- .C0(N_462), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3),
- .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite),
- .F1(N_462));
- SLICE_22 SLICE_22( .D1(N_213), .C1(\Din_c[5] ), .B1(\Din_c[4] ),
- .A1(\Din_c[3] ), .B0(CmdValid_2_i_o2_1_o3), .A0(XOR8MEG18),
- .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid),
- .F1(CmdValid_2_i_o2_1_o3));
- SLICE_23 SLICE_23( .D1(un1_CmdEnable20_0_0_o3), .C1(\MAin_c[1] ),
- .B1(\MAin_c[0] ), .A1(CmdEnable), .B0(CmdValid_2_i_o2_1_o3),
- .A0(XOR8MEG18), .DI0(N_36_fast), .CLK(PHI2_c), .F0(N_36_fast),
- .Q0(CmdValid_fast), .F1(XOR8MEG18));
- SLICE_24 SLICE_24( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[0] ),
- .B1(Cmdn8MEGEN), .A1(CmdLEDEN_4_u_i_0_a3_0_0), .C0(n8MEGEN), .B0(N_531),
- .A0(Cmdn8MEGEN_4_u_i_0_0), .DI0(N_38_i), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(N_38_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0_0));
+ SLICE_16 SLICE_16( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0),
+ .B0(\S[1] ), .A0(CO0), .DI0(N_253_i), .LSR(RASr2), .CLK(RCLK_c),
+ .F0(N_253_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+ SLICE_17 SLICE_17( .D1(un1_CmdEnable20_0_a2_1_0), .C1(un1_CmdEnable20_0_0),
+ .B1(N_294), .A1(C1Submitted), .D0(CmdEnable_0_sqmuxa),
+ .C0(un1_CmdEnable20_i), .B0(CmdEnable17), .A0(CmdEnable),
+ .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable),
+ .F1(un1_CmdEnable20_i));
+ SLICE_18 SLICE_18( .D1(N_140), .C1(\Din_c[1] ), .B1(CmdLEDEN_4_u_i_a2_0_0),
+ .A1(CmdLEDEN), .C0(N_380), .B0(LEDEN), .A0(CmdLEDEN_4_u_i_0),
+ .DI0(N_284_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_284_i), .Q0(CmdLEDEN),
+ .F1(CmdLEDEN_4_u_i_0));
+ SLICE_19 SLICE_19( .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c),
+ .F0(VCC), .Q0(CmdUFMData), .F1(GND));
+ SLICE_20 SLICE_20( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ),
+ .A1(\Din_c[7] ), .D0(N_380), .C0(N_140), .B0(\Din_c[1] ), .A0(CmdUFMShift),
+ .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3),
+ .Q0(CmdUFMShift), .F1(N_374));
+ SLICE_21 SLICE_21( .B1(N_140), .A1(CmdUFMWrite), .D0(N_380), .C0(N_279),
+ .B0(\Din_c[1] ), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18),
+ .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_279));
+ SLICE_22 SLICE_22( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[4] ),
+ .A1(\Din_c[3] ), .B0(N_140), .A0(XOR8MEG18_i), .DI0(CmdValid_r),
+ .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_140));
+ SLICE_23 SLICE_23( .D1(\MAin_c[1] ), .C1(CmdEnable), .B1(N_294),
+ .A1(\MAin_c[0] ), .B0(N_140), .A0(XOR8MEG18_i), .DI0(N_36_fast),
+ .CLK(PHI2_c), .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18_i));
+ SLICE_24 SLICE_24( .D1(N_140), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN),
+ .A1(CmdLEDEN_4_u_i_a2_0_0), .C0(n8MEGEN), .B0(N_380),
+ .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_285_i), .CE(XOR8MEG18), .CLK(PHI2_c),
+ .F0(N_285_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0));
SLICE_25 SLICE_25( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i),
.CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i));
- SLICE_26 SLICE_26( .B1(CO0), .A1(CASr2), .B0(nRCS_9_u_i_0_o2_1_RNIL2K71),
- .A0(\IS[0] ), .DI0(N_351_i_i), .CLK(RCLK_c), .F0(N_351_i_i), .Q0(\IS[0] ),
- .F1(N_267));
- SLICE_27 SLICE_27( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ),
- .A0(\IS[0] ), .DI1(N_348_i_i), .DI0(N_344_i), .CE(N_360_i), .CLK(RCLK_c),
- .F0(N_344_i), .Q0(\IS[1] ), .F1(N_348_i_i), .Q1(\IS[2] ));
- SLICE_28 SLICE_28( .A1(\IS[0] ), .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ),
- .A0(\IS[3] ), .DI0(N_350_i_i), .CE(N_360_i), .CLK(RCLK_c), .F0(N_350_i_i),
- .Q0(\IS[3] ), .F1(\IS_i[0] ));
- SLICE_29 SLICE_29( .D1(N_581), .C1(InitReady3_0_a3_1), .B1(\FS[11] ),
- .A1(\FS[10] ), .B0(InitReady), .A0(InitReady3), .DI0(N_757_0),
- .CLK(RCLK_c), .F0(N_757_0), .Q0(InitReady), .F1(InitReady3));
- SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN),
- .C0(LEDEN_6_i_m2_i_m2), .B0(CmdValid_RNIOOBE2), .A0(LEDEN), .DI0(LEDENe_0),
- .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2_i_m2));
- SLICE_31 SLICE_31( .B0(Ready_fast), .A0(\CROW_c[0] ), .M1(PHI2r2),
- .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .Q1(PHI2r3));
- SLICE_32 SLICE_32( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c),
+ SLICE_26 SLICE_26( .B1(Ready_fast), .A1(\CROW_c[1] ), .B0(\Din_c[5] ),
+ .A0(\Din_c[2] ), .M0(nFWE_c_i), .CLK(nCRAS_c), .F0(N_381), .Q0(FWEr_fast),
+ .F1(\RBAd_0[1] ));
+ SLICE_27 SLICE_27( .B1(N_43), .A1(Ready), .C0(N_43), .B0(Ready),
+ .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), .F0(N_60_i_i), .Q0(\IS[0] ),
+ .F1(N_244_i));
+ SLICE_28 SLICE_28( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ),
+ .A0(\IS[0] ), .DI1(N_57_i_i), .DI0(N_53_i), .CE(N_244_i), .CLK(RCLK_c),
+ .F0(N_53_i), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] ));
+ SLICE_29 SLICE_29( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ),
+ .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_58_i_i), .CE(N_244_i),
+ .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_49));
+ SLICE_30 SLICE_30( .D1(N_142), .C1(InitReady3_0_a2_2), .B1(\FS[14] ),
+ .A1(\FS[13] ), .B0(InitReady), .A0(InitReady3), .DI0(N_586_0),
+ .CLK(RCLK_c), .F0(N_586_0), .Q0(InitReady), .F1(InitReady3));
+ SLICE_31 SLICE_31( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN),
+ .C0(LEDEN_6_i_m2), .B0(CmdValid_RNITBH02), .A0(LEDEN), .DI0(LEDENe_0),
+ .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2));
+ SLICE_32 SLICE_32( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ),
+ .D0(\Bank[7] ), .C0(\Bank[6] ), .B0(\Bank[5] ), .A0(\Bank[4] ),
+ .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), .F0(un1_ADWR_i_o2_11), .Q0(PHI2r2),
+ .F1(\RA_c[4] ), .Q1(PHI2r3));
+ SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c),
.DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr),
.F1(LED_c), .Q1(RASr2));
- SLICE_33 SLICE_33( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ),
- .B0(CmdEnable16), .A0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c),
- .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\RA_c[3] ));
- SLICE_34 SLICE_34( .D1(N_216), .C1(InitReady), .B1(RASr2), .A1(Ready),
- .D0(Ready), .C0(RCKEEN_8_u_0_1_0), .B0(RCKEEN_8_u_0_0_0), .A0(CBR),
+ SLICE_34 SLICE_34( .D1(\FS[5] ), .C1(\FS[4] ), .B1(\FS[2] ), .A1(\FS[1] ),
+ .D0(N_133), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), .M0(RASr2),
+ .CLK(RCLK_c), .F0(\wb_dati_5_1_iv_0_a2_1_1[7] ), .Q0(RASr3),
+ .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_4));
+ SLICE_35 SLICE_35( .D1(N_41), .C1(InitReady), .B1(RASr2), .A1(Ready),
+ .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR),
.DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN),
- .F1(RCKEEN_8_u_0_0_0));
- SLICE_35 SLICE_35( .B1(\S[1] ), .A1(RASr2), .D0(RCKEEN), .C0(RASr3),
+ .F1(RCKEEN_8_u_0_0));
+ SLICE_36 SLICE_36( .B1(RCKE_c), .A1(RASr2), .D0(RCKEEN), .C0(RASr3),
.B0(RASr2), .A0(RASr), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2),
- .Q0(RCKE_c), .F1(m3_0_a2_0));
- SLICE_36 SLICE_36( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady),
- .C0(N_347), .B0(Ready_0_sqmuxa_0_a2_4_a3_2), .A0(Ready), .DI0(N_758_0),
- .CLK(RCLK_c), .F0(N_758_0), .Q0(Ready), .F1(N_347));
- SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_4_a3_2), .C1(Ready), .B1(N_347),
- .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_759_0),
- .CLK(RCLK_c), .F0(N_759_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
- SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast),
+ .Q0(RCKE_c), .F1(nRWE_0io_RNO_2));
+ SLICE_37 SLICE_37( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady),
+ .C0(N_248), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_587_0),
+ .CLK(RCLK_c), .F0(N_587_0), .Q0(Ready), .F1(N_248));
+ SLICE_38 SLICE_38( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_248),
+ .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_588_0),
+ .CLK(RCLK_c), .F0(N_588_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
+ SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast),
.A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c),
.F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
- SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast),
+ SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast),
.A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c),
.F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
- SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast),
+ SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast),
.A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c),
.F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
- SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast),
+ SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast),
.A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c),
.F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
- SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast),
+ SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast),
.A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c),
.F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
- SLICE_43 SLICE_43( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0),
- .B0(\S[1] ), .A0(CO0), .DI0(N_216), .LSR(RASr2), .CLK(RCLK_c), .F0(N_216),
- .Q0(\S[1] ), .F1(Ready_0_sqmuxa_0_a2_4_a3_2));
- SLICE_44 SLICE_44( .D1(XOR8MEG), .C1(N_213), .B1(\Din_c[5] ),
- .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_0_a3_0_2), .C0(N_441), .B0(LEDEN),
+ SLICE_44 SLICE_44( .D1(Ready), .C1(RASr2), .B1(N_41), .A1(CBR_fast),
+ .B0(\S[1] ), .A0(CO0), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41),
+ .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1));
+ SLICE_45 SLICE_45( .D1(XOR8MEG), .C1(N_134), .B1(\Din_c[5] ),
+ .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_a2_0_2), .C0(N_274), .B0(LEDEN),
.A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_441));
- SLICE_45 SLICE_45( .D1(g1_0), .C1(N_4), .B1(InitReady), .A1(CmdValid),
- .C0(n8MEGENe_1_0), .B0(n8MEGEN), .A0(CmdValid_RNIOOBE2), .DI0(n8MEGENe_0),
- .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNIOOBE2));
- SLICE_46 SLICE_46( .B1(FWEr), .A1(CASr3), .D0(Ready), .C0(N_345_i),
- .B0(N_248_i_1_1), .A0(CBR), .DI0(nRowColSel_0_0_0), .LSR(nRRAS_0_sqmuxa),
- .CLK(RCLK_c), .F0(nRowColSel_0_0_0), .Q0(nRowColSel), .F1(N_248_i_1_1));
- SLICE_47 SLICE_47( .D1(\wb_adr_5_i_0_0[1] ), .C1(N_417), .B1(N_416),
- .A1(N_382), .D0(\wb_adr_5_i_0_3[0] ), .C0(\wb_adr_5_i_0_0[0] ), .B0(N_423),
- .A0(N_383), .DI1(N_229_i), .DI0(N_230_i), .CE(un1_wb_rst14_i_0),
- .CLK(RCLK_c), .F0(N_230_i), .Q0(\wb_adr[0] ), .F1(N_229_i),
- .Q1(\wb_adr[1] ));
- SLICE_48 SLICE_48( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ),
- .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ),
- .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] ));
- SLICE_49 SLICE_49( .D1(\wb_adr[4] ), .C1(N_210), .B1(InitReady),
- .A1(\FS[15] ), .D0(\wb_adr[3] ), .C0(N_210), .B0(InitReady), .A0(\FS[15] ),
- .DI1(N_385), .DI0(N_384), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_384),
- .Q0(\wb_adr[4] ), .F1(N_385), .Q1(\wb_adr[5] ));
- SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .D0(\wb_adr[5] ),
- .C0(N_210), .B0(InitReady), .A0(\FS[15] ), .DI1(\wb_adr_5[7] ),
- .DI0(N_386), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_386),
- .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] ));
- SLICE_51 SLICE_51( .D1(wb_cyc_stb_4_iv_0_a3_0_0), .C1(N_471_3), .B1(N_471_2),
- .A1(N_214), .D0(un1_PHI2r3), .C0(N_471), .B0(InitReady), .A0(CmdUFMWrite),
- .DI0(wb_cyc_stb_4), .CE(N_178), .LSR(wb_rst10), .CLK(RCLK_c),
- .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_471));
- SLICE_52 SLICE_52( .D1(\wb_dati_5_1_iv_0_1[1] ), .C1(N_578), .B1(N_207),
- .A1(\FS[11] ), .D0(wb_we), .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(N_576),
- .A0(InitReady), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[0] ),
- .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] ));
- SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_i_i_a3_1[3] ),
- .C1(\wb_dati_5_1_iv_i_i_1[3] ), .B1(\wb_dati_5_1_iv_i_i_0[3] ), .A1(N_579),
- .C0(\wb_dati[1] ), .B0(N_361), .A0(InitReady),
- .DI1(\wb_dati_5_1_iv_i_i[3] ), .DI0(\wb_dati_5[2] ), .CE(un1_wb_rst14_i_0),
- .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ),
- .F1(\wb_dati_5_1_iv_i_i[3] ), .Q1(\wb_dati[3] ));
- SLICE_54 SLICE_54( .C1(\wb_dati[4] ), .B1(N_361), .A1(InitReady),
- .D0(\wb_dati_5_1_iv_0_1[4] ), .C0(\wb_dati_5_1_iv_0_0[4] ), .B0(N_578),
- .A0(\FS[9] ), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[4] ),
+ .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_274));
+ SLICE_46 SLICE_46( .D1(g1_0), .C1(N_4), .B1(InitReady), .A1(CmdValid),
+ .C0(n8MEGENe_1_0), .B0(n8MEGEN), .A0(CmdValid_RNITBH02), .DI0(n8MEGENe_0),
+ .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNITBH02));
+ SLICE_47 SLICE_47( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ),
+ .C0(Ready), .B0(N_255), .A0(CO0), .DI0(nRowColSel_0_0),
+ .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel),
+ .F1(N_255));
+ SLICE_48 SLICE_48( .D1(\wb_adr_5_i_i_0[1] ), .C1(N_384), .B1(\FS[12] ),
+ .A1(\FS[11] ), .D0(\wb_adr_5_i_i_5[0] ), .C0(N_367), .B0(N_313),
+ .A0(\FS[11] ), .DI1(N_282), .DI0(N_283), .CE(N_122), .CLK(RCLK_c),
+ .F0(N_283), .Q0(\wb_adr[0] ), .F1(N_282), .Q1(\wb_adr[1] ));
+ SLICE_49 SLICE_49( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ),
+ .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_122),
+ .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ),
+ .Q1(\wb_adr[3] ));
+ SLICE_50 SLICE_50( .C1(\wb_adr[4] ), .B1(N_132), .A1(InitReady),
+ .C0(\wb_adr[3] ), .B0(N_132), .A0(InitReady), .DI1(N_80), .DI0(N_81),
+ .CE(N_122), .CLK(RCLK_c), .F0(N_81), .Q0(\wb_adr[4] ), .F1(N_80),
+ .Q1(\wb_adr[5] ));
+ SLICE_51 SLICE_51( .B1(\wb_adr[6] ), .A1(InitReady), .C0(\wb_adr[5] ),
+ .B0(N_132), .A0(InitReady), .DI1(\wb_adr_5[7] ),
+ .DI0(\wb_adr_5_i_m2_0[6] ), .CE(N_122), .CLK(RCLK_c),
+ .F0(\wb_adr_5_i_m2_0[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ),
+ .Q1(\wb_adr[7] ));
+ SLICE_52 SLICE_52( .D1(wb_req), .C1(N_330_4), .B1(N_132), .A1(\FS[0] ),
+ .D0(un1_PHI2r3), .C0(N_330), .B0(InitReady), .A0(CmdUFMWrite),
+ .DI0(wb_cyc_stb_4), .CE(N_103), .LSR(wb_rst10), .CLK(RCLK_c),
+ .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_330));
+ SLICE_53 SLICE_53( .D1(N_303), .C1(N_302), .B1(N_233), .A1(N_226),
+ .D0(wb_we), .C0(\wb_dati_5_0_iv_0_a2_0[0] ), .B0(N_383), .A0(InitReady),
+ .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_122), .CLK(RCLK_c),
+ .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ),
+ .Q1(\wb_dati[1] ));
+ SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_1[3] ), .C1(\wb_dati[2] ),
+ .B1(N_341), .A1(InitReady), .D0(\wb_dati_5_1_iv_0_o2_0[5] ),
+ .C0(\wb_dati[1] ), .B0(N_335), .A0(InitReady), .DI1(\wb_dati_5[3] ),
+ .DI0(\wb_dati_5[2] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[2] ),
+ .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] ));
+ SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_o2_0[5] ), .C1(\wb_dati[4] ),
+ .B1(N_335), .A1(InitReady), .C0(\wb_dati_5_1_iv_0_2[4] ),
+ .B0(\wb_dati_5_1_iv_0_0[4] ), .A0(N_335), .DI1(\wb_dati_5[5] ),
+ .DI0(\wb_dati_5[4] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[4] ),
.Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] ));
- SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_0[7] ), .C1(N_488), .B1(N_486),
- .A1(N_484), .D0(\wb_dati_5_1_iv_0_1[6] ), .C0(N_578), .B0(N_207),
- .A0(\FS[11] ), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[6] ),
- .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] ));
- SLICE_56 SLICE_56( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), .A1(N_581),
- .C0(wb_req), .B0(N_92_i), .A0(N_31_i), .DI0(wb_reqe_0), .LSR(wb_rst10),
- .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_31_i));
- SLICE_57 SLICE_57( .D1(\FS[16] ), .C1(\FS[17] ), .B1(\FS[15] ),
- .A1(InitReady), .D0(wb_rst10), .C0(wb_rst), .B0(N_515), .A0(N_92_i),
+ SLICE_56 SLICE_56( .D1(\wb_dati_5_1_iv_0_a2_1_1[7] ),
+ .C1(\wb_dati_5_1_iv_0_1[7] ), .B1(N_375), .A1(N_345),
+ .D0(\wb_dati_5_1_iv_0_0[6] ), .C0(N_383), .B0(N_348_2), .A0(N_233),
+ .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), .CE(N_122), .CLK(RCLK_c),
+ .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ),
+ .Q1(\wb_dati[7] ));
+ SLICE_57 SLICE_57( .D1(N_131), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ),
+ .C0(wb_req), .B0(N_94_i), .A0(N_34_i), .DI0(wb_reqe_0), .LSR(wb_rst10),
+ .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_34_i));
+ SLICE_58 SLICE_58( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady),
+ .A1(\FS[15] ), .D0(wb_rst10), .C0(wb_rst), .B0(N_94_i), .A0(\FS[14] ),
.DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10));
- SLICE_58 SLICE_58( .D1(\wb_adr[0] ), .C1(N_210), .B1(InitReady),
- .A1(\FS[15] ), .D0(wb_we_0_i_0_1), .C0(N_210), .B0(InitReady),
- .A0(CmdUFMData), .DI0(N_231_i), .CE(un1_wb_rst14_i_0), .LSR(wb_rst10),
- .CLK(RCLK_c), .F0(N_231_i), .Q0(wb_we), .F1(N_382));
- wb_dati_5_1_iv_0_o3_5__SLICE_59 \wb_dati_5_1_iv_0_o3[5]/SLICE_59 (
- .D1(\FS[12] ), .C1(N_217), .B1(N_214), .A1(N_479), .D0(\FS[13] ),
- .C0(N_209), .B0(N_214), .A0(N_479), .M0(\FS[9] ), .OFX0(N_361));
- SLICE_60 SLICE_60( .D1(m3_0_a2_0), .C1(Ready), .B1(CO0), .A1(CBR_fast),
- .D0(CO0), .C0(N_408), .B0(nRCAS_0_sqmuxa_1), .A0(\S[1] ), .F0(N_248_i_sx),
- .F1(nRCAS_0_sqmuxa_1));
- SLICE_61 SLICE_61( .D1(\S[1] ), .C1(Ready), .B1(N_408), .A1(CO0), .C0(CASr2),
- .B0(CO0), .A0(un1_nRCAS_6_sqmuxa_i_0_0), .F0(nRCAS_r_i_0_o2_0_0),
- .F1(un1_nRCAS_6_sqmuxa_i_0_0));
- SLICE_62 SLICE_62( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ),
- .A1(InitReady), .C0(\FS[14] ), .B0(InitReady), .A0(N_599), .F0(N_407),
- .F1(N_599));
- SLICE_63 SLICE_63( .D1(wb_we_0_i_0_a3_0_0), .C1(N_427), .B1(N_207),
- .A1(\FS[12] ), .D0(wb_we_0_i_0_0), .C0(N_407), .B0(\FS[13] ),
- .A0(\FS[12] ), .F0(wb_we_0_i_0_1), .F1(wb_we_0_i_0_0));
- SLICE_64 SLICE_64( .D1(N_539), .C1(\MAin_c[0] ), .B1(\Din_c[6] ),
- .A1(\Din_c[3] ), .D0(N_594), .C0(N_518), .B0(\MAin_c[1] ),
- .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_594));
- SLICE_65 SLICE_65( .D1(\wb_adr_5_i_0_a3_0_1[0] ), .C1(N_424), .B1(\FS[10] ),
- .A1(\FS[9] ), .D0(\wb_adr_5_i_0_1[0] ), .C0(N_542), .B0(N_208),
- .A0(\FS[9] ), .F0(\wb_adr_5_i_0_3[0] ), .F1(\wb_adr_5_i_0_1[0] ));
- SLICE_66 SLICE_66( .D1(\FS[16] ), .C1(\FS[17] ), .B1(\FS[15] ),
- .A1(InitReady), .D0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .C0(\wb_dati[6] ),
- .B0(N_214), .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[7] ), .F1(N_214));
- SLICE_67 SLICE_67( .D1(N_579), .C1(N_208), .B1(\FS[10] ), .A1(\FS[9] ),
- .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_208),
- .F1(\wb_dati_5_1_iv_0_0[4] ));
- SLICE_68 SLICE_68( .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[11] ),
- .C0(\ufmefb/g0_0_a3_2 ), .B0(N_226), .A0(N_214), .F0(N_4), .F1(N_226));
- SLICE_69 SLICE_69( .D1(\wb_dati_5_1_iv_0_a3_0_1[1] ), .C1(N_214),
- .B1(\FS[14] ), .A1(\FS[12] ), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ),
- .A0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_a3_0_1[1] ), .F1(N_477));
- SLICE_70 SLICE_70( .D1(N_542), .C1(N_236), .B1(\FS[13] ), .A1(\FS[11] ),
- .C0(\FS[14] ), .B0(InitReady), .A0(\FS[12] ), .F0(N_542), .F1(N_424));
- SLICE_71 SLICE_71( .D1(N_596), .C1(N_536), .B1(N_502), .A1(N_412),
- .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_596),
- .F1(\wb_dati_5_1_iv_i_i_1[3] ));
- SLICE_72 SLICE_72( .D1(nRRAS_0_sqmuxa), .C1(RCKE_c), .B1(RASr2), .A1(N_522),
- .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa),
- .F1(nRCS_9_u_i_0_o3));
- SLICE_73 SLICE_73( .D1(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), .C1(\wb_dati[2] ),
- .B1(N_502), .A1(InitReady), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ),
- .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_i_i_a3_3_0[3] ),
- .F1(\wb_dati_5_1_iv_i_i_0[3] ));
- SLICE_74 SLICE_74( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .D0(InitReady),
- .C0(RASr2), .B0(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .A0(Ready), .F0(N_408),
- .F1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0));
- SLICE_75 SLICE_75( .B1(InitReady), .A1(\FS[14] ), .D0(\FS[12] ),
- .C0(\FS[11] ), .B0(N_207), .A0(N_515), .F0(\wb_adr_5_i_0_0[1] ),
- .F1(N_515));
- SLICE_76 SLICE_76( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[11] ),
- .A1(\FS[10] ), .D0(\FS[9] ), .C0(N_214), .B0(\FS[12] ), .A0(N_217),
- .F0(N_486), .F1(N_217));
- SLICE_77 SLICE_77( .D1(N_214), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ),
- .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(N_578), .F0(N_484),
- .F1(N_578));
- SLICE_78 SLICE_78( .D1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .C1(N_221),
- .B1(N_216), .A1(\IS[0] ), .D0(N_522), .C0(RASr2), .B0(RCKE_c),
- .A0(nRRAS_0_sqmuxa), .F0(N_246_i), .F1(N_522));
- SLICE_79 SLICE_79( .B1(RASr2), .A1(InitReady), .D0(Ready), .C0(N_221),
- .B0(\S[1] ), .A0(CO0), .F0(N_360_i), .F1(N_221));
- SLICE_80 SLICE_80( .C1(N_593), .B1(N_518), .A1(\MAin_c[1] ),
- .D0(un1_CmdEnable20_0_0_a3_1_1), .C0(un1_CmdEnable20_0_0_0),
- .B0(un1_CmdEnable20_0_0_o3), .A0(C1Submitted), .M1(nCCAS_c_i),
- .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR),
- .F1(un1_CmdEnable20_0_0_a3_1_1), .Q1(CBR_fast));
- SLICE_81 SLICE_81( .C1(\S[1] ), .B1(Ready), .A1(CBR), .D0(nRWE_s_i_0_tz_0),
- .C0(N_595), .B0(N_590), .A0(nRCAS_0_sqmuxa_1), .F0(N_49_i), .F1(N_590));
- SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ),
- .A1(N_213), .B0(XOR8MEG18), .A0(N_531), .M0(\Din_c[0] ),
- .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), .F0(CmdUFMData_1_sqmuxa),
- .Q0(CmdUFMData), .F1(N_531));
- SLICE_83 SLICE_83( .B1(FWEr), .A1(CO0), .D0(N_595), .C0(N_590),
- .B0(N_248_i_1_0), .A0(nRCS_9_u_i_0_o3), .F0(N_247_i), .F1(N_248_i_1_0));
- SLICE_84 SLICE_84( .D1(\Bank[5] ), .C1(\Bank[4] ), .B1(\Bank[3] ),
- .A1(\Bank[1] ), .D0(un1_CmdEnable20_0_0_o3_11),
- .C0(un1_CmdEnable20_0_0_o3_10), .B0(\Bank[7] ), .A0(\Bank[6] ),
- .F0(un1_CmdEnable20_0_0_o3), .F1(un1_CmdEnable20_0_0_o3_11));
- SLICE_85 SLICE_85( .D1(N_576), .C1(N_537), .B1(N_514), .A1(\FS[10] ),
- .D0(\wb_dati[5] ), .C0(N_473), .B0(N_472), .A0(InitReady),
- .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_473));
- SLICE_86 SLICE_86( .D1(N_536), .C1(N_502), .B1(N_207), .A1(\FS[11] ),
- .D0(\wb_dati[3] ), .C0(N_479), .B0(N_473), .A0(InitReady),
- .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(N_479));
- SLICE_87 SLICE_87( .C1(\FS[14] ), .B1(N_214), .A1(\FS[12] ), .D0(N_579),
- .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_488), .F1(N_579));
- SLICE_88 SLICE_88( .D1(CO0), .C1(\S[1] ), .B1(N_221), .A1(Ready),
- .D0(nRCS_9_u_i_0_o2_1_RNIL2K71), .C0(\IS[3] ), .B0(\IS[2] ), .A0(\IS[1] ),
- .F0(RA10s_i), .F1(nRCS_9_u_i_0_o2_1_RNIL2K71));
- SLICE_89 SLICE_89( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_579), .C0(N_236),
- .B0(\FS[13] ), .A0(\FS[11] ), .F0(N_472), .F1(N_236));
- SLICE_90 SLICE_90( .D1(nRCS_9_u_i_0_o2_1_RNIL2K71), .C1(\IS[2] ),
- .B1(\IS[1] ), .A1(\IS[0] ), .D0(nRWE_s_i_0_a3_1_0), .C0(nRRAS_0_sqmuxa),
- .B0(RCKE_c), .A0(RASr2), .F0(nRWE_s_i_0_tz_0), .F1(nRWE_s_i_0_a3_1_0));
- SLICE_91 SLICE_91( .D1(\FS[9] ), .C1(N_214), .B1(\FS[13] ), .A1(N_209),
- .D0(\wb_dati[0] ), .C0(N_477), .B0(N_412), .A0(InitReady),
- .F0(\wb_dati_5_1_iv_0_1[1] ), .F1(N_412));
- SLICE_92 SLICE_92( .C1(wb_req), .B1(N_471_3), .A1(\FS[0] ),
- .D0(wb_cyc_stb_2_sqmuxa_i_a3_0), .C0(wb_ack), .B0(N_471_2), .A0(N_214),
- .F0(N_178), .F1(wb_cyc_stb_2_sqmuxa_i_a3_0));
- SLICE_93 SLICE_93( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[3] ),
- .A1(\MAin_c[2] ), .D0(un1_CmdEnable20_0_0_o3_4),
- .C0(un1_CmdEnable20_0_0_o3_3), .B0(\Bank[2] ), .A0(\Bank[0] ),
- .F0(un1_CmdEnable20_0_0_o3_10), .F1(un1_CmdEnable20_0_0_o3_4));
- SLICE_94 SLICE_94( .D1(N_248_i_sx), .C1(N_248_i_1_0), .B1(N_248_i_1_1),
- .A1(N_248_i_1), .D0(nRCAS_r_i_0_o2_0_0), .C0(N_267), .B0(FWEr), .A0(CBR),
- .F0(N_248_i_1), .F1(N_248_i));
- SLICE_95 SLICE_95( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_536), .C0(N_207),
- .B0(InitReady), .A0(\FS[11] ), .F0(N_427), .F1(N_536));
- SLICE_96 SLICE_96( .B1(InitReady), .A1(\FS[14] ), .D0(N_511), .C0(N_404),
- .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_adr_5_i_0_0[0] ), .F1(N_511));
- SLICE_97 SLICE_97( .B1(\FS[17] ), .A1(\FS[16] ), .D0(\wb_dati[7] ),
- .C0(N_210), .B0(InitReady), .A0(\FS[15] ), .F0(N_383), .F1(N_210));
- SLICE_98 SLICE_98( .B1(\FS[4] ), .A1(\FS[3] ),
- .D0(wb_cyc_stb_4_iv_0_a3_0_2_0), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[2] ),
- .F0(N_471_2), .F1(wb_cyc_stb_4_iv_0_a3_0_2_0));
- SLICE_99 SLICE_99( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_505),
- .C0(\MAin_c[0] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(N_593), .F1(N_505));
- SLICE_100 SLICE_100( .B1(\Din_c[7] ), .A1(\Din_c[6] ), .D0(N_539),
- .C0(XOR8MEG_3_u_0_0_0_a2), .B0(N_213), .A0(\Din_c[3] ),
- .F0(XOR8MEG_3_u_0_0_a3_0_2), .F1(N_213));
- SLICE_101 SLICE_101( .B1(\FS[14] ), .A1(\FS[12] ), .D0(N_537), .C0(N_514),
- .B0(\FS[10] ), .A0(\FS[9] ), .F0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F1(N_537));
- SLICE_102 SLICE_102( .B1(\FS[13] ), .A1(\FS[11] ), .D0(N_514), .C0(\FS[14] ),
- .B0(\FS[12] ), .A0(\FS[10] ), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), .F1(N_514));
- SLICE_103 SLICE_103( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady),
- .C0(G_4_0_a3_0), .B0(CmdValid_fast), .A0(CmdUFMShift),
- .F0(un1_wb_rst14_i_0), .F1(G_4_0_a3_0));
- SLICE_104 SLICE_104( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ),
- .D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ),
- .F0(\ufmefb/g0_0_a3_2 ), .F1(N_581));
- SLICE_105 SLICE_105( .D1(N_226), .C1(InitReady), .B1(\FS[14] ),
- .A1(\FS[13] ), .C0(\FS[14] ), .B0(InitReady), .A0(\FS[13] ),
- .F0(wb_we_0_i_0_a3_0_0), .F1(N_417));
- SLICE_106 SLICE_106( .D1(N_599), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ),
- .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_599), .F0(N_423), .F1(N_416));
- SLICE_107 SLICE_107( .C1(PHI2r3), .B1(PHI2r2), .A1(CmdValid), .D0(PHI2r3),
- .C0(PHI2r2), .B0(InitReady), .A0(CmdValid), .M0(CASr2), .CLK(RCLK_c),
- .F0(N_92_i), .Q0(CASr3), .F1(un1_PHI2r3));
- SLICE_108 SLICE_108( .D1(\S[1] ), .C1(FWEr), .B1(CO0), .A1(CASr2), .D0(FWEr),
- .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_595), .F1(RCKEEN_8_u_0_1_0));
- SLICE_109 SLICE_109( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ),
- .A1(\FS[9] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_404),
- .F1(\wb_dati_5_1_iv_i_i_a3_1[3] ));
- SLICE_110 SLICE_110( .D1(InitReady), .C1(\FS[13] ), .B1(\FS[12] ),
+ SLICE_59 SLICE_59( .D1(\wb_dati[3] ), .C1(N_394), .B1(N_362), .A1(InitReady),
+ .D0(wb_we_0_0_0_0), .C0(N_353), .B0(InitReady), .A0(CmdUFMData),
+ .DI0(wb_we_0_0_0), .CE(N_122), .LSR(wb_rst10), .CLK(RCLK_c),
+ .F0(wb_we_0_0_0), .Q0(wb_we), .F1(\wb_dati_5_1_iv_0_0[4] ));
+ SLICE_60 SLICE_60( .D1(\FS[9] ), .C1(N_132), .B1(\FS[13] ), .A1(N_129),
+ .D0(N_362), .C0(N_226), .B0(N_223), .A0(\FS[13] ),
+ .F0(\wb_dati_5_1_iv_0_1[3] ), .F1(N_226));
+ SLICE_61 SLICE_61( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady),
+ .A1(\FS[15] ), .D0(\wb_adr[0] ), .C0(N_428_tz), .B0(N_132), .A0(InitReady),
+ .F0(\wb_adr_5_i_i_0[1] ), .F1(N_132));
+ SLICE_62 SLICE_62( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2),
+ .D0(\S[1] ), .C0(Ready), .B0(N_49), .A0(N_43), .F0(N_39), .F1(N_43));
+ SLICE_63 SLICE_63( .D1(N_142), .C1(N_131), .B1(N_125), .A1(\FS[13] ),
+ .D0(N_356), .C0(N_133), .B0(N_131), .A0(\FS[12] ), .F0(wb_we_0_0_0_0),
+ .F1(N_356));
+ SLICE_64 SLICE_64( .D1(N_381), .C1(\MAin_c[0] ), .B1(\Din_c[6] ),
+ .A1(\Din_c[3] ), .D0(N_393), .C0(N_374), .B0(\MAin_c[1] ),
+ .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0), .F1(N_393));
+ SLICE_65 SLICE_65( .D1(\wb_adr_5_i_i_a2_0[1] ), .C1(N_142), .B1(\FS[14] ),
+ .A1(\FS[13] ), .D0(N_125), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[11] ),
+ .F0(\wb_adr_5_i_i_a2_0[1] ), .F1(N_428_tz));
+ SLICE_66 SLICE_66( .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[9] ),
+ .D0(\wb_adr_5_i_i_a2_3_0[0] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ),
+ .F0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F1(\wb_adr_5_i_i_a2_3_0[0] ));
+ SLICE_67 SLICE_67( .D1(g0_0_a3_1), .C1(N_142), .B1(N_132), .A1(N_125),
+ .C0(wb_ack), .B0(\FS[14] ), .A0(\FS[13] ), .F0(g0_0_a3_1), .F1(N_4));
+ SLICE_68 SLICE_68( .D1(nRRAS_0_sqmuxa), .C1(IS_0_sqmuxa_0_o2),
+ .B1(nRWE_0io_RNO_2), .A1(nRWE_0io_RNO_1), .C0(CO0), .B0(\S[1] ),
+ .A0(Ready), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_0));
+ SLICE_69 SLICE_69( .D1(\wb_dati_5_1_iv_0_0[7] ), .C1(N_367), .B1(N_220),
+ .A1(\FS[11] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[12] ), .F0(N_220),
+ .F1(\wb_dati_5_1_iv_0_1[7] ));
+ SLICE_70 SLICE_70( .D1(\FS[11] ), .C1(\FS[12] ), .B1(\FS[13] ),
+ .A1(\FS[14] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(N_348_2),
+ .F0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F1(N_348_2));
+ SLICE_71 SLICE_71( .C1(N_143), .B1(N_131), .A1(\FS[14] ), .D0(\FS[9] ),
+ .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_143), .F1(N_353));
+ SLICE_72 SLICE_72( .D1(\FS[14] ), .C1(N_132), .B1(\FS[13] ), .A1(N_137),
+ .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_137),
+ .F1(N_335));
+ SLICE_73 SLICE_73( .D1(\MAin_c[1] ), .C1(N_374), .B1(\Din_c[3] ),
+ .A1(\Din_c[5] ), .D0(un1_CmdEnable20_0_a2_3_0), .C0(N_382),
+ .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c_i), .M0(nCCAS_c_i),
+ .CLK(nCRAS_c), .F0(CmdEnable17), .Q0(CBR), .F1(un1_CmdEnable20_0_a2_3_0),
+ .Q1(CBR_fast));
+ SLICE_74 SLICE_74( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[4] ),
+ .A1(\Din_c[3] ), .D0(N_382), .C0(N_380), .B0(\MAin_c[1] ), .A0(CmdEnable),
+ .F0(CmdUFMData_1_sqmuxa), .F1(N_380));
+ SLICE_75 SLICE_75( .D1(un1_ADWR_i_o2_11), .C1(un1_ADWR_i_o2_10),
+ .B1(\Bank[3] ), .A1(\Bank[1] ), .B0(N_294), .A0(\MAin_c[0] ), .F0(N_382),
+ .F1(N_294));
+ SLICE_76 SLICE_76( .B1(N_374), .A1(\MAin_c[1] ), .D0(N_393), .C0(N_378),
+ .B0(N_294), .A0(ADSubmitted), .M0(CASr2), .CLK(RCLK_c),
+ .F0(CmdEnable_0_sqmuxa), .Q0(CASr3), .F1(N_378));
+ SLICE_77 SLICE_77( .C1(\FS[14] ), .B1(N_132), .A1(\wb_adr_5_i_i_a2_6_0[0] ),
+ .D0(\wb_adr_5_i_i_1[0] ), .C0(N_384), .B0(N_315), .A0(N_314),
+ .F0(\wb_adr_5_i_i_5[0] ), .F1(N_314));
+ SLICE_78 SLICE_78( .B1(Ready), .A1(N_43), .D0(IS_0_sqmuxa_0_o2),
+ .C0(\IS[3] ), .B0(\IS[2] ), .A0(\IS[1] ), .F0(RA10s_i),
+ .F1(IS_0_sqmuxa_0_o2));
+ SLICE_79 SLICE_79( .C1(\FS[9] ), .B1(N_132), .A1(\FS[10] ),
+ .D0(\wb_adr_5_i_i_a2_6_0[0] ), .C0(N_383), .B0(N_367), .A0(N_348_2),
+ .F0(\wb_dati_5_1_iv_0_2[4] ), .F1(N_383));
+ SLICE_80 SLICE_80( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_367), .C0(N_125),
+ .B0(\FS[12] ), .A0(\FS[11] ), .F0(N_233), .F1(N_125));
+ SLICE_81 SLICE_81( .D1(nRCS_9_u_i_0), .C1(N_37_i_1), .B1(nRCS_0io_RNO_0),
+ .A1(N_28_i_1), .D0(nRCS_9_u_i_0_0), .C0(N_49), .B0(N_43), .A0(\IS[0] ),
+ .F0(nRCS_9_u_i_0), .F1(N_28_i));
+ SLICE_82 SLICE_82( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_383), .C0(N_376),
+ .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_345), .F1(N_376));
+ SLICE_83 SLICE_83( .D1(\FS[9] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[12] ),
+ .D0(N_394), .C0(N_226), .B0(N_133), .A0(N_132),
+ .F0(\wb_dati_5_1_iv_0_o2_0[5] ), .F1(N_394));
+ SLICE_84 SLICE_84( .B1(N_132), .A1(\FS[14] ),
+ .D0(\wb_dati_5_1_iv_0_a2_1[6] ), .C0(\wb_dati[5] ), .B0(N_362),
+ .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[6] ), .F1(N_362));
+ SLICE_85 SLICE_85( .D1(N_132), .C1(N_125), .B1(\FS[13] ), .A1(\FS[12] ),
+ .D0(\wb_dati[7] ), .C0(\wb_adr_5_i_i_1_0[0] ), .B0(N_307), .A0(InitReady),
+ .F0(\wb_adr_5_i_i_1[0] ), .F1(N_307));
+ SLICE_86 SLICE_86( .B1(\FS[14] ), .A1(\FS[13] ),
+ .D0(\wb_adr_5_i_i_1_0_tz_0[0] ), .C0(N_133), .B0(N_132), .A0(\FS[12] ),
+ .F0(\wb_adr_5_i_i_1_0[0] ), .F1(N_133));
+ SLICE_87 SLICE_87( .B1(wb_req), .A1(\FS[0] ), .D0(wb_ack), .C0(N_330_4),
+ .B0(N_295), .A0(N_132), .F0(N_103), .F1(N_295));
+ SLICE_88 SLICE_88( .B1(N_132), .A1(\FS[9] ), .D0(N_375), .C0(\FS[13] ),
+ .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_315), .F1(N_375));
+ SLICE_89 SLICE_89( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[4] ),
+ .A1(\MAin_c[2] ), .D0(un1_ADWR_i_o2_4), .C0(un1_ADWR_i_o2_3),
+ .B0(\Bank[2] ), .A0(\Bank[0] ), .F0(un1_ADWR_i_o2_10),
+ .F1(un1_ADWR_i_o2_4));
+ SLICE_90 SLICE_90( .D1(\IS[0] ), .C1(N_43), .B1(N_49), .A1(nRCS_9_u_i_0_0),
+ .D0(Ready), .C0(RCKE_c), .B0(RASr2), .A0(N_41), .F0(nRCS_9_u_i_0_0),
+ .F1(N_25_i));
+ SLICE_91 SLICE_91( .B1(\FS[7] ), .A1(\FS[6] ),
+ .D0(wb_cyc_stb_2_sqmuxa_i_a2_3_4), .C0(wb_cyc_stb_2_sqmuxa_i_a2_3_3),
+ .B0(\FS[8] ), .A0(\FS[3] ), .F0(N_330_4),
+ .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_3));
+ SLICE_92 SLICE_92( .D1(nRCAS_0_sqmuxa_1), .C1(nRWE_0io_RNO_0), .B1(N_37_i_1),
+ .A1(N_28_i_1), .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2),
+ .F0(N_37_i_1), .F1(N_37_i));
+ SLICE_93 SLICE_93( .B1(\Din_c[4] ), .A1(\Din_c[0] ), .D0(N_381), .C0(N_371),
+ .B0(N_134), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_a2_0_2), .F1(N_371));
+ SLICE_94 SLICE_94( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_141), .C0(\FS[13] ),
+ .B0(\FS[12] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_1[6] ), .F1(N_141));
+ SLICE_95 SLICE_95( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady),
+ .C0(G_8_0_a3_0_0), .B0(CmdValid_fast), .A0(CmdUFMShift), .F0(N_122),
+ .F1(G_8_0_a3_0_0));
+ SLICE_96 SLICE_96( .D1(nRCAS_0io_RNO_1), .C1(FWEr), .B1(CO0), .A1(CBR),
+ .D0(\S[1] ), .C0(N_242_i_1), .B0(nRCAS_0_sqmuxa_1), .A0(N_39),
+ .F0(N_242_i), .F1(N_242_i_1));
+ SLICE_97 SLICE_97( .C1(PHI2r3), .B1(PHI2r2), .A1(CmdValid), .D0(PHI2r3),
+ .C0(PHI2r2), .B0(InitReady), .A0(CmdValid), .F0(N_94_i), .F1(un1_PHI2r3));
+ SLICE_98 SLICE_98( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[12] ),
+ .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_223),
+ .F1(\wb_adr_5_i_i_a2_6_0[0] ));
+ SLICE_99 SLICE_99( .C1(N_132), .B1(\FS[14] ), .A1(\FS[13] ), .D0(N_394),
+ .C0(N_132), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_303), .F1(N_367));
+ SLICE_100 SLICE_100( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ),
.A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ),
- .F0(N_209), .F1(\wb_adr_5_i_0_a3_0_1[0] ));
- SLICE_111 SLICE_111( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel),
+ .F0(N_129), .F1(\wb_dati_5_0_iv_0_a2_0[0] ));
+ SLICE_101 SLICE_101( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_362), .C0(N_125),
+ .B0(\FS[12] ), .A0(\FS[11] ), .F0(N_341), .F1(N_142));
+ SLICE_102 SLICE_102( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel),
.A0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c));
- SLICE_112 SLICE_112( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ),
- .A1(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[0] ),
- .F0(XOR8MEG_3_u_0_0_0_a2), .F1(N_518));
- SLICE_113 SLICE_113( .B1(N_214), .A1(\FS[14] ), .B0(N_214), .A0(\FS[9] ),
- .F0(N_576), .F1(N_502));
- SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ),
- .C0(nFWE_c), .B0(\MAin_c[6] ), .A0(\MAin_c[4] ),
- .F0(un1_CmdEnable20_0_0_o3_3), .F1(\RA_c[6] ));
- SLICE_115 SLICE_115( .C1(nRowColSel), .B1(\RowA[9] ), .A1(\MAin_c[9] ),
- .C0(nRowColSel), .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ),
- .F1(\RA_c[9] ));
- SLICE_116 SLICE_116( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ),
- .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ),
- .F1(\RA_c[7] ));
- SLICE_117 SLICE_117( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ),
- .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ),
- .F1(\RA_c[5] ));
- SLICE_118 SLICE_118( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ),
- .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ),
- .F1(\RA_c[4] ));
- SLICE_119 SLICE_119( .D1(\Din_c[6] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ),
- .A1(\Din_c[5] ), .B0(\Din_c[5] ), .A0(\Din_c[2] ), .F0(N_539),
- .F1(CmdLEDEN_4_u_i_0_a3_0_0));
- SLICE_120 SLICE_120( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(n8MEGEN),
+ SLICE_103 SLICE_103( .D1(\FS[17] ), .C1(\FS[16] ), .B1(\FS[15] ),
+ .A1(\FS[10] ), .C0(InitReady), .B0(\FS[17] ), .A0(\FS[16] ), .F0(N_131),
+ .F1(InitReady3_0_a2_2));
+ SLICE_104 SLICE_104( .D1(\Din_c[6] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ),
+ .A1(\Din_c[5] ), .B0(\Din_c[7] ), .A0(\Din_c[6] ), .F0(N_134),
+ .F1(CmdLEDEN_4_u_i_a2_0_0));
+ SLICE_105 SLICE_105( .B1(FWEr), .A1(CO0), .D0(\S[1] ), .C0(FWEr), .B0(CO0),
+ .A0(CASr2), .F0(RCKEEN_8_u_1), .F1(nRCS_0io_RNO_0));
+ SLICE_106 SLICE_106( .D1(\MAin_c[0] ), .C1(N_294), .B1(CmdEnable),
+ .A1(\MAin_c[1] ), .D0(un1_CmdEnable20_0_a2_3_0), .C0(\MAin_c[0] ),
+ .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(un1_CmdEnable20_0_a2_1_0),
+ .F1(XOR8MEG18));
+ SLICE_107 SLICE_107( .D1(N_132), .C1(N_125), .B1(\FS[14] ), .A1(\FS[13] ),
+ .C0(N_383), .B0(\FS[13] ), .A0(\FS[12] ), .F0(N_313), .F1(N_384));
+ SLICE_108 SLICE_108( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN),
+ .D0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .C0(\wb_dati[6] ), .B0(N_132),
+ .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[7] ), .F1(n8MEGENe_1_0));
+ SLICE_109 SLICE_109( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ),
+ .C0(nFWE_c), .B0(\MAin_c[6] ), .A0(\MAin_c[3] ), .F0(un1_ADWR_i_o2_3),
+ .F1(\RA_c[3] ));
+ SLICE_110 SLICE_110( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ),
+ .C0(nRowColSel), .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ),
+ .F1(\RA_c[8] ));
+ SLICE_111 SLICE_111( .C1(nRowColSel), .B1(\RowA[0] ), .A1(\MAin_c[0] ),
+ .C0(nRowColSel), .B0(\RowA[7] ), .A0(\MAin_c[7] ), .F0(\RA_c[7] ),
+ .F1(\RA_c[0] ));
+ SLICE_112 SLICE_112( .C1(nRowColSel), .B1(\RowA[1] ), .A1(\MAin_c[1] ),
+ .C0(nRowColSel), .B0(\RowA[6] ), .A0(\MAin_c[6] ), .F0(\RA_c[6] ),
+ .F1(\RA_c[1] ));
+ SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ),
+ .C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ),
+ .F1(\RA_c[2] ));
+ SLICE_114 SLICE_114( .A1(\IS[0] ), .C0(\IS[2] ), .B0(\IS[1] ), .A0(\IS[0] ),
+ .F0(nRWE_0io_RNO_1), .F1(\IS_i[0] ));
+ SLICE_115 SLICE_115( .B1(Ready_fast), .A1(\CROW_c[0] ), .D0(n8MEGEN),
.C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0),
- .F1(\RBAd_0[1] ));
- SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[5] ),
- .A0(\FS[1] ), .F0(N_471_3), .F1(wb_cyc_stb_4_iv_0_a3_0_0));
- SLICE_122 SLICE_122( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN),
- .B0(PHI2r3), .A0(PHI2r2), .F0(g1_0), .F1(n8MEGENe_1_0));
- SLICE_123 SLICE_123( .B1(\FS[10] ), .A1(\FS[9] ), .C0(\FS[17] ),
- .B0(\FS[16] ), .A0(\FS[15] ), .F0(InitReady3_0_a3_1), .F1(N_207));
+ .F1(\RBAd_0[0] ));
+ SLICE_116 SLICE_116( .B1(\wb_dati[0] ), .A1(InitReady), .B0(PHI2r3),
+ .A0(PHI2r2), .F0(g1_0), .F1(N_302));
+ SLICE_117 SLICE_117( .C1(\S[1] ), .B1(Ready), .A1(CBR_fast), .B0(CASr3),
+ .A0(CASr2), .F0(nRCAS_0io_RNO_1), .F1(N_28_i_1));
RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i),
.RD0(RD[0]));
RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ),
@@ -475,15 +460,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
- nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_248_i), .CLK(RCLK_c));
+ nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_242_i), .CLK(RCLK_c));
nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
- nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_246_i), .CLK(RCLK_c));
+ nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c));
nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
- nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_49_i), .CLK(RCLK_c));
+ nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c));
RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+ RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout));
+ RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND),
+ .CLK(RCLK_c));
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
- nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_247_i), .CLK(RCLK_c));
+ nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c));
RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i),
.RD7(RD[7]));
RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ),
@@ -926,9 +914,9 @@ endmodule
module SLICE_10 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut4 un1_ADWR_i_i_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut4 ADSubmitted_r_0_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40003 ADSubmitted_r_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40003 ADSubmitted_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -968,7 +956,7 @@ module SLICE_11 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
- lut40004 CmdEnable16_0_a2_1_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -995,7 +983,7 @@ endmodule
module lut40004 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40005 ( input A, B, C, D, output Z );
@@ -1031,18 +1019,21 @@ module lut40006 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_16 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
+ F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
- lut40007 nRowColSel_0_0_0_x2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
+ lut40007 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40008 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -1060,7 +1051,7 @@ endmodule
module lut40007 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40008 ( input A, B, C, D, output Z );
@@ -1078,9 +1069,8 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
- lut40004 un1_CmdEnable20_0_0_a2_0_RNI00E51( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- lut40010 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40010 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1106,6 +1096,11 @@ endmodule
module lut40010 ( input A, B, C, D, output Z );
+ ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40011 ( input A, B, C, D, output Z );
+
ROM16X1A #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
@@ -1113,8 +1108,8 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
- lut40011 CmdLEDEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40012 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40012 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1138,20 +1133,53 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
endmodule
-module lut40011 ( input A, B, C, D, output Z );
+module lut40012 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40012 ( input A, B, C, D, output Z );
+module lut40013 ( input A, B, C, D, output Z );
ROM16X1A #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
+module SLICE_19 ( input M0, CE, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+
+ lut40014 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40015 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
+ vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+ specify
+ (CLK => Q0) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+ $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+ endspecify
+
+endmodule
+
+module lut40014 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40015 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
+ F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
- lut40013 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40016 un1_CmdEnable20_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40017 CmdUFMShift_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1159,6 +1187,10 @@ module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
gnd DRIVEGND( .PWR0(GNDI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -1172,7 +1204,12 @@ module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
endmodule
-module lut40013 ( input A, B, C, D, output Z );
+module lut40016 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40017 ( input A, B, C, D, output Z );
ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
@@ -1181,10 +1218,9 @@ module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
- lut40014 CmdUFMWrite_3_u_0_0_0_a3( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
+ lut40018 CmdUFMWrite_3_u_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40015 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40019 CmdUFMWrite_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1206,12 +1242,12 @@ module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
endmodule
-module lut40014 ( input A, B, C, D, output Z );
+module lut40018 ( input A, B, C, D, output Z );
ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40015 ( input A, B, C, D, output Z );
+module lut40019 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
@@ -1219,8 +1255,8 @@ endmodule
module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40016 CmdValid_2_i_o2_1_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut4 CmdValid_r( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40020 CmdValid_2_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40021 CmdValid_r( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1242,16 +1278,21 @@ module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40016 ( input A, B, C, D, output Z );
+module lut40020 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFF73) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
+module lut40021 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40017 CmdUFMData_1_sqmuxa_0_a3_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut4 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40022 CmdEnable_RNI7PMB1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40021 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1273,17 +1314,17 @@ module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40017 ( input A, B, C, D, output Z );
+module lut40022 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
- lut40013 Cmdn8MEGEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40018 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40017 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40023 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1307,7 +1348,7 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
endmodule
-module lut40018 ( input A, B, C, D, output Z );
+module lut40023 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
@@ -1315,9 +1356,9 @@ endmodule
module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40019 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40024 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40006 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40006 nFWE_pad_RNI420B( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1335,17 +1376,42 @@ module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40019 ( input A, B, C, D, output Z );
+module lut40024 ( input A, B, C, D, output Z );
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_26 ( input B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly;
+
+ lut40018 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40021 XOR8MEG_3_u_0_a2_2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+ endspecify
+
+endmodule
+
+module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40020 RCKEEN_8_u_0_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40021 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40021 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40025 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1353,6 +1419,7 @@ module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
@@ -1363,23 +1430,18 @@ module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40020 ( input A, B, C, D, output Z );
+module lut40025 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40021 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_27 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
+module SLICE_28 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40022 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40026 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40007 IS_n1_0_x2_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40027 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1403,22 +1465,30 @@ module SLICE_27 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
endmodule
-module lut40022 ( input A, B, C, D, output Z );
+module lut40026 ( input A, B, C, D, output Z );
ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+module lut40027 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
+ Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
- lut40006 RA10_0io_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40028 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40023 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40029 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -1433,16 +1503,21 @@ module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
endmodule
-module lut40023 ( input A, B, C, D, output Z );
+module lut40028 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_30 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40024 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40019 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40030 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40024 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1463,17 +1538,17 @@ module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40024 ( input A, B, C, D, output Z );
+module lut40030 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_31 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40025 LEDEN_6_i_m2_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40031 LEDEN_6_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40026 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40032 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1493,21 +1568,23 @@ module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40025 ( input A, B, C, D, output Z );
+module lut40031 ( input A, B, C, D, output Z );
ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40026 ( input A, B, C, D, output Z );
+module lut40032 ( input A, B, C, D, output Z );
ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
+ F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
- lut40014 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40033 \un9_RA_i_m2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
+ lut40034 un1_ADWR_i_o2_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1515,6 +1592,11 @@ module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
@@ -1527,10 +1609,20 @@ module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
endmodule
-module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
+module lut40033 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40034 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
- lut40027 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40035 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40006 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
@@ -1554,26 +1646,31 @@ module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
endmodule
-module lut40027 ( input A, B, C, D, output Z );
+module lut40035 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_33 ( input C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 );
- wire GNDI, VCCI, M0_dly, CLK_dly;
+module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
+ F1 );
+ wire VCCI, GNDI, M0_dly, CLK_dly;
- lut40028 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40014 CmdEnable_0_sqmuxa_0_a3_0_a3( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
+ lut40036 wb_cyc_stb_2_sqmuxa_i_a2_3_4( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40037 \wb_dati_5_1_iv_0_a2_1_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0));
vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
@@ -1584,17 +1681,22 @@ module SLICE_33 ( input C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 );
endmodule
-module lut40028 ( input A, B, C, D, output Z );
+module lut40036 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
+module lut40037 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
- lut40029 RCKEEN_8_u_0_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40030 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40038 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40039 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1617,22 +1719,22 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
endmodule
-module lut40029 ( input A, B, C, D, output Z );
+module lut40038 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40030 ( input A, B, C, D, output Z );
+module lut40039 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_36 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut4 RASr2_RNI6PUF( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40040 nRWE_0io_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40031 RCKE_2_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40041 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1652,18 +1754,23 @@ module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40031 ( input A, B, C, D, output Z );
+module lut40040 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40041 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_36 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
+module SLICE_37 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40032 Ready_0_sqmuxa_0_a2_4_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40042 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40043 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1684,21 +1791,21 @@ module SLICE_36 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
endmodule
-module lut40032 ( input A, B, C, D, output Z );
+module lut40042 ( input A, B, C, D, output Z );
ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40033 ( input A, B, C, D, output Z );
+module lut40043 ( input A, B, C, D, output Z );
ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40034 Ready_0_sqmuxa_0_a2_4_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40019 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40016 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40024 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1719,17 +1826,12 @@ module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40034 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40014 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1752,12 +1854,12 @@ module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40014 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1780,12 +1882,12 @@ module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40035 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40044 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1808,17 +1910,17 @@ module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module lut40035 ( input A, B, C, D, output Z );
+module lut40044 ( input A, B, C, D, output Z );
ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40014 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1841,12 +1943,12 @@ module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_43 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40035 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40044 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1869,12 +1971,12 @@ module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
+module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
- lut40004 Ready_0_sqmuxa_0_a2_4_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40019 \S_0_i_o2_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40004 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40024 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
@@ -1899,12 +2001,12 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
endmodule
-module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
+module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
- lut40036 XOR8MEG_3_u_0_0_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40037 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40045 XOR8MEG_3_u_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40046 XOR8MEG_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1929,22 +2031,22 @@ module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
endmodule
-module lut40036 ( input A, B, C, D, output Z );
+module lut40045 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40037 ( input A, B, C, D, output Z );
+module lut40046 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_45 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0,
+module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40038 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40039 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40047 CmdValid_RNITBH02( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40048 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1966,28 +2068,29 @@ module SLICE_45 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0,
endmodule
-module lut40038 ( input A, B, C, D, output Z );
+module lut40047 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40039 ( input A, B, C, D, output Z );
+module lut40048 ( input A, B, C, D, output Z );
ROM16X1A #(16'h4E4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_46 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
- F1 );
- wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
+ F0, Q0, F1 );
+ wire VCCI, DI0_dly, CLK_dly, LSR_dly;
- lut40040 nRowColSel_0_0_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40041 nRowColSel_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40049 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40050 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -2005,22 +2108,22 @@ module SLICE_46 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
endmodule
-module lut40040 ( input A, B, C, D, output Z );
+module lut40049 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40041 ( input A, B, C, D, output Z );
+module lut40050 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40042 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40042 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40051 \wb_adr_5_i_i[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40052 \wb_adr_5_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2048,18 +2151,23 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40042 ( input A, B, C, D, output Z );
+module lut40051 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
+module lut40052 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_49 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40014 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40014 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40018 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2082,25 +2190,23 @@ module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
endmodule
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
- output F0, Q0, F1, Q1 );
- wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_50 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
+ Q0, F1, Q1 );
+ wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40043 \wb_adr_5_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40043 \wb_adr_5_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40053 \wb_adr_5_i_m2_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40053 \wb_adr_5_i_m2_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
- gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -2115,18 +2221,18 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40043 ( input A, B, C, D, output Z );
+module lut40053 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCE02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hB3B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
- Q0, F1, Q1 );
+module SLICE_51 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
+ F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40014 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40043 \wb_adr_5_i_m2_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40053 \wb_adr_5_i_m2_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2136,7 +2242,6 @@ module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -2151,12 +2256,12 @@ module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
endmodule
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
- lut40044 wb_cyc_stb_4_iv_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40038 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40004 wb_cyc_stb_4_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40047 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2182,17 +2287,12 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
endmodule
-module lut40044 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40045 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40046 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40054 \wb_dati_5_1_iv_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40055 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2220,29 +2320,62 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40045 ( input A, B, C, D, output Z );
+module lut40054 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40046 ( input A, B, C, D, output Z );
+module lut40055 ( input A, B, C, D, output Z );
ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
- F0, Q0, F1, Q1 );
- wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+ output F0, Q0, F1, Q1 );
+ wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40047 \wb_dati_5_1_iv_i_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40048 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
+ lut40052 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40052 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ (CLK => Q1) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+ $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_55 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
+ F0, Q0, F1, Q1 );
+ wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+ lut40052 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40028 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+ vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
+ .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
+ .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
@@ -2262,59 +2395,12 @@ module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
endmodule
-module lut40047 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
- F0, Q0, F1, Q1 );
- wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
- lut40048 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40049 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
- .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
- vcc DRIVEVCC( .PWR1(VCCI));
- vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
- .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- (CLK => Q1) = (0:0:0,0:0:0);
- $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
- $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
- $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- endspecify
-
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFF4A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40050 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40045 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40056 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40057 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2342,17 +2428,22 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40050 ( input A, B, C, D, output Z );
+module lut40056 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hEFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0,
+module lut40057 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
- lut40051 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40025 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40058 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40031 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
@@ -2377,17 +2468,17 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0,
endmodule
-module lut40051 ( input A, B, C, D, output Z );
+module lut40058 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
+module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
- lut40051 \FS_RNIHVJI_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40052 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40036 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40059 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2410,17 +2501,17 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
endmodule
-module lut40052 ( input A, B, C, D, output Z );
+module lut40059 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hD850) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
- lut40043 \wb_adr_5_i_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40053 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40055 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40060 wb_we_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2446,60 +2537,15 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
endmodule
-module lut40053 ( input A, B, C, D, output Z );
+module lut40060 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h008B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0,
- M0, output OFX0 );
- wire
- \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ,
- \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ;
-
- lut40054 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1),
- .D(D1),
- .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ));
- lut40055 \wb_dati_5_1_iv_0_o3[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ));
- selmux2 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K0K1MUX (
- .D0(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ),
- .D1(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ),
- .SD(M0), .Z(OFX0));
-
- specify
- (D1 => OFX0) = (0:0:0,0:0:0);
- (C1 => OFX0) = (0:0:0,0:0:0);
- (B1 => OFX0) = (0:0:0,0:0:0);
- (A1 => OFX0) = (0:0:0,0:0:0);
- (D0 => OFX0) = (0:0:0,0:0:0);
- (C0 => OFX0) = (0:0:0,0:0:0);
- (B0 => OFX0) = (0:0:0,0:0:0);
- (A0 => OFX0) = (0:0:0,0:0:0);
- (M0 => OFX0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
- MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+ ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40056 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40057 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40061 \wb_dati_5_1_iv_0_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40019 \wb_dati_5_1_iv_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2514,96 +2560,15 @@ module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40056 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40058 un1_nRCAS_6_sqmuxa_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40018 nRCAS_r_i_0_o2_0_2_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0FEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40044 \wb_adr_5_i_0_a2_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40059 wb_we_0_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40059 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40060 wb_we_0_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40061 wb_we_0_i_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFDF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
module lut40061 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40062 un1_CmdEnable20_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40063 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40062 wb_cyc_stb_2_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40063 \wb_adr_5_i_i_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2620,18 +2585,18 @@ endmodule
module lut40062 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40063 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hBA30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40064 \wb_adr_5_i_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40065 \wb_adr_5_i_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40064 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40065 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2648,18 +2613,18 @@ endmodule
module lut40064 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40065 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40066 \FS_RNIHVJI[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40013 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40036 wb_we_0_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40066 wb_we_0_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2676,67 +2641,13 @@ endmodule
module lut40066 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40067 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40068 \wb_adr_5_i_0_o2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h1BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h1919) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_68 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40032 \FS_RNIF2MA[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40069 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(B0), .C(C0), .D(GNDI),
- .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40070 \wb_dati_5_1_iv_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40034 \wb_dati_5_1_iv_0_a3_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
+ lut40067 CmdEnable_0_sqmuxa_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40068 un1_CmdEnable20_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2751,23 +2662,56 @@ module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40070 ( input A, B, C, D, output Z );
+module lut40067 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module lut40068 ( input A, B, C, D, output Z );
- lut40034 \wb_adr_5_i_0_a3_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40071 \FS_RNIJO0F[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
+ ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40069 \wb_adr_5_i_i_0_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40070 \wb_adr_5_i_i_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40070 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0804) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40071 \wb_adr_5_i_i_a2_3_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40072 \wb_adr_5_i_i_1_0_tz_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -2777,14 +2721,20 @@ endmodule
module lut40071 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+module lut40072 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40072 \wb_dati_5_1_iv_i_i_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40073 \wb_dati_5_1_iv_i_i_1_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
+ lut40037 wb_cyc_stb_2_sqmuxa_i_o2_RNI167R( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40073 \ufmefb/EFBInst_0_RNI8K48 ( .A(A0), .B(B0), .C(C0), .D(GNDI),
.Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
@@ -2800,21 +2750,16 @@ module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
endmodule
-module lut40072 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
module lut40073 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2A2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+module SLICE_68 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40074 nRCS_9_u_i_0_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40075 Ready_RNICVV51( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40074 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40071 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
specify
@@ -2831,26 +2776,22 @@ endmodule
module lut40074 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40075 ( input A, B, C, D, output Z );
+module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40076 \wb_dati_5_1_iv_i_i_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40056 \wb_dati_5_1_iv_i_i_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ lut40075 \wb_dati_5_1_iv_0_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40076 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
.Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -2858,19 +2799,43 @@ module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40076 ( input A, B, C, D, output Z );
+module lut40075 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40076 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h9B9B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40077 un1_nRCAS_6_sqmuxa_i_0_0_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI),
+ lut40007 \wb_dati_5_1_iv_0_a2_3_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1));
+ lut40073 \wb_dati_5_1_iv_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
+ .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
- lut40078 un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER( .A(A0), .B(B0), .C(C0),
- .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40077 wb_we_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40078 wb_we_0_0_0_a2_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(C1 => F1) = (0:0:0,0:0:0);
@@ -2886,22 +2851,23 @@ endmodule
module lut40077 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40078 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_75 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40079 \wb_adr_5_i_0_a2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40080 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40079 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40080 \wb_dati_5_1_iv_0_a2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -2914,123 +2880,30 @@ endmodule
module lut40079 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40080 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h08AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
+ Q0, F1, Q1 );
+ wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
- lut40081 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40042 \wb_dati_5_1_iv_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h1019) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40017 \FS_RNIGOCT[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40082 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40082 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40083 nRCS_9_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40084 nRRAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40083 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40084 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40020 nRCS_9_u_i_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40051 nRCS_9_u_i_0_o2_1_RNIL2K71_0( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_80 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
- F1, Q1 );
- wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
- lut40085 un1_CmdEnable20_0_0_a3_1_1( .A(A1), .B(B1), .C(C1), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40086 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40081 un1_CmdEnable20_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 CmdEnable17_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN),
.LSR(GNDI), .Q(Q0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
@@ -3048,25 +2921,198 @@ module SLICE_80 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
endmodule
+module lut40081 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40030 CmdUFMData_1_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_75 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40064 un1_ADWR_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut4 XOR8MEG18_0_a2_0( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, M0_dly, CLK_dly;
+
+ lut40018 CmdEnable_0_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40004 CmdEnable_0_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
+ .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40071 \wb_adr_5_i_i_a2_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40054 \wb_adr_5_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40024 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40082 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40082 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40071 \wb_adr_5_i_i_a2_11[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40083 \wb_dati_5_1_iv_0_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40083 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40084 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40067 \wb_dati_5_1_iv_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40084 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40085 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40086 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
module lut40085 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40086 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_81 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_82 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40087 RCKEEN_8_u_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut4 \wb_dati_5_1_iv_0_a2_2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40088 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40087 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
- (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3079,48 +3125,33 @@ endmodule
module lut40087 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40088 ( input A, B, C, D, output Z );
+module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 );
- wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
-
- lut40044 CmdLEDEN_4_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40014 CmdUFMData_1_sqmuxa_0_a3( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
- .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
- vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
- vcc DRIVEVCC( .PWR1(VCCI));
- inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+ lut40037 \wb_dati_5_1_iv_0_a2_9[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40019 \wb_dati_5_1_iv_0_o2_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
- $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
-module SLICE_83 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_84 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40079 nRCAS_r_i_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40021 \FS_RNICHC8[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40089 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40083 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
@@ -3133,15 +3164,10 @@ module SLICE_83 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40089 ( input A, B, C, D, output Z );
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- ROM16X1A #(16'h0515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40090 un1_CmdEnable20_0_0_o3_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40091 un1_CmdEnable20_0_0_o3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40088 \wb_adr_5_i_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40089 \wb_adr_5_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -3156,66 +3182,150 @@ module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40088 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40089 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40044 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40090 \wb_adr_5_i_i_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
module lut40090 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40008 wb_cyc_stb_2_sqmuxa_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40057 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40021 \wb_dati_5_1_iv_0_a2_7[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40067 \wb_adr_5_i_i_a2_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40034 un1_ADWR_i_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40062 un1_ADWR_i_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40091 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40092 nRCS_9_u_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40091 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40024 \wb_dati_5_1_iv_0_a3_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40047 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40092 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40047 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40092 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_91 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40071 \wb_dati_5_1_iv_i_i_a2_4[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
+ lut40021 wb_cyc_stb_2_sqmuxa_i_a2_3_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40093 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40049 wb_cyc_stb_2_sqmuxa_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40093 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 nRWE_s_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
@@ -3229,17 +3339,55 @@ endmodule
module lut40093 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_93 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40050 nRCS_9_u_i_0_o2_1_RNIL2K71( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40094 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut4 XOR8MEG_3_u_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40004 XOR8MEG_3_u_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40008 \wb_dati_5_1_iv_0_o2_0[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40088 \wb_dati_5_1_iv_0_a2_1_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40040 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40094 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3252,18 +3400,17 @@ endmodule
module lut40094 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40008 \wb_dati_5_1_iv_0_o2_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40095 \wb_dati_5_1_iv_0_a3[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40095 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40096 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3276,83 +3423,46 @@ endmodule
module lut40095 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40042 nRWE_s_i_0_a3_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40065 nRWE_s_i_0_tz_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40017 \wb_dati_5_1_iv_i_i_a3_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- lut40047 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40096 wb_cyc_stb_2_sqmuxa_i_a3_0( .A(A1), .B(B1), .C(C1), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40097 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40096 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hC4C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40073 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40097 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40097 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40090 un1_CmdEnable20_0_0_o3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40098 un1_CmdEnable20_0_0_o3_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40077 \wb_adr_5_i_i_a2_6_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40098 \wb_dati_5_1_iv_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
@@ -3366,13 +3476,33 @@ endmodule
module lut40098 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40084 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40099 nRCAS_r_i_0_o2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40071 \FS_RNI1FVB[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40007 \wb_dati_5_1_iv_0_a2_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40099 \wb_dati_5_0_iv_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40100 \wb_dati_5_1_iv_0_0_o2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -3389,16 +3519,20 @@ endmodule
module lut40099 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40100 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut4 \wb_dati_5_1_iv_i_i_a2_2[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
+ lut40084 \FS_RNI7O57[11] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40100 wb_we_0_i_0_a3_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40067 \wb_dati_5_1_iv_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
@@ -3411,22 +3545,34 @@ module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40100 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_102 ( input B1, A1, B0, A0, output F0, F1 );
wire GNDI;
- lut4 \wb_adr_5_i_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40084 RDQML_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40101 \wb_adr_5_i_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40044 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_103 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40081 InitReady3_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40028 \FS_RNIQV0F[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -3434,36 +3580,35 @@ module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40101 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40024 XOR8MEG_3_u_0_o2_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
module lut40101 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hC800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40019 \FS_RNIH267[16] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40021 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40043 \wb_adr_5_i_0_m2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40079 wb_cyc_stb_4_iv_0_a3_0_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40102 wb_cyc_stb_4_iv_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40102 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
@@ -3478,17 +3623,17 @@ endmodule
module lut40102 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40014 CmdLEDEN_4_u_i_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40056 un1_CmdEnable20_0_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40067 XOR8MEG18_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 un1_CmdEnable20_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3499,37 +3644,18 @@ module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_107 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40019 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40079 \FS_RNITL2J[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40103 \wb_adr_5_i_i_a2_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
- lut40056 XOR8MEG_3_u_0_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40040 \wb_dati_5_1_iv_0_a2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40103 \wb_dati_5_1_iv_0_a3_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -3539,18 +3665,18 @@ endmodule
module lut40103 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_102 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40014 \wb_dati_5_0_iv_0_a2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
+ lut40104 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40104 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40017 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3563,20 +3689,20 @@ endmodule
module lut40104 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_109 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40040 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40033 \un9_RA_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40105 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40105 un1_ADWR_i_o2_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -3586,21 +3712,20 @@ endmodule
module lut40105 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_110 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40085 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40033 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40004 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40033 \un9_RA_i_m2[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -3608,15 +3733,14 @@ module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40106 \wb_adr_5_i_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40069 wb_we_0_i_0_0_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40033 \un9_RA_i_m2[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
+ lut40033 \un9_RA_i_m2[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
@@ -3627,372 +3751,90 @@ module SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
endmodule
+module SLICE_112 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40033 \un9_RA_i_m2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40033 \un9_RA_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40033 \un9_RA_i_m2[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40033 \un9_RA_i_m2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_114 ( input A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40006 RA10_0io_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40071 nRWE_0io_RNO_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+ specify
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40018 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40106 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
module lut40106 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_106 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40107 \wb_adr_5_i_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40108 \wb_adr_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40107 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hA300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40108 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
- F1 );
- wire GNDI, VCCI, M0_dly, CLK_dly;
-
- lut40108 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40109 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
- .LSR(GNDI), .Q(Q0));
- vcc DRIVEVCC( .PWR1(VCCI));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- endspecify
-
-endmodule
-
-module lut40109 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40110 RCKEEN_8_u_0_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40056 nRWE_s_i_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40110 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_109 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40111 \wb_dati_5_1_iv_i_i_a3_1_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- lut40112 \wb_adr_5_i_0_o2_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40111 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40112 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40113 \wb_adr_5_i_0_a3_0_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40114 \wb_dati_5_1_iv_i_i_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40113 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40114 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_111 ( input B1, A1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40020 RDQML_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40035 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_112 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40034 un1_CmdEnable20_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut4 XOR8MEG_3_u_0_0_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_113 ( input B1, A1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40079 \FS_RNI7U6M[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40079 \wb_dati_5_1_iv_i_i_a2_3[3] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
- .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40028 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40115 un1_CmdEnable20_0_0_o3_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40115 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_115 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40028 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40028 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_116 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40028 \un9_RA_i_m2_i_m2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40028 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_117 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40028 \un9_RA_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40028 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_118 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40028 \un9_RA_i_m2_i_m2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40028 \un9_RA_i_m2_i_m2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_119 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40116 CmdLEDEN_4_u_i_0_a3_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40079 XOR8MEG_3_u_0_0_a2_0( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40116 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_120 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40014 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40117 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40117 ( input A, B, C, D, output Z );
-
ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_121 ( input B1, A1, C0, B0, A0, output F0, F1 );
+module SLICE_116 ( input B1, A1, B0, A0, output F0, F1 );
wire GNDI;
- lut40014 wb_cyc_stb_4_iv_0_a3_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ lut40018 \wb_dati_5_1_iv_0_a2_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40071 wb_cyc_stb_4_iv_0_a3_0_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_122 ( input C1, B1, A1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40118 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
lut40040 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
specify
- (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -4001,22 +3843,17 @@ module SLICE_122 ( input C1, B1, A1, B0, A0, output F0, F1 );
endmodule
-module lut40118 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_123 ( input B1, A1, C0, B0, A0, output F0, F1 );
+module SLICE_117 ( input C1, B1, A1, B0, A0, output F0, F1 );
wire GNDI;
- lut40020 \wb_adr_5_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40103 RCKEEN_8_u_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40085 InitReady3_0_a3_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut4 nRCAS_0io_RNO_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
specify
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
@@ -4069,7 +3906,7 @@ endmodule
module Dout_0_ ( input PADDO, output Dout0 );
- xo2iobuf0119 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+ xo2iobuf0107 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
specify
(PADDO => Dout0) = (0:0:0,0:0:0);
@@ -4077,14 +3914,14 @@ module Dout_0_ ( input PADDO, output Dout0 );
endmodule
-module xo2iobuf0119 ( input I, output PAD );
+module xo2iobuf0107 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module PHI2 ( output PADDI, input PHI2 );
- xo2iobuf0120 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+ xo2iobuf0108 PHI2_pad( .Z(PADDI), .PAD(PHI2));
specify
(PHI2 => PADDI) = (0:0:0,0:0:0);
@@ -4094,7 +3931,7 @@ module PHI2 ( output PADDI, input PHI2 );
endmodule
-module xo2iobuf0120 ( output Z, input PAD );
+module xo2iobuf0108 ( output Z, input PAD );
IB INST1( .I(PAD), .O(Z));
endmodule
@@ -4124,7 +3961,7 @@ endmodule
module RDQML ( input PADDO, output RDQML );
- xo2iobuf0121 RDQML_pad( .I(PADDO), .PAD(RDQML));
+ xo2iobuf0109 RDQML_pad( .I(PADDO), .PAD(RDQML));
specify
(PADDO => RDQML) = (0:0:0,0:0:0);
@@ -4132,14 +3969,14 @@ module RDQML ( input PADDO, output RDQML );
endmodule
-module xo2iobuf0121 ( input I, output PAD );
+module xo2iobuf0109 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module RDQMH ( input PADDO, output RDQMH );
- xo2iobuf0121 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+ xo2iobuf0109 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
specify
(PADDO => RDQMH) = (0:0:0,0:0:0);
@@ -4149,7 +3986,7 @@ endmodule
module nRCAS ( input IOLDO, output nRCAS );
- xo2iobuf0121 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
+ xo2iobuf0109 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
specify
(IOLDO => nRCAS) = (0:0:0,0:0:0);
@@ -4160,7 +3997,7 @@ endmodule
module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0122 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0110 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4174,7 +4011,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
endmodule
-module mfflsre0122 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0110 ( input D0, SP, CK, LSR, output Q );
FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
@@ -4182,7 +4019,7 @@ endmodule
module nRRAS ( input IOLDO, output nRRAS );
- xo2iobuf0121 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
+ xo2iobuf0109 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
specify
(IOLDO => nRRAS) = (0:0:0,0:0:0);
@@ -4193,7 +4030,7 @@ endmodule
module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0122 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0110 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4209,7 +4046,7 @@ endmodule
module nRWE ( input IOLDO, output nRWE );
- xo2iobuf0121 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+ xo2iobuf0109 nRWE_pad( .I(IOLDO), .PAD(nRWE));
specify
(IOLDO => nRWE) = (0:0:0,0:0:0);
@@ -4220,7 +4057,7 @@ endmodule
module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0122 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0110 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4236,7 +4073,7 @@ endmodule
module RCKE ( input PADDO, output RCKE );
- xo2iobuf0121 RCKE_pad( .I(PADDO), .PAD(RCKE));
+ xo2iobuf0109 RCKE_pad( .I(PADDO), .PAD(RCKE));
specify
(PADDO => RCKE) = (0:0:0,0:0:0);
@@ -4244,9 +4081,42 @@ module RCKE ( input PADDO, output RCKE );
endmodule
+module RCLKout ( input IOLDO, output RCLKout );
+
+ xo2iobuf0107 RCLKout_pad( .I(IOLDO), .PAD(RCLKout));
+
+ specify
+ (IOLDO => RCLKout) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK );
+ wire GNDI, ONEG_dly, CLK_dly, OPOS_dly;
+
+ xo2oddr rck( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI),
+ .Q(IOLDO));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (CLK => IOLDO) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, ONEG, 0:0:0, 0:0:0,,,, CLK_dly, ONEG_dly);
+ $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ endspecify
+
+endmodule
+
+module xo2oddr ( input D0, D1, SCLK, RST, output Q );
+
+ ODDRXE INST1( .D0(D0), .D1(D1), .SCLK(SCLK), .RST(RST), .Q(Q));
+ defparam INST1.GSR = "DISABLED";
+endmodule
+
module RCLK ( output PADDI, input RCLK );
- xo2iobuf0120 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+ xo2iobuf0108 RCLK_pad( .Z(PADDI), .PAD(RCLK));
specify
(RCLK => PADDI) = (0:0:0,0:0:0);
@@ -4258,7 +4128,7 @@ endmodule
module nRCS ( input IOLDO, output nRCS );
- xo2iobuf0121 nRCS_pad( .I(IOLDO), .PAD(nRCS));
+ xo2iobuf0109 nRCS_pad( .I(IOLDO), .PAD(nRCS));
specify
(IOLDO => nRCS) = (0:0:0,0:0:0);
@@ -4269,7 +4139,7 @@ endmodule
module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0122 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0110 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4509,7 +4379,7 @@ endmodule
module RA_11_ ( input IOLDO, output RA11 );
- xo2iobuf0121 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+ xo2iobuf0109 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
specify
(IOLDO => RA11) = (0:0:0,0:0:0);
@@ -4536,7 +4406,7 @@ endmodule
module RA_10_ ( input IOLDO, output RA10 );
- xo2iobuf0121 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+ xo2iobuf0109 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
specify
(IOLDO => RA10) = (0:0:0,0:0:0);
@@ -4547,7 +4417,7 @@ endmodule
module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
wire VCCI, OPOS_dly, CLK_dly, LSR_dly;
- mfflsre0123 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
+ mfflsre0111 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -4561,7 +4431,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
endmodule
-module mfflsre0123 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0111 ( input D0, SP, CK, LSR, output Q );
FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
@@ -4569,7 +4439,7 @@ endmodule
module RA_9_ ( input PADDO, output RA9 );
- xo2iobuf0121 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+ xo2iobuf0109 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
specify
(PADDO => RA9) = (0:0:0,0:0:0);
@@ -4579,7 +4449,7 @@ endmodule
module RA_8_ ( input PADDO, output RA8 );
- xo2iobuf0121 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+ xo2iobuf0109 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
specify
(PADDO => RA8) = (0:0:0,0:0:0);
@@ -4589,7 +4459,7 @@ endmodule
module RA_7_ ( input PADDO, output RA7 );
- xo2iobuf0121 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+ xo2iobuf0109 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
specify
(PADDO => RA7) = (0:0:0,0:0:0);
@@ -4599,7 +4469,7 @@ endmodule
module RA_6_ ( input PADDO, output RA6 );
- xo2iobuf0121 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+ xo2iobuf0109 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
specify
(PADDO => RA6) = (0:0:0,0:0:0);
@@ -4609,7 +4479,7 @@ endmodule
module RA_5_ ( input PADDO, output RA5 );
- xo2iobuf0121 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+ xo2iobuf0109 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
specify
(PADDO => RA5) = (0:0:0,0:0:0);
@@ -4619,7 +4489,7 @@ endmodule
module RA_4_ ( input PADDO, output RA4 );
- xo2iobuf0121 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+ xo2iobuf0109 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
specify
(PADDO => RA4) = (0:0:0,0:0:0);
@@ -4629,7 +4499,7 @@ endmodule
module RA_3_ ( input PADDO, output RA3 );
- xo2iobuf0121 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+ xo2iobuf0109 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
specify
(PADDO => RA3) = (0:0:0,0:0:0);
@@ -4639,7 +4509,7 @@ endmodule
module RA_2_ ( input PADDO, output RA2 );
- xo2iobuf0121 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+ xo2iobuf0109 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
specify
(PADDO => RA2) = (0:0:0,0:0:0);
@@ -4649,7 +4519,7 @@ endmodule
module RA_1_ ( input PADDO, output RA1 );
- xo2iobuf0121 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+ xo2iobuf0109 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
specify
(PADDO => RA1) = (0:0:0,0:0:0);
@@ -4659,7 +4529,7 @@ endmodule
module RA_0_ ( input PADDO, output RA0 );
- xo2iobuf0121 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+ xo2iobuf0109 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
specify
(PADDO => RA0) = (0:0:0,0:0:0);
@@ -4669,7 +4539,7 @@ endmodule
module RBA_1_ ( input IOLDO, output RBA1 );
- xo2iobuf0121 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
+ xo2iobuf0109 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
specify
(IOLDO => RBA1) = (0:0:0,0:0:0);
@@ -4697,7 +4567,7 @@ endmodule
module RBA_0_ ( input IOLDO, output RBA0 );
- xo2iobuf0121 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
+ xo2iobuf0109 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
specify
(IOLDO => RBA0) = (0:0:0,0:0:0);
@@ -4725,7 +4595,7 @@ endmodule
module LED ( input PADDO, output LED );
- xo2iobuf0124 LED_pad( .I(PADDO), .PAD(LED));
+ xo2iobuf0112 LED_pad( .I(PADDO), .PAD(LED));
specify
(PADDO => LED) = (0:0:0,0:0:0);
@@ -4733,14 +4603,14 @@ module LED ( input PADDO, output LED );
endmodule
-module xo2iobuf0124 ( input I, output PAD );
+module xo2iobuf0112 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module nFWE ( output PADDI, input nFWE );
- xo2iobuf0120 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+ xo2iobuf0108 nFWE_pad( .Z(PADDI), .PAD(nFWE));
specify
(nFWE => PADDI) = (0:0:0,0:0:0);
@@ -4752,7 +4622,7 @@ endmodule
module nCRAS ( output PADDI, input nCRAS );
- xo2iobuf0120 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+ xo2iobuf0108 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
specify
(nCRAS => PADDI) = (0:0:0,0:0:0);
@@ -4764,7 +4634,7 @@ endmodule
module nCCAS ( output PADDI, input nCCAS );
- xo2iobuf0120 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+ xo2iobuf0108 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
specify
(nCCAS => PADDI) = (0:0:0,0:0:0);
@@ -4776,7 +4646,7 @@ endmodule
module Dout_7_ ( input PADDO, output Dout7 );
- xo2iobuf0119 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+ xo2iobuf0107 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
specify
(PADDO => Dout7) = (0:0:0,0:0:0);
@@ -4786,7 +4656,7 @@ endmodule
module Dout_6_ ( input PADDO, output Dout6 );
- xo2iobuf0119 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+ xo2iobuf0107 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
specify
(PADDO => Dout6) = (0:0:0,0:0:0);
@@ -4796,7 +4666,7 @@ endmodule
module Dout_5_ ( input PADDO, output Dout5 );
- xo2iobuf0119 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+ xo2iobuf0107 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
specify
(PADDO => Dout5) = (0:0:0,0:0:0);
@@ -4806,7 +4676,7 @@ endmodule
module Dout_4_ ( input PADDO, output Dout4 );
- xo2iobuf0119 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+ xo2iobuf0107 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
specify
(PADDO => Dout4) = (0:0:0,0:0:0);
@@ -4816,7 +4686,7 @@ endmodule
module Dout_3_ ( input PADDO, output Dout3 );
- xo2iobuf0119 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+ xo2iobuf0107 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
specify
(PADDO => Dout3) = (0:0:0,0:0:0);
@@ -4826,7 +4696,7 @@ endmodule
module Dout_2_ ( input PADDO, output Dout2 );
- xo2iobuf0119 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+ xo2iobuf0107 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
specify
(PADDO => Dout2) = (0:0:0,0:0:0);
@@ -4836,7 +4706,7 @@ endmodule
module Dout_1_ ( input PADDO, output Dout1 );
- xo2iobuf0119 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+ xo2iobuf0107 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
specify
(PADDO => Dout1) = (0:0:0,0:0:0);
@@ -4846,7 +4716,7 @@ endmodule
module Din_7_ ( output PADDI, input Din7 );
- xo2iobuf0120 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+ xo2iobuf0108 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
specify
(Din7 => PADDI) = (0:0:0,0:0:0);
@@ -4875,7 +4745,7 @@ endmodule
module Din_6_ ( output PADDI, input Din6 );
- xo2iobuf0120 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+ xo2iobuf0108 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
specify
(Din6 => PADDI) = (0:0:0,0:0:0);
@@ -4904,7 +4774,7 @@ endmodule
module Din_5_ ( output PADDI, input Din5 );
- xo2iobuf0120 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+ xo2iobuf0108 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
specify
(Din5 => PADDI) = (0:0:0,0:0:0);
@@ -4933,7 +4803,7 @@ endmodule
module Din_4_ ( output PADDI, input Din4 );
- xo2iobuf0120 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+ xo2iobuf0108 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
specify
(Din4 => PADDI) = (0:0:0,0:0:0);
@@ -4962,7 +4832,7 @@ endmodule
module Din_3_ ( output PADDI, input Din3 );
- xo2iobuf0120 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+ xo2iobuf0108 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
specify
(Din3 => PADDI) = (0:0:0,0:0:0);
@@ -4991,7 +4861,7 @@ endmodule
module Din_2_ ( output PADDI, input Din2 );
- xo2iobuf0120 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+ xo2iobuf0108 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
specify
(Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5020,7 +4890,7 @@ endmodule
module Din_1_ ( output PADDI, input Din1 );
- xo2iobuf0120 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+ xo2iobuf0108 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
specify
(Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5049,7 +4919,7 @@ endmodule
module Din_0_ ( output PADDI, input Din0 );
- xo2iobuf0120 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+ xo2iobuf0108 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
specify
(Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5078,7 +4948,7 @@ endmodule
module CROW_1_ ( output PADDI, input CROW1 );
- xo2iobuf0120 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+ xo2iobuf0108 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
specify
(CROW1 => PADDI) = (0:0:0,0:0:0);
@@ -5090,7 +4960,7 @@ endmodule
module CROW_0_ ( output PADDI, input CROW0 );
- xo2iobuf0120 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+ xo2iobuf0108 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
specify
(CROW0 => PADDI) = (0:0:0,0:0:0);
@@ -5102,7 +4972,7 @@ endmodule
module MAin_9_ ( output PADDI, input MAin9 );
- xo2iobuf0120 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+ xo2iobuf0108 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
specify
(MAin9 => PADDI) = (0:0:0,0:0:0);
@@ -5114,7 +4984,7 @@ endmodule
module MAin_8_ ( output PADDI, input MAin8 );
- xo2iobuf0120 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+ xo2iobuf0108 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
specify
(MAin8 => PADDI) = (0:0:0,0:0:0);
@@ -5126,7 +4996,7 @@ endmodule
module MAin_7_ ( output PADDI, input MAin7 );
- xo2iobuf0120 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+ xo2iobuf0108 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
specify
(MAin7 => PADDI) = (0:0:0,0:0:0);
@@ -5138,7 +5008,7 @@ endmodule
module MAin_6_ ( output PADDI, input MAin6 );
- xo2iobuf0120 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+ xo2iobuf0108 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
specify
(MAin6 => PADDI) = (0:0:0,0:0:0);
@@ -5150,7 +5020,7 @@ endmodule
module MAin_5_ ( output PADDI, input MAin5 );
- xo2iobuf0120 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+ xo2iobuf0108 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
specify
(MAin5 => PADDI) = (0:0:0,0:0:0);
@@ -5162,7 +5032,7 @@ endmodule
module MAin_4_ ( output PADDI, input MAin4 );
- xo2iobuf0120 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+ xo2iobuf0108 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
specify
(MAin4 => PADDI) = (0:0:0,0:0:0);
@@ -5174,7 +5044,7 @@ endmodule
module MAin_3_ ( output PADDI, input MAin3 );
- xo2iobuf0120 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+ xo2iobuf0108 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
specify
(MAin3 => PADDI) = (0:0:0,0:0:0);
@@ -5186,7 +5056,7 @@ endmodule
module MAin_2_ ( output PADDI, input MAin2 );
- xo2iobuf0120 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+ xo2iobuf0108 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
specify
(MAin2 => PADDI) = (0:0:0,0:0:0);
@@ -5198,7 +5068,7 @@ endmodule
module MAin_1_ ( output PADDI, input MAin1 );
- xo2iobuf0120 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+ xo2iobuf0108 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
specify
(MAin1 => PADDI) = (0:0:0,0:0:0);
@@ -5210,7 +5080,7 @@ endmodule
module MAin_0_ ( output PADDI, input MAin0 );
- xo2iobuf0120 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+ xo2iobuf0108 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
specify
(MAin0 => PADDI) = (0:0:0,0:0:0);
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
index d43e751..11861ea 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
@@ -23,23 +23,35 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
-Mapped on: 09/21/23 05:39:45
+Mapped on: 10/19/23 23:50:56
Design Summary
- Number of registers: 109 out of 1520 (7%)
- PFU registers: 84 out of 1280 (7%)
+ Number of registers: 110 out of 1520 (7%)
+ PFU registers: 85 out of 1280 (7%)
PIO registers: 25 out of 240 (10%)
- Number of SLICEs: 120 out of 640 (19%)
- SLICEs as Logic/ROM: 120 out of 640 (19%)
+ Number of SLICEs: 115 out of 640 (18%)
+ SLICEs as Logic/ROM: 115 out of 640 (18%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 10 out of 640 (2%)
- Number of LUT4s: 237 out of 1280 (19%)
- Number used as logic LUTs: 217
+ Number of LUT4s: 229 out of 1280 (18%)
+ Number used as logic LUTs: 209
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
- Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
+ Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
+ Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
+ Number of IDDR cells: 0
+ Number of ODDR cells: 1
+ Number of TDDR cells: 0
+ Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
+ Number of PIO using IDDR only: 0 (0 differential)
+ Number of PIO using ODDR only: 1 (0 differential)
+ Number of PIO using TDDR only: 0 (0 differential)
+ Number of PIO using IDDR/ODDR: 0 (0 differential)
+ Number of PIO using IDDR/TDDR: 0 (0 differential)
+ Number of PIO using ODDR/TDDR: 0 (0 differential)
+ Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
@@ -55,6 +67,7 @@ Mapped on: 09/21/23 05:39:45
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
+
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
@@ -66,15 +79,14 @@ Mapped on: 09/21/23 05:39:45
ripple logic.
Number of clocks: 4
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
- Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
-
- Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
+ Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
+ Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 5
- Net N_178: 1 loads, 1 LSLICEs
+ Net N_103: 1 loads, 1 LSLICEs
Net XOR8MEG18: 5 loads, 5 LSLICEs
- Net N_360_i: 2 loads, 2 LSLICEs
- Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
+ Net N_122: 9 loads, 9 LSLICEs
+ Net N_244_i: 2 loads, 2 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
@@ -84,16 +96,16 @@ Mapped on: 09/21/23 05:39:45
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
- Net InitReady: 41 loads
- Net FS[11]: 23 loads
- Net FS[13]: 22 loads
- Net FS[10]: 21 loads
- Net FS[12]: 21 loads
- Net FS[9]: 20 loads
+ Net InitReady: 31 loads
+ Net FS[12]: 23 loads
+ Net FS[13]: 23 loads
+ Net FS[11]: 21 loads
+ Net N_132: 20 loads
Net FS[14]: 18 loads
- Net CO0: 15 loads
+ Net FS[10]: 16 loads
+ Net FS[9]: 14 loads
+ Net Ready: 14 loads
Net Ready_fast: 14 loads
- Net N_214: 13 loads
@@ -116,6 +128,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
@@ -127,7 +140,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN |
-
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -141,6 +153,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
+| RCLKout | OUTPUT | LVCMOS33 | |
++---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
@@ -172,6 +186,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | |
+
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -184,7 +199,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
-
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
@@ -229,6 +243,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | |
+
+---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -241,7 +256,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | |
-
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@@ -260,7 +274,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
-Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
@@ -288,6 +301,7 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
@@ -299,7 +313,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
@@ -326,7 +339,6 @@ Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
-Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@@ -347,6 +359,7 @@ Block ufmefb/GND was optimized away.
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
+
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
@@ -357,7 +370,6 @@ Block ufmefb/GND was optimized away.
Timer/Counter Function Summary:
------------------------------
None
-
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
@@ -400,16 +412,6 @@ Instance Name: ufmefb/EFBInst_0
-
-
-
-
-
-
-
-
-
-
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
index ebbb023..2dd6f36 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
-Thu Sep 21 05:39:56 2023
+Thu Oct 19 23:51:05 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -61,11 +61,12 @@ Pinout by Port Name:
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
-| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
+| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
+| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST |
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
@@ -143,7 +144,7 @@ Vccio by Bank:
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
-| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
+| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
@@ -155,7 +156,7 @@ Vccio by Bank:
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
-| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
+| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
@@ -273,11 +274,12 @@ LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65";
-LOCATE COMP "RA[9]" SITE "62";
+LOCATE COMP "RA[9]" SITE "47";
LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "63";
+LOCATE COMP "RCLKout" SITE "62";
LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36";
@@ -306,7 +308,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
-Thu Sep 21 05:39:59 2023
+Thu Oct 19 23:51:08 2023
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
index 8d70ad1..99bd304 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
-Thu Sep 21 05:39:49 2023
+Thu Oct 19 23:50:59 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
@@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
-5_1 * 0 5.578 0 0.304 0 13 Completed
+5_1 * 0 5.798 0 0.304 0 12 Completed
* : Design saved.
-Total (real) run time for 1-seed: 13 secs
+Total (real) run time for 1-seed: 12 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
-Thu Sep 21 05:39:49 2023
+Thu Oct 19 23:50:59 2023
Best Par Run
@@ -63,47 +63,47 @@ Ignore Preference Error(s): True
Device utilization summary:
- PIO (prelim) 63+4(JTAG)/108 62% used
- 63+4(JTAG)/80 84% bonded
- IOLOGIC 25/108 23% used
+ PIO (prelim) 64+4(JTAG)/108 63% used
+ 64+4(JTAG)/80 85% bonded
+ IOLOGIC 26/108 24% used
- SLICE 120/640 18% used
+ SLICE 115/640 17% used
EFB 1/1 100% used
-Number of Signals: 388
-Number of Connections: 1017
+Number of Signals: 383
+Number of Connections: 993
Pin Constraint Summary:
- 63 out of 63 pins locked (100% locked).
+ 64 out of 64 pins locked (100% locked).
-The following 2 signals are selected to use the primary clock routing resources:
- RCLK_c (driver: RCLK, clk load #: 47)
+The following 3 signals are selected to use the primary clock routing resources:
+ RCLK_c (driver: RCLK, clk load #: 48)
PHI2_c (driver: PHI2, clk load #: 20)
+ nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-The following 2 signals are selected to use the secondary clock routing resources:
- nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
+The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
-WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
-.........
-Finished Placer Phase 0. REAL time: 0 secs
+........
+Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
-....................
-Placer score = 68062.
-Finished Placer Phase 1. REAL time: 7 secs
+.....................
+Placer score = 66969.
+Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
-Placer score = 67096
-Finished Placer Phase 2. REAL time: 7 secs
+Placer score = 66494
+Finished Placer Phase 2. REAL time: 6 secs
@@ -117,13 +117,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%)
Global Clocks:
- PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47
+ PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20
- SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0
+ PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 10
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
- PRIMARY : 2 out of 8 (25%)
- SECONDARY: 2 out of 8 (25%)
+ PRIMARY : 3 out of 8 (37%)
+ SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
@@ -132,9 +132,9 @@ Edge Clocks:
I/O Usage Summary (final):
- 63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
- 63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
- Number of PIO comps: 63; differential: 0.
+ 64 + 4(JTAG) out of 108 (63.0%) PIO sites used.
+ 64 + 4(JTAG) out of 80 (85.0%) bonded PIO sites used.
+ Number of PIO comps: 64; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
@@ -143,20 +143,21 @@ I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
-| 2 | 12 / 20 ( 60%) | 3.3V | - |
+| 2 | 13 / 20 ( 65%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
-Total placer CPU time: 6 secs
+Total placer CPU time: 5 secs
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-0 connections routed; 1017 unrouted.
+0 connections routed; 993 unrouted.
Starting router resource preassignment
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-Completed router resource preassignment. Real time: 11 secs
+Completed router resource preassignment. Real time: 10 secs
-Start NBR router at 05:40:00 09/21/23
+Start NBR router at 23:51:09 10/19/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@@ -171,41 +172,50 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
-Start NBR special constraint process at 05:40:00 09/21/23
+Start NBR special constraint process at 23:51:09 10/19/23
-Start NBR section for initial routing at 05:40:01 09/21/23
+Start NBR section for initial routing at 23:51:09 10/19/23
Level 1, iteration 1
-0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
+0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs
Level 2, iteration 1
-0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
+0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs
Level 3, iteration 1
-0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
+0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs
Level 4, iteration 1
-5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
+17(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 5.804ns/0.000ns; real time: 11 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
-Start NBR section for normal routing at 05:40:01 09/21/23
+Start NBR section for normal routing at 23:51:10 10/19/23
Level 4, iteration 1
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
+11(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 2
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
+Level 4, iteration 3
+2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
+Level 4, iteration 4
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
+Level 4, iteration 5
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
-Start NBR section for setup/hold timing optimization with effort level 3 at 05:40:01 09/21/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 23:51:10 10/19/23
-Start NBR section for re-routing at 05:40:01 09/21/23
+Start NBR section for re-routing at 23:51:10 10/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
-Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
+Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs
-Start NBR section for post-routing at 05:40:01 09/21/23
+Start NBR section for post-routing at 23:51:10 10/19/23
End NBR router with 0 unrouted connection
@@ -213,17 +223,17 @@ NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
- Estimated worst slack<setup> : 5.578ns
+ Estimated worst slack<setup> : 5.798ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-Total CPU time 12 secs
-Total REAL time: 13 secs
+Total CPU time 11 secs
+Total REAL time: 12 secs
Completely routed.
-End of route. 1017 routed (100.00%); 0 unrouted.
+End of route. 993 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
@@ -237,14 +247,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst slack<setup/<ns>> = 5.578
+PAR_SUMMARY::Worst slack<setup/<ns>> = 5.798
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
-Total CPU time to completion: 13 secs
-Total REAL time to completion: 13 secs
+Total CPU time to completion: 11 secs
+Total REAL time to completion: 12 secs
par done!
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
index fc280bb..5f70fd7 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
-# Written on Thu Sep 21 05:39:37 2023
+# Written on Thu Oct 19 23:50:49 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
index a544d8f..5850c48 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
@@ -62,7 +62,7 @@
| Updated: |
-2023/09/21 05:40:22 |
+2023/10/20 00:05:05 |
| Implementation Location: |
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html
index dfca0e2..629aef2 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html
@@ -12,7 +12,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
-# Thu Sep 21 05:39:34 2023
+# Thu Oct 19 23:50:47 2023
#Implementation: impl1
@@ -60,10 +60,16 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
+
+Compiler output is up to date. No re-compile necessary
+
Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@@ -74,6 +80,9 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
+@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2GS .......
@@ -86,13 +95,15 @@ Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
+Running optimization stage 2 on ODDRXE .......
+Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:47 2023
###########################################################]
###########################################################[
@@ -119,7 +130,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:48 2023
###########################################################]
@@ -134,7 +145,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:35 2023
+# Thu Oct 19 23:50:48 2023
###########################################################]
###########################################################[
@@ -155,18 +166,17 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
-# Thu Sep 21 05:39:36 2023
+# Thu Oct 19 23:50:49 2023
###########################################################]
-Premap Report
-
-# Thu Sep 21 05:39:37 2023
+# Thu Oct 19 23:50:49 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -188,7 +198,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
@@ -232,17 +242,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -326,12 +336,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:39:38 2023
+# Thu Oct 19 23:50:50 2023
###########################################################]
-Map & Optimize Report
-
-# Thu Sep 21 05:39:39 2023
+# Thu Oct 19 23:50:50 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -350,42 +358,42 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
-@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
+@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].
-Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Available hyper_sources - for debug and ip models
@@ -407,50 +415,63 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
- 1 0h:00m:01s -2.98ns 201 / 106
- 2 0h:00m:01s -2.98ns 217 / 106
- 3 0h:00m:01s -2.76ns 215 / 106
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
+ 1 0h:00m:01s -2.76ns 193 / 106
+ 2 0h:00m:01s -2.76ns 209 / 106
+ 3 0h:00m:01s -2.76ns 208 / 106
+ 4 0h:00m:01s -2.76ns 206 / 106
+ 5 0h:00m:01s -2.76ns 206 / 106
+ 6 0h:00m:01s -2.76ns 205 / 106
+ 7 0h:00m:01s -2.76ns 205 / 106
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
-Added 3 Registers via timing driven replication
-Added 1 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 2 LUTs via timing driven replication
- 4 0h:00m:02s -1.97ns 220 / 109
+ 8 0h:00m:01s -1.83ns 209 / 110
+ 9 0h:00m:01s -1.83ns 209 / 110
+ 10 0h:00m:01s -1.83ns 209 / 110
+ 11 0h:00m:01s -1.83ns 209 / 110
+ 12 0h:00m:01s -1.83ns 209 / 110
- 5 0h:00m:02s -1.97ns 220 / 109
+ 13 0h:00m:01s -1.83ns 208 / 110
+ 14 0h:00m:01s -1.83ns 209 / 110
+ 15 0h:00m:01s -1.83ns 209 / 110
+ 16 0h:00m:01s -1.83ns 209 / 110
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB)
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
-Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
+@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock RCLK with period 16.00ns
@N: MT615 |Found clock PHI2 with period 350.00ns
@@ -459,7 +480,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:39:43 2023
+# Timing report written on Thu Oct 19 23:50:54 2023
#
@@ -479,15 +500,15 @@ Performance Summary
*******************
-Worst slack in design: -2.605
+Worst slack in design: -1.828
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup
-RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup
+RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
-nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup
+nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -510,12 +531,12 @@ Starting Ending | constraint slack | constraint slack | constraint
---------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
-RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
+RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
-PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428
-nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605
+PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428
+nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693
===============================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -549,30 +570,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
-Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
-Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
-Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
+Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041
+Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041
+Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041
==========================================================================================
Ending Points with Worst Slack
******************************
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------
-wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
-=========================================================================================
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------
+wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
+wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
+==============================================================================
@@ -588,7 +609,7 @@ Path information for path number 1:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -603,7 +624,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -616,7 +637,7 @@ Path information for path number 2:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -631,7 +652,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -644,7 +665,7 @@ Path information for path number 3:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -659,7 +680,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -672,7 +693,7 @@ Path information for path number 4:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -687,7 +708,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -700,7 +721,7 @@ Path information for path number 5:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.828
+ = Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@@ -715,7 +736,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
-un1_wb_rst14_i_0 Net - - - - 17
+N_122 Net - - - - 17
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@@ -738,13 +759,13 @@ Instance Reference Type Pin Net Time Slac
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
-IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
-IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
-IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
-InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
-FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
-FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
-FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
+FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100
+FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108
+FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132
+InitReady RCLK FD1S3AX Q InitReady 1.317 9.708
+FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845
+FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845
+FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877
==================================================================================
@@ -841,7 +862,7 @@ Path information for path number 3:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[0] / D
+ Ending point: RowA[1] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -850,10 +871,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[0] ORCALUT4 B In 0.000 1.256 r -
-RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
-RowAd_0[0] Net - - - - 1
-RowA[0] FD1S3AX D In 0.000 1.873 r -
+RowAd[1] ORCALUT4 B In 0.000 1.256 r -
+RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[1] Net - - - - 1
+RowA[1] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -869,7 +890,7 @@ Path information for path number 4:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[5] / D
+ Ending point: RowA[4] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -878,10 +899,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[5] ORCALUT4 B In 0.000 1.256 r -
-RowAd[5] ORCALUT4 Z Out 0.617 1.873 f -
-RowAd_0[5] Net - - - - 1
-RowA[5] FD1S3AX D In 0.000 1.873 f -
+RowAd[4] ORCALUT4 B In 0.000 1.256 r -
+RowAd[4] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[4] Net - - - - 1
+RowA[4] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -897,7 +918,7 @@ Path information for path number 5:
Number of logic level(s): 1
Starting point: Ready_fast / Q
- Ending point: RowA[8] / D
+ Ending point: RowA[2] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@@ -906,10 +927,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
-RowAd[8] ORCALUT4 B In 0.000 1.256 r -
-RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
-RowAd_0[8] Net - - - - 1
-RowA[8] FD1S3AX D In 0.000 1.873 r -
+RowAd[2] ORCALUT4 B In 0.000 1.256 r -
+RowAd[2] ORCALUT4 Z Out 0.617 1.873 r -
+RowAd_0[2] Net - - - - 1
+RowA[2] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@@ -924,29 +945,30 @@ Detailed Report for Clock: nCRAS
Starting Points with Worst Slack
********************************
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605
-CBR nCRAS FD1S3AX Q CBR 1.180 -1.797
-FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
-==============================================================================
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------
+CBR nCRAS FD1S3AX Q CBR 1.148 -1.693
+FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693
+CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661
+FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589
+================================================================================
Ending Points with Worst Slack
******************************
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------
-nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
-nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
-nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
-nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
-RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
-==========================================================================================
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------
+RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693
+nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693
+nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693
+nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693
+nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661
+========================================================================================
@@ -960,32 +982,29 @@ Path information for path number 1:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 3.694
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : -2.605
+ = Slack (non-critical) : -1.693
- Number of logic level(s): 3
- Starting point: CBR_fast / Q
+ Number of logic level(s): 2
+ Starting point: CBR / Q
Ending point: nRCAS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-CBR_fast FD1S3AX Q Out 0.972 0.972 r -
-CBR_fast Net - - - - 1
-CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r -
-CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
-nRCAS_0_sqmuxa_1 Net - - - - 2
-nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
-nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
-N_248_i_sx Net - - - - 1
-nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
-====================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+----------------------------------------------------------------------------------
+CBR FD1S3AX Q Out 1.148 1.148 r -
+CBR Net - - - - 4
+nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r -
+nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
+N_242_i_1 Net - - - - 1
+nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f -
+nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
+N_242_i Net - - - - 1
+nRCAS_0io OFS1P3BX D In 0.000 2.781 r -
+==================================================================================
Path information for path number 2:
@@ -994,29 +1013,29 @@ Path information for path number 2:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: CBR / Q
- Ending point: nRCS_0io / D
+ Starting point: FWEr / Q
+ Ending point: RCKEEN / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
- The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+ The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-CBR FD1S3AX Q Out 1.180 1.180 r -
-CBR Net - - - - 5
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
-N_590 Net - - - - 2
-nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
-nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_247_i Net - - - - 1
-nRCS_0io OFS1P3BX D In 0.000 2.885 r -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r -
+RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r -
+RCKEEN_8_u_1 Net - - - - 1
+RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r -
+RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r -
+RCKEEN_8 Net - - - - 1
+RCKEEN FD1S3AX D In 0.000 2.781 r -
+=================================================================================
Path information for path number 3:
@@ -1025,29 +1044,29 @@ Path information for path number 3:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: FWEr / Q
- Ending point: nRCAS_0io / D
+ Starting point: CBR / Q
+ Ending point: nRowColSel / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
- The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+ The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-FWEr FD1S3AX Q Out 1.180 1.180 r -
-FWEr Net - - - - 5
-nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
-nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
-N_248_i_1_0 Net - - - - 2
-nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
-=================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR FD1S3AX Q Out 1.148 1.148 r -
+CBR Net - - - - 4
+nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r -
+nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f -
+N_255 Net - - - - 1
+nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f -
+nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f -
+nRowColSel_0_0 Net - - - - 1
+nRowColSel FD1S3IX D In 0.000 2.781 f -
+======================================================================================
Path information for path number 4:
@@ -1056,29 +1075,29 @@ Path information for path number 4:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
- Starting point: CBR / Q
- Ending point: nRWE_0io / D
+ Starting point: FWEr / Q
+ Ending point: nRCS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-CBR FD1S3AX Q Out 1.180 1.180 r -
-CBR Net - - - - 5
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
-RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
-N_590 Net - - - - 2
-nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
-nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
-N_49_i Net - - - - 1
-nRWE_0io OFS1P3BX D In 0.000 2.885 r -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r -
+nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
+nRCS_0io_RNO_0 Net - - - - 1
+nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f -
+nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
+N_28_i Net - - - - 1
+nRCS_0io OFS1P3BX D In 0.000 2.781 r -
+=================================================================================
Path information for path number 5:
@@ -1087,9 +1106,9 @@ Path information for path number 5:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- - Propagation time: 2.885
+ - Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : -1.797
+ = Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
@@ -1097,19 +1116,19 @@ Path information for path number 5:
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr FD1S3AX Q Out 1.180 1.180 r -
-FWEr Net - - - - 5
-nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
-nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
-N_248_i_1_1 Net - - - - 2
-nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
-nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
-N_248_i Net - - - - 1
-nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
-======================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+----------------------------------------------------------------------------------
+FWEr FD1S3AX Q Out 1.148 1.148 r -
+FWEr Net - - - - 4
+nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r -
+nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r -
+N_242_i_1 Net - - - - 1
+nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r -
+nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f -
+N_242_i Net - - - - 1
+nRCAS_0io OFS1P3BX D In 0.000 2.781 f -
+==================================================================================
@@ -1142,7 +1161,7 @@ Instance Reference Type Pin Net Time Sla
-----------------------------------------------------------------------------------
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
-wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
+wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912
===================================================================================
@@ -1168,25 +1187,25 @@ Path information for path number 1:
The start point is clocked by System [rising]
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
-wb_ack Net - - - - 2
-ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r -
-ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r -
-g0_0_a3_2 Net - - - - 1
-ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r -
-ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r -
-N_4 Net - - - - 1
-CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
-CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
-CmdValid_RNIOOBE2 Net - - - - 2
-LEDENe ORCALUT4 B In 0.000 2.554 r -
-LEDENe ORCALUT4 Z Out 0.617 3.171 r -
-LEDENe_0 Net - - - - 1
-LEDEN FD1S3AX D In 0.000 3.171 r -
-==============================================================================================
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+-----------------------------------------------------------------------------------------------------
+ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
+wb_ack Net - - - - 2
+ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r -
+ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r -
+g0_0_a3_1 Net - - - - 1
+wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r -
+wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r -
+N_4 Net - - - - 1
+CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r -
+CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r -
+CmdValid_RNITBH02 Net - - - - 2
+LEDENe ORCALUT4 B In 0.000 2.554 r -
+LEDENe ORCALUT4 Z Out 0.617 3.171 r -
+LEDENe_0 Net - - - - 1
+LEDEN FD1S3AX D In 0.000 3.171 r -
+=====================================================================================================
@@ -1194,18 +1213,18 @@ LEDEN FD1S3AX D In 0.000 3.171 r
Timing exceptions that could not be applied
-Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
-Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
-Register bits: 109 of 1280 (9%)
+Register bits: 110 of 1280 (9%)
PIC Latch: 0
-I/O cells: 63
+I/O cells: 64
Details:
@@ -1214,27 +1233,27 @@ CCU2D: 10
EFB: 1
FD1P3AX: 25
FD1P3IX: 2
-FD1S3AX: 53
+FD1S3AX: 54
FD1S3IX: 4
GSR: 1
IB: 25
IFS1P3DX: 9
INV: 7
-OB: 30
+OB: 31
+ODDRXE: 1
OFS1P3BX: 4
OFS1P3DX: 11
OFS1P3JX: 1
-ORCALUT4: 213
-PFUMX: 1
+ORCALUT4: 203
PUR: 1
VHI: 2
VLO: 2
Mapper successful!
-At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:39:43 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Thu Oct 19 23:50:54 2023
###########################################################]
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
index 9652fc8..44d8626 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:39:46 2023
+Thu Oct 19 23:50:57 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -42,7 +42,7 @@ Report level: verbose report, limited to 1 item per preference
Preference Summary
FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors) 147 items scored, 0 timing errors detected.
-Report: 53.254MHz is the maximum frequency for this preference.
+Report: 57.904MHz is the maximum frequency for this preference.
FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
@@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
-FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 878 items scored, 0 timing errors detected.
-Report: 100.492MHz is the maximum frequency for this preference.
+FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 868 items scored, 0 timing errors detected.
+Report: 97.666MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@@ -65,42 +65,42 @@ BLOCK RESETPATHS
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
+Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
- Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
+ Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels.
Constraint Details:
- 9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
+ 8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
- 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
+ 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns
Physical Path Details:
- Data path Din[0]_MGIOL to SLICE_17:
+ Data path Din[0]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
-CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
-ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
-ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
-ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
-CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
-ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
-ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
+ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0]
+CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89
+ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75
+ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294
+CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75
+ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382
+CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73
+ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17
+CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10
+ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
- 9.223 (33.1% logic, 66.9% route), 6 logic levels.
+ 8.469 (36.0% logic, 64.0% route), 6 logic levels.
-Report: 53.254MHz is the maximum frequency for this preference.
+Report: 57.904MHz is the maximum frequency for this preference.
================================================================================
@@ -141,48 +141,48 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 6.049ns
+Passed: The following path meets requirements by 5.761ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q IS[1] (from RCLK_c +)
- Destination: FF Data in nRCAS_0io (to RCLK_c +)
+ Source: FF Q FS[11] (from RCLK_c +)
+ Destination: FF Data in wb_adr[0] (to RCLK_c +)
- Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
+ Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels.
Constraint Details:
- 9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
+ 10.073ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
- 0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns
Physical Path Details:
- Data path SLICE_27 to nRCAS_MGIOL:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
-ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
-CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
-ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
-CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
-ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
-CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
-ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
-CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
-ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
-CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
-ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
-CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
-ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
+REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c)
+ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11]
+CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66
+ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0]
+CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66
+ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0]
+CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86
+ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0]
+CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85
+ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0]
+CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
+ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0]
+CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48
+ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c)
--------
- 9.798 (34.9% logic, 65.1% route), 7 logic levels.
+ 10.073 (34.0% logic, 66.0% route), 7 logic levels.
-Report: 100.492MHz is the maximum frequency for this preference.
+Report: 97.666MHz is the maximum frequency for this preference.
Report Summary
--------------
@@ -190,13 +190,13 @@ Report: 100.492MHz is the maximum frequency for this preference.
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
-FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
+FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
-FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
+FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7
| | |
----------------------------------------------------------------------------
@@ -209,7 +209,7 @@ All preferences were met.
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -221,7 +221,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -251,11 +251,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
+Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:39:46 2023
+Thu Oct 19 23:50:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -280,7 +280,7 @@ Report level: verbose report, limited to 1 item per preference
FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
-FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 878 items scored, 0 timing errors detected.
+FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 868 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@@ -317,7 +317,7 @@ Passed: The following path meets requirements by 0.447ns
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
-ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
@@ -336,7 +336,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@@ -390,7 +390,7 @@ All preferences were met.
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -402,7 +402,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -432,7 +432,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
+Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
index 9c0153f..d59b6fe 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:40:03 2023
+Thu Oct 19 23:51:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -42,7 +42,7 @@ Report level: verbose report, limited to 10 items per preference
Preference Summary
FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors) 147 items scored, 0 timing errors detected.
-Report: 41.034MHz is the maximum frequency for this preference.
+Report: 50.206MHz is the maximum frequency for this preference.
FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
@@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
-FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 878 items scored, 0 timing errors detected.
-Report: 95.951MHz is the maximum frequency for this preference.
+FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 868 items scored, 0 timing errors detected.
+Report: 98.020MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@@ -65,21 +65,21 @@ BLOCK RESETPATHS
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 160.229ns (weighted slack = 320.458ns)
+Passed: The following path meets requirements by 162.455ns (weighted slack = 324.910ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 11.846ns (25.8% logic, 74.2% route), 6 logic levels.
+ Delay: 9.620ns (31.7% logic, 68.3% route), 6 logic levels.
Constraint Details:
- 11.846ns physical path delay Din[0]_MGIOL to SLICE_17 meets
+ 9.620ns physical path delay Din[0]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 160.229ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.455ns
Physical Path Details:
@@ -88,18 +88,18 @@ Passed: The following path meets requirements by 160.229ns (weighted slack = 320
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 11.846 (25.8% logic, 74.2% route), 6 logic levels.
+ 9.620 (31.7% logic, 68.3% route), 6 logic levels.
Clock Skew Details:
@@ -113,287 +113,26 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 161.365ns (weighted slack = 322.730ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdUFMData (to PHI2_c -)
-
- Delay: 10.569ns (24.2% logic, 75.8% route), 5 logic levels.
-
- Constraint Details:
-
- 10.569ns physical path delay Din[0]_MGIOL to SLICE_82 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.307ns CE_SET requirement (totaling 171.934ns) by 161.365ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_82:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.718 R5C10A.F1 to R5C10C.B0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10C.B0 to R5C10C.F0 SLICE_82
-ROUTE 1 0.653 R5C10C.F0 to R5C10C.CE CmdUFMData_1_sqmuxa (to PHI2_c)
- --------
- 10.569 (24.2% logic, 75.8% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_82:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.468ns (weighted slack = 322.936ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[2] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.607ns (28.8% logic, 71.2% route), 6 logic levels.
-
- Constraint Details:
-
- 10.607ns physical path delay Din[2]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.468ns
-
- Physical Path Details:
-
- Data path Din[2]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c)
-ROUTE 1 1.512 IOL_T12A.IN to R4C11A.C0 Bank[2]
-CTOF_DEL --- 0.495 R4C11A.C0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.607 (28.8% logic, 71.2% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[2]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.870ns (weighted slack = 323.740ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdValid (to PHI2_c -)
-
- Delay: 10.205ns (25.1% logic, 74.9% route), 5 logic levels.
-
- Constraint Details:
-
- 10.205ns physical path delay Din[0]_MGIOL to SLICE_22 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.870ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_22:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 1.007 R5C10A.F1 to R5C10D.A0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10D.A0 to R5C10D.F0 SLICE_22
-ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 CmdValid_r (to PHI2_c)
- --------
- 10.205 (25.1% logic, 74.9% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_22:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10D.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.985ns (weighted slack = 323.970ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[1] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.090ns (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
- 10.090ns physical path delay Din[1]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.985ns
-
- Physical Path Details:
-
- Data path Din[1]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c)
-ROUTE 1 1.601 IOL_T10B.IN to R2C10A.A1 Bank[1]
-CTOF_DEL --- 0.495 R2C10A.A1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.090 (30.2% logic, 69.8% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[1]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.032ns (weighted slack = 324.064ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[5] (from PHI2_c +)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 10.043ns (30.4% logic, 69.6% route), 6 logic levels.
-
- Constraint Details:
-
- 10.043ns physical path delay Din[5]_MGIOL to SLICE_17 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.032ns
-
- Physical Path Details:
-
- Data path Din[5]_MGIOL to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c)
-ROUTE 1 1.554 IOL_T9B.IN to R2C10A.B1 Bank[5]
-CTOF_DEL --- 0.495 R2C10A.B1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 10.043 (30.4% logic, 69.6% route), 6 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[5]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns)
+Passed: The following path meets requirements by 162.715ns (weighted slack = 325.430ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
- Delay: 9.978ns (25.6% logic, 74.4% route), 5 logic levels.
+ Delay: 9.360ns (32.6% logic, 67.4% route), 6 logic levels.
Constraint Details:
- 9.978ns physical path delay Din[0]_MGIOL to SLICE_10 meets
+ 9.360ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.097ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.715ns
Physical Path Details:
@@ -402,16 +141,18 @@ Passed: The following path meets requirements by 162.097ns (weighted slack = 324
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 0.987 R5C12C.F1 to R5C13B.A0 CmdEnable16
-CTOF_DEL --- 0.495 R5C13B.A0 to R5C13B.F0 SLICE_10
-ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17
+CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
- 9.978 (25.6% logic, 74.4% route), 5 logic levels.
+ 9.360 (32.6% logic, 67.4% route), 6 logic levels.
Clock Skew Details:
@@ -425,130 +166,132 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13B.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 162.159ns (weighted slack = 324.318ns)
+Passed: The following path meets requirements by 162.913ns (weighted slack = 325.826ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q Bank_0io[0] (from PHI2_c +)
- Destination: FF Data in CmdValid_fast (to PHI2_c -)
-
- Delay: 9.916ns (25.8% logic, 74.2% route), 5 logic levels.
-
- Constraint Details:
-
- 9.916ns physical path delay Din[0]_MGIOL to SLICE_23 meets
- 172.414ns delay constraint less
- 0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.159ns
-
- Physical Path Details:
-
- Data path Din[0]_MGIOL to SLICE_23:
-
- Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
-ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.718 R5C10A.F1 to R5C10A.B0 XOR8MEG18
-CTOF_DEL --- 0.495 R5C10A.B0 to R5C10A.F0 SLICE_23
-ROUTE 1 0.000 R5C10A.F0 to R5C10A.DI0 N_36_fast (to PHI2_c)
- --------
- 9.916 (25.8% logic, 74.2% route), 5 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to Din[0]_MGIOL:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
- --------
- 4.369 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_23:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C10A.CLK PHI2_c
- --------
- 4.196 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.410ns (weighted slack = 324.820ns)
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Bank_0io[4] (from PHI2_c +)
+ Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 9.665ns (31.6% logic, 68.4% route), 6 logic levels.
+ Delay: 9.162ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
- 9.665ns physical path delay Din[4]_MGIOL to SLICE_17 meets
+ 9.162ns physical path delay Din[7]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
- 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.410ns
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.913ns
Physical Path Details:
- Data path Din[4]_MGIOL to SLICE_17:
+ Data path Din[7]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
-C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE 1 1.176 IOL_T9A.IN to R2C10A.D1 Bank[4]
-CTOF_DEL --- 0.495 R2C10A.D1 to R2C10A.F1 SLICE_84
-ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11
-CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11
-ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16
-CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33
-ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
+ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7]
+CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 9.665 (31.6% logic, 68.4% route), 6 logic levels.
+ 9.162 (33.3% logic, 66.7% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path PHI2 to Din[4]_MGIOL:
+ Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.369 8.PADDI to IOL_T9A.CLK PHI2_c
+ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 162.515ns (weighted slack = 325.030ns)
+Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[7] (from PHI2_c +)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
+
+ Delay: 8.902ns (34.3% logic, 65.7% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.902ns physical path delay Din[7]_MGIOL to SLICE_10 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.173ns
+
+ Physical Path Details:
+
+ Data path Din[7]_MGIOL to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
+ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7]
+CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17
+CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
+ --------
+ 8.902 (34.3% logic, 65.7% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[7]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
- Delay: 9.419ns (21.9% logic, 78.1% route), 4 logic levels.
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
Constraint Details:
- 9.419ns physical path delay Din[0]_MGIOL to SLICE_18 meets
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
- 0.307ns CE_SET requirement (totaling 171.934ns) by 162.515ns
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
Physical Path Details:
@@ -557,14 +300,14 @@ Passed: The following path meets requirements by 162.515ns (weighted slack = 325
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
-CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93
-ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10
-CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84
-ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3
-CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.716 R5C10A.F1 to R5C9B.CE XOR8MEG18 (to PHI2_c)
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R3C10B.CE XOR8MEG18 (to PHI2_c)
--------
- 9.419 (21.9% logic, 78.1% route), 4 logic levels.
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
Clock Skew Details:
@@ -578,11 +321,262 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 4.196 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 4.196 8.PADDI to R3C10B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
-Report: 41.034MHz is the maximum frequency for this preference.
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in CmdUFMShift (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_20 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_20:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R4C10B.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_20:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R4C10B.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in CmdUFMWrite (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_21 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R4C10D.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
+
+ Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.671ns physical path delay Din[0]_MGIOL to SLICE_24 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294
+CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106
+ROUTE 5 1.413 R5C11C.F1 to R3C10C.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 8.671 (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.326ns (weighted slack = 326.652ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[6] (from PHI2_c +)
+ Destination: FF Data in CmdEnable (to PHI2_c -)
+
+ Delay: 8.749ns (34.9% logic, 65.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.749ns physical path delay Din[6]_MGIOL to SLICE_17 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.326ns
+
+ Physical Path Details:
+
+ Data path Din[6]_MGIOL to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c)
+ROUTE 1 1.802 IOL_L2D.IN to R3C9D.D0 Bank[6]
+CTOF_DEL --- 0.495 R3C9D.D0 to R3C9D.F0 SLICE_32
+ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11
+CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75
+ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294
+CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75
+ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382
+CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73
+ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17
+CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
+ --------
+ 8.749 (34.9% logic, 65.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[6]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.343ns (weighted slack = 326.686ns)
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Bank_0io[0] (from PHI2_c +)
+ Destination: FF Data in ADSubmitted (to PHI2_c -)
+
+ Delay: 8.732ns (29.3% logic, 70.7% route), 5 logic levels.
+
+ Constraint Details:
+
+ 8.732ns physical path delay Din[0]_MGIOL to SLICE_10 meets
+ 172.414ns delay constraint less
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.343ns
+
+ Physical Path Details:
+
+ Data path Din[0]_MGIOL to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
+ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0]
+CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89
+ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10
+CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75
+ROUTE 8 1.456 R4C10A.F1 to R5C12C.A1 N_294
+CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_10
+ROUTE 1 0.967 R5C12C.F1 to R5C12C.A0 N_22_i
+CTOF_DEL --- 0.495 R5C12C.A0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
+ --------
+ 8.732 (29.3% logic, 70.7% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to Din[0]_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
+ --------
+ 4.369 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_10:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c
+ --------
+ 4.196 (0.0% logic, 100.0% route), 0 logic levels.
+
+Report: 50.206MHz is the maximum frequency for this preference.
================================================================================
@@ -623,540 +617,528 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
-Passed: The following path meets requirements by 5.578ns
+Passed: The following path meets requirements by 5.798ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels.
+ Delay: 10.036ns (24.2% logic, 75.8% route), 5 logic levels.
Constraint Details:
- 10.256ns physical path delay SLICE_2 to SLICE_54 meets
+ 10.036ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.798ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 2.663 R5C5C.Q1 to R2C7A.A1 FS[12]
+CTOF_DEL --- 0.495 R2C7A.A1 to R2C7A.F1 SLICE_101
+ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142
+CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 10.256 (30.7% logic, 69.3% route), 6 logic levels.
+ 10.036 (24.2% logic, 75.8% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.578ns
+Passed: The following path meets requirements by 6.138ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
+ Destination: FF Data in n8MEGEN (to RCLK_c +)
- Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels.
+ Delay: 9.523ns (76.3% logic, 23.7% route), 3 logic levels.
Constraint Details:
- 10.256ns physical path delay SLICE_2 to SLICE_54 meets
+ 9.523ns physical path delay ufmefb/EFBInst_0 to SLICE_46 meets
16.000ns delay constraint less
- 0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns
+ 0.173ns skew and
+ 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.138ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path ufmefb/EFBInst_0 to SLICE_46:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
+ROUTE 1 1.297 EFB.WBDATO0 to R3C5B.C1 wb_dato[0]
+CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_108
+ROUTE 1 0.958 R3C5B.F1 to R3C8B.D0 n8MEGENe_1_0
+CTOF_DEL --- 0.495 R3C8B.D0 to R3C8B.F0 SLICE_46
+ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n8MEGENe_0 (to RCLK_c)
--------
- 10.256 (30.7% logic, 69.3% route), 6 logic levels.
+ 9.523 (76.3% logic, 23.7% route), 3 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c
--------
- 2.264 (0.0% logic, 100.0% route), 0 logic levels.
+ 2.437 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_46:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C8B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.743ns
+Passed: The following path meets requirements by 6.414ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[4] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_adr[0] (to RCLK_c +)
- Delay: 10.091ns (29.0% logic, 71.0% route), 6 logic levels.
+ Delay: 9.420ns (36.3% logic, 63.7% route), 7 logic levels.
Constraint Details:
- 10.091ns physical path delay SLICE_2 to SLICE_54 meets
+ 9.420ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.743ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.414ns
Physical Path Details:
- Data path SLICE_2 to SLICE_54:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473
-CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86
-ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4]
-CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54
-ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 2.237 R5C5C.Q1 to R2C7D.A1 FS[12]
+CTOF_DEL --- 0.495 R2C7D.A1 to R2C7D.F1 SLICE_66
+ROUTE 1 0.436 R2C7D.F1 to R2C7D.C0 wb_adr_5_i_i_a2_3_0[0]
+CTOF_DEL --- 0.495 R2C7D.C0 to R2C7D.F0 SLICE_66
+ROUTE 1 0.967 R2C7D.F0 to R2C7B.A0 wb_adr_5_i_i_1_0_tz_0[0]
+CTOF_DEL --- 0.495 R2C7B.A0 to R2C7B.F0 SLICE_86
+ROUTE 1 1.001 R2C7B.F0 to R2C6A.B0 wb_adr_5_i_i_1_0[0]
+CTOF_DEL --- 0.495 R2C6A.B0 to R2C6A.F0 SLICE_85
+ROUTE 1 1.042 R2C6A.F0 to R4C6D.D0 wb_adr_5_i_i_1[0]
+CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_77
+ROUTE 1 0.315 R4C6D.F0 to R4C6C.D0 wb_adr_5_i_i_5[0]
+CTOF_DEL --- 0.495 R4C6C.D0 to R4C6C.F0 SLICE_48
+ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 N_283 (to RCLK_c)
--------
- 10.091 (29.0% logic, 71.0% route), 6 logic levels.
+ 9.420 (36.3% logic, 63.7% route), 7 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.835ns
+Passed: The following path meets requirements by 6.769ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[9] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels.
+ Delay: 9.065ns (32.3% logic, 67.7% route), 6 logic levels.
Constraint Details:
- 9.999ns physical path delay SLICE_1 to SLICE_54 meets
+ 9.065ns physical path delay SLICE_5 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.769ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_5 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q0 SLICE_5 (from RCLK_c)
+ROUTE 14 1.803 R5C5B.Q0 to R3C6D.B1 FS[9]
+CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_80
+ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125
+CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.999 (31.5% logic, 68.5% route), 6 logic levels.
+ 9.065 (32.3% logic, 67.7% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.835ns
+Passed: The following path meets requirements by 7.019ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[5] (to RCLK_c +)
+ Source: FF Q FS[13] (from RCLK_c +)
+ Destination: FF Data in wb_dati[7] (to RCLK_c +)
- Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels.
+ Delay: 8.815ns (33.2% logic, 66.8% route), 6 logic levels.
Constraint Details:
- 9.999ns physical path delay SLICE_1 to SLICE_54 meets
+ 8.815ns physical path delay SLICE_3 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.019ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_3 to SLICE_56:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361
-CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54
-ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c)
+REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c)
+ROUTE 23 1.929 R5C5D.Q0 to R3C5D.A1 FS[13]
+CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 SLICE_70
+ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2
+CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70
+ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
+CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108
+ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7]
+CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69
+ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56
+ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
--------
- 9.999 (31.5% logic, 68.5% route), 6 logic levels.
+ 8.815 (33.2% logic, 66.8% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.851ns
+Passed: The following path meets requirements by 7.040ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[6] (to RCLK_c +)
+ Source: FF Q FS[13] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.983ns (29.3% logic, 70.7% route), 6 logic levels.
+ Delay: 8.794ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
- 9.983ns physical path delay SLICE_2 to SLICE_55 meets
+ 8.794ns physical path delay SLICE_3 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.851ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.040ns
Physical Path Details:
- Data path SLICE_2 to SLICE_55:
+ Data path SLICE_3 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 0.976 R3C4C.F1 to R3C4C.A0 N_473
-CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_85
-ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6]
-CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55
-ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c)
+REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c)
+ROUTE 23 3.158 R5C5D.Q0 to R4C7C.A0 FS[13]
+CTOF_DEL --- 0.495 R4C7C.A0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.983 (29.3% logic, 70.7% route), 6 logic levels.
+ 8.794 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_55:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.867ns
+Passed: The following path meets requirements by 7.108ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[6] (to RCLK_c +)
+ Source: FF Q FS[12] (from RCLK_c +)
+ Destination: FF Data in wb_dati[7] (to RCLK_c +)
- Delay: 9.967ns (29.4% logic, 70.6% route), 6 logic levels.
+ Delay: 8.726ns (33.5% logic, 66.5% route), 6 logic levels.
Constraint Details:
- 9.967ns physical path delay SLICE_2 to SLICE_55 meets
+ 8.726ns physical path delay SLICE_4 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.867ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.108ns
Physical Path Details:
- Data path SLICE_2 to SLICE_55:
+ Data path SLICE_4 to SLICE_56:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.559 R2C5D.F1 to R3C5A.B1 N_214
-CTOF_DEL --- 0.495 R3C5A.B1 to R3C5A.F1 SLICE_87
-ROUTE 4 1.323 R3C5A.F1 to R5C4B.A0 N_579
-CTOF_DEL --- 0.495 R5C4B.A0 to R5C4B.F0 SLICE_89
-ROUTE 1 1.023 R5C4B.F0 to R3C4C.B0 N_472
-CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_85
-ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6]
-CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55
-ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 1.840 R5C5C.Q1 to R3C5D.B1 FS[12]
+CTOF_DEL --- 0.495 R3C5D.B1 to R3C5D.F1 SLICE_70
+ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2
+CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70
+ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
+CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108
+ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7]
+CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69
+ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7]
+CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56
+ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
--------
- 9.967 (29.4% logic, 70.6% route), 6 logic levels.
+ 8.726 (33.5% logic, 66.5% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_55:
+ Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.956ns
+Passed: The following path meets requirements by 7.132ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[2] (to RCLK_c +)
+ Source: FF Q FS[10] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels.
+ Delay: 8.702ns (33.6% logic, 66.4% route), 6 logic levels.
Constraint Details:
- 9.878ns physical path delay SLICE_2 to SLICE_53 meets
+ 8.702ns physical path delay SLICE_5 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.132ns
Physical Path Details:
- Data path SLICE_2 to SLICE_53:
+ Data path SLICE_5 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361
-CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53
-ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c)
+REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q1 SLICE_5 (from RCLK_c)
+ROUTE 16 1.440 R5C5B.Q1 to R3C6D.A1 FS[10]
+CTOF_DEL --- 0.495 R3C6D.A1 to R3C6D.F1 SLICE_80
+ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125
+CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65
+ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1]
+CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.878 (31.9% logic, 68.1% route), 6 logic levels.
+ 8.702 (33.6% logic, 66.4% route), 6 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_53:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 5.956ns
+Passed: The following path meets requirements by 7.246ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[16] (from RCLK_c +)
- Destination: FF Data in wb_dati[2] (to RCLK_c +)
+ Source: FF Q FS[11] (from RCLK_c +)
+ Destination: FF Data in wb_adr[1] (to RCLK_c +)
- Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels.
+ Delay: 8.588ns (28.3% logic, 71.7% route), 5 logic levels.
Constraint Details:
- 9.878ns physical path delay SLICE_2 to SLICE_53 meets
+ 8.588ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns
+ 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.246ns
Physical Path Details:
- Data path SLICE_2 to SLICE_53:
+ Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16]
-CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214
-CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113
-ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502
-CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86
-ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479
-CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59
-ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361
-CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53
-ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c)
+REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q0 SLICE_4 (from RCLK_c)
+ROUTE 21 1.215 R5C5C.Q0 to R2C7A.D1 FS[11]
+CTOF_DEL --- 0.495 R2C7A.D1 to R2C7A.F1 SLICE_101
+ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142
+CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65
+ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz
+CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61
+ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1]
+CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48
+ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c)
--------
- 9.878 (31.9% logic, 68.1% route), 6 logic levels.
+ 8.588 (28.3% logic, 71.7% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_2:
+ Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_53:
+ Destination Clock Path RCLK to SLICE_48:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 6.000ns
+Passed: The following path meets requirements by 7.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
- Source: FF Q FS[17] (from RCLK_c +)
- Destination: FF Data in wb_dati[4] (to RCLK_c +)
+ Source: FF Q InitReady (from RCLK_c +)
+ Destination: FF Data in nRWE_0io (to RCLK_c +)
- Delay: 9.834ns (29.8% logic, 70.2% route), 6 logic levels.
+ Delay: 8.771ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
- 9.834ns physical path delay SLICE_1 to SLICE_54 meets
+ 8.771ns physical path delay SLICE_30 to nRWE_MGIOL meets
16.000ns delay constraint less
- 0.000ns skew and
- 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.000ns
+ -0.173ns skew and
+ 0.153ns DO_SET requirement (totaling 16.020ns) by 7.249ns
Physical Path Details:
- Data path SLICE_1 to SLICE_54:
+ Data path SLICE_30 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17]
-CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66
-ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214
-CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113
-ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576
-CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85
-ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473
-CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86
-ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4]
-CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54
-ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c)
+REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_30 (from RCLK_c)
+ROUTE 31 1.714 R4C8D.Q0 to R7C15A.D1 InitReady
+CTOF_DEL --- 0.495 R7C15A.D1 to R7C15A.F1 SLICE_62
+ROUTE 6 1.032 R7C15A.F1 to R7C16A.B1 N_43
+CTOF_DEL --- 0.495 R7C16A.B1 to R7C16A.F1 SLICE_78
+ROUTE 2 0.775 R7C16A.F1 to R7C14B.C1 IS_0_sqmuxa_0_o2
+CTOF_DEL --- 0.495 R7C14B.C1 to R7C14B.F1 SLICE_68
+ROUTE 1 1.023 R7C14B.F1 to R8C14C.B1 nRWE_0io_RNO_0
+CTOF_DEL --- 0.495 R8C14C.B1 to R8C14C.F1 SLICE_92
+ROUTE 1 1.795 R8C14C.F1 to IOL_B20D.OPOS N_37_i (to RCLK_c)
--------
- 9.834 (29.8% logic, 70.2% route), 6 logic levels.
+ 8.771 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_1:
+ Source Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_54:
+ Destination Clock Path RCLK to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c
+ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c
--------
- 2.264 (0.0% logic, 100.0% route), 0 logic levels.
+ 2.437 (0.0% logic, 100.0% route), 0 logic levels.
-Report: 95.951MHz is the maximum frequency for this preference.
+Report: 98.020MHz is the maximum frequency for this preference.
Report Summary
--------------
@@ -1164,13 +1146,13 @@ Report: 95.951MHz is the maximum frequency for this preference.
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
-FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 41.034 MHz| 6
+FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 50.206 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
-FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.951 MHz| 6
+FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 98.020 MHz| 5
| | |
----------------------------------------------------------------------------
@@ -1183,7 +1165,7 @@ All preferences were met.
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -1195,7 +1177,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -1225,11 +1207,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage)
+Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:40:03 2023
+Thu Oct 19 23:51:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -1254,7 +1236,7 @@ Report level: verbose report, limited to 10 items per preference
FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors) 0 items scored, 0 timing errors detected.
-FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 878 items scored, 0 timing errors detected.
+FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors) 868 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@@ -1268,6 +1250,51 @@ BLOCK RESETPATHS
--------------------------------------------------------------------------------
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q C1Submitted (from PHI2_c -)
+ Destination: FF Data in C1Submitted (to PHI2_c -)
+
+ Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.366ns physical path delay SLICE_11 to SLICE_11 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+ Data path SLICE_11 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C12A.CLK to R5C12A.Q0 SLICE_11 (from PHI2_c)
+ROUTE 2 0.132 R5C12A.Q0 to R5C12A.A0 C1Submitted
+CTOF_DEL --- 0.101 R5C12A.A0 to R5C12A.F0 SLICE_11
+ROUTE 1 0.000 R5C12A.F0 to R5C12A.DI0 C1Submitted_RNO (to PHI2_c)
+ --------
+ 0.366 (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_11:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
@@ -1289,10 +1316,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_20 (from PHI2_c)
-ROUTE 2 0.132 R5C9D.Q0 to R5C9D.A0 CmdUFMShift
-CTOF_DEL --- 0.101 R5C9D.A0 to R5C9D.F0 SLICE_20
-ROUTE 1 0.000 R5C9D.F0 to R5C9D.DI0 CmdUFMShift_3 (to PHI2_c)
+REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_20 (from PHI2_c)
+ROUTE 2 0.132 R4C10B.Q0 to R4C10B.A0 CmdUFMShift
+CTOF_DEL --- 0.101 R4C10B.A0 to R4C10B.F0 SLICE_20
+ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1301,14 +1328,14 @@ ROUTE 1 0.000 R5C9D.F0 to R5C9D.DI0 CmdUFMShift_3 (to PHI
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1334,10 +1361,10 @@ Passed: The following path meets requirements by 0.382ns
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c)
-ROUTE 2 0.135 R5C13B.Q0 to R5C13B.D0 ADSubmitted
-CTOF_DEL --- 0.101 R5C13B.D0 to R5C13B.F0 SLICE_10
-ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c)
+REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_10 (from PHI2_c)
+ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 ADSubmitted
+CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_10
+ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.369 (63.4% logic, 36.6% route), 2 logic levels.
@@ -1346,104 +1373,200 @@ ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.382ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q C1Submitted (from PHI2_c -)
- Destination: FF Data in C1Submitted (to PHI2_c -)
-
- Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels.
-
- Constraint Details:
-
- 0.369ns physical path delay SLICE_11 to SLICE_11 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.382ns
-
- Physical Path Details:
-
- Data path SLICE_11 to SLICE_11:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_11 (from PHI2_c)
-ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 C1Submitted
-CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_11
-ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 C1Submitted_RNO (to PHI2_c)
- --------
- 0.369 (63.4% logic, 36.6% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_11:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_11:
-
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 0.382ns
+Passed: The following path meets requirements by 0.387ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
- Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels.
+ Delay: 0.374ns (62.6% logic, 37.4% route), 2 logic levels.
Constraint Details:
- 0.369ns physical path delay SLICE_17 to SLICE_17 meets
+ 0.374ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.382ns
+ 0.000ns skew requirement (totaling -0.013ns) by 0.387ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c)
-ROUTE 2 0.135 R5C13C.Q0 to R5C13C.D0 CmdEnable
-CTOF_DEL --- 0.101 R5C13C.D0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.140 R5C11D.Q0 to R5C11D.D0 CmdEnable
+CTOF_DEL --- 0.101 R5C11D.D0 to R5C11D.F0 SLICE_17
+ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c)
--------
- 0.369 (63.4% logic, 36.6% route), 2 logic levels.
+ 0.374 (62.6% logic, 37.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CmdUFMWrite (from PHI2_c -)
+ Destination: FF Data in CmdUFMWrite (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_21 to SLICE_21 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_21 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_21 (from PHI2_c)
+ROUTE 2 0.212 R4C10D.Q0 to R4C10D.A1 CmdUFMWrite
+CTOF_DEL --- 0.101 R4C10D.A1 to R4C10D.F1 SLICE_21
+ROUTE 1 0.056 R4C10D.F1 to R4C10D.C0 N_279
+CTOF_DEL --- 0.101 R4C10D.C0 to R4C10D.F0 SLICE_21
+ROUTE 1 0.000 R4C10D.F0 to R4C10D.DI0 CmdUFMWrite_3 (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_21:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q Cmdn8MEGEN (from PHI2_c -)
+ Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_24 to SLICE_24 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_24 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_24 (from PHI2_c)
+ROUTE 2 0.212 R3C10C.Q0 to R3C10C.A1 Cmdn8MEGEN
+CTOF_DEL --- 0.101 R3C10C.A1 to R3C10C.F1 SLICE_24
+ROUTE 1 0.056 R3C10C.F1 to R3C10C.C0 Cmdn8MEGEN_4_u_i_0
+CTOF_DEL --- 0.101 R3C10C.C0 to R3C10C.F0 SLICE_24
+ROUTE 1 0.000 R3C10C.F0 to R3C10C.DI0 N_285_i (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_24:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.616ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q XOR8MEG (from PHI2_c -)
+ Destination: FF Data in XOR8MEG (to PHI2_c -)
+
+ Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
+
+ Constraint Details:
+
+ 0.603ns physical path delay SLICE_45 to SLICE_45 meets
+ -0.013ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.013ns) by 0.616ns
+
+ Physical Path Details:
+
+ Data path SLICE_45 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C10D.CLK to R5C10D.Q0 SLICE_45 (from PHI2_c)
+ROUTE 2 0.212 R5C10D.Q0 to R5C10D.A1 XOR8MEG
+CTOF_DEL --- 0.101 R5C10D.A1 to R5C10D.F1 SLICE_45
+ROUTE 1 0.056 R5C10D.F1 to R5C10D.C0 N_274
+CTOF_DEL --- 0.101 R5C10D.C0 to R5C10D.F0 SLICE_45
+ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 XOR8MEG_3 (to PHI2_c)
+ --------
+ 0.603 (55.6% logic, 44.4% route), 3 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1469,12 +1592,12 @@ Passed: The following path meets requirements by 0.628ns
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_18 (from PHI2_c)
-ROUTE 2 0.224 R5C9B.Q0 to R5C9B.B1 CmdLEDEN
-CTOF_DEL --- 0.101 R5C9B.B1 to R5C9B.F1 SLICE_18
-ROUTE 1 0.056 R5C9B.F1 to R5C9B.C0 CmdLEDEN_4_u_i_0_0
-CTOF_DEL --- 0.101 R5C9B.C0 to R5C9B.F0 SLICE_18
-ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_40_i (to PHI2_c)
+REG_DEL --- 0.133 R3C10B.CLK to R3C10B.Q0 SLICE_18 (from PHI2_c)
+ROUTE 2 0.224 R3C10B.Q0 to R3C10B.B1 CmdLEDEN
+CTOF_DEL --- 0.101 R3C10B.B1 to R3C10B.F1 SLICE_18
+ROUTE 1 0.056 R3C10B.F1 to R3C10B.C0 CmdLEDEN_4_u_i_0
+CTOF_DEL --- 0.101 R3C10B.C0 to R3C10B.F0 SLICE_18
+ROUTE 1 0.000 R3C10B.F0 to R3C10B.DI0 N_284_i (to PHI2_c)
--------
0.615 (54.5% logic, 45.5% route), 3 logic levels.
@@ -1483,247 +1606,106 @@ ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_40_i (to PHI2_c)
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
-Passed: The following path meets requirements by 0.628ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q XOR8MEG (from PHI2_c -)
- Destination: FF Data in XOR8MEG (to PHI2_c -)
-
- Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels.
-
- Constraint Details:
-
- 0.615ns physical path delay SLICE_44 to SLICE_44 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.628ns
-
- Physical Path Details:
-
- Data path SLICE_44 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_44 (from PHI2_c)
-ROUTE 2 0.224 R5C10B.Q0 to R5C10B.B1 XOR8MEG
-CTOF_DEL --- 0.101 R5C10B.B1 to R5C10B.F1 SLICE_44
-ROUTE 1 0.056 R5C10B.F1 to R5C10B.C0 N_441
-CTOF_DEL --- 0.101 R5C10B.C0 to R5C10B.F0 SLICE_44
-ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 XOR8MEG_3 (to PHI2_c)
- --------
- 0.615 (54.5% logic, 45.5% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_44:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.693ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q Cmdn8MEGEN (from PHI2_c -)
- Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
-
- Delay: 0.680ns (49.3% logic, 50.7% route), 3 logic levels.
-
- Constraint Details:
-
- 0.680ns physical path delay SLICE_24 to SLICE_24 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.693ns
-
- Physical Path Details:
-
- Data path SLICE_24 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_24 (from PHI2_c)
-ROUTE 2 0.135 R5C9C.Q0 to R5C9C.D1 Cmdn8MEGEN
-CTOF_DEL --- 0.101 R5C9C.D1 to R5C9C.F1 SLICE_24
-ROUTE 1 0.210 R5C9C.F1 to R5C9C.A0 Cmdn8MEGEN_4_u_i_0_0
-CTOF_DEL --- 0.101 R5C9C.A0 to R5C9C.F0 SLICE_24
-ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 N_38_i (to PHI2_c)
- --------
- 0.680 (49.3% logic, 50.7% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_24:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.702ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q CmdUFMWrite (from PHI2_c -)
- Destination: FF Data in CmdUFMWrite (to PHI2_c -)
-
- Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels.
-
- Constraint Details:
-
- 0.689ns physical path delay SLICE_21 to SLICE_21 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.702ns
-
- Physical Path Details:
-
- Data path SLICE_21 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_21 (from PHI2_c)
-ROUTE 2 0.212 R5C9A.Q0 to R5C9A.A1 CmdUFMWrite
-CTOF_DEL --- 0.101 R5C9A.A1 to R5C9A.F1 SLICE_21
-ROUTE 1 0.142 R5C9A.F1 to R5C9A.B0 N_462
-CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_21
-ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 CmdUFMWrite_3 (to PHI2_c)
- --------
- 0.689 (48.6% logic, 51.4% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_21:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.710ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q ADSubmitted (from PHI2_c -)
- Destination: FF Data in CmdEnable (to PHI2_c -)
-
- Delay: 0.697ns (48.1% logic, 51.9% route), 3 logic levels.
-
- Constraint Details:
-
- 0.697ns physical path delay SLICE_10 to SLICE_17 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.710ns
-
- Physical Path Details:
-
- Data path SLICE_10 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c)
-ROUTE 2 0.139 R5C13B.Q0 to R5C14C.C0 ADSubmitted
-CTOF_DEL --- 0.101 R5C14C.C0 to R5C14C.F0 SLICE_33
-ROUTE 1 0.223 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa
-CTOF_DEL --- 0.101 R5C13C.B0 to R5C13C.F0 SLICE_17
-ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c)
- --------
- 0.697 (48.1% logic, 51.9% route), 3 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path PHI2 to SLICE_10:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path PHI2 to SLICE_17:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
- --------
- 1.423 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.723ns
+Passed: The following path meets requirements by 0.632ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
- Destination: FF Data in XOR8MEG (to PHI2_c -)
+ Destination: FF Data in CmdValid_fast (to PHI2_c -)
- Delay: 0.695ns (33.7% logic, 66.3% route), 2 logic levels.
+ Delay: 0.619ns (54.1% logic, 45.9% route), 3 logic levels.
Constraint Details:
- 0.695ns physical path delay SLICE_17 to SLICE_44 meets
- -0.028ns CE_HLD and
+ 0.619ns physical path delay SLICE_17 to SLICE_23 meets
+ -0.013ns DIN_HLD and
0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.028ns) by 0.723ns
+ 0.000ns skew requirement (totaling -0.013ns) by 0.632ns
Physical Path Details:
- Data path SLICE_17 to SLICE_44:
+ Data path SLICE_17 to SLICE_23:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c)
-ROUTE 2 0.309 R5C13C.Q0 to R5C10A.B1 CmdEnable
-CTOF_DEL --- 0.101 R5C10A.B1 to R5C10A.F1 SLICE_23
-ROUTE 8 0.152 R5C10A.F1 to R5C10B.CE XOR8MEG18 (to PHI2_c)
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.226 R5C11D.Q0 to R4C10C.C1 CmdEnable
+CTOF_DEL --- 0.101 R4C10C.C1 to R4C10C.F1 SLICE_23
+ROUTE 2 0.058 R4C10C.F1 to R4C10C.C0 XOR8MEG18_i
+CTOF_DEL --- 0.101 R4C10C.C0 to R4C10C.F0 SLICE_23
+ROUTE 1 0.000 R4C10C.F0 to R4C10C.DI0 N_36_fast (to PHI2_c)
--------
- 0.695 (33.7% logic, 66.3% route), 2 logic levels.
+ 0.619 (54.1% logic, 45.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path PHI2 to SLICE_44:
+ Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
-ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
+ROUTE 21 1.423 8.PADDI to R4C10C.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.661ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CmdEnable (from PHI2_c -)
+ Destination: FF Data in XOR8MEG (to PHI2_c -)
+
+ Delay: 0.633ns (37.0% logic, 63.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.633ns physical path delay SLICE_17 to SLICE_45 meets
+ -0.028ns CE_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.028ns) by 0.661ns
+
+ Physical Path Details:
+
+ Data path SLICE_17 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c)
+ROUTE 4 0.140 R5C11D.Q0 to R5C11C.D1 CmdEnable
+CTOF_DEL --- 0.101 R5C11C.D1 to R5C11C.F1 SLICE_106
+ROUTE 5 0.259 R5C11C.F1 to R5C10D.CE XOR8MEG18 (to PHI2_c)
+ --------
+ 0.633 (37.0% logic, 63.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path PHI2 to SLICE_17:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c
+ --------
+ 1.423 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path PHI2 to SLICE_45:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1742,7 +1724,7 @@ ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
- 878 items scored, 0 timing errors detected.
+ 868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@@ -1767,8 +1749,8 @@ Passed: The following path meets requirements by 0.304ns
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R5C13D.CLK to R5C13D.Q0 SLICE_12 (from RCLK_c)
-ROUTE 1 0.152 R5C13D.Q0 to R5C13D.M1 CASr (to RCLK_c)
+REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q0 SLICE_12 (from RCLK_c)
+ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
@@ -1777,14 +1759,57 @@ ROUTE 1 0.152 R5C13D.Q0 to R5C13D.M1 CASr (to RCLK_c)
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q CASr2 (from RCLK_c +)
+ Destination: FF Data in CASr3 (to RCLK_c +)
+
+ Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.287ns physical path delay SLICE_12 to SLICE_76 meets
+ -0.019ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+ Data path SLICE_12 to SLICE_76:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q1 SLICE_12 (from RCLK_c)
+ROUTE 4 0.154 R5C12B.Q1 to R5C12D.M0 CASr2 (to RCLK_c)
+ --------
+ 0.287 (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path RCLK to SLICE_12:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path RCLK to SLICE_76:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R5C12D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1800,34 +1825,34 @@ Passed: The following path meets requirements by 0.306ns
Constraint Details:
- 0.287ns physical path delay SLICE_32 to SLICE_32 meets
+ 0.287ns physical path delay SLICE_33 to SLICE_33 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
- Data path SLICE_32 to SLICE_32:
+ Data path SLICE_33 to SLICE_33:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C14C.CLK to R7C14C.Q0 SLICE_32 (from RCLK_c)
-ROUTE 2 0.154 R7C14C.Q0 to R7C14C.M1 RASr (to RCLK_c)
+REG_DEL --- 0.133 R7C10D.CLK to R7C10D.Q0 SLICE_33 (from RCLK_c)
+ROUTE 2 0.154 R7C10D.Q0 to R7C10D.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_32:
+ Source Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_32:
+ Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1843,38 +1868,81 @@ Passed: The following path meets requirements by 0.311ns
Constraint Details:
- 0.292ns physical path delay SLICE_31 to SLICE_31 meets
+ 0.292ns physical path delay SLICE_32 to SLICE_32 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.311ns
Physical Path Details:
- Data path SLICE_31 to SLICE_31:
+ Data path SLICE_32 to SLICE_32:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R4C8A.CLK to R4C8A.Q0 SLICE_31 (from RCLK_c)
-ROUTE 5 0.159 R4C8A.Q0 to R4C8A.M1 PHI2r2 (to RCLK_c)
+REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_32 (from RCLK_c)
+ROUTE 5 0.159 R3C9D.Q0 to R3C9D.M1 PHI2r2 (to RCLK_c)
--------
0.292 (45.5% logic, 54.5% route), 1 logic levels.
Clock Skew Details:
- Source Clock Path RCLK to SLICE_31:
+ Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
- Destination Clock Path RCLK to SLICE_31:
+ Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
+Passed: The following path meets requirements by 0.347ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q wb_dati[3] (from RCLK_c +)
+ Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
+
+ Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.306ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets
+ -0.095ns WBDATI_HLD and
+ 0.000ns delay constraint less
+ -0.054ns skew requirement (totaling -0.041ns) by 0.347ns
+
+ Physical Path Details:
+
+ Data path SLICE_54 to ufmefb/EFBInst_0:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.133 R2C6D.CLK to R2C6D.Q1 SLICE_54 (from RCLK_c)
+ROUTE 2 0.173 R2C6D.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c)
+ --------
+ 0.306 (43.5% logic, 56.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path RCLK to SLICE_54:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.788 63.PADDI to R2C6D.CLK RCLK_c
+ --------
+ 0.788 (0.0% logic, 100.0% route), 0 logic levels.
+
+ Destination Clock Path RCLK to ufmefb/EFBInst_0:
+
+ Name Fanout Delay (ns) Site Resource
+ROUTE 48 0.842 63.PADDI to EFB.WBCLKI RCLK_c
+ --------
+ 0.842 (0.0% logic, 100.0% route), 0 logic levels.
+
+
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
@@ -1896,10 +1964,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C6A.CLK to R7C6A.Q1 SLICE_0 (from RCLK_c)
-ROUTE 3 0.132 R7C6A.Q1 to R7C6A.A1 FS[0]
-CTOF_DEL --- 0.101 R7C6A.A1 to R7C6A.F1 SLICE_0
-ROUTE 1 0.000 R7C6A.F1 to R7C6A.DI1 FS_s[0] (to RCLK_c)
+REG_DEL --- 0.133 R5C4A.CLK to R5C4A.Q1 SLICE_0 (from RCLK_c)
+ROUTE 3 0.132 R5C4A.Q1 to R5C4A.A1 FS[0]
+CTOF_DEL --- 0.101 R5C4A.A1 to R5C4A.F1 SLICE_0
+ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1908,14 +1976,14 @@ ROUTE 1 0.000 R7C6A.F1 to R7C6A.DI1 FS_s[0] (to RCLK_c)
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1941,10 +2009,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c)
-ROUTE 6 0.132 R7C8B.Q0 to R7C8B.A0 FS[17]
-CTOF_DEL --- 0.101 R7C8B.A0 to R7C8B.F0 SLICE_1
-ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 FS_s[17] (to RCLK_c)
+REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_1 (from RCLK_c)
+ROUTE 5 0.132 R5C6B.Q0 to R5C6B.A0 FS[17]
+CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_1
+ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1953,14 +2021,14 @@ ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 FS_s[17] (to RCLK_c)
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -1986,10 +2054,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q0 SLICE_2 (from RCLK_c)
-ROUTE 9 0.132 R7C8A.Q0 to R7C8A.A0 FS[15]
-CTOF_DEL --- 0.101 R7C8A.A0 to R7C8A.F0 SLICE_2
-ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 FS_s[15] (to RCLK_c)
+REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_2 (from RCLK_c)
+ROUTE 4 0.132 R5C6A.Q0 to R5C6A.A0 FS[15]
+CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_2
+ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -1998,14 +2066,14 @@ ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 FS_s[15] (to RCLK_c)
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -2031,10 +2099,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c)
-ROUTE 6 0.132 R7C8A.Q1 to R7C8A.A1 FS[16]
-CTOF_DEL --- 0.101 R7C8A.A1 to R7C8A.F1 SLICE_2
-ROUTE 1 0.000 R7C8A.F1 to R7C8A.DI1 FS_s[16] (to RCLK_c)
+REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q1 SLICE_2 (from RCLK_c)
+ROUTE 5 0.132 R5C6A.Q1 to R5C6A.A1 FS[16]
+CTOF_DEL --- 0.101 R5C6A.A1 to R5C6A.F1 SLICE_2
+ROUTE 1 0.000 R5C6A.F1 to R5C6A.DI1 FS_s[16] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -2043,104 +2111,14 @@ ROUTE 1 0.000 R7C8A.F1 to R7C8A.DI1 FS_s[16] (to RCLK_c)
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q FS[14] (from RCLK_c +)
- Destination: FF Data in FS[14] (to RCLK_c +)
-
- Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
- 0.366ns physical path delay SLICE_3 to SLICE_3 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
- Data path SLICE_3 to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q1 SLICE_3 (from RCLK_c)
-ROUTE 18 0.132 R7C7D.Q1 to R7C7D.A1 FS[14]
-CTOF_DEL --- 0.101 R7C7D.A1 to R7C7D.F1 SLICE_3
-ROUTE 1 0.000 R7C7D.F1 to R7C7D.DI1 FS_s[14] (to RCLK_c)
- --------
- 0.366 (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
-
- Source: FF Q FS[13] (from RCLK_c +)
- Destination: FF Data in FS[13] (to RCLK_c +)
-
- Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
- 0.366ns physical path delay SLICE_3 to SLICE_3 meets
- -0.013ns DIN_HLD and
- 0.000ns delay constraint less
- 0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
- Data path SLICE_3 to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q0 SLICE_3 (from RCLK_c)
-ROUTE 22 0.132 R7C7D.Q0 to R7C7D.A0 FS[13]
-CTOF_DEL --- 0.101 R7C7D.A0 to R7C7D.F0 SLICE_3
-ROUTE 1 0.000 R7C7D.F0 to R7C7D.DI0 FS_s[13] (to RCLK_c)
- --------
- 0.366 (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details:
-
- Source Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
- --------
- 0.788 (0.0% logic, 100.0% route), 0 logic levels.
-
- Destination Clock Path RCLK to SLICE_3:
-
- Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -2166,10 +2144,10 @@ Passed: The following path meets requirements by 0.379ns
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
-REG_DEL --- 0.133 R7C7C.CLK to R7C7C.Q1 SLICE_4 (from RCLK_c)
-ROUTE 21 0.132 R7C7C.Q1 to R7C7C.A1 FS[12]
-CTOF_DEL --- 0.101 R7C7C.A1 to R7C7C.F1 SLICE_4
-ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 FS_s[12] (to RCLK_c)
+REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c)
+ROUTE 23 0.132 R5C5C.Q1 to R5C5C.A1 FS[12]
+CTOF_DEL --- 0.101 R5C5C.A1 to R5C5C.F1 SLICE_4
+ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 FS_s[12] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
@@ -2178,14 +2156,14 @@ ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 FS_s[12] (to RCLK_c)
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
-ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c
+ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
@@ -2214,7 +2192,7 @@ All preferences were met.
Found 4 clocks:
-Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
+Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@@ -2226,7 +2204,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
-Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
+Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@@ -2256,7 +2234,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
-Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage)
+Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf
index a8cd816..6eacea8 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2GS")
- (DATE "Thu Sep 21 05:40:13 2023")
+ (DATE "Thu Oct 19 23:51:19 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")
@@ -259,7 +259,7 @@
(INSTANCE SLICE_10)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -305,7 +305,7 @@
(INSTANCE SLICE_12)
(DELAY
(ABSOLUTE
- (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
@@ -325,9 +325,11 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
@@ -375,8 +377,8 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
@@ -390,11 +392,32 @@
(SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
)
)
+ (CELL
+ (CELLTYPE "SLICE_19")
+ (INSTANCE SLICE_19)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
+ )
+ )
(CELL
(CELLTYPE "SLICE_20")
(INSTANCE SLICE_20)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -416,7 +439,7 @@
(INSTANCE SLICE_21)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -444,7 +467,7 @@
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
@@ -465,8 +488,8 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
@@ -507,9 +530,9 @@
(INSTANCE SLICE_25)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
@@ -528,7 +551,28 @@
(ABSOLUTE
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_27")
+ (INSTANCE SLICE_27)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
@@ -542,14 +586,14 @@
)
)
(CELL
- (CELLTYPE "SLICE_27")
- (INSTANCE SLICE_27)
+ (CELLTYPE "SLICE_28")
+ (INSTANCE SLICE_28)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -566,10 +610,12 @@
)
)
(CELL
- (CELLTYPE "SLICE_28")
- (INSTANCE SLICE_28)
+ (CELLTYPE "SLICE_29")
+ (INSTANCE SLICE_29)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -588,8 +634,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_29")
- (INSTANCE SLICE_29)
+ (CELLTYPE "SLICE_30")
+ (INSTANCE SLICE_30)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -609,42 +655,22 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_30")
- (INSTANCE SLICE_30)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_31")
(INSTANCE SLICE_31)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
(TIMINGCHECK
- (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
- (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -656,17 +682,20 @@
(INSTANCE SLICE_32)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
(TIMINGCHECK
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
(SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -681,13 +710,14 @@
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
(TIMINGCHECK
- (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -711,7 +741,7 @@
)
)
(TIMINGCHECK
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
)
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
@@ -723,7 +753,9 @@
(INSTANCE SLICE_35)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -746,7 +778,6 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -769,10 +800,11 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
)
@@ -790,32 +822,32 @@
(INSTANCE SLICE_38)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
)
)
+ (TIMINGCHECK
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ )
(TIMINGCHECK
(WIDTH (posedge CLK) (1250:1250:1250))
(WIDTH (negedge CLK) (1250:1250:1250))
)
- (TIMINGCHECK
- (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
- )
)
(CELL
(CELLTYPE "SLICE_39")
(INSTANCE SLICE_39)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
@@ -835,9 +867,9 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
@@ -858,7 +890,7 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -878,7 +910,29 @@
(INSTANCE SLICE_42)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_43")
+ (INSTANCE SLICE_43)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -896,8 +950,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_43")
- (INSTANCE SLICE_43)
+ (CELLTYPE "SLICE_44")
+ (INSTANCE SLICE_44)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -921,8 +975,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_44")
- (INSTANCE SLICE_44)
+ (CELLTYPE "SLICE_45")
+ (INSTANCE SLICE_45)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -946,8 +1000,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_45")
- (INSTANCE SLICE_45)
+ (CELLTYPE "SLICE_46")
+ (INSTANCE SLICE_46)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -969,12 +1023,14 @@
)
)
(CELL
- (CELLTYPE "SLICE_46")
- (INSTANCE SLICE_46)
+ (CELLTYPE "SLICE_47")
+ (INSTANCE SLICE_47)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -994,8 +1050,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_47")
- (INSTANCE SLICE_47)
+ (CELLTYPE "SLICE_48")
+ (INSTANCE SLICE_48)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1020,41 +1076,14 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_48")
- (INSTANCE SLICE_48)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_49")
(INSTANCE SLICE_49)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -1076,10 +1105,10 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -1098,6 +1127,30 @@
(CELL
(CELLTYPE "SLICE_51")
(INSTANCE SLICE_51)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_52")
+ (INSTANCE SLICE_52)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1124,8 +1177,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_52")
- (INSTANCE SLICE_52)
+ (CELLTYPE "SLICE_53")
+ (INSTANCE SLICE_53)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1150,37 +1203,12 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "SLICE_53")
- (INSTANCE SLICE_53)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
- (IOPATH CLK Q1 (392:422:452)(392:422:452))
- )
- )
- (TIMINGCHECK
- (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
- (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- )
(CELL
(CELLTYPE "SLICE_54")
(INSTANCE SLICE_54)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1211,7 +1239,6 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1239,9 +1266,36 @@
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH CLK Q1 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+ (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_57")
+ (INSTANCE SLICE_57)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
(TIMINGCHECK
@@ -1256,8 +1310,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_57")
- (INSTANCE SLICE_57)
+ (CELLTYPE "SLICE_58")
+ (INSTANCE SLICE_58)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1280,8 +1334,8 @@
)
)
(CELL
- (CELLTYPE "SLICE_58")
- (INSTANCE SLICE_58)
+ (CELLTYPE "SLICE_59")
+ (INSTANCE SLICE_59)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1307,23 +1361,6 @@
(WIDTH (negedge CLK) (1250:1250:1250))
)
)
- (CELL
- (CELLTYPE "wb_dati_5_1_iv_0_o3_5__SLICE_59")
- (INSTANCE wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 OFX0 (457:589:721)(457:589:721))
- (IOPATH C1 OFX0 (457:589:721)(457:589:721))
- (IOPATH B1 OFX0 (457:589:721)(457:589:721))
- (IOPATH A1 OFX0 (457:589:721)(457:589:721))
- (IOPATH D0 OFX0 (457:589:721)(457:589:721))
- (IOPATH C0 OFX0 (457:589:721)(457:589:721))
- (IOPATH B0 OFX0 (457:589:721)(457:589:721))
- (IOPATH A0 OFX0 (457:589:721)(457:589:721))
- (IOPATH M0 OFX0 (322:349:376)(322:349:376))
- )
- )
- )
(CELL
(CELLTYPE "SLICE_60")
(INSTANCE SLICE_60)
@@ -1351,6 +1388,7 @@
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
@@ -1364,6 +1402,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1425,7 +1464,6 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1456,6 +1494,7 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1473,7 +1512,6 @@
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -1488,7 +1526,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -1501,10 +1539,10 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
@@ -1519,6 +1557,7 @@
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -1537,112 +1576,6 @@
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_74")
- (INSTANCE SLICE_74)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_75")
- (INSTANCE SLICE_75)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_76")
- (INSTANCE SLICE_76)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_77")
- (INSTANCE SLICE_77)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_78")
- (INSTANCE SLICE_78)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_79")
- (INSTANCE SLICE_79)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_80")
- (INSTANCE SLICE_80)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
(IOPATH CLK Q0 (392:422:452)(392:422:452))
(IOPATH CLK Q1 (392:422:452)(392:422:452))
)
@@ -1656,6 +1589,116 @@
(SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
)
)
+ (CELL
+ (CELLTYPE "SLICE_74")
+ (INSTANCE SLICE_74)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_75")
+ (INSTANCE SLICE_75)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_76")
+ (INSTANCE SLICE_76)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (1250:1250:1250))
+ (WIDTH (negedge CLK) (1250:1250:1250))
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_77")
+ (INSTANCE SLICE_77)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_78")
+ (INSTANCE SLICE_78)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_79")
+ (INSTANCE SLICE_79)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "SLICE_80")
+ (INSTANCE SLICE_80)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
+ )
+ )
+ )
(CELL
(CELLTYPE "SLICE_81")
(INSTANCE SLICE_81)
@@ -1663,6 +1706,7 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1677,22 +1721,13 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
- (TIMINGCHECK
- (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
- (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
- )
)
(CELL
(CELLTYPE "SLICE_83")
@@ -1700,6 +1735,8 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1715,8 +1752,6 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1746,8 +1781,6 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1762,7 +1795,6 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1776,9 +1808,7 @@
(INSTANCE SLICE_88)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1794,6 +1824,8 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1824,8 +1856,6 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1841,6 +1871,7 @@
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1853,9 +1884,7 @@
(INSTANCE SLICE_93)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1870,8 +1899,6 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1886,7 +1913,7 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1900,6 +1927,8 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1913,8 +1942,9 @@
(INSTANCE SLICE_97)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1927,6 +1957,7 @@
(INSTANCE SLICE_98)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1941,6 +1972,7 @@
(INSTANCE SLICE_99)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1955,7 +1987,9 @@
(INSTANCE SLICE_100)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1969,7 +2003,7 @@
(INSTANCE SLICE_101)
(DELAY
(ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1983,11 +2017,9 @@
(INSTANCE SLICE_102)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
@@ -1997,12 +2029,13 @@
(INSTANCE SLICE_103)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
)
@@ -2014,10 +2047,9 @@
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
)
@@ -2026,11 +2058,10 @@
(INSTANCE SLICE_105)
(DELAY
(ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
@@ -2045,6 +2076,7 @@
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2056,23 +2088,15 @@
(INSTANCE SLICE_107)
(DELAY
(ABSOLUTE
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
- (IOPATH CLK Q0 (392:422:452)(392:422:452))
)
)
- (TIMINGCHECK
- (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
- )
- (TIMINGCHECK
- (WIDTH (posedge CLK) (1250:1250:1250))
- (WIDTH (negedge CLK) (1250:1250:1250))
- )
)
(CELL
(CELLTYPE "SLICE_108")
@@ -2081,7 +2105,6 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -2097,7 +2120,6 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -2112,9 +2134,7 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2126,8 +2146,10 @@
(INSTANCE SLICE_111)
(DELAY
(ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
)
@@ -2140,8 +2162,8 @@
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
)
@@ -2152,10 +2174,12 @@
(INSTANCE SLICE_113)
(DELAY
(ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
+ (IOPATH D1 F1 (367:431:495)(367:431:495))
+ (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
+ (IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
)
@@ -2165,10 +2189,8 @@
(DELAY
(ABSOLUTE
(IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
+ (IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
@@ -2179,10 +2201,10 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
(IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH D0 F0 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
+ (IOPATH B0 F0 (367:431:495)(367:431:495))
(IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
@@ -2193,109 +2215,25 @@
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
+ (IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
)
)
)
(CELL
(CELLTYPE "SLICE_117")
(INSTANCE SLICE_117)
- (DELAY
- (ABSOLUTE
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_118")
- (INSTANCE SLICE_118)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_119")
- (INSTANCE SLICE_119)
(DELAY
(ABSOLUTE
(IOPATH D1 F1 (367:431:495)(367:431:495))
(IOPATH C1 F1 (367:431:495)(367:431:495))
(IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
(IOPATH C0 F0 (367:431:495)(367:431:495))
(IOPATH B0 F0 (367:431:495)(367:431:495))
)
)
)
- (CELL
- (CELLTYPE "SLICE_120")
- (INSTANCE SLICE_120)
- (DELAY
- (ABSOLUTE
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_121")
- (INSTANCE SLICE_121)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_122")
- (INSTANCE SLICE_122)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH C1 F1 (367:431:495)(367:431:495))
- (IOPATH B1 F1 (367:431:495)(367:431:495))
- (IOPATH B0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
- (CELL
- (CELLTYPE "SLICE_123")
- (INSTANCE SLICE_123)
- (DELAY
- (ABSOLUTE
- (IOPATH D1 F1 (367:431:495)(367:431:495))
- (IOPATH A1 F1 (367:431:495)(367:431:495))
- (IOPATH D0 F0 (367:431:495)(367:431:495))
- (IOPATH C0 F0 (367:431:495)(367:431:495))
- (IOPATH A0 F0 (367:431:495)(367:431:495))
- )
- )
- )
(CELL
(CELLTYPE "RD_0_")
(INSTANCE RD\[0\]_I)
@@ -2468,6 +2406,32 @@
)
)
)
+ (CELL
+ (CELLTYPE "RCLKout")
+ (INSTANCE RCLKout_I)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH IOLDO RCLKout (2773:2901:3030)(2773:2901:3030))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "RCLKout_MGIOL")
+ (INSTANCE RCLKout_MGIOL)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH CLK IOLDO (1172:1208:1244)(1172:1208:1244))
+ )
+ )
+ (TIMINGCHECK
+ (SETUPHOLD ONEG (posedge CLK) (72:72:72)(-52:-52:-52))
+ (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+ )
+ (TIMINGCHECK
+ (WIDTH (posedge CLK) (4807:4807:4807))
+ (WIDTH (negedge CLK) (4807:4807:4807))
+ )
+ )
(CELL
(CELLTYPE "RCLK")
(INSTANCE RCLK_I)
@@ -3463,8 +3427,8 @@
(DELAY
(ABSOLUTE
(INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_0/Q1 SLICE_92/B1 (1450:1645:1841)(1450:1645:1841))
- (INTERCONNECT SLICE_0/Q1 SLICE_121/B1 (1450:1645:1841)(1450:1645:1841))
+ (INTERCONNECT SLICE_0/Q1 SLICE_52/D1 (973:1072:1171)(973:1072:1171))
+ (INTERCONNECT SLICE_0/Q1 SLICE_87/B1 (1215:1382:1549)(1215:1382:1549))
(INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
(INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (2061:2162:2264)(2061:2162:2264))
@@ -3487,26 +3451,24 @@
(INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_46/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_49/CLK (2061:2162:2264)(2061:2162:2264))
@@ -3514,7 +3476,7 @@
(INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (2061:2162:2264)(2061:2162:2264))
@@ -3523,13 +3485,16 @@
(INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (2061:2162:2264)(2061:2162:2264))
- (INTERCONNECT RCLK_I/PADDI SLICE_107/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (2061:2162:2264)(2061:2162:2264))
+ (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (2061:2162:2264)(2061:2162:2264))
(INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (2208:2322:2437)(2208:2322:2437))
+ (INTERCONNECT RCLK_I/PADDI RCLKout_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (2208:2322:2436)(2208:2322:2436))
(INTERCONNECT RCLK_I/PADDI
@@ -3537,230 +3502,213 @@
(2208:2322:2437))
(INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_1/Q0 SLICE_56/D1 (1016:1110:1204)(1016:1110:1204))
- (INTERCONNECT SLICE_1/Q0 SLICE_57/D1 (1391:1517:1644)(1391:1517:1644))
- (INTERCONNECT SLICE_1/Q0 SLICE_66/C1 (1806:2030:2255)(1806:2030:2255))
- (INTERCONNECT SLICE_1/Q0 SLICE_97/B1 (1997:2223:2449)(1997:2223:2449))
- (INTERCONNECT SLICE_1/Q0 SLICE_123/D0 (1755:1913:2071)(1755:1913:2071))
+ (INTERCONNECT SLICE_1/Q0 SLICE_58/C1 (819:962:1105)(819:962:1105))
+ (INTERCONNECT SLICE_1/Q0 SLICE_61/C1 (819:962:1105)(819:962:1105))
+ (INTERCONNECT SLICE_1/Q0 SLICE_103/C1 (819:962:1105)(819:962:1105))
+ (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (819:962:1105)(819:962:1105))
(INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_2/Q1 SLICE_56/C1 (1027:1176:1325)(1027:1176:1325))
- (INTERCONNECT SLICE_2/Q1 SLICE_57/B1 (1960:2189:2419)(1960:2189:2419))
- (INTERCONNECT SLICE_2/Q1 SLICE_66/B1 (2037:2274:2512)(2037:2274:2512))
- (INTERCONNECT SLICE_2/Q1 SLICE_97/C1 (1766:1979:2192)(1766:1979:2192))
- (INTERCONNECT SLICE_2/Q1 SLICE_123/C0 (1766:1979:2192)(1766:1979:2192))
+ (INTERCONNECT SLICE_2/Q1 SLICE_58/B1 (1493:1691:1890)(1493:1691:1890))
+ (INTERCONNECT SLICE_2/Q1 SLICE_61/D1 (1230:1356:1483)(1230:1356:1483))
+ (INTERCONNECT SLICE_2/Q1 SLICE_103/B1 (1493:1691:1890)(1493:1691:1890))
+ (INTERCONNECT SLICE_2/Q1 SLICE_103/B0 (1493:1691:1890)(1493:1691:1890))
(INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_2/Q0 SLICE_49/D1 (1810:1972:2134)(1810:1972:2134))
- (INTERCONNECT SLICE_2/Q0 SLICE_49/D0 (1810:1972:2134)(1810:1972:2134))
- (INTERCONNECT SLICE_2/Q0 SLICE_50/B0 (2379:2644:2909)(2379:2644:2909))
- (INTERCONNECT SLICE_2/Q0 SLICE_57/C1 (1903:2115:2327)(1903:2115:2327))
- (INTERCONNECT SLICE_2/Q0 SLICE_58/C1 (1903:2115:2327)(1903:2115:2327))
- (INTERCONNECT SLICE_2/Q0 SLICE_66/A1 (1651:1846:2042)(1651:1846:2042))
- (INTERCONNECT SLICE_2/Q0 SLICE_97/B0 (2047:2276:2506)(2047:2276:2506))
- (INTERCONNECT SLICE_2/Q0 SLICE_123/A0 (2466:2720:2974)(2466:2720:2974))
+ (INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (1013:1166:1319)(1013:1166:1319))
+ (INTERCONNECT SLICE_2/Q0 SLICE_61/A1 (1013:1166:1319)(1013:1166:1319))
+ (INTERCONNECT SLICE_2/Q0 SLICE_103/A1 (1013:1166:1319)(1013:1166:1319))
(INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_3/Q1 SLICE_62/B0 (1242:1414:1586)(1242:1414:1586))
- (INTERCONNECT SLICE_3/Q1 SLICE_69/B1 (1600:1812:2024)(1600:1812:2024))
- (INTERCONNECT SLICE_3/Q1 SLICE_70/A0 (1595:1798:2001)(1595:1798:2001))
- (INTERCONNECT SLICE_3/Q1 SLICE_75/D1 (1374:1510:1647)(1374:1510:1647))
- (INTERCONNECT SLICE_3/Q1 SLICE_76/B1 (1964:2207:2451)(1964:2207:2451))
- (INTERCONNECT SLICE_3/Q1 SLICE_77/A1 (1932:2173:2414)(1932:2173:2414))
- (INTERCONNECT SLICE_3/Q1 SLICE_87/C1 (1733:1963:2194)(1733:1963:2194))
- (INTERCONNECT SLICE_3/Q1 SLICE_96/A1 (1959:2193:2428)(1959:2193:2428))
- (INTERCONNECT SLICE_3/Q1 SLICE_101/B1 (1683:1881:2079)(1683:1881:2079))
- (INTERCONNECT SLICE_3/Q1 SLICE_102/C0 (1452:1637:1822)(1452:1637:1822))
- (INTERCONNECT SLICE_3/Q1 SLICE_104/C1 (1381:1572:1763)(1381:1572:1763))
- (INTERCONNECT SLICE_3/Q1 SLICE_104/C0 (1381:1572:1763)(1381:1572:1763))
- (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (1600:1812:2024)(1600:1812:2024))
- (INTERCONNECT SLICE_3/Q1 SLICE_105/B0 (1600:1812:2024)(1600:1812:2024))
- (INTERCONNECT SLICE_3/Q1 SLICE_106/D1 (1000:1104:1208)(1000:1104:1208))
- (INTERCONNECT SLICE_3/Q1 SLICE_110/D0 (1712:1884:2057)(1712:1884:2057))
- (INTERCONNECT SLICE_3/Q1 SLICE_113/A1 (1220:1390:1561)(1220:1390:1561))
- (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/C0 (1432:1616:1801)
- (1432:1616:1801))
- (INTERCONNECT SLICE_3/Q0 SLICE_63/B0 (2048:2279:2510)(2048:2279:2510))
- (INTERCONNECT SLICE_3/Q0 SLICE_67/D0 (1031:1126:1222)(1031:1126:1222))
- (INTERCONNECT SLICE_3/Q0 SLICE_69/B0 (2048:2279:2510)(2048:2279:2510))
- (INTERCONNECT SLICE_3/Q0 SLICE_70/B1 (1273:1436:1600)(1273:1436:1600))
- (INTERCONNECT SLICE_3/Q0 SLICE_76/C1 (1432:1616:1801)(1432:1616:1801))
- (INTERCONNECT SLICE_3/Q0 SLICE_77/B1 (1663:1860:2058)(1663:1860:2058))
- (INTERCONNECT SLICE_3/Q0 SLICE_87/A0 (1958:2188:2418)(1958:2188:2418))
- (INTERCONNECT SLICE_3/Q0 SLICE_89/D0 (1411:1539:1668)(1411:1539:1668))
- (INTERCONNECT SLICE_3/Q0 SLICE_91/D1 (1421:1550:1680)(1421:1550:1680))
- (INTERCONNECT SLICE_3/Q0 SLICE_95/B1 (2048:2279:2510)(2048:2279:2510))
- (INTERCONNECT SLICE_3/Q0 SLICE_96/D0 (1411:1539:1668)(1411:1539:1668))
- (INTERCONNECT SLICE_3/Q0 SLICE_102/C1 (1786:2001:2216)(1786:2001:2216))
- (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (1401:1528:1656)(1401:1528:1656))
- (INTERCONNECT SLICE_3/Q0 SLICE_104/D0 (1401:1528:1656)(1401:1528:1656))
- (INTERCONNECT SLICE_3/Q0 SLICE_105/D1 (2144:2344:2544)(2144:2344:2544))
- (INTERCONNECT SLICE_3/Q0 SLICE_105/D0 (2144:2344:2544)(2144:2344:2544))
- (INTERCONNECT SLICE_3/Q0 SLICE_106/B1 (2418:2681:2944)(2418:2681:2944))
- (INTERCONNECT SLICE_3/Q0 SLICE_106/B0 (2418:2681:2944)(2418:2681:2944))
- (INTERCONNECT SLICE_3/Q0 SLICE_109/D1 (1411:1539:1668)(1411:1539:1668))
- (INTERCONNECT SLICE_3/Q0 SLICE_110/A1 (1568:1764:1960)(1568:1764:1960))
+ (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_3/Q1 SLICE_30/C1 (1006:1165:1324)(1006:1165:1324))
+ (INTERCONNECT SLICE_3/Q1 SLICE_57/D1 (995:1099:1203)(995:1099:1203))
+ (INTERCONNECT SLICE_3/Q1 SLICE_58/B0 (1237:1409:1581)(1237:1409:1581))
+ (INTERCONNECT SLICE_3/Q1 SLICE_65/D1 (1370:1506:1643)(1370:1506:1643))
+ (INTERCONNECT SLICE_3/Q1 SLICE_67/D0 (1380:1517:1655)(1380:1517:1655))
+ (INTERCONNECT SLICE_3/Q1 SLICE_70/C1 (557:674:792)(557:674:792))
+ (INTERCONNECT SLICE_3/Q1 SLICE_71/D1 (1380:1517:1655)(1380:1517:1655))
+ (INTERCONNECT SLICE_3/Q1 SLICE_72/D1 (916:1010:1105)(916:1010:1105))
+ (INTERCONNECT SLICE_3/Q1 SLICE_77/D1 (1370:1506:1643)(1370:1506:1643))
+ (INTERCONNECT SLICE_3/Q1 SLICE_82/B0 (788:918:1049)(788:918:1049))
+ (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (927:1076:1226)(927:1076:1226))
+ (INTERCONNECT SLICE_3/Q1 SLICE_86/A1 (1630:1824:2018)(1630:1824:2018))
+ (INTERCONNECT SLICE_3/Q1 SLICE_99/D1 (1380:1517:1655)(1380:1517:1655))
+ (INTERCONNECT SLICE_3/Q1 SLICE_99/D0 (1380:1517:1655)(1380:1517:1655))
+ (INTERCONNECT SLICE_3/Q1 SLICE_100/A1 (1928:2168:2408)(1928:2168:2408))
+ (INTERCONNECT SLICE_3/Q1 SLICE_100/A0 (1928:2168:2408)(1928:2168:2408))
+ (INTERCONNECT SLICE_3/Q1 SLICE_107/D1 (1370:1506:1643)(1370:1506:1643))
+ (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_3/Q0 SLICE_30/B1 (1478:1671:1864)(1478:1671:1864))
+ (INTERCONNECT SLICE_3/Q0 SLICE_57/C1 (1247:1427:1607)(1247:1427:1607))
+ (INTERCONNECT SLICE_3/Q0 SLICE_60/D1 (2307:2531:2756)(2307:2531:2756))
+ (INTERCONNECT SLICE_3/Q0 SLICE_60/C0 (1991:2235:2480)(1991:2235:2480))
+ (INTERCONNECT SLICE_3/Q0 SLICE_63/A1 (2580:2869:3158)(2580:2869:3158))
+ (INTERCONNECT SLICE_3/Q0 SLICE_65/A1 (2580:2869:3158)(2580:2869:3158))
+ (INTERCONNECT SLICE_3/Q0 SLICE_65/A0 (2580:2869:3158)(2580:2869:3158))
+ (INTERCONNECT SLICE_3/Q0 SLICE_66/A0 (1200:1369:1538)(1200:1369:1538))
+ (INTERCONNECT SLICE_3/Q0 SLICE_67/B0 (1923:2161:2399)(1923:2161:2399))
+ (INTERCONNECT SLICE_3/Q0 SLICE_70/A1 (1522:1725:1929)(1522:1725:1929))
+ (INTERCONNECT SLICE_3/Q0 SLICE_71/C0 (2708:3021:3335)(2708:3021:3335))
+ (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (2560:2847:3134)(2560:2847:3134))
+ (INTERCONNECT SLICE_3/Q0 SLICE_82/D0 (1323:1463:1603)(1323:1463:1603))
+ (INTERCONNECT SLICE_3/Q0 SLICE_85/B1 (1559:1765:1972)(1559:1765:1972))
+ (INTERCONNECT SLICE_3/Q0 SLICE_86/D1 (1317:1455:1594)(1317:1455:1594))
+ (INTERCONNECT SLICE_3/Q0 SLICE_88/A0 (1533:1738:1944)(1533:1738:1944))
+ (INTERCONNECT SLICE_3/Q0 SLICE_94/C0 (2688:2999:3311)(2688:2999:3311))
+ (INTERCONNECT SLICE_3/Q0 SLICE_99/C1 (1698:1924:2151)(1698:1924:2151))
+ (INTERCONNECT SLICE_3/Q0 SLICE_99/C0 (2745:3055:3365)(2745:3055:3365))
+ (INTERCONNECT SLICE_3/Q0 SLICE_100/C1 (1698:1924:2151)(1698:1924:2151))
+ (INTERCONNECT SLICE_3/Q0 SLICE_107/B1 (3309:3667:4026)(3309:3667:4026))
+ (INTERCONNECT SLICE_3/Q0 SLICE_107/C0 (2751:3061:3372)(2751:3061:3372))
(INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/B1 (1603:1814:2026)
- (1603:1814:2026))
- (INTERCONNECT SLICE_4/Q1 SLICE_63/D1 (1034:1142:1251)(1034:1142:1251))
- (INTERCONNECT SLICE_4/Q1 SLICE_63/D0 (1034:1142:1251)(1034:1142:1251))
- (INTERCONNECT SLICE_4/Q1 SLICE_69/D1 (1034:1142:1251)(1034:1142:1251))
- (INTERCONNECT SLICE_4/Q1 SLICE_70/B0 (1651:1860:2069)(1651:1860:2069))
- (INTERCONNECT SLICE_4/Q1 SLICE_73/B0 (1646:1854:2063)(1646:1854:2063))
- (INTERCONNECT SLICE_4/Q1 SLICE_75/C0 (1736:1966:2196)(1736:1966:2196))
- (INTERCONNECT SLICE_4/Q1 SLICE_76/A0 (1614:1820:2026)(1614:1820:2026))
- (INTERCONNECT SLICE_4/Q1 SLICE_77/D1 (1404:1544:1685)(1404:1544:1685))
- (INTERCONNECT SLICE_4/Q1 SLICE_87/D1 (1444:1576:1709)(1444:1576:1709))
- (INTERCONNECT SLICE_4/Q1 SLICE_95/D1 (1034:1142:1251)(1034:1142:1251))
- (INTERCONNECT SLICE_4/Q1 SLICE_96/A0 (1978:2215:2453)(1978:2215:2453))
- (INTERCONNECT SLICE_4/Q1 SLICE_101/A1 (1655:1852:2049)(1655:1852:2049))
- (INTERCONNECT SLICE_4/Q1 SLICE_102/B0 (1687:1886:2086)(1687:1886:2086))
- (INTERCONNECT SLICE_4/Q1 SLICE_104/B1 (1692:1893:2094)(1692:1893:2094))
- (INTERCONNECT SLICE_4/Q1 SLICE_104/B0 (1692:1893:2094)(1692:1893:2094))
- (INTERCONNECT SLICE_4/Q1 SLICE_106/C1 (1010:1170:1330)(1010:1170:1330))
- (INTERCONNECT SLICE_4/Q1 SLICE_106/C0 (1010:1170:1330)(1010:1170:1330))
- (INTERCONNECT SLICE_4/Q1 SLICE_110/C1 (1420:1616:1812)(1420:1616:1812))
- (INTERCONNECT SLICE_4/Q1 SLICE_110/C0 (1420:1616:1812)(1420:1616:1812))
- (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_4/Q0 SLICE_29/C1 (606:731:857)(606:731:857))
- (INTERCONNECT SLICE_4/Q0 SLICE_52/A1 (1945:2180:2415)(1945:2180:2415))
- (INTERCONNECT SLICE_4/Q0 SLICE_55/C0 (1376:1568:1761)(1376:1568:1761))
- (INTERCONNECT SLICE_4/Q0 SLICE_62/D1 (1297:1435:1573)(1297:1435:1573))
- (INTERCONNECT SLICE_4/Q0 SLICE_67/A0 (1945:2180:2415)(1945:2180:2415))
- (INTERCONNECT SLICE_4/Q0 SLICE_68/A1 (805:941:1077)(805:941:1077))
- (INTERCONNECT SLICE_4/Q0 SLICE_69/A0 (1882:2118:2354)(1882:2118:2354))
- (INTERCONNECT SLICE_4/Q0 SLICE_70/A1 (1180:1348:1517)(1180:1348:1517))
- (INTERCONNECT SLICE_4/Q0 SLICE_71/A0 (1945:2180:2415)(1945:2180:2415))
- (INTERCONNECT SLICE_4/Q0 SLICE_73/C0 (1731:1954:2177)(1731:1954:2177))
- (INTERCONNECT SLICE_4/Q0 SLICE_75/D0 (1692:1864:2037)(1692:1864:2037))
- (INTERCONNECT SLICE_4/Q0 SLICE_76/A1 (1902:2140:2378)(1902:2140:2378))
- (INTERCONNECT SLICE_4/Q0 SLICE_77/C0 (1376:1568:1761)(1376:1568:1761))
- (INTERCONNECT SLICE_4/Q0 SLICE_86/D1 (2047:2250:2453)(2047:2250:2453))
- (INTERCONNECT SLICE_4/Q0 SLICE_87/C0 (1376:1568:1761)(1376:1568:1761))
- (INTERCONNECT SLICE_4/Q0 SLICE_89/B0 (2337:2605:2874)(2337:2605:2874))
- (INTERCONNECT SLICE_4/Q0 SLICE_95/B0 (1914:2152:2391)(1914:2152:2391))
- (INTERCONNECT SLICE_4/Q0 SLICE_102/A1 (1945:2180:2415)(1945:2180:2415))
- (INTERCONNECT SLICE_4/Q0 SLICE_109/C1 (2106:2361:2617)(2106:2361:2617))
- (INTERCONNECT SLICE_4/Q0 SLICE_109/C0 (2106:2361:2617)(2106:2361:2617))
- (INTERCONNECT SLICE_4/Q0 SLICE_110/B1 (1539:1745:1951)(1539:1745:1951))
- (INTERCONNECT SLICE_4/Q0 SLICE_110/A0 (1180:1348:1517)(1180:1348:1517))
+ (INTERCONNECT SLICE_4/Q1 SLICE_34/C0 (539:652:765)(539:652:765))
+ (INTERCONNECT SLICE_4/Q1 SLICE_48/C1 (2283:2565:2848)(2283:2565:2848))
+ (INTERCONNECT SLICE_4/Q1 SLICE_57/B1 (1442:1638:1834)(1442:1638:1834))
+ (INTERCONNECT SLICE_4/Q1 SLICE_63/B0 (1817:2045:2274)(1817:2045:2274))
+ (INTERCONNECT SLICE_4/Q1 SLICE_65/B0 (1442:1638:1834)(1442:1638:1834))
+ (INTERCONNECT SLICE_4/Q1 SLICE_66/A1 (1785:2011:2237)(1785:2011:2237))
+ (INTERCONNECT SLICE_4/Q1 SLICE_69/B0 (1447:1643:1840)(1447:1643:1840))
+ (INTERCONNECT SLICE_4/Q1 SLICE_70/B1 (1447:1643:1840)(1447:1643:1840))
+ (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (1918:2170:2422)(1918:2170:2422))
+ (INTERCONNECT SLICE_4/Q1 SLICE_80/A0 (1035:1196:1357)(1035:1196:1357))
+ (INTERCONNECT SLICE_4/Q1 SLICE_82/D1 (1575:1735:1896)(1575:1735:1896))
+ (INTERCONNECT SLICE_4/Q1 SLICE_83/B1 (1857:2097:2337)(1857:2097:2337))
+ (INTERCONNECT SLICE_4/Q1 SLICE_85/D1 (1615:1787:1959)(1615:1787:1959))
+ (INTERCONNECT SLICE_4/Q1 SLICE_86/D0 (1923:2122:2322)(1923:2122:2322))
+ (INTERCONNECT SLICE_4/Q1 SLICE_94/A0 (2117:2379:2642)(2117:2379:2642))
+ (INTERCONNECT SLICE_4/Q1 SLICE_98/D1 (825:920:1016)(825:920:1016))
+ (INTERCONNECT SLICE_4/Q1 SLICE_98/D0 (825:920:1016)(825:920:1016))
+ (INTERCONNECT SLICE_4/Q1 SLICE_100/B1 (1857:2097:2337)(1857:2097:2337))
+ (INTERCONNECT SLICE_4/Q1 SLICE_100/B0 (1067:1230:1394)(1067:1230:1394))
+ (INTERCONNECT SLICE_4/Q1 SLICE_101/A1 (2133:2398:2663)(2133:2398:2663))
+ (INTERCONNECT SLICE_4/Q1 SLICE_101/A0 (2133:2398:2663)(2133:2398:2663))
+ (INTERCONNECT SLICE_4/Q1 SLICE_107/B0 (2187:2447:2708)(2187:2447:2708))
+ (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_4/Q0 SLICE_34/B0 (1413:1608:1803)(1413:1608:1803))
+ (INTERCONNECT SLICE_4/Q0 SLICE_48/B1 (1413:1608:1803)(1413:1608:1803))
+ (INTERCONNECT SLICE_4/Q0 SLICE_48/B0 (1413:1608:1803)(1413:1608:1803))
+ (INTERCONNECT SLICE_4/Q0 SLICE_65/D0 (1380:1517:1655)(1380:1517:1655))
+ (INTERCONNECT SLICE_4/Q0 SLICE_66/D1 (1005:1110:1215)(1005:1110:1215))
+ (INTERCONNECT SLICE_4/Q0 SLICE_66/D0 (1005:1110:1215)(1005:1110:1215))
+ (INTERCONNECT SLICE_4/Q0 SLICE_69/D1 (1755:1925:2095)(1755:1925:2095))
+ (INTERCONNECT SLICE_4/Q0 SLICE_70/D1 (1233:1363:1494)(1233:1363:1494))
+ (INTERCONNECT SLICE_4/Q0 SLICE_71/A0 (1590:1793:1996)(1590:1793:1996))
+ (INTERCONNECT SLICE_4/Q0 SLICE_72/D0 (2119:2320:2522)(2119:2320:2522))
+ (INTERCONNECT SLICE_4/Q0 SLICE_80/C0 (1386:1578:1770)(1386:1578:1770))
+ (INTERCONNECT SLICE_4/Q0 SLICE_82/A1 (1195:1363:1532)(1195:1363:1532))
+ (INTERCONNECT SLICE_4/Q0 SLICE_83/D1 (1005:1110:1215)(1005:1110:1215))
+ (INTERCONNECT SLICE_4/Q0 SLICE_88/C0 (1323:1516:1709)(1323:1516:1709))
+ (INTERCONNECT SLICE_4/Q0 SLICE_94/D0 (1560:1725:1891)(1560:1725:1891))
+ (INTERCONNECT SLICE_4/Q0 SLICE_98/A0 (1559:1759:1959)(1559:1759:1959))
+ (INTERCONNECT SLICE_4/Q0 SLICE_100/D1 (1755:1925:2095)(1755:1925:2095))
+ (INTERCONNECT SLICE_4/Q0 SLICE_100/D0 (1375:1512:1649)(1375:1512:1649))
+ (INTERCONNECT SLICE_4/Q0 SLICE_101/D1 (1005:1110:1215)(1005:1110:1215))
+ (INTERCONNECT SLICE_4/Q0 SLICE_101/B0 (1574:1782:1990)(1574:1782:1990))
(INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_5/Q1 SLICE_29/B1 (837:975:1114)(837:975:1114))
- (INTERCONNECT SLICE_5/Q1 SLICE_62/B1 (1217:1388:1560)(1217:1388:1560))
- (INTERCONNECT SLICE_5/Q1 SLICE_65/B1 (1222:1394:1566)(1222:1394:1566))
- (INTERCONNECT SLICE_5/Q1 SLICE_67/B1 (1222:1394:1566)(1222:1394:1566))
- (INTERCONNECT SLICE_5/Q1 SLICE_67/B0 (1222:1394:1566)(1222:1394:1566))
- (INTERCONNECT SLICE_5/Q1 SLICE_68/D1 (595:665:736)(595:665:736))
- (INTERCONNECT SLICE_5/Q1 SLICE_69/D0 (1350:1486:1622)(1350:1486:1622))
- (INTERCONNECT SLICE_5/Q1 SLICE_71/D0 (1350:1486:1622)(1350:1486:1622))
- (INTERCONNECT SLICE_5/Q1 SLICE_73/D0 (1714:1881:2049)(1714:1881:2049))
- (INTERCONNECT SLICE_5/Q1 SLICE_76/D1 (1355:1491:1628)(1355:1491:1628))
- (INTERCONNECT SLICE_5/Q1 SLICE_77/D0 (1355:1491:1628)(1355:1491:1628))
- (INTERCONNECT SLICE_5/Q1 SLICE_85/D1 (1730:1899:2068)(1730:1899:2068))
- (INTERCONNECT SLICE_5/Q1 SLICE_87/D0 (1355:1491:1628)(1355:1491:1628))
- (INTERCONNECT SLICE_5/Q1 SLICE_89/D1 (1355:1491:1628)(1355:1491:1628))
- (INTERCONNECT SLICE_5/Q1 SLICE_101/D0 (1730:1899:2068)(1730:1899:2068))
- (INTERCONNECT SLICE_5/Q1 SLICE_102/D0 (1730:1899:2068)(1730:1899:2068))
- (INTERCONNECT SLICE_5/Q1 SLICE_109/B1 (1924:2163:2403)(1924:2163:2403))
- (INTERCONNECT SLICE_5/Q1 SLICE_109/D0 (1355:1491:1628)(1355:1491:1628))
- (INTERCONNECT SLICE_5/Q1 SLICE_110/B0 (1222:1394:1566)(1222:1394:1566))
- (INTERCONNECT SLICE_5/Q1 SLICE_123/D1 (975:1078:1182)(975:1078:1182))
- (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_5/Q0 SLICE_54/A0 (1605:1809:2013)(1605:1809:2013))
- (INTERCONNECT SLICE_5/Q0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/M0 (1317:1447:1577)
- (1317:1447:1577))
- (INTERCONNECT SLICE_5/Q0 SLICE_62/C1 (1006:1164:1323)(1006:1164:1323))
- (INTERCONNECT SLICE_5/Q0 SLICE_65/D1 (1733:1908:2084)(1733:1908:2084))
- (INTERCONNECT SLICE_5/Q0 SLICE_65/B0 (1637:1843:2050)(1637:1843:2050))
- (INTERCONNECT SLICE_5/Q0 SLICE_67/C1 (1744:1974:2205)(1744:1974:2205))
- (INTERCONNECT SLICE_5/Q0 SLICE_68/C1 (1376:1566:1757)(1376:1566:1757))
- (INTERCONNECT SLICE_5/Q0 SLICE_69/C0 (1036:1197:1359)(1036:1197:1359))
- (INTERCONNECT SLICE_5/Q0 SLICE_71/C0 (1036:1197:1359)(1036:1197:1359))
- (INTERCONNECT SLICE_5/Q0 SLICE_73/A0 (1605:1809:2013)(1605:1809:2013))
- (INTERCONNECT SLICE_5/Q0 SLICE_76/B0 (1637:1843:2050)(1637:1843:2050))
- (INTERCONNECT SLICE_5/Q0 SLICE_77/A0 (1605:1809:2013)(1605:1809:2013))
- (INTERCONNECT SLICE_5/Q0 SLICE_89/C1 (1457:1643:1830)(1457:1643:1830))
- (INTERCONNECT SLICE_5/Q0 SLICE_91/C1 (1036:1197:1359)(1036:1197:1359))
- (INTERCONNECT SLICE_5/Q0 SLICE_101/C0 (1451:1637:1823)(1451:1637:1823))
- (INTERCONNECT SLICE_5/Q0 SLICE_109/A1 (1994:2228:2462)(1994:2228:2462))
- (INTERCONNECT SLICE_5/Q0 SLICE_109/A0 (1994:2228:2462)(1994:2228:2462))
- (INTERCONNECT SLICE_5/Q0 SLICE_113/C0 (1036:1197:1359)(1036:1197:1359))
- (INTERCONNECT SLICE_5/Q0 SLICE_123/A1 (1575:1776:1977)(1575:1776:1977))
+ (INTERCONNECT SLICE_5/Q1 SLICE_34/D0 (871:966:1062)(871:966:1062))
+ (INTERCONNECT SLICE_5/Q1 SLICE_66/B0 (1595:1813:2031)(1595:1813:2031))
+ (INTERCONNECT SLICE_5/Q1 SLICE_69/A0 (1938:2186:2434)(1938:2186:2434))
+ (INTERCONNECT SLICE_5/Q1 SLICE_70/C0 (2066:2338:2611)(2066:2338:2611))
+ (INTERCONNECT SLICE_5/Q1 SLICE_71/D0 (1353:1503:1653)(1353:1503:1653))
+ (INTERCONNECT SLICE_5/Q1 SLICE_72/A0 (1938:2186:2434)(1938:2186:2434))
+ (INTERCONNECT SLICE_5/Q1 SLICE_79/D1 (2098:2312:2527)(2098:2312:2527))
+ (INTERCONNECT SLICE_5/Q1 SLICE_80/A1 (1124:1282:1440)(1124:1282:1440))
+ (INTERCONNECT SLICE_5/Q1 SLICE_83/A1 (1938:2186:2434)(1938:2186:2434))
+ (INTERCONNECT SLICE_5/Q1 SLICE_88/D0 (2425:2674:2924)(2425:2674:2924))
+ (INTERCONNECT SLICE_5/Q1 SLICE_94/A1 (1938:2186:2434)(1938:2186:2434))
+ (INTERCONNECT SLICE_5/Q1 SLICE_98/C1 (1686:1926:2167)(1686:1926:2167))
+ (INTERCONNECT SLICE_5/Q1 SLICE_98/C0 (1686:1926:2167)(1686:1926:2167))
+ (INTERCONNECT SLICE_5/Q1 SLICE_100/C0 (1252:1434:1617)(1252:1434:1617))
+ (INTERCONNECT SLICE_5/Q1 SLICE_103/D1 (1664:1847:2031)(1664:1847:2031))
+ (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_5/Q0 SLICE_60/C1 (1001:1159:1318)(1001:1159:1318))
+ (INTERCONNECT SLICE_5/Q0 SLICE_66/C1 (1001:1159:1318)(1001:1159:1318))
+ (INTERCONNECT SLICE_5/Q0 SLICE_69/D0 (990:1093:1197)(990:1093:1197))
+ (INTERCONNECT SLICE_5/Q0 SLICE_70/A0 (1200:1369:1538)(1200:1369:1538))
+ (INTERCONNECT SLICE_5/Q0 SLICE_71/B0 (1596:1799:2002)(1596:1799:2002))
+ (INTERCONNECT SLICE_5/Q0 SLICE_72/B0 (1049:1212:1376)(1049:1212:1376))
+ (INTERCONNECT SLICE_5/Q0 SLICE_79/B1 (772:900:1028)(772:900:1028))
+ (INTERCONNECT SLICE_5/Q0 SLICE_80/B1 (1413:1608:1803)(1413:1608:1803))
+ (INTERCONNECT SLICE_5/Q0 SLICE_83/C1 (1001:1159:1318)(1001:1159:1318))
+ (INTERCONNECT SLICE_5/Q0 SLICE_88/A1 (1200:1369:1538)(1200:1369:1538))
+ (INTERCONNECT SLICE_5/Q0 SLICE_94/D1 (807:902:998)(807:902:998))
+ (INTERCONNECT SLICE_5/Q0 SLICE_98/B1 (1602:1805:2009)(1602:1805:2009))
+ (INTERCONNECT SLICE_5/Q0 SLICE_98/B0 (1602:1805:2009)(1602:1805:2009))
(INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_6/Q1 SLICE_121/C0 (849:999:1150)(849:999:1150))
+ (INTERCONNECT SLICE_6/Q1 SLICE_91/D0 (526:578:630)(526:578:630))
(INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_6/Q0 SLICE_98/A0 (1070:1230:1390)(1070:1230:1390))
+ (INTERCONNECT SLICE_6/Q0 SLICE_91/C1 (544:658:773)(544:658:773))
(INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_7/Q1 SLICE_98/D0 (533:592:652)(533:592:652))
+ (INTERCONNECT SLICE_7/Q1 SLICE_91/D1 (533:592:652)(533:592:652))
(INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_7/Q0 SLICE_121/D0 (857:949:1042)(857:949:1042))
+ (INTERCONNECT SLICE_7/Q0 SLICE_34/C1 (803:944:1086)(803:944:1086))
(INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_8/Q1 SLICE_98/C1 (537:644:751)(537:644:751))
+ (INTERCONNECT SLICE_8/Q1 SLICE_34/A1 (743:868:993)(743:868:993))
(INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_8/Q0 SLICE_98/B1 (768:888:1008)(768:888:1008))
+ (INTERCONNECT SLICE_8/Q0 SLICE_91/B0 (1102:1264:1427)(1102:1264:1427))
(INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_9/Q1 SLICE_98/B0 (775:902:1030)(775:902:1030))
+ (INTERCONNECT SLICE_9/Q1 SLICE_34/B1 (775:902:1030)(775:902:1030))
(INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_9/Q0 SLICE_121/A0 (1067:1225:1383)(1067:1225:1383))
+ (INTERCONNECT SLICE_9/Q0 SLICE_34/D1 (860:954:1049)(860:954:1049))
(INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_84/F0 SLICE_10/D1 (1344:1473:1603)(1344:1473:1603))
- (INTERCONNECT SLICE_84/F0 SLICE_11/A1 (1929:2156:2384)(1929:2156:2384))
- (INTERCONNECT SLICE_84/F0 SLICE_11/A0 (1929:2156:2384)(1929:2156:2384))
- (INTERCONNECT SLICE_84/F0 SLICE_17/C1 (1355:1539:1724)(1355:1539:1724))
- (INTERCONNECT SLICE_84/F0 SLICE_23/C1 (2094:2342:2591)(2094:2342:2591))
- (INTERCONNECT SLICE_84/F0 SLICE_80/A0 (1554:1749:1944)(1554:1749:1944))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/A1 (2507:2754:3002)(2507:2754:3002))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B1 (3257:3578:3899)(3257:3578:3899))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B0 (3257:3578:3899)(3257:3578:3899))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_17/D1 (2297:2479:2661)(2297:2479:2661))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/D1 (3031:3276:3522)(3031:3276:3522))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_38/B1 (3273:3586:3900)(3273:3586:3900))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_64/B0 (3257:3578:3899)(3257:3578:3899))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_80/D1 (2624:2841:3058)(2624:2841:3058))
- (INTERCONNECT MAin\[1\]_I/PADDI SLICE_117/D0 (3395:3672:3949)(3395:3672:3949))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/C1 (2061:2277:2494)(2061:2277:2494))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D1 (2779:3003:3228)(2779:3003:3228))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D0 (2779:3003:3228)(2779:3003:3228))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/B1 (2271:2498:2726)(2271:2498:2726))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_39/B1 (2287:2516:2745)(2287:2516:2745))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_64/D0 (2377:2573:2770)(2377:2573:2770))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/B1 (2619:2883:3148)(2619:2883:3148))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/D0 (2736:2963:3191)(2736:2963:3191))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/C1 (2061:2277:2494)(2061:2277:2494))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_106/C1 (2061:2277:2494)(2061:2277:2494))
+ (INTERCONNECT MAin\[1\]_I/PADDI SLICE_112/A1 (2255:2481:2708)(2255:2481:2708))
+ (INTERCONNECT SLICE_75/F1 SLICE_10/A1 (1131:1293:1456)(1131:1293:1456))
+ (INTERCONNECT SLICE_75/F1 SLICE_11/C1 (932:1084:1236)(932:1084:1236))
+ (INTERCONNECT SLICE_75/F1 SLICE_11/C0 (932:1084:1236)(932:1084:1236))
+ (INTERCONNECT SLICE_75/F1 SLICE_17/D1 (911:1007:1103)(911:1007:1103))
+ (INTERCONNECT SLICE_75/F1 SLICE_23/A1 (481:577:673)(481:577:673))
+ (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (513:611:710)(513:611:710))
+ (INTERCONNECT SLICE_75/F1 SLICE_76/D0 (921:1018:1115)(921:1018:1115))
+ (INTERCONNECT SLICE_75/F1 SLICE_106/A1 (1121:1282:1444)(1121:1282:1444))
(INTERCONNECT SLICE_10/Q0 SLICE_10/D0 (523:578:633)(523:578:633))
- (INTERCONNECT SLICE_10/Q0 SLICE_33/C0 (537:644:751)(537:644:751))
- (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_17/F1 SLICE_10/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_11/F1 SLICE_10/A0 (738:862:987)(738:862:987))
- (INTERCONNECT SLICE_11/F1 SLICE_11/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_11/F1 SLICE_33/B0 (1036:1197:1359)(1036:1197:1359))
+ (INTERCONNECT SLICE_10/Q0 SLICE_76/C0 (534:644:754)(534:644:754))
+ (INTERCONNECT SLICE_73/F0 SLICE_10/C0 (537:645:753)(537:645:753))
+ (INTERCONNECT SLICE_73/F0 SLICE_17/B0 (765:889:1013)(765:889:1013))
+ (INTERCONNECT SLICE_11/F1 SLICE_10/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT SLICE_11/F1 SLICE_11/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT SLICE_10/F1 SLICE_10/A0 (730:848:967)(730:848:967))
(INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0))
(INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_17/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (3649:3922:4196)(3649:3922:4196))
+ (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (3649:3922:4196)(3649:3922:4196))
- (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (3649:3922:4196)(3649:3922:4196))
- (INTERCONNECT PHI2_I/PADDI SLICE_82/CLK (3649:3922:4196)(3649:3922:4196))
+ (INTERCONNECT PHI2_I/PADDI SLICE_45/CLK (3649:3922:4196)(3649:3922:4196))
(INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (424:441:459)(424:441:459))
(INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369))
(INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369))
@@ -3771,787 +3719,768 @@
(INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369))
(INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369))
(INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369))
- (INTERCONNECT SLICE_64/F1 SLICE_11/D1 (269:296:324)(269:296:324))
- (INTERCONNECT SLICE_64/F1 SLICE_64/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_112/F1 SLICE_11/C1 (539:653:767)(539:653:767))
- (INTERCONNECT SLICE_112/F1 SLICE_17/A1 (1342:1538:1734)(1342:1538:1734))
- (INTERCONNECT SLICE_112/F1 SLICE_64/D0 (860:955:1051)(860:955:1051))
- (INTERCONNECT SLICE_112/F1 SLICE_80/A1 (1342:1538:1734)(1342:1538:1734))
- (INTERCONNECT SLICE_11/Q0 SLICE_11/D0 (523:578:633)(523:578:633))
- (INTERCONNECT SLICE_11/Q0 SLICE_80/B0 (1102:1264:1427)(1102:1264:1427))
+ (INTERCONNECT SLICE_64/F1 SLICE_11/B1 (770:894:1018)(770:894:1018))
+ (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (767:894:1021)(767:894:1021))
+ (INTERCONNECT SLICE_64/F1 SLICE_76/B0 (777:908:1040)(777:908:1040))
+ (INTERCONNECT SLICE_20/F1 SLICE_11/A1 (1640:1837:2034)(1640:1837:2034))
+ (INTERCONNECT SLICE_20/F1 SLICE_64/C0 (917:1062:1207)(917:1062:1207))
+ (INTERCONNECT SLICE_20/F1 SLICE_73/D1 (906:996:1086)(906:996:1086))
+ (INTERCONNECT SLICE_20/F1 SLICE_76/A1 (1116:1271:1427)(1116:1271:1427))
+ (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (479:571:663)(479:571:663))
+ (INTERCONNECT SLICE_11/Q0 SLICE_17/B1 (1102:1264:1427)(1102:1264:1427))
(INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT nCCAS_I/PADDI SLICE_12/C0 (3434:3821:4209)(3434:3821:4209))
- (INTERCONNECT nCCAS_I/PADDI SLICE_25/B1 (3334:3694:4054)(3334:3694:4054))
- (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[5\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[4\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[3\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
- (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226))
+ (INTERCONNECT nCCAS_I/PADDI SLICE_12/D0 (4075:4484:4893)(4075:4484:4893))
+ (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (3609:4008:4408)(3609:4008:4408))
+ (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[5\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[4\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[3\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
+ (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603))
(INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (3:6:9)(3:6:9))
- (INTERCONNECT SLICE_12/F0 SLICE_80/M0 (499:545:592)(499:545:592))
- (INTERCONNECT SLICE_12/F0 SLICE_80/M1 (499:545:592)(499:545:592))
+ (INTERCONNECT SLICE_12/F0 SLICE_73/M0 (1127:1235:1343)(1127:1235:1343))
+ (INTERCONNECT SLICE_12/F0 SLICE_73/M1 (1127:1235:1343)(1127:1235:1343))
(INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (485:526:568)(485:526:568))
- (INTERCONNECT SLICE_12/Q1 SLICE_26/A1 (1654:1853:2052)(1654:1853:2052))
- (INTERCONNECT SLICE_12/Q1 SLICE_61/D0 (1450:1584:1718)(1450:1584:1718))
- (INTERCONNECT SLICE_12/Q1 SLICE_107/M0 (1259:1381:1503)(1259:1381:1503))
- (INTERCONNECT SLICE_12/Q1 SLICE_108/B1 (2389:2658:2927)(2389:2658:2927))
- (INTERCONNECT SLICE_12/Q1 SLICE_108/A0 (2030:2261:2493)(2030:2261:2493))
- (INTERCONNECT SLICE_16/Q0 SLICE_16/D1 (558:623:688)(558:623:688))
- (INTERCONNECT SLICE_16/Q0 SLICE_16/D0 (558:623:688)(558:623:688))
- (INTERCONNECT SLICE_16/Q0 SLICE_26/C1 (811:974:1138)(811:974:1138))
- (INTERCONNECT SLICE_16/Q0 SLICE_43/C1 (1320:1513:1707)(1320:1513:1707))
- (INTERCONNECT SLICE_16/Q0 SLICE_43/B0 (1224:1395:1567)(1224:1395:1567))
- (INTERCONNECT SLICE_16/Q0 SLICE_60/A1 (744:883:1023)(744:883:1023))
- (INTERCONNECT SLICE_16/Q0 SLICE_60/D0 (532:594:656)(532:594:656))
- (INTERCONNECT SLICE_16/Q0 SLICE_61/D1 (532:594:656)(532:594:656))
- (INTERCONNECT SLICE_16/Q0 SLICE_61/A0 (744:883:1023)(744:883:1023))
- (INTERCONNECT SLICE_16/Q0 SLICE_72/D0 (800:908:1017)(800:908:1017))
- (INTERCONNECT SLICE_16/Q0 SLICE_79/D0 (1684:1855:2026)(1684:1855:2026))
- (INTERCONNECT SLICE_16/Q0 SLICE_83/A1 (1567:1768:1970)(1567:1768:1970))
- (INTERCONNECT SLICE_16/Q0 SLICE_88/D1 (1684:1855:2026)(1684:1855:2026))
- (INTERCONNECT SLICE_16/Q0 SLICE_108/D1 (558:623:688)(558:623:688))
- (INTERCONNECT SLICE_16/Q0 SLICE_108/D0 (558:623:688)(558:623:688))
- (INTERCONNECT SLICE_43/Q0 SLICE_16/A1 (743:886:1030)(743:886:1030))
- (INTERCONNECT SLICE_43/Q0 SLICE_16/A0 (743:886:1030)(743:886:1030))
- (INTERCONNECT SLICE_43/Q0 SLICE_35/C1 (544:677:810)(544:677:810))
- (INTERCONNECT SLICE_43/Q0 SLICE_43/D1 (525:582:639)(525:582:639))
- (INTERCONNECT SLICE_43/Q0 SLICE_43/A0 (481:575:669)(481:575:669))
- (INTERCONNECT SLICE_43/Q0 SLICE_60/A0 (1020:1199:1378)(1020:1199:1378))
- (INTERCONNECT SLICE_43/Q0 SLICE_61/A1 (1020:1199:1378)(1020:1199:1378))
- (INTERCONNECT SLICE_43/Q0 SLICE_72/B0 (1427:1641:1855)(1427:1641:1855))
- (INTERCONNECT SLICE_43/Q0 SLICE_79/A0 (1722:1968:2215)(1722:1968:2215))
- (INTERCONNECT SLICE_43/Q0 SLICE_81/A1 (1765:2008:2252)(1765:2008:2252))
- (INTERCONNECT SLICE_43/Q0 SLICE_88/C1 (1893:2161:2429)(1893:2161:2429))
- (INTERCONNECT SLICE_43/Q0 SLICE_108/A1 (743:886:1030)(743:886:1030))
+ (INTERCONNECT SLICE_12/Q1 SLICE_76/M0 (488:531:575)(488:531:575))
+ (INTERCONNECT SLICE_12/Q1 SLICE_92/C0 (1002:1158:1314)(1002:1158:1314))
+ (INTERCONNECT SLICE_12/Q1 SLICE_105/C0 (1366:1553:1741)(1366:1553:1741))
+ (INTERCONNECT SLICE_12/Q1 SLICE_117/C0 (1002:1158:1314)(1002:1158:1314))
+ (INTERCONNECT SLICE_33/Q1 SLICE_16/D1 (1003:1106:1209)(1003:1106:1209))
+ (INTERCONNECT SLICE_33/Q1 SLICE_16/LSR (1022:1129:1236)(1022:1129:1236))
+ (INTERCONNECT SLICE_33/Q1 SLICE_34/M0 (1661:1809:1957)(1661:1809:1957))
+ (INTERCONNECT SLICE_33/Q1 SLICE_35/B1 (1572:1778:1984)(1572:1778:1984))
+ (INTERCONNECT SLICE_33/Q1 SLICE_36/D1 (1003:1106:1209)(1003:1106:1209))
+ (INTERCONNECT SLICE_33/Q1 SLICE_36/D0 (1003:1106:1209)(1003:1106:1209))
+ (INTERCONNECT SLICE_33/Q1 SLICE_44/A1 (1583:1783:1984)(1583:1783:1984))
+ (INTERCONNECT SLICE_33/Q1 SLICE_44/LSR (1392:1531:1670)(1392:1531:1670))
+ (INTERCONNECT SLICE_33/Q1 SLICE_62/A1 (1182:1347:1513)(1182:1347:1513))
+ (INTERCONNECT SLICE_33/Q1 SLICE_90/A0 (1577:1777:1977)(1577:1777:1977))
+ (INTERCONNECT SLICE_29/Q0 SLICE_16/C1 (873:1024:1176)(873:1024:1176))
+ (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (547:661:775)(547:661:775))
+ (INTERCONNECT SLICE_29/Q0 SLICE_29/C0 (547:661:775)(547:661:775))
+ (INTERCONNECT SLICE_29/Q0 SLICE_78/A0 (735:857:980)(735:857:980))
+ (INTERCONNECT SLICE_16/Q0 SLICE_16/B1 (788:917:1046)(788:917:1046))
+ (INTERCONNECT SLICE_16/Q0 SLICE_16/B0 (788:917:1046)(788:917:1046))
+ (INTERCONNECT SLICE_16/Q0 SLICE_44/B0 (1163:1326:1489)(1163:1326:1489))
+ (INTERCONNECT SLICE_16/Q0 SLICE_47/B0 (783:913:1043)(783:913:1043))
+ (INTERCONNECT SLICE_16/Q0 SLICE_62/C1 (557:673:789)(557:673:789))
+ (INTERCONNECT SLICE_16/Q0 SLICE_68/B0 (783:913:1043)(783:913:1043))
+ (INTERCONNECT SLICE_16/Q0 SLICE_92/B0 (1163:1326:1489)(1163:1326:1489))
+ (INTERCONNECT SLICE_16/Q0 SLICE_96/B1 (1163:1326:1489)(1163:1326:1489))
+ (INTERCONNECT SLICE_16/Q0 SLICE_105/A1 (756:884:1012)(756:884:1012))
+ (INTERCONNECT SLICE_16/Q0 SLICE_105/A0 (756:884:1012)(756:884:1012))
+ (INTERCONNECT SLICE_44/Q0 SLICE_16/A1 (1349:1541:1734)(1349:1541:1734))
+ (INTERCONNECT SLICE_44/Q0 SLICE_16/C0 (823:970:1117)(823:970:1117))
+ (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (483:579:675)(483:579:675))
+ (INTERCONNECT SLICE_44/Q0 SLICE_47/A0 (804:943:1083)(804:943:1083))
+ (INTERCONNECT SLICE_44/Q0 SLICE_62/B1 (1200:1373:1547)(1200:1373:1547))
+ (INTERCONNECT SLICE_44/Q0 SLICE_62/D0 (1139:1266:1393)(1139:1266:1393))
+ (INTERCONNECT SLICE_44/Q0 SLICE_68/C0 (605:734:863)(605:734:863))
+ (INTERCONNECT SLICE_44/Q0 SLICE_96/D0 (538:599:660)(538:599:660))
+ (INTERCONNECT SLICE_44/Q0 SLICE_105/D0 (1176:1299:1423)(1176:1299:1423))
+ (INTERCONNECT SLICE_44/Q0 SLICE_117/C1 (549:665:781)(549:665:781))
(INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q1 SLICE_16/LSR (916:1020:1124)(916:1020:1124))
- (INTERCONNECT SLICE_32/Q1 SLICE_33/M0 (871:963:1056)(871:963:1056))
- (INTERCONNECT SLICE_32/Q1 SLICE_34/D1 (897:997:1097)(897:997:1097))
- (INTERCONNECT SLICE_32/Q1 SLICE_35/A1 (759:885:1012)(759:885:1012))
- (INTERCONNECT SLICE_32/Q1 SLICE_35/D0 (897:997:1097)(897:997:1097))
- (INTERCONNECT SLICE_32/Q1 SLICE_43/A1 (1508:1699:1891)(1508:1699:1891))
- (INTERCONNECT SLICE_32/Q1 SLICE_43/LSR (1644:1809:1974)(1644:1809:1974))
- (INTERCONNECT SLICE_32/Q1 SLICE_72/A1 (1508:1699:1891)(1508:1699:1891))
- (INTERCONNECT SLICE_32/Q1 SLICE_74/A0 (1129:1287:1446)(1129:1287:1446))
- (INTERCONNECT SLICE_32/Q1 SLICE_78/A0 (1508:1699:1891)(1508:1699:1891))
- (INTERCONNECT SLICE_32/Q1 SLICE_79/A1 (1508:1699:1891)(1508:1699:1891))
- (INTERCONNECT SLICE_32/Q1 SLICE_90/A0 (1493:1683:1873)(1493:1683:1873))
- (INTERCONNECT SLICE_16/F1 SLICE_46/D0 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_99/F0 SLICE_17/B1 (767:891:1015)(767:891:1015))
- (INTERCONNECT SLICE_99/F0 SLICE_80/B1 (767:891:1015)(767:891:1015))
- (INTERCONNECT SLICE_17/Q0 SLICE_17/D0 (523:578:633)(523:578:633))
- (INTERCONNECT SLICE_17/Q0 SLICE_23/B1 (1034:1188:1343)(1034:1188:1343))
- (INTERCONNECT SLICE_33/F0 SLICE_17/B0 (765:883:1001)(765:883:1001))
- (INTERCONNECT SLICE_80/F0 SLICE_17/A0 (476:566:656)(476:566:656))
+ (INTERCONNECT SLICE_16/F1 SLICE_37/D0 (269:296:324)(269:296:324))
+ (INTERCONNECT SLICE_16/F1 SLICE_38/C1 (534:645:756)(534:645:756))
+ (INTERCONNECT SLICE_64/F0 SLICE_17/C1 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_106/F0 SLICE_17/A1 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_17/Q0 SLICE_17/D0 (534:591:648)(534:591:648))
+ (INTERCONNECT SLICE_17/Q0 SLICE_23/C1 (809:951:1093)(809:951:1093))
+ (INTERCONNECT SLICE_17/Q0 SLICE_74/A0 (1372:1556:1740)(1372:1556:1740))
+ (INTERCONNECT SLICE_17/Q0 SLICE_106/D1 (534:591:648)(534:591:648))
+ (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_76/F0 SLICE_17/A0 (733:848:964)(733:848:964))
(INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_119/F1 SLICE_18/D1 (536:594:652)(536:594:652))
- (INTERCONNECT SLICE_119/F1 SLICE_24/C1 (874:1022:1170)(874:1022:1170))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_18/C1 (2103:2317:2531)(2103:2317:2531))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/C0 (2430:2679:2928)(2430:2679:2928))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/D0 (2092:2251:2410)(2092:2251:2410))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_44/B0 (2704:2963:3222)(2704:2963:3222))
- (INTERCONNECT Din\[1\]_I/PADDI SLICE_112/B1 (2704:2963:3222)(2704:2963:3222))
- (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (2557:2757:2957)(2557:2757:2957))
- (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (544:554:565)(544:554:565))
+ (INTERCONNECT SLICE_104/F1 SLICE_18/D1 (269:296:324)(269:296:324))
+ (INTERCONNECT SLICE_104/F1 SLICE_24/D1 (523:579:635)(523:579:635))
+ (INTERCONNECT SLICE_22/F1 SLICE_18/C1 (536:650:764)(536:650:764))
+ (INTERCONNECT SLICE_22/F1 SLICE_20/B0 (1125:1295:1466)(1125:1295:1466))
+ (INTERCONNECT SLICE_22/F1 SLICE_21/D1 (883:985:1088)(883:985:1088))
+ (INTERCONNECT SLICE_22/F1 SLICE_22/B0 (778:907:1036)(778:907:1036))
+ (INTERCONNECT SLICE_22/F1 SLICE_23/A0 (1093:1261:1429)(1093:1261:1429))
+ (INTERCONNECT SLICE_22/F1 SLICE_24/B1 (778:907:1036)(778:907:1036))
(INTERCONNECT SLICE_18/Q0 SLICE_18/B1 (765:888:1011)(765:888:1011))
- (INTERCONNECT SLICE_18/Q0 SLICE_30/A1 (1070:1230:1390)(1070:1230:1390))
- (INTERCONNECT SLICE_22/F1 SLICE_18/A1 (742:872:1003)(742:872:1003))
- (INTERCONNECT SLICE_22/F1 SLICE_20/D0 (532:597:662)(532:597:662))
- (INTERCONNECT SLICE_22/F1 SLICE_21/C1 (543:663:783)(543:663:783))
- (INTERCONNECT SLICE_22/F1 SLICE_22/C0 (284:372:461)(284:372:461))
- (INTERCONNECT SLICE_22/F1 SLICE_23/D0 (527:589:651)(527:589:651))
- (INTERCONNECT SLICE_22/F1 SLICE_24/B1 (774:907:1040)(774:907:1040))
- (INTERCONNECT SLICE_30/Q0 SLICE_18/D0 (530:590:650)(530:590:650))
- (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (481:575:669)(481:575:669))
- (INTERCONNECT SLICE_30/Q0 SLICE_32/B1 (1342:1511:1681)(1342:1511:1681))
- (INTERCONNECT SLICE_30/Q0 SLICE_44/D0 (796:890:985)(796:890:985))
+ (INTERCONNECT SLICE_18/Q0 SLICE_31/B1 (775:902:1030)(775:902:1030))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_18/A1 (1731:1913:2096)(1731:1913:2096))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/D1 (1542:1661:1780)(1542:1661:1780))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/D0 (1542:1661:1780)(1542:1661:1780))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/B0 (1784:1971:2158)(1784:1971:2158))
+ (INTERCONNECT Din\[1\]_I/PADDI SLICE_45/D0 (1906:2056:2207)(1906:2056:2207))
+ (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (2846:3095:3344)(2846:3095:3344))
+ (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (544:554:565)(544:554:565))
(INTERCONNECT SLICE_18/F1 SLICE_18/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_82/F1 SLICE_18/A0 (754:881:1008)(754:881:1008))
- (INTERCONNECT SLICE_82/F1 SLICE_20/B0 (1124:1290:1457)(1124:1290:1457))
- (INTERCONNECT SLICE_82/F1 SLICE_21/A0 (754:881:1008)(754:881:1008))
- (INTERCONNECT SLICE_82/F1 SLICE_24/B0 (1124:1290:1457)(1124:1290:1457))
- (INTERCONNECT SLICE_82/F1 SLICE_82/C0 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_74/F1 SLICE_18/B0 (1044:1209:1374)(1044:1209:1374))
+ (INTERCONNECT SLICE_74/F1 SLICE_20/C0 (873:1026:1180)(873:1026:1180))
+ (INTERCONNECT SLICE_74/F1 SLICE_21/A0 (740:867:995)(740:867:995))
+ (INTERCONNECT SLICE_74/F1 SLICE_24/A0 (1012:1174:1337)(1012:1174:1337))
+ (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (767:894:1021)(767:894:1021))
+ (INTERCONNECT SLICE_31/Q0 SLICE_18/A0 (749:874:1000)(749:874:1000))
+ (INTERCONNECT SLICE_31/Q0 SLICE_31/B0 (765:888:1011)(765:888:1011))
+ (INTERCONNECT SLICE_31/Q0 SLICE_33/B1 (1623:1816:2010)(1623:1816:2010))
+ (INTERCONNECT SLICE_31/Q0 SLICE_45/B0 (1151:1311:1471)(1151:1311:1471))
(INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_23/F1 SLICE_18/CE (572:644:716)(572:644:716))
- (INTERCONNECT SLICE_23/F1 SLICE_20/CE (572:644:716)(572:644:716))
- (INTERCONNECT SLICE_23/F1 SLICE_21/CE (572:644:716)(572:644:716))
- (INTERCONNECT SLICE_23/F1 SLICE_22/A0 (748:877:1007)(748:877:1007))
- (INTERCONNECT SLICE_23/F1 SLICE_23/B0 (515:616:718)(515:616:718))
- (INTERCONNECT SLICE_23/F1 SLICE_24/CE (572:644:716)(572:644:716))
- (INTERCONNECT SLICE_23/F1 SLICE_44/CE (557:625:693)(557:625:693))
- (INTERCONNECT SLICE_23/F1 SLICE_82/B0 (515:616:718)(515:616:718))
+ (INTERCONNECT SLICE_106/F1 SLICE_18/CE (1155:1284:1413)(1155:1284:1413))
+ (INTERCONNECT SLICE_106/F1 SLICE_20/CE (1155:1284:1413)(1155:1284:1413))
+ (INTERCONNECT SLICE_106/F1 SLICE_21/CE (1155:1284:1413)(1155:1284:1413))
+ (INTERCONNECT SLICE_106/F1 SLICE_24/CE (1155:1284:1413)(1155:1284:1413))
+ (INTERCONNECT SLICE_106/F1 SLICE_45/CE (879:978:1078)(879:978:1078))
+ (INTERCONNECT Din\[0\]_I/PADDI SLICE_19/M0 (2687:2899:3112)(2687:2899:3112))
+ (INTERCONNECT Din\[0\]_I/PADDI SLICE_20/B1 (2653:2911:3170)(2653:2911:3170))
+ (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/D0 (2411:2601:2792)(2411:2601:2792))
+ (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/C1 (2042:2254:2467)(2042:2254:2467))
+ (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/A1 (2621:2877:3133)(2621:2877:3133))
+ (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (4042:4397:4753)(4042:4397:4753))
+ (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (424:441:459)(424:441:459))
+ (INTERCONNECT SLICE_74/F0 SLICE_19/CE (539:596:653)(539:596:653))
+ (INTERCONNECT SLICE_19/F0 RCLKout_MGIOL/ONEG (1854:2023:2192)(1854:2023:2192))
+ (INTERCONNECT SLICE_19/Q0 SLICE_59/A0 (1620:1808:1997)(1620:1808:1997))
+ (INTERCONNECT SLICE_19/F1 RCLKout_MGIOL/OPOS (2236:2438:2640)(2236:2438:2640))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_20/C1 (1727:1909:2092)(1727:1909:2092))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/A1 (2307:2533:2759)(2307:2533:2759))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_45/B1 (2671:2936:3201)(2671:2936:3201))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_74/B1 (1969:2165:2362)(1969:2165:2362))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/C1 (2440:2692:2944)(2440:2692:2944))
+ (INTERCONNECT Din\[4\]_I/PADDI SLICE_104/A1 (2634:2895:3156)(2634:2895:3156))
+ (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (3052:3278:3505)(3052:3278:3505))
+ (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565))
+ (INTERCONNECT Din\[7\]_I/PADDI SLICE_20/A1 (2731:3026:3322)(2731:3026:3322))
+ (INTERCONNECT Din\[7\]_I/PADDI SLICE_104/D1 (2194:2389:2584)(2194:2389:2584))
+ (INTERCONNECT Din\[7\]_I/PADDI SLICE_104/D0 (2194:2389:2584)(2194:2389:2584))
+ (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (4271:4657:5044)(4271:4657:5044))
+ (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459))
(INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_20/Q0 SLICE_103/B0 (1034:1188:1343)(1034:1188:1343))
+ (INTERCONNECT SLICE_20/Q0 SLICE_95/A0 (1002:1154:1306)(1002:1154:1306))
(INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_21/Q0 SLICE_21/A1 (733:853:974)(733:853:974))
- (INTERCONNECT SLICE_21/Q0 SLICE_51/A0 (1433:1620:1808)(1433:1620:1808))
- (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/C0 (2047:2260:2473)(2047:2260:2473))
- (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/A1 (2246:2469:2693)(2246:2469:2693))
- (INTERCONNECT Din\[0\]_I/PADDI SLICE_82/M0 (3062:3307:3552)(3062:3307:3552))
- (INTERCONNECT Din\[0\]_I/PADDI SLICE_112/D1 (3103:3360:3617)(3103:3360:3617))
- (INTERCONNECT Din\[0\]_I/PADDI SLICE_112/B0 (3018:3308:3598)(3018:3308:3598))
- (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (3303:3594:3886)(3303:3594:3886))
- (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (424:441:459)(424:441:459))
- (INTERCONNECT SLICE_21/F1 SLICE_21/B0 (508:600:693)(508:600:693))
+ (INTERCONNECT SLICE_21/Q0 SLICE_52/B0 (1034:1188:1343)(1034:1188:1343))
+ (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (277:356:436)(277:356:436))
(INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_100/F1 SLICE_22/D1 (529:594:659)(529:594:659))
- (INTERCONNECT SLICE_100/F1 SLICE_44/D1 (529:594:659)(529:594:659))
- (INTERCONNECT SLICE_100/F1 SLICE_82/B1 (771:904:1037)(771:904:1037))
- (INTERCONNECT SLICE_100/F1 SLICE_100/C0 (280:362:445)(280:362:445))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/C1 (2100:2312:2525)(2100:2312:2525))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_44/C1 (2100:2312:2525)(2100:2312:2525))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/C1 (2100:2312:2525)(2100:2312:2525))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_99/C1 (2464:2708:2952)(2464:2708:2952))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/D1 (2416:2608:2801)(2416:2608:2801))
- (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/C0 (2100:2312:2525)(2100:2312:2525))
- (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (3780:4087:4394)(3780:4087:4394))
+ (INTERCONNECT SLICE_104/F0 SLICE_22/D1 (523:579:635)(523:579:635))
+ (INTERCONNECT SLICE_104/F0 SLICE_45/C1 (814:957:1101)(814:957:1101))
+ (INTERCONNECT SLICE_104/F0 SLICE_74/D1 (1531:1682:1834)(1531:1682:1834))
+ (INTERCONNECT SLICE_104/F0 SLICE_93/D0 (803:891:980)(803:891:980))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/C1 (1725:1907:2089)(1725:1907:2089))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_26/C0 (2296:2506:2716)(2296:2506:2716))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_45/D1 (2073:2231:2389)(2073:2231:2389))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_73/C1 (2448:2692:2937)(2448:2692:2937))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_74/A1 (2288:2512:2736)(2288:2512:2736))
+ (INTERCONNECT Din\[5\]_I/PADDI SLICE_104/B1 (2283:2513:2743)(2283:2513:2743))
+ (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (3066:3294:3522)(3066:3294:3522))
(INTERCONNECT Din\[5\]_I/PADDI Din\[5\]_MGIOL/DI (544:554:565)(544:554:565))
- (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/B1 (2274:2501:2728)(2274:2501:2728))
- (INTERCONNECT Din\[3\]_I/PADDI SLICE_64/B1 (2665:2928:3191)(2665:2928:3191))
- (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A1 (1915:2104:2294)(1915:2104:2294))
- (INTERCONNECT Din\[3\]_I/PADDI SLICE_99/B1 (2665:2928:3191)(2665:2928:3191))
- (INTERCONNECT Din\[3\]_I/PADDI SLICE_100/B0 (2644:2903:3162)(2644:2903:3162))
- (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (3774:4093:4412)(3774:4093:4412))
+ (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/B1 (1835:2022:2210)(1835:2022:2210))
+ (INTERCONNECT Din\[3\]_I/PADDI SLICE_64/D1 (2380:2561:2742)(2380:2561:2742))
+ (INTERCONNECT Din\[3\]_I/PADDI SLICE_73/A1 (2590:2836:3083)(2590:2836:3083))
+ (INTERCONNECT Din\[3\]_I/PADDI SLICE_74/C1 (2338:2576:2814)(2338:2576:2814))
+ (INTERCONNECT Din\[3\]_I/PADDI SLICE_93/A0 (2954:3232:3510)(2954:3232:3510))
+ (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (3320:3599:3879)(3320:3599:3879))
(INTERCONNECT Din\[3\]_I/PADDI Din\[3\]_MGIOL/DI (544:554:565)(544:554:565))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/A1 (2298:2522:2746)(2298:2522:2746))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_44/A1 (2636:2897:3158)(2636:2897:3158))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_82/D1 (2426:2621:2817)(2426:2621:2817))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_112/C1 (2104:2318:2532)(2104:2318:2532))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_112/C0 (2104:2318:2532)(2104:2318:2532))
- (INTERCONNECT Din\[4\]_I/PADDI SLICE_119/A1 (2303:2527:2752)(2303:2527:2752))
- (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (3048:3273:3498)(3048:3273:3498))
- (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565))
+ (INTERCONNECT SLICE_23/F1 SLICE_22/C0 (537:645:753)(537:645:753))
+ (INTERCONNECT SLICE_23/F1 SLICE_23/C0 (280:362:445)(280:362:445))
(INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_22/Q0 SLICE_45/B1 (1401:1585:1770)(1401:1585:1770))
- (INTERCONNECT SLICE_22/Q0 SLICE_107/A1 (1707:1926:2145)(1707:1926:2145))
- (INTERCONNECT SLICE_22/Q0 SLICE_107/A0 (1707:1926:2145)(1707:1926:2145))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/A1 (2160:2388:2616)(2160:2388:2616))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_38/D0 (2729:2967:3205)(2729:2967:3205))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A1 (2535:2795:3056)(2535:2795:3056))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A0 (2535:2795:3056)(2535:2795:3056))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_99/A0 (2535:2795:3056)(2535:2795:3056))
- (INTERCONNECT MAin\[0\]_I/PADDI SLICE_116/A0 (2939:3242:3546)(2939:3242:3546))
+ (INTERCONNECT SLICE_22/Q0 SLICE_46/C1 (889:1040:1192)(889:1040:1192))
+ (INTERCONNECT SLICE_22/Q0 SLICE_97/C1 (889:1040:1192)(889:1040:1192))
+ (INTERCONNECT SLICE_22/Q0 SLICE_97/C0 (889:1040:1192)(889:1040:1192))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/D1 (2210:2396:2583)(2210:2396:2583))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_39/B0 (2822:3108:3395)(2822:3108:3395))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A1 (2800:3085:3370)(2800:3085:3370))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A0 (2800:3085:3370)(2800:3085:3370))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_75/D0 (2210:2396:2583)(2210:2396:2583))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_106/B1 (3159:3481:3804)(3159:3481:3804))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_106/D0 (2590:2809:3029)(2590:2809:3029))
+ (INTERCONNECT MAin\[0\]_I/PADDI SLICE_111/B1 (2822:3108:3395)(2822:3108:3395))
(INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_23/Q0 SLICE_103/A0 (1326:1511:1696)(1326:1511:1696))
- (INTERCONNECT SLICE_24/Q0 SLICE_24/D1 (523:578:633)(523:578:633))
- (INTERCONNECT SLICE_24/Q0 SLICE_122/B1 (768:888:1008)(768:888:1008))
- (INTERCONNECT SLICE_45/Q0 SLICE_24/C0 (539:652:765)(539:652:765))
- (INTERCONNECT SLICE_45/Q0 SLICE_45/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_45/Q0 SLICE_120/C0 (1249:1433:1618)(1249:1433:1618))
- (INTERCONNECT SLICE_24/F1 SLICE_24/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_23/Q0 SLICE_95/D0 (1410:1533:1656)(1410:1533:1656))
+ (INTERCONNECT SLICE_24/Q0 SLICE_24/A1 (733:853:974)(733:853:974))
+ (INTERCONNECT SLICE_24/Q0 SLICE_108/A1 (1177:1341:1505)(1177:1341:1505))
+ (INTERCONNECT SLICE_24/F1 SLICE_24/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_46/Q0 SLICE_24/B0 (781:909:1037)(781:909:1037))
+ (INTERCONNECT SLICE_46/Q0 SLICE_46/A0 (479:571:663)(479:571:663))
+ (INTERCONNECT SLICE_46/Q0 SLICE_115/B0 (1560:1763:1967)(1560:1763:1967))
(INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT nFWE_I/PADDI SLICE_25/C1 (2866:3138:3410)(2866:3138:3410))
- (INTERCONNECT nFWE_I/PADDI SLICE_25/C0 (2866:3138:3410)(2866:3138:3410))
- (INTERCONNECT nFWE_I/PADDI SLICE_114/A0 (3531:3846:4162)(3531:3846:4162))
- (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_32/A1 (3537:3929:4322)(3537:3929:4322))
- (INTERCONNECT nCRAS_I/PADDI SLICE_32/A0 (3537:3929:4322)(3537:3929:4322))
- (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2802:3073:3344)(2802:3073:3344))
- (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (2949:3233:3517)(2949:3233:3517))
- (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (2949:3233:3517)(2949:3233:3517))
- (INTERCONNECT SLICE_25/Q0 SLICE_46/B1 (1404:1590:1777)(1404:1590:1777))
- (INTERCONNECT SLICE_25/Q0 SLICE_83/D1 (1168:1287:1406)(1168:1287:1406))
- (INTERCONNECT SLICE_25/Q0 SLICE_94/B0 (1410:1597:1784)(1410:1597:1784))
- (INTERCONNECT SLICE_25/Q0 SLICE_108/C1 (984:1138:1292)(984:1138:1292))
- (INTERCONNECT SLICE_25/Q0 SLICE_108/C0 (984:1138:1292)(984:1138:1292))
- (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (1578:1720:1863)(1578:1720:1863))
- (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (2368:2588:2808)(2368:2588:2808))
- (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (2368:2588:2808)(2368:2588:2808))
- (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (2368:2588:2808)(2368:2588:2808))
- (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (2368:2588:2808)(2368:2588:2808))
- (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (1578:1720:1863)(1578:1720:1863))
- (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (1578:1720:1863)(1578:1720:1863))
- (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (1578:1720:1863)(1578:1720:1863))
- (INTERCONNECT SLICE_88/F1 SLICE_26/C0 (539:650:761)(539:650:761))
- (INTERCONNECT SLICE_88/F1 SLICE_88/C0 (282:367:453)(282:367:453))
- (INTERCONNECT SLICE_88/F1 SLICE_90/C1 (282:367:453)(282:367:453))
- (INTERCONNECT SLICE_26/Q0 SLICE_26/A0 (483:579:675)(483:579:675))
- (INTERCONNECT SLICE_26/Q0 SLICE_27/B1 (780:909:1038)(780:909:1038))
- (INTERCONNECT SLICE_26/Q0 SLICE_27/D0 (538:599:660)(538:599:660))
- (INTERCONNECT SLICE_26/Q0 SLICE_28/A1 (748:874:1001)(748:874:1001))
- (INTERCONNECT SLICE_26/Q0 SLICE_28/C0 (549:665:781)(549:665:781))
- (INTERCONNECT SLICE_26/Q0 SLICE_36/A1 (1450:1646:1843)(1450:1646:1843))
- (INTERCONNECT SLICE_26/Q0 SLICE_78/B1 (1155:1319:1483)(1155:1319:1483))
- (INTERCONNECT SLICE_26/Q0 SLICE_90/A1 (1080:1244:1409)(1080:1244:1409))
- (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_26/F1 SLICE_94/D0 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_27/Q0 SLICE_27/D1 (536:595:654)(536:595:654))
- (INTERCONNECT SLICE_27/Q0 SLICE_27/A0 (481:575:669)(481:575:669))
- (INTERCONNECT SLICE_27/Q0 SLICE_28/D0 (536:595:654)(536:595:654))
- (INTERCONNECT SLICE_27/Q0 SLICE_36/B1 (1044:1207:1370)(1044:1207:1370))
- (INTERCONNECT SLICE_27/Q0 SLICE_74/B1 (772:900:1028)(772:900:1028))
- (INTERCONNECT SLICE_27/Q0 SLICE_88/D0 (1172:1299:1426)(1172:1299:1426))
- (INTERCONNECT SLICE_27/Q0 SLICE_90/D1 (1172:1299:1426)(1172:1299:1426))
- (INTERCONNECT SLICE_27/Q1 SLICE_27/A1 (483:579:675)(483:579:675))
- (INTERCONNECT SLICE_27/Q1 SLICE_28/A0 (737:861:986)(737:861:986))
- (INTERCONNECT SLICE_27/Q1 SLICE_36/D1 (798:894:991)(798:894:991))
- (INTERCONNECT SLICE_27/Q1 SLICE_74/C1 (543:660:777)(543:660:777))
- (INTERCONNECT SLICE_27/Q1 SLICE_88/A0 (753:882:1012)(753:882:1012))
- (INTERCONNECT SLICE_27/Q1 SLICE_90/B1 (785:917:1049)(785:917:1049))
- (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0))
+ (INTERCONNECT nFWE_I/PADDI SLICE_25/D1 (2526:2717:2908)(2526:2717:2908))
+ (INTERCONNECT nFWE_I/PADDI SLICE_25/D0 (2526:2717:2908)(2526:2717:2908))
+ (INTERCONNECT nFWE_I/PADDI SLICE_109/C0 (2363:2611:2859)(2363:2611:2859))
+ (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (3:6:9)(3:6:9))
+ (INTERCONNECT SLICE_25/F0 SLICE_26/M0 (488:532:577)(488:532:577))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_26/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_33/A1 (2300:2518:2736)(2300:2518:2736))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_33/A0 (2300:2518:2736)(2300:2518:2736))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (4050:4346:4642)(4050:4346:4642))
+ (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (4197:4506:4815)(4197:4506:4815))
+ (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (4197:4506:4815)(4197:4506:4815))
+ (INTERCONNECT SLICE_25/Q0 SLICE_47/B1 (1581:1778:1975)(1581:1778:1975))
+ (INTERCONNECT SLICE_25/Q0 SLICE_96/C1 (1677:1896:2115)(1677:1896:2115))
+ (INTERCONNECT SLICE_25/Q0 SLICE_105/B1 (2283:2548:2814)(2283:2548:2814))
+ (INTERCONNECT SLICE_25/Q0 SLICE_105/B0 (2283:2548:2814)(2283:2548:2814))
+ (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (1314:1454:1595)(1314:1454:1595))
+ (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (1826:1998:2170)(1826:1998:2170))
+ (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (1826:1998:2170)(1826:1998:2170))
+ (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (1826:1998:2170)(1826:1998:2170))
+ (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (1826:1998:2170)(1826:1998:2170))
+ (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (1646:1823:2000)(1646:1823:2000))
+ (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (1646:1823:2000)(1646:1823:2000))
+ (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (1314:1454:1595)(1314:1454:1595))
+ (INTERCONNECT CROW\[1\]_I/PADDI SLICE_26/C1 (2222:2468:2714)(2222:2468:2714))
+ (INTERCONNECT SLICE_38/Q0 SLICE_26/A1 (1184:1351:1519)(1184:1351:1519))
+ (INTERCONNECT SLICE_38/Q0 SLICE_38/A0 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_38/Q0 SLICE_39/D1 (1468:1601:1735)(1468:1601:1735))
+ (INTERCONNECT SLICE_38/Q0 SLICE_39/D0 (1468:1601:1735)(1468:1601:1735))
+ (INTERCONNECT SLICE_38/Q0 SLICE_40/B1 (2151:2378:2606)(2151:2378:2606))
+ (INTERCONNECT SLICE_38/Q0 SLICE_40/B0 (2151:2378:2606)(2151:2378:2606))
+ (INTERCONNECT SLICE_38/Q0 SLICE_41/D1 (1909:2068:2228)(1909:2068:2228))
+ (INTERCONNECT SLICE_38/Q0 SLICE_41/D0 (1909:2068:2228)(1909:2068:2228))
+ (INTERCONNECT SLICE_38/Q0 SLICE_42/D1 (1468:1601:1735)(1468:1601:1735))
+ (INTERCONNECT SLICE_38/Q0 SLICE_42/D0 (1468:1601:1735)(1468:1601:1735))
+ (INTERCONNECT SLICE_38/Q0 SLICE_43/B1 (1147:1308:1470)(1147:1308:1470))
+ (INTERCONNECT SLICE_38/Q0 SLICE_43/B0 (1147:1308:1470)(1147:1308:1470))
+ (INTERCONNECT SLICE_38/Q0 SLICE_115/D1 (1838:2003:2169)(1838:2003:2169))
+ (INTERCONNECT SLICE_38/Q0 SLICE_115/D0 (1838:2003:2169)(1838:2003:2169))
+ (INTERCONNECT Din\[2\]_I/PADDI SLICE_26/D0 (1836:1962:2088)(1836:1962:2088))
+ (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/D0 (2069:2225:2382)(2069:2225:2382))
+ (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/C0 (2407:2653:2900)(2407:2653:2900))
+ (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (3059:3306:3554)(3059:3306:3554))
+ (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565))
+ (INTERCONNECT SLICE_26/F0 SLICE_64/B1 (1225:1391:1558)(1225:1391:1558))
+ (INTERCONNECT SLICE_26/F0 SLICE_93/B0 (1225:1391:1558)(1225:1391:1558))
+ (INTERCONNECT SLICE_26/Q0 SLICE_92/A0 (1067:1225:1383)(1067:1225:1383))
+ (INTERCONNECT SLICE_26/F1 RBA\[1\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723))
+ (INTERCONNECT SLICE_37/Q0 SLICE_27/B1 (1162:1328:1495)(1162:1328:1495))
+ (INTERCONNECT SLICE_37/Q0 SLICE_27/B0 (1162:1328:1495)(1162:1328:1495))
+ (INTERCONNECT SLICE_37/Q0 SLICE_35/C1 (877:1032:1188)(877:1032:1188))
+ (INTERCONNECT SLICE_37/Q0 SLICE_35/B0 (778:922:1066)(778:922:1066))
+ (INTERCONNECT SLICE_37/Q0 SLICE_37/A0 (485:583:681)(485:583:681))
+ (INTERCONNECT SLICE_37/Q0 SLICE_38/A1 (750:878:1007)(750:878:1007))
+ (INTERCONNECT SLICE_37/Q0 SLICE_44/D1 (1295:1426:1557)(1295:1426:1557))
+ (INTERCONNECT SLICE_37/Q0 SLICE_47/D1 (536:612:688)(536:612:688))
+ (INTERCONNECT SLICE_37/Q0 SLICE_47/D0 (536:612:688)(536:612:688))
+ (INTERCONNECT SLICE_37/Q0 SLICE_62/A0 (750:878:1007)(750:878:1007))
+ (INTERCONNECT SLICE_37/Q0 SLICE_68/D0 (536:612:688)(536:612:688))
+ (INTERCONNECT SLICE_37/Q0 SLICE_78/D1 (545:611:677)(545:611:677))
+ (INTERCONNECT SLICE_37/Q0 SLICE_90/D0 (1295:1426:1557)(1295:1426:1557))
+ (INTERCONNECT SLICE_37/Q0 SLICE_117/D1 (1295:1426:1557)(1295:1426:1557))
+ (INTERCONNECT SLICE_62/F1 SLICE_27/A1 (1012:1174:1337)(1012:1174:1337))
+ (INTERCONNECT SLICE_62/F1 SLICE_27/A0 (1012:1174:1337)(1012:1174:1337))
+ (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (513:611:710)(513:611:710))
+ (INTERCONNECT SLICE_62/F1 SLICE_78/B1 (772:902:1032)(772:902:1032))
+ (INTERCONNECT SLICE_62/F1 SLICE_81/C0 (552:671:790)(552:671:790))
+ (INTERCONNECT SLICE_62/F1 SLICE_90/B1 (783:915:1047)(783:915:1047))
+ (INTERCONNECT SLICE_27/Q0 SLICE_27/C0 (538:652:766)(538:652:766))
+ (INTERCONNECT SLICE_27/Q0 SLICE_28/C1 (544:667:790)(544:667:790))
+ (INTERCONNECT SLICE_27/Q0 SLICE_28/C0 (544:667:790)(544:667:790))
+ (INTERCONNECT SLICE_27/Q0 SLICE_29/B0 (1224:1395:1567)(1224:1395:1567))
+ (INTERCONNECT SLICE_27/Q0 SLICE_37/A1 (2034:2268:2503)(2034:2268:2503))
+ (INTERCONNECT SLICE_27/Q0 SLICE_81/A0 (1889:2125:2361)(1889:2125:2361))
+ (INTERCONNECT SLICE_27/Q0 SLICE_90/D1 (530:586:642)(530:586:642))
+ (INTERCONNECT SLICE_27/Q0 SLICE_114/C1 (544:667:790)(544:667:790))
+ (INTERCONNECT SLICE_27/Q0 SLICE_114/A0 (1192:1361:1530)(1192:1361:1530))
(INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_79/F0 SLICE_27/CE (1146:1271:1397)(1146:1271:1397))
- (INTERCONNECT SLICE_79/F0 SLICE_27/CE (1146:1271:1397)(1146:1271:1397))
- (INTERCONNECT SLICE_79/F0 SLICE_28/CE (1146:1271:1397)(1146:1271:1397))
- (INTERCONNECT SLICE_28/Q0 SLICE_28/B0 (767:892:1017)(767:892:1017))
- (INTERCONNECT SLICE_28/Q0 SLICE_43/B1 (1147:1308:1470)(1147:1308:1470))
- (INTERCONNECT SLICE_28/Q0 SLICE_74/A1 (751:878:1006)(751:878:1006))
- (INTERCONNECT SLICE_28/Q0 SLICE_88/B0 (1104:1268:1433)(1104:1268:1433))
+ (INTERCONNECT SLICE_27/F1 SLICE_28/CE (601:672:744)(601:672:744))
+ (INTERCONNECT SLICE_27/F1 SLICE_28/CE (601:672:744)(601:672:744))
+ (INTERCONNECT SLICE_27/F1 SLICE_29/CE (601:672:744)(601:672:744))
+ (INTERCONNECT SLICE_28/Q0 SLICE_28/B1 (808:941:1074)(808:941:1074))
+ (INTERCONNECT SLICE_28/Q0 SLICE_28/A0 (481:575:669)(481:575:669))
+ (INTERCONNECT SLICE_28/Q0 SLICE_29/A1 (776:906:1037)(776:906:1037))
+ (INTERCONNECT SLICE_28/Q0 SLICE_29/A0 (776:906:1037)(776:906:1037))
+ (INTERCONNECT SLICE_28/Q0 SLICE_37/B1 (777:906:1036)(777:906:1036))
+ (INTERCONNECT SLICE_28/Q0 SLICE_78/C0 (577:697:817)(577:697:817))
+ (INTERCONNECT SLICE_28/Q0 SLICE_114/D0 (566:631:696)(566:631:696))
+ (INTERCONNECT SLICE_28/Q1 SLICE_28/A1 (483:579:675)(483:579:675))
+ (INTERCONNECT SLICE_28/Q1 SLICE_29/D1 (548:611:674)(548:611:674))
+ (INTERCONNECT SLICE_28/Q1 SLICE_29/D0 (548:611:674)(548:611:674))
+ (INTERCONNECT SLICE_28/Q1 SLICE_37/D1 (530:586:642)(530:586:642))
+ (INTERCONNECT SLICE_28/Q1 SLICE_78/D0 (527:586:645)(527:586:645))
+ (INTERCONNECT SLICE_28/Q1 SLICE_114/C0 (559:677:795)(559:677:795))
+ (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_28/F1 RA\[10\]_MGIOL/OPOS (1553:1694:1835)(1553:1694:1835))
- (INTERCONNECT SLICE_104/F1 SLICE_29/D1 (269:296:324)(269:296:324))
- (INTERCONNECT SLICE_104/F1 SLICE_56/A1 (1070:1231:1392)(1070:1231:1392))
- (INTERCONNECT SLICE_123/F0 SLICE_29/A1 (1067:1225:1383)(1067:1225:1383))
- (INTERCONNECT SLICE_29/F1 SLICE_29/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (485:583:681)(485:583:681))
- (INTERCONNECT SLICE_29/Q0 SLICE_30/B1 (778:922:1066)(778:922:1066))
- (INTERCONNECT SLICE_29/Q0 SLICE_34/B1 (1962:2213:2464)(1962:2213:2464))
- (INTERCONNECT SLICE_29/Q0 SLICE_36/A0 (2664:2976:3288)(2664:2976:3288))
- (INTERCONNECT SLICE_29/Q0 SLICE_37/C1 (2101:2371:2641)(2101:2371:2641))
- (INTERCONNECT SLICE_29/Q0 SLICE_45/D1 (536:612:688)(536:612:688))
- (INTERCONNECT SLICE_29/Q0 SLICE_48/A1 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_48/A0 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_49/A1 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_49/A0 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_50/A1 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_50/A0 (1925:2167:2410)(1925:2167:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_51/D0 (535:605:675)(535:605:675))
- (INTERCONNECT SLICE_29/Q0 SLICE_52/D0 (2110:2321:2533)(2110:2321:2533))
- (INTERCONNECT SLICE_29/Q0 SLICE_53/B0 (2352:2631:2911)(2352:2631:2911))
- (INTERCONNECT SLICE_29/Q0 SLICE_54/C1 (2121:2387:2654)(2121:2387:2654))
- (INTERCONNECT SLICE_29/Q0 SLICE_56/B1 (777:915:1053)(777:915:1053))
- (INTERCONNECT SLICE_29/Q0 SLICE_57/A1 (2715:3026:3338)(2715:3026:3338))
- (INTERCONNECT SLICE_29/Q0 SLICE_58/A1 (2715:3026:3338)(2715:3026:3338))
- (INTERCONNECT SLICE_29/Q0 SLICE_58/A0 (2715:3026:3338)(2715:3026:3338))
- (INTERCONNECT SLICE_29/Q0 SLICE_62/A1 (749:880:1011)(749:880:1011))
- (INTERCONNECT SLICE_29/Q0 SLICE_62/A0 (3085:3428:3772)(3085:3428:3772))
- (INTERCONNECT SLICE_29/Q0 SLICE_66/D1 (979:1084:1189)(979:1084:1189))
- (INTERCONNECT SLICE_29/Q0 SLICE_66/B0 (3111:3456:3802)(3111:3456:3802))
- (INTERCONNECT SLICE_29/Q0 SLICE_70/D0 (812:917:1023)(812:917:1023))
- (INTERCONNECT SLICE_29/Q0 SLICE_73/A1 (2320:2597:2874)(2320:2597:2874))
- (INTERCONNECT SLICE_29/Q0 SLICE_74/D0 (1819:1995:2172)(1819:1995:2172))
- (INTERCONNECT SLICE_29/Q0 SLICE_75/A1 (2715:3026:3338)(2715:3026:3338))
- (INTERCONNECT SLICE_29/Q0 SLICE_79/C1 (2085:2348:2612)(2085:2348:2612))
- (INTERCONNECT SLICE_29/Q0 SLICE_85/C0 (2121:2387:2654)(2121:2387:2654))
- (INTERCONNECT SLICE_29/Q0 SLICE_86/D0 (2110:2321:2533)(2110:2321:2533))
- (INTERCONNECT SLICE_29/Q0 SLICE_91/B0 (1926:2168:2410)(1926:2168:2410))
- (INTERCONNECT SLICE_29/Q0 SLICE_95/D0 (2880:3158:3437)(2880:3158:3437))
- (INTERCONNECT SLICE_29/Q0 SLICE_96/D1 (812:917:1023)(812:917:1023))
- (INTERCONNECT SLICE_29/Q0 SLICE_97/D0 (979:1084:1189)(979:1084:1189))
- (INTERCONNECT SLICE_29/Q0 SLICE_103/D0 (3250:3560:3871)(3250:3560:3871))
- (INTERCONNECT SLICE_29/Q0 SLICE_105/A1 (3090:3434:3778)(3090:3434:3778))
- (INTERCONNECT SLICE_29/Q0 SLICE_105/A0 (3090:3434:3778)(3090:3434:3778))
- (INTERCONNECT SLICE_29/Q0 SLICE_107/D0 (3250:3560:3871)(3250:3560:3871))
- (INTERCONNECT SLICE_29/Q0 SLICE_110/D1 (812:917:1023)(812:917:1023))
- (INTERCONNECT SLICE_29/Q0 SLICE_122/C1 (3261:3626:3992)(3261:3626:3992))
(INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_30/C1 (1525:1724:1923)
- (1525:1724:1923))
- (INTERCONNECT SLICE_45/F1 SLICE_30/C0 (534:645:756)(534:645:756))
- (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_30/F1 SLICE_30/B0 (508:600:693)(508:600:693))
+ (INTERCONNECT SLICE_29/F1 SLICE_62/C0 (536:647:758)(536:647:758))
+ (INTERCONNECT SLICE_29/F1 SLICE_81/D0 (1228:1354:1481)(1228:1354:1481))
+ (INTERCONNECT SLICE_29/F1 SLICE_90/A1 (1765:1992:2219)(1765:1992:2219))
+ (INTERCONNECT SLICE_101/F1 SLICE_30/D1 (800:885:971)(800:885:971))
+ (INTERCONNECT SLICE_101/F1 SLICE_63/C1 (1181:1353:1526)(1181:1353:1526))
+ (INTERCONNECT SLICE_101/F1 SLICE_65/B1 (1733:1953:2173)(1733:1953:2173))
+ (INTERCONNECT SLICE_101/F1 SLICE_67/C1 (1181:1353:1526)(1181:1353:1526))
+ (INTERCONNECT SLICE_103/F1 SLICE_30/A1 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_30/F1 SLICE_30/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (485:583:681)(485:583:681))
+ (INTERCONNECT SLICE_30/Q0 SLICE_31/D1 (539:633:727)(539:633:727))
+ (INTERCONNECT SLICE_30/Q0 SLICE_35/D1 (1456:1596:1736)(1456:1596:1736))
+ (INTERCONNECT SLICE_30/Q0 SLICE_37/B0 (2068:2308:2548)(2068:2308:2548))
+ (INTERCONNECT SLICE_30/Q0 SLICE_38/B1 (2068:2308:2548)(2068:2308:2548))
+ (INTERCONNECT SLICE_30/Q0 SLICE_46/B1 (781:943:1105)(781:943:1105))
+ (INTERCONNECT SLICE_30/Q0 SLICE_49/A1 (1836:2099:2363)(1836:2099:2363))
+ (INTERCONNECT SLICE_30/Q0 SLICE_49/A0 (1836:2099:2363)(1836:2099:2363))
+ (INTERCONNECT SLICE_30/Q0 SLICE_50/C1 (1637:1890:2143)(1637:1890:2143))
+ (INTERCONNECT SLICE_30/Q0 SLICE_50/C0 (1637:1890:2143)(1637:1890:2143))
+ (INTERCONNECT SLICE_30/Q0 SLICE_51/B1 (1868:2134:2400)(1868:2134:2400))
+ (INTERCONNECT SLICE_30/Q0 SLICE_51/B0 (1868:2134:2400)(1868:2134:2400))
+ (INTERCONNECT SLICE_30/Q0 SLICE_52/D0 (535:605:675)(535:605:675))
+ (INTERCONNECT SLICE_30/Q0 SLICE_53/B0 (1063:1261:1459)(1063:1261:1459))
+ (INTERCONNECT SLICE_30/Q0 SLICE_54/A1 (1411:1639:1868)(1411:1639:1868))
+ (INTERCONNECT SLICE_30/Q0 SLICE_54/A0 (1411:1639:1868)(1411:1639:1868))
+ (INTERCONNECT SLICE_30/Q0 SLICE_55/B1 (1818:2081:2345)(1818:2081:2345))
+ (INTERCONNECT SLICE_30/Q0 SLICE_58/D1 (540:603:666)(540:603:666))
+ (INTERCONNECT SLICE_30/Q0 SLICE_59/B1 (1063:1261:1459)(1063:1261:1459))
+ (INTERCONNECT SLICE_30/Q0 SLICE_59/B0 (1063:1261:1459)(1063:1261:1459))
+ (INTERCONNECT SLICE_30/Q0 SLICE_61/B1 (777:915:1053)(777:915:1053))
+ (INTERCONNECT SLICE_30/Q0 SLICE_61/B0 (777:915:1053)(777:915:1053))
+ (INTERCONNECT SLICE_30/Q0 SLICE_62/D1 (1446:1580:1714)(1446:1580:1714))
+ (INTERCONNECT SLICE_30/Q0 SLICE_84/B0 (1818:2081:2345)(1818:2081:2345))
+ (INTERCONNECT SLICE_30/Q0 SLICE_85/D0 (1201:1364:1527)(1201:1364:1527))
+ (INTERCONNECT SLICE_30/Q0 SLICE_95/C0 (816:999:1183)(816:999:1183))
+ (INTERCONNECT SLICE_30/Q0 SLICE_97/B0 (781:943:1105)(781:943:1105))
+ (INTERCONNECT SLICE_30/Q0 SLICE_103/D0 (540:603:666)(540:603:666))
+ (INTERCONNECT SLICE_30/Q0 SLICE_108/D1 (2273:2535:2798)(2273:2535:2798))
+ (INTERCONNECT SLICE_30/Q0 SLICE_108/C0 (1957:2239:2522)(1957:2239:2522))
+ (INTERCONNECT SLICE_30/Q0 SLICE_116/D1 (539:633:727)(539:633:727))
(INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT CROW\[0\]_I/PADDI SLICE_31/C0 (1585:1770:1955)(1585:1770:1955))
- (INTERCONNECT SLICE_37/Q0 SLICE_31/A0 (2007:2234:2461)(2007:2234:2461))
- (INTERCONNECT SLICE_37/Q0 SLICE_37/A0 (481:575:669)(481:575:669))
- (INTERCONNECT SLICE_37/Q0 SLICE_38/A1 (1213:1383:1554)(1213:1383:1554))
- (INTERCONNECT SLICE_37/Q0 SLICE_38/A0 (1213:1383:1554)(1213:1383:1554))
- (INTERCONNECT SLICE_37/Q0 SLICE_39/A1 (1593:1796:2000)(1593:1796:2000))
- (INTERCONNECT SLICE_37/Q0 SLICE_39/A0 (1593:1796:2000)(1593:1796:2000))
- (INTERCONNECT SLICE_37/Q0 SLICE_40/A1 (1588:1791:1994)(1588:1791:1994))
- (INTERCONNECT SLICE_37/Q0 SLICE_40/A0 (1588:1791:1994)(1588:1791:1994))
- (INTERCONNECT SLICE_37/Q0 SLICE_41/A1 (1593:1796:2000)(1593:1796:2000))
- (INTERCONNECT SLICE_37/Q0 SLICE_41/A0 (1593:1796:2000)(1593:1796:2000))
- (INTERCONNECT SLICE_37/Q0 SLICE_42/C1 (1759:1983:2208)(1759:1983:2208))
- (INTERCONNECT SLICE_37/Q0 SLICE_42/C0 (1759:1983:2208)(1759:1983:2208))
- (INTERCONNECT SLICE_37/Q0 SLICE_120/A1 (1441:1631:1821)(1441:1631:1821))
- (INTERCONNECT SLICE_37/Q0 SLICE_120/A0 (1441:1631:1821)(1441:1631:1821))
- (INTERCONNECT SLICE_31/Q0 SLICE_31/M1 (499:544:590)(499:544:590))
- (INTERCONNECT SLICE_31/Q0 SLICE_103/A1 (744:866:989)(744:866:989))
- (INTERCONNECT SLICE_31/Q0 SLICE_107/C1 (892:1045:1199)(892:1045:1199))
- (INTERCONNECT SLICE_31/Q0 SLICE_107/C0 (892:1045:1199)(892:1045:1199))
- (INTERCONNECT SLICE_31/Q0 SLICE_122/B0 (1123:1289:1456)(1123:1289:1456))
- (INTERCONNECT PHI2_MGIOL/IN SLICE_31/M0 (1806:1973:2141)(1806:1973:2141))
- (INTERCONNECT SLICE_31/F0 RBA\[0\]_MGIOL/OPOS (2677:2905:3134)(2677:2905:3134))
- (INTERCONNECT SLICE_31/Q1 SLICE_103/C1 (534:644:754)(534:644:754))
- (INTERCONNECT SLICE_31/Q1 SLICE_107/B1 (786:914:1043)(786:914:1043))
- (INTERCONNECT SLICE_31/Q1 SLICE_107/B0 (786:914:1043)(786:914:1043))
- (INTERCONNECT SLICE_31/Q1 SLICE_122/A0 (754:880:1006)(754:880:1006))
- (INTERCONNECT SLICE_80/Q0 SLICE_32/C1 (957:1111:1265)(957:1111:1265))
- (INTERCONNECT SLICE_80/Q0 SLICE_34/A0 (1531:1728:1925)(1531:1728:1925))
- (INTERCONNECT SLICE_80/Q0 SLICE_46/A0 (1531:1728:1925)(1531:1728:1925))
- (INTERCONNECT SLICE_80/Q0 SLICE_81/C1 (2430:2711:2993)(2430:2711:2993))
- (INTERCONNECT SLICE_80/Q0 SLICE_94/A0 (2228:2492:2756)(2228:2492:2756))
- (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_32/Q0 SLICE_32/M1 (488:531:575)(488:531:575))
- (INTERCONNECT SLICE_32/Q0 SLICE_35/B0 (1034:1188:1343)(1034:1188:1343))
- (INTERCONNECT SLICE_32/F1 LED_I/PADDO (1839:2016:2193)(1839:2016:2193))
- (INTERCONNECT SLICE_46/Q0 SLICE_33/D1 (1301:1436:1571)(1301:1436:1571))
- (INTERCONNECT SLICE_46/Q0 SLICE_111/B1 (1215:1382:1549)(1215:1382:1549))
- (INTERCONNECT SLICE_46/Q0 SLICE_111/B0 (1215:1382:1549)(1215:1382:1549))
- (INTERCONNECT SLICE_46/Q0 SLICE_114/B1 (1543:1746:1949)(1543:1746:1949))
- (INTERCONNECT SLICE_46/Q0 SLICE_115/A1 (1776:2008:2240)(1776:2008:2240))
- (INTERCONNECT SLICE_46/Q0 SLICE_115/D0 (1239:1370:1502)(1239:1370:1502))
- (INTERCONNECT SLICE_46/Q0 SLICE_116/B1 (2240:2510:2780)(2240:2510:2780))
- (INTERCONNECT SLICE_46/Q0 SLICE_116/D0 (1671:1838:2005)(1671:1838:2005))
- (INTERCONNECT SLICE_46/Q0 SLICE_117/C1 (1598:1823:2049)(1598:1823:2049))
- (INTERCONNECT SLICE_46/Q0 SLICE_117/B0 (1481:1680:1880)(1481:1680:1880))
- (INTERCONNECT SLICE_46/Q0 SLICE_118/D1 (1587:1757:1928)(1587:1757:1928))
- (INTERCONNECT SLICE_46/Q0 SLICE_118/D0 (1587:1757:1928)(1587:1757:1928))
- (INTERCONNECT SLICE_39/Q1 SLICE_33/B1 (772:897:1023)(772:897:1023))
- (INTERCONNECT MAin\[3\]_I/PADDI SLICE_33/A1 (2992:3267:3543)(2992:3267:3543))
- (INTERCONNECT MAin\[3\]_I/PADDI SLICE_39/B1 (3024:3302:3580)(3024:3302:3580))
- (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/C1 (3521:3849:4177)(3521:3849:4177))
- (INTERCONNECT SLICE_33/Q0 SLICE_35/A0 (1150:1314:1478)(1150:1314:1478))
- (INTERCONNECT SLICE_33/F1 RA\[3\]_I/PADDO (1470:1661:1852)(1470:1661:1852))
- (INTERCONNECT SLICE_43/F0 SLICE_34/C1 (592:720:848)(592:720:848))
- (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (5:11:17)(5:11:17))
- (INTERCONNECT SLICE_43/F0 SLICE_78/C1 (873:1026:1180)(873:1026:1180))
- (INTERCONNECT SLICE_36/Q0 SLICE_34/A1 (1392:1595:1798)(1392:1595:1798))
- (INTERCONNECT SLICE_36/Q0 SLICE_34/D0 (855:957:1060)(855:957:1060))
- (INTERCONNECT SLICE_36/Q0 SLICE_36/D0 (550:615:680)(550:615:680))
- (INTERCONNECT SLICE_36/Q0 SLICE_37/B1 (774:900:1026)(774:900:1026))
- (INTERCONNECT SLICE_36/Q0 SLICE_46/C0 (1241:1431:1621)(1241:1431:1621))
- (INTERCONNECT SLICE_36/Q0 SLICE_60/C1 (1241:1431:1621)(1241:1431:1621))
- (INTERCONNECT SLICE_36/Q0 SLICE_61/B1 (774:900:1026)(774:900:1026))
- (INTERCONNECT SLICE_36/Q0 SLICE_72/A0 (760:890:1021)(760:890:1021))
- (INTERCONNECT SLICE_36/Q0 SLICE_74/B0 (1154:1332:1510)(1154:1332:1510))
- (INTERCONNECT SLICE_36/Q0 SLICE_79/B0 (792:925:1058)(792:925:1058))
- (INTERCONNECT SLICE_36/Q0 SLICE_81/D1 (1600:1767:1934)(1600:1767:1934))
- (INTERCONNECT SLICE_36/Q0 SLICE_88/B1 (1842:2077:2312)(1842:2077:2312))
- (INTERCONNECT SLICE_34/F1 SLICE_34/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_108/F1 SLICE_34/B0 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_34/Q0 SLICE_35/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_31/C1 (1161:1328:1496)
+ (1161:1328:1496))
+ (INTERCONNECT SLICE_31/F1 SLICE_31/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_46/F1 SLICE_31/A0 (733:854:976)(733:854:976))
+ (INTERCONNECT SLICE_46/F1 SLICE_46/C0 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_47/Q0 SLICE_32/D1 (1887:2040:2194)(1887:2040:2194))
+ (INTERCONNECT SLICE_47/Q0 SLICE_102/A1 (1193:1358:1524)(1193:1358:1524))
+ (INTERCONNECT SLICE_47/Q0 SLICE_102/A0 (1193:1358:1524)(1193:1358:1524))
+ (INTERCONNECT SLICE_47/Q0 SLICE_109/C1 (2642:2915:3188)(2642:2915:3188))
+ (INTERCONNECT SLICE_47/Q0 SLICE_110/A1 (1193:1358:1524)(1193:1358:1524))
+ (INTERCONNECT SLICE_47/Q0 SLICE_110/C0 (1321:1511:1701)(1321:1511:1701))
+ (INTERCONNECT SLICE_47/Q0 SLICE_111/D1 (3011:3262:3513)(3011:3262:3513))
+ (INTERCONNECT SLICE_47/Q0 SLICE_111/D0 (3011:3262:3513)(3011:3262:3513))
+ (INTERCONNECT SLICE_47/Q0 SLICE_112/D1 (3011:3262:3513)(3011:3262:3513))
+ (INTERCONNECT SLICE_47/Q0 SLICE_112/C0 (3349:3690:4031)(3349:3690:4031))
+ (INTERCONNECT SLICE_47/Q0 SLICE_113/A1 (2841:3124:3408)(2841:3124:3408))
+ (INTERCONNECT SLICE_47/Q0 SLICE_113/A0 (2841:3124:3408)(2841:3124:3408))
+ (INTERCONNECT MAin\[4\]_I/PADDI SLICE_32/C1 (1992:2199:2406)(1992:2199:2406))
+ (INTERCONNECT MAin\[4\]_I/PADDI SLICE_41/A0 (2970:3263:3556)(2970:3263:3556))
+ (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/A1 (2919:3199:3480)(2919:3199:3480))
+ (INTERCONNECT SLICE_41/Q0 SLICE_32/B1 (1462:1650:1838)(1462:1650:1838))
+ (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_32/D0 (1514:1658:1802)(1514:1658:1802))
+ (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_32/C0 (986:1141:1297)(986:1141:1297))
+ (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_32/B0 (1285:1461:1638)(1285:1461:1638))
+ (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_32/A0 (1806:2010:2215)(1806:2010:2215))
+ (INTERCONNECT SLICE_32/Q0 SLICE_32/M1 (499:544:590)(499:544:590))
+ (INTERCONNECT SLICE_32/Q0 SLICE_95/D1 (534:591:648)(534:591:648))
+ (INTERCONNECT SLICE_32/Q0 SLICE_97/D1 (529:593:657)(529:593:657))
+ (INTERCONNECT SLICE_32/Q0 SLICE_97/D0 (529:593:657)(529:593:657))
+ (INTERCONNECT SLICE_32/Q0 SLICE_116/B0 (771:903:1035)(771:903:1035))
+ (INTERCONNECT PHI2_MGIOL/IN SLICE_32/M0 (1817:1968:2119)(1817:1968:2119))
+ (INTERCONNECT SLICE_32/F0 SLICE_75/C1 (800:939:1079)(800:939:1079))
+ (INTERCONNECT SLICE_32/F1 RA\[4\]_I/PADDO (1916:2133:2351)(1916:2133:2351))
+ (INTERCONNECT SLICE_32/Q1 SLICE_95/A1 (733:853:974)(733:853:974))
+ (INTERCONNECT SLICE_32/Q1 SLICE_97/A1 (739:868:998)(739:868:998))
+ (INTERCONNECT SLICE_32/Q1 SLICE_97/A0 (739:868:998)(739:868:998))
+ (INTERCONNECT SLICE_32/Q1 SLICE_116/C0 (540:659:778)(540:659:778))
+ (INTERCONNECT SLICE_73/Q0 SLICE_33/D1 (1008:1099:1191)(1008:1099:1191))
+ (INTERCONNECT SLICE_73/Q0 SLICE_35/D0 (2075:2265:2456)(2075:2265:2456))
+ (INTERCONNECT SLICE_73/Q0 SLICE_47/A1 (1952:2172:2393)(1952:2172:2393))
+ (INTERCONNECT SLICE_73/Q0 SLICE_96/A1 (2649:2936:3224)(2649:2936:3224))
+ (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_33/Q0 SLICE_33/M1 (488:531:575)(488:531:575))
+ (INTERCONNECT SLICE_33/Q0 SLICE_36/B0 (1139:1298:1457)(1139:1298:1457))
+ (INTERCONNECT SLICE_33/F1 LED_I/PADDO (1475:1620:1766)(1475:1620:1766))
+ (INTERCONNECT SLICE_86/F1 SLICE_34/A0 (1511:1715:1920)(1511:1715:1920))
+ (INTERCONNECT SLICE_86/F1 SLICE_63/A0 (1184:1353:1523)(1184:1353:1523))
+ (INTERCONNECT SLICE_86/F1 SLICE_83/C0 (539:650:761)(539:650:761))
+ (INTERCONNECT SLICE_86/F1 SLICE_86/B0 (767:894:1021)(767:894:1021))
+ (INTERCONNECT SLICE_34/F0 SLICE_56/C1 (800:939:1079)(800:939:1079))
+ (INTERCONNECT SLICE_34/Q0 SLICE_36/C0 (1447:1632:1817)(1447:1632:1817))
+ (INTERCONNECT SLICE_34/F1 SLICE_91/A0 (476:566:656)(476:566:656))
+ (INTERCONNECT SLICE_44/F0 SLICE_35/A1 (740:864:989)(740:864:989))
+ (INTERCONNECT SLICE_44/F0 SLICE_44/C1 (284:372:461)(284:372:461))
+ (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (7:16:25)(7:16:25))
+ (INTERCONNECT SLICE_44/F0 SLICE_90/B0 (779:913:1048)(779:913:1048))
+ (INTERCONNECT SLICE_105/F0 SLICE_35/C0 (846:994:1143)(846:994:1143))
+ (INTERCONNECT SLICE_35/F1 SLICE_35/A0 (730:848:967)(730:848:967))
(INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_35/Q0 SLICE_72/B1 (1148:1306:1464)(1148:1306:1464))
- (INTERCONNECT SLICE_35/Q0 SLICE_78/B0 (1148:1306:1464)(1148:1306:1464))
- (INTERCONNECT SLICE_35/Q0 SLICE_90/D0 (1270:1391:1513)(1270:1391:1513))
- (INTERCONNECT SLICE_35/Q0 RCKE_I/PADDO (2087:2313:2539)(2087:2313:2539))
- (INTERCONNECT SLICE_35/F1 SLICE_60/B1 (772:897:1023)(772:897:1023))
- (INTERCONNECT SLICE_43/F1 SLICE_36/C0 (537:645:753)(537:645:753))
- (INTERCONNECT SLICE_43/F1 SLICE_37/A1 (733:854:976)(733:854:976))
- (INTERCONNECT SLICE_36/F1 SLICE_36/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_36/F1 SLICE_37/D1 (860:955:1051)(860:955:1051))
+ (INTERCONNECT SLICE_35/Q0 SLICE_36/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_36/Q0 SLICE_36/A1 (735:857:980)(735:857:980))
+ (INTERCONNECT SLICE_36/Q0 SLICE_90/C0 (1237:1420:1603)(1237:1420:1603))
+ (INTERCONNECT SLICE_36/Q0 RCKE_I/PADDO (1875:2078:2282)(1875:2078:2282))
(INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_37/F1 SLICE_37/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_36/F1 SLICE_68/D1 (266:290:315)(266:290:315))
+ (INTERCONNECT SLICE_37/F1 SLICE_37/C0 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_37/F1 SLICE_38/D1 (269:296:324)(269:296:324))
(INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_38/F1 SLICE_38/DI1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_38/F1 SLICE_38/C0 (277:356:436)(277:356:436))
(INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_38/Q0 SLICE_116/B0 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_38/Q1 SLICE_117/C0 (541:653:766)(541:653:766))
- (INTERCONNECT MAin\[2\]_I/PADDI SLICE_39/B0 (2638:2895:3152)(2638:2895:3152))
- (INTERCONNECT MAin\[2\]_I/PADDI SLICE_93/B1 (2632:2888:3145)(2632:2888:3145))
- (INTERCONNECT MAin\[2\]_I/PADDI SLICE_118/B0 (3366:3686:4006)(3366:3686:4006))
(INTERCONNECT SLICE_39/F1 SLICE_39/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_39/Q0 SLICE_118/C0 (975:1126:1278)(975:1126:1278))
- (INTERCONNECT MAin\[5\]_I/PADDI SLICE_40/D1 (2873:3079:3285)(2873:3079:3285))
- (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/D1 (3112:3357:3603)(3112:3357:3603))
- (INTERCONNECT MAin\[5\]_I/PADDI SLICE_117/A1 (3083:3354:3626)(3083:3354:3626))
- (INTERCONNECT MAin\[4\]_I/PADDI SLICE_40/C0 (2884:3145:3406)(2884:3145:3406))
- (INTERCONNECT MAin\[4\]_I/PADDI SLICE_114/B0 (3555:3855:4155)(3555:3855:4155))
- (INTERCONNECT MAin\[4\]_I/PADDI SLICE_118/A1 (3083:3354:3626)(3083:3354:3626))
+ (INTERCONNECT SLICE_39/Q0 SLICE_111/A1 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_39/Q1 SLICE_112/C1 (531:639:747)(531:639:747))
+ (INTERCONNECT MAin\[3\]_I/PADDI SLICE_40/D1 (2427:2605:2784)(2427:2605:2784))
+ (INTERCONNECT MAin\[3\]_I/PADDI SLICE_109/A1 (2637:2881:3125)(2637:2881:3125))
+ (INTERCONNECT MAin\[3\]_I/PADDI SLICE_109/A0 (2637:2881:3125)(2637:2881:3125))
+ (INTERCONNECT MAin\[2\]_I/PADDI SLICE_40/D0 (2031:2188:2346)(2031:2188:2346))
+ (INTERCONNECT MAin\[2\]_I/PADDI SLICE_89/B1 (2637:2894:3151)(2637:2894:3151))
+ (INTERCONNECT MAin\[2\]_I/PADDI SLICE_113/C1 (2042:2254:2467)(2042:2254:2467))
(INTERCONNECT SLICE_40/F1 SLICE_40/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_40/F0 SLICE_40/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_40/Q0 SLICE_118/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_40/Q1 SLICE_117/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT MAin\[7\]_I/PADDI SLICE_41/D1 (2782:2992:3202)(2782:2992:3202))
- (INTERCONNECT MAin\[7\]_I/PADDI SLICE_93/A1 (3720:4058:4397)(3720:4058:4397))
- (INTERCONNECT MAin\[7\]_I/PADDI SLICE_116/C1 (3157:3453:3750)(3157:3453:3750))
- (INTERCONNECT MAin\[6\]_I/PADDI SLICE_41/C0 (2438:2671:2905)(2438:2671:2905))
- (INTERCONNECT MAin\[6\]_I/PADDI SLICE_114/C1 (2438:2671:2905)(2438:2671:2905))
- (INTERCONNECT MAin\[6\]_I/PADDI SLICE_114/C0 (2438:2671:2905)(2438:2671:2905))
+ (INTERCONNECT SLICE_40/Q0 SLICE_113/D1 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_40/Q1 SLICE_109/D1 (520:573:626)(520:573:626))
+ (INTERCONNECT MAin\[5\]_I/PADDI SLICE_41/A1 (2637:2881:3125)(2637:2881:3125))
+ (INTERCONNECT MAin\[5\]_I/PADDI SLICE_89/C1 (2802:3067:3332)(2802:3067:3332))
+ (INTERCONNECT MAin\[5\]_I/PADDI SLICE_113/B0 (2669:2915:3162)(2669:2915:3162))
(INTERCONNECT SLICE_41/F1 SLICE_41/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_41/Q0 SLICE_114/A1 (730:848:967)(730:848:967))
- (INTERCONNECT SLICE_41/Q1 SLICE_116/D1 (530:587:645)(530:587:645))
- (INTERCONNECT MAin\[9\]_I/PADDI SLICE_42/A1 (2634:2873:3113)(2634:2873:3113))
- (INTERCONNECT MAin\[9\]_I/PADDI SLICE_111/C1 (1989:2191:2394)(1989:2191:2394))
- (INTERCONNECT MAin\[9\]_I/PADDI SLICE_111/C0 (1989:2191:2394)(1989:2191:2394))
- (INTERCONNECT MAin\[9\]_I/PADDI SLICE_115/B1 (2666:2908:3150)(2666:2908:3150))
- (INTERCONNECT MAin\[8\]_I/PADDI SLICE_42/B0 (3110:3382:3655)(3110:3382:3655))
- (INTERCONNECT MAin\[8\]_I/PADDI SLICE_115/C0 (2879:3138:3398)(2879:3138:3398))
+ (INTERCONNECT SLICE_41/Q1 SLICE_113/D0 (520:573:626)(520:573:626))
+ (INTERCONNECT MAin\[7\]_I/PADDI SLICE_42/C1 (2429:2662:2896)(2429:2662:2896))
+ (INTERCONNECT MAin\[7\]_I/PADDI SLICE_89/D1 (3109:3354:3599)(3109:3354:3599))
+ (INTERCONNECT MAin\[7\]_I/PADDI SLICE_111/B0 (2660:2906:3153)(2660:2906:3153))
+ (INTERCONNECT MAin\[6\]_I/PADDI SLICE_42/C0 (2424:2657:2890)(2424:2657:2890))
+ (INTERCONNECT MAin\[6\]_I/PADDI SLICE_109/D0 (3275:3531:3788)(3275:3531:3788))
+ (INTERCONNECT MAin\[6\]_I/PADDI SLICE_112/D0 (2751:2966:3181)(2751:2966:3181))
(INTERCONNECT SLICE_42/F1 SLICE_42/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_42/Q0 SLICE_115/A0 (730:848:967)(730:848:967))
- (INTERCONNECT SLICE_42/Q1 SLICE_115/D1 (520:573:626)(520:573:626))
- (INTERCONNECT SLICE_44/Q0 SLICE_44/B1 (765:888:1011)(765:888:1011))
- (INTERCONNECT SLICE_44/Q0 SLICE_120/B0 (1185:1353:1522)(1185:1353:1522))
- (INTERCONNECT SLICE_44/F1 SLICE_44/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_100/F0 SLICE_44/A0 (733:848:964)(733:848:964))
- (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_122/F0 SLICE_45/C1 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_68/F0 SLICE_45/A1 (733:848:964)(733:848:964))
- (INTERCONNECT SLICE_122/F1 SLICE_45/D0 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_42/Q0 SLICE_112/B0 (762:883:1004)(762:883:1004))
+ (INTERCONNECT SLICE_42/Q1 SLICE_111/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT MAin\[9\]_I/PADDI SLICE_43/A1 (2193:2405:2618)(2193:2405:2618))
+ (INTERCONNECT MAin\[9\]_I/PADDI SLICE_102/D1 (1983:2130:2277)(1983:2130:2277))
+ (INTERCONNECT MAin\[9\]_I/PADDI SLICE_102/D0 (1983:2130:2277)(1983:2130:2277))
+ (INTERCONNECT MAin\[9\]_I/PADDI SLICE_110/B0 (2225:2440:2655)(2225:2440:2655))
+ (INTERCONNECT MAin\[8\]_I/PADDI SLICE_43/C0 (1965:2170:2375)(1965:2170:2375))
+ (INTERCONNECT MAin\[8\]_I/PADDI SLICE_110/C1 (1965:2170:2375)(1965:2170:2375))
+ (INTERCONNECT SLICE_43/F1 SLICE_43/DI1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_43/Q0 SLICE_110/D1 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_43/Q1 SLICE_110/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_73/Q1 SLICE_44/B1 (1589:1787:1985)(1589:1787:1985))
+ (INTERCONNECT SLICE_73/Q1 SLICE_117/B1 (1589:1787:1985)(1589:1787:1985))
+ (INTERCONNECT SLICE_44/F1 SLICE_92/D1 (269:296:324)(269:296:324))
+ (INTERCONNECT SLICE_44/F1 SLICE_96/C0 (534:645:756)(534:645:756))
+ (INTERCONNECT SLICE_45/Q0 SLICE_45/A1 (733:853:974)(733:853:974))
+ (INTERCONNECT SLICE_45/Q0 SLICE_115/A0 (1002:1154:1306)(1002:1154:1306))
+ (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_93/F0 SLICE_45/A0 (730:848:967)(730:848:967))
(INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_107/Q0 SLICE_46/D1 (1547:1671:1796)(1547:1671:1796))
- (INTERCONNECT SLICE_107/Q0 SLICE_108/B0 (2153:2377:2601)(2153:2377:2601))
- (INTERCONNECT SLICE_46/F1 SLICE_46/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_46/F1 SLICE_94/B1 (768:889:1010)(768:889:1010))
+ (INTERCONNECT SLICE_67/F1 SLICE_46/D1 (523:573:623)(523:573:623))
+ (INTERCONNECT SLICE_116/F0 SLICE_46/A1 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_108/F1 SLICE_46/D0 (789:873:958)(789:873:958))
(INTERCONNECT SLICE_46/F0 SLICE_46/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_72/F0 SLICE_46/LSR (927:1039:1151)(927:1039:1151))
- (INTERCONNECT SLICE_72/F0 SLICE_72/D1 (536:597:658)(536:597:658))
- (INTERCONNECT SLICE_72/F0 SLICE_78/D0 (536:597:658)(536:597:658))
- (INTERCONNECT SLICE_72/F0 SLICE_90/C0 (539:650:761)(539:650:761))
- (INTERCONNECT SLICE_105/F1 SLICE_47/D1 (523:573:623)(523:573:623))
- (INTERCONNECT SLICE_58/F1 SLICE_47/C1 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_75/F0 SLICE_47/B1 (508:600:693)(508:600:693))
- (INTERCONNECT SLICE_106/F1 SLICE_47/A1 (740:863:986)(740:863:986))
- (INTERCONNECT SLICE_65/F0 SLICE_47/D0 (789:873:958)(789:873:958))
- (INTERCONNECT SLICE_97/F0 SLICE_47/C0 (541:653:766)(541:653:766))
- (INTERCONNECT SLICE_96/F0 SLICE_47/B0 (1462:1650:1838)(1462:1650:1838))
- (INTERCONNECT SLICE_106/F0 SLICE_47/A0 (740:863:986)(740:863:986))
- (INTERCONNECT SLICE_47/F1 SLICE_47/DI1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_76/Q0 SLICE_47/C1 (1019:1165:1312)(1019:1165:1312))
+ (INTERCONNECT SLICE_76/Q0 SLICE_92/D0 (1378:1501:1625)(1378:1501:1625))
+ (INTERCONNECT SLICE_76/Q0 SLICE_117/B0 (1620:1811:2003)(1620:1811:2003))
+ (INTERCONNECT SLICE_47/F1 SLICE_47/C0 (277:356:436)(277:356:436))
(INTERCONNECT SLICE_47/F0 SLICE_47/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_103/F0 SLICE_47/CE (994:1095:1197)(994:1095:1197))
- (INTERCONNECT SLICE_103/F0 SLICE_47/CE (994:1095:1197)(994:1095:1197))
- (INTERCONNECT SLICE_103/F0 SLICE_48/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_48/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_49/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_49/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_50/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_50/CE (1749:1916:2083)(1749:1916:2083))
- (INTERCONNECT SLICE_103/F0 SLICE_52/CE (1374:1508:1643)(1374:1508:1643))
- (INTERCONNECT SLICE_103/F0 SLICE_52/CE (1374:1508:1643)(1374:1508:1643))
- (INTERCONNECT SLICE_103/F0 SLICE_53/CE (1744:1910:2077)(1744:1910:2077))
- (INTERCONNECT SLICE_103/F0 SLICE_53/CE (1744:1910:2077)(1744:1910:2077))
- (INTERCONNECT SLICE_103/F0 SLICE_54/CE (1744:1910:2077)(1744:1910:2077))
- (INTERCONNECT SLICE_103/F0 SLICE_54/CE (1744:1910:2077)(1744:1910:2077))
- (INTERCONNECT SLICE_103/F0 SLICE_55/CE (1374:1508:1643)(1374:1508:1643))
- (INTERCONNECT SLICE_103/F0 SLICE_55/CE (1374:1508:1643)(1374:1508:1643))
- (INTERCONNECT SLICE_103/F0 SLICE_58/CE (994:1095:1197)(994:1095:1197))
- (INTERCONNECT SLICE_47/Q0 SLICE_58/B1 (765:888:1011)(765:888:1011))
- (INTERCONNECT SLICE_47/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1236:1368:1501)
- (1236:1368:1501))
- (INTERCONNECT SLICE_47/Q1 SLICE_48/D0 (795:880:965)(795:880:965))
- (INTERCONNECT SLICE_47/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1603:1765:1928)
- (1603:1765:1928))
- (INTERCONNECT SLICE_48/Q0 SLICE_48/B1 (765:888:1011)(765:888:1011))
- (INTERCONNECT SLICE_48/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (1341:1478:1615)
- (1341:1478:1615))
+ (INTERCONNECT SLICE_68/F0 SLICE_47/LSR (542:602:662)(542:602:662))
+ (INTERCONNECT SLICE_68/F0 SLICE_68/B1 (765:889:1013)(765:889:1013))
+ (INTERCONNECT SLICE_107/F1 SLICE_48/D1 (269:296:324)(269:296:324))
+ (INTERCONNECT SLICE_107/F1 SLICE_77/C0 (534:645:756)(534:645:756))
+ (INTERCONNECT SLICE_61/F0 SLICE_48/A1 (1430:1615:1801)(1430:1615:1801))
+ (INTERCONNECT SLICE_77/F0 SLICE_48/D0 (266:290:315)(266:290:315))
+ (INTERCONNECT SLICE_107/F0 SLICE_48/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_99/F1 SLICE_48/A0 (738:859:981)(738:859:981))
+ (INTERCONNECT SLICE_99/F1 SLICE_69/B1 (772:902:1032)(772:902:1032))
+ (INTERCONNECT SLICE_99/F1 SLICE_79/A0 (1006:1168:1330)(1006:1168:1330))
+ (INTERCONNECT SLICE_99/F1 SLICE_80/D0 (271:301:332)(271:301:332))
(INTERCONNECT SLICE_48/F1 SLICE_48/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_48/F0 SLICE_48/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_48/Q1 SLICE_49/B0 (765:888:1011)(765:888:1011))
+ (INTERCONNECT SLICE_95/F0 SLICE_48/CE (1315:1452:1589)(1315:1452:1589))
+ (INTERCONNECT SLICE_95/F0 SLICE_48/CE (1315:1452:1589)(1315:1452:1589))
+ (INTERCONNECT SLICE_95/F0 SLICE_49/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_49/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_50/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_50/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_51/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_51/CE (1450:1581:1712)(1450:1581:1712))
+ (INTERCONNECT SLICE_95/F0 SLICE_53/CE (1455:1586:1718)(1455:1586:1718))
+ (INTERCONNECT SLICE_95/F0 SLICE_53/CE (1455:1586:1718)(1455:1586:1718))
+ (INTERCONNECT SLICE_95/F0 SLICE_54/CE (1825:1988:2152)(1825:1988:2152))
+ (INTERCONNECT SLICE_95/F0 SLICE_54/CE (1825:1988:2152)(1825:1988:2152))
+ (INTERCONNECT SLICE_95/F0 SLICE_55/CE (2189:2384:2579)(2189:2384:2579))
+ (INTERCONNECT SLICE_95/F0 SLICE_55/CE (2189:2384:2579)(2189:2384:2579))
+ (INTERCONNECT SLICE_95/F0 SLICE_56/CE (1455:1586:1718)(1455:1586:1718))
+ (INTERCONNECT SLICE_95/F0 SLICE_56/CE (1455:1586:1718)(1455:1586:1718))
+ (INTERCONNECT SLICE_95/F0 SLICE_59/CE (1819:1982:2145)(1819:1982:2145))
+ (INTERCONNECT SLICE_48/Q0 SLICE_61/C0 (536:647:758)(536:647:758))
+ (INTERCONNECT SLICE_48/Q0
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1666:1838:2010)
+ (1666:1838:2010))
+ (INTERCONNECT SLICE_48/Q1 SLICE_49/C0 (911:1055:1200)(911:1055:1200))
(INTERCONNECT SLICE_48/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1236:1368:1501)
- (1236:1368:1501))
- (INTERCONNECT SLICE_97/F1 SLICE_49/C1 (816:962:1109)(816:962:1109))
- (INTERCONNECT SLICE_97/F1 SLICE_49/C0 (816:962:1109)(816:962:1109))
- (INTERCONNECT SLICE_97/F1 SLICE_50/C0 (816:962:1109)(816:962:1109))
- (INTERCONNECT SLICE_97/F1 SLICE_58/D1 (541:605:669)(541:605:669))
- (INTERCONNECT SLICE_97/F1 SLICE_58/D0 (541:605:669)(541:605:669))
- (INTERCONNECT SLICE_97/F1 SLICE_97/C0 (536:650:764)(536:650:764))
- (INTERCONNECT SLICE_49/Q0 SLICE_49/B1 (765:888:1011)(765:888:1011))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1381:1513:1645)
+ (1381:1513:1645))
+ (INTERCONNECT SLICE_49/Q0 SLICE_49/D1 (523:578:633)(523:578:633))
(INTERCONNECT SLICE_49/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (1341:1478:1615)
- (1341:1478:1615))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (909:1006:1104)
+ (909:1006:1104))
(INTERCONNECT SLICE_49/F1 SLICE_49/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_49/Q1 SLICE_50/D0 (523:578:633)(523:578:633))
+ (INTERCONNECT SLICE_49/Q1 SLICE_50/A0 (733:853:974)(733:853:974))
(INTERCONNECT SLICE_49/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1341:1478:1615)
- (1341:1478:1615))
- (INTERCONNECT SLICE_50/Q0 SLICE_50/D1 (523:578:633)(523:578:633))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1014:1116:1218)
+ (1014:1116:1218))
+ (INTERCONNECT SLICE_61/F1 SLICE_50/D1 (993:1109:1225)(993:1109:1225))
+ (INTERCONNECT SLICE_61/F1 SLICE_50/D0 (993:1109:1225)(993:1109:1225))
+ (INTERCONNECT SLICE_61/F1 SLICE_51/C0 (1004:1175:1346)(1004:1175:1346))
+ (INTERCONNECT SLICE_61/F1 SLICE_52/C1 (544:670:796)(544:670:796))
+ (INTERCONNECT SLICE_61/F1 SLICE_60/B1 (1610:1826:2043)(1610:1826:2043))
+ (INTERCONNECT SLICE_61/F1 SLICE_61/D0 (533:604:675)(533:604:675))
+ (INTERCONNECT SLICE_61/F1 SLICE_67/D1 (538:612:686)(538:612:686))
+ (INTERCONNECT SLICE_61/F1 SLICE_72/B1 (1610:1826:2043)(1610:1826:2043))
+ (INTERCONNECT SLICE_61/F1 SLICE_77/B1 (521:631:742)(521:631:742))
+ (INTERCONNECT SLICE_61/F1 SLICE_79/C1 (575:707:840)(575:707:840))
+ (INTERCONNECT SLICE_61/F1 SLICE_83/B0 (1610:1826:2043)(1610:1826:2043))
+ (INTERCONNECT SLICE_61/F1 SLICE_84/D1 (934:1043:1153)(934:1043:1153))
+ (INTERCONNECT SLICE_61/F1 SLICE_85/C1 (950:1115:1280)(950:1115:1280))
+ (INTERCONNECT SLICE_61/F1 SLICE_86/C0 (815:978:1142)(815:978:1142))
+ (INTERCONNECT SLICE_61/F1 SLICE_87/C0 (290:387:485)(290:387:485))
+ (INTERCONNECT SLICE_61/F1 SLICE_88/C1 (575:707:840)(575:707:840))
+ (INTERCONNECT SLICE_61/F1 SLICE_99/B1 (1181:1359:1537)(1181:1359:1537))
+ (INTERCONNECT SLICE_61/F1 SLICE_99/B0 (1181:1359:1537)(1181:1359:1537))
+ (INTERCONNECT SLICE_61/F1 SLICE_107/C1 (575:707:840)(575:707:840))
+ (INTERCONNECT SLICE_61/F1 SLICE_108/B0 (1176:1353:1531)(1176:1353:1531))
+ (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (733:853:974)(733:853:974))
(INTERCONNECT SLICE_50/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (909:1006:1104)
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (909:1006:1104)
(909:1006:1104))
(INTERCONNECT SLICE_50/F1 SLICE_50/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_50/Q1 SLICE_51/A0 (733:853:974)(733:853:974))
(INTERCONNECT SLICE_50/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (1233:1363:1494)
- (1233:1363:1494))
- (INTERCONNECT SLICE_66/F1 SLICE_51/D1 (987:1090:1194)(987:1090:1194))
- (INTERCONNECT SLICE_66/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D1 (1012:1118:1224)
- (1012:1118:1224))
- (INTERCONNECT SLICE_66/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D0 (1012:1118:1224)
- (1012:1118:1224))
- (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_66/F1 SLICE_68/D0 (987:1090:1194)(987:1090:1194))
- (INTERCONNECT SLICE_66/F1 SLICE_69/A1 (1586:1789:1992)(1586:1789:1992))
- (INTERCONNECT SLICE_66/F1 SLICE_76/D0 (1012:1118:1224)(1012:1118:1224))
- (INTERCONNECT SLICE_66/F1 SLICE_77/C1 (1023:1184:1345)(1023:1184:1345))
- (INTERCONNECT SLICE_66/F1 SLICE_87/B1 (1218:1388:1559)(1218:1388:1559))
- (INTERCONNECT SLICE_66/F1 SLICE_91/A1 (1222:1393:1565)(1222:1393:1565))
- (INTERCONNECT SLICE_66/F1 SLICE_92/D0 (987:1090:1194)(987:1090:1194))
- (INTERCONNECT SLICE_66/F1 SLICE_113/B1 (1254:1428:1602)(1254:1428:1602))
- (INTERCONNECT SLICE_66/F1 SLICE_113/B0 (1254:1428:1602)(1254:1428:1602))
- (INTERCONNECT SLICE_121/F0 SLICE_51/C1 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_121/F0 SLICE_92/D1 (269:296:324)(269:296:324))
- (INTERCONNECT SLICE_121/F1 SLICE_51/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_98/F0 SLICE_51/A1 (1051:1210:1370)(1051:1210:1370))
- (INTERCONNECT SLICE_98/F0 SLICE_92/C0 (852:1001:1150)(852:1001:1150))
- (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_107/F1 SLICE_51/B0 (772:897:1023)(772:897:1023))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1341:1478:1615)
+ (1341:1478:1615))
+ (INTERCONNECT SLICE_51/Q0 SLICE_51/D1 (523:578:633)(523:578:633))
+ (INTERCONNECT SLICE_51/Q0
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (909:1006:1104)
+ (909:1006:1104))
+ (INTERCONNECT SLICE_51/F1 SLICE_51/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_92/F0 SLICE_51/CE (539:596:653)(539:596:653))
- (INTERCONNECT SLICE_57/F1 SLICE_51/LSR (817:909:1001)(817:909:1001))
- (INTERCONNECT SLICE_57/F1 SLICE_56/LSR (817:909:1001)(817:909:1001))
- (INTERCONNECT SLICE_57/F1 SLICE_57/D0 (534:592:650)(534:592:650))
- (INTERCONNECT SLICE_57/F1 SLICE_58/LSR (553:615:677)(553:615:677))
- (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin
- (1343:1474:1606)(1343:1474:1606))
- (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin
- (1689:1859:2030)(1689:1859:2030))
- (INTERCONNECT SLICE_123/F1 SLICE_52/D1 (975:1078:1181)(975:1078:1181))
- (INTERCONNECT SLICE_123/F1 SLICE_55/A0 (1555:1755:1956)(1555:1755:1956))
- (INTERCONNECT SLICE_123/F1 SLICE_63/B1 (770:894:1018)(770:894:1018))
- (INTERCONNECT SLICE_123/F1 SLICE_75/A0 (1555:1755:1956)(1555:1755:1956))
- (INTERCONNECT SLICE_123/F1 SLICE_86/C1 (807:958:1110)(807:958:1110))
- (INTERCONNECT SLICE_123/F1 SLICE_95/A0 (740:867:995)(740:867:995))
- (INTERCONNECT SLICE_91/F0 SLICE_52/C1 (975:1126:1278)(975:1126:1278))
- (INTERCONNECT SLICE_77/F1 SLICE_52/B1 (1104:1270:1437)(1104:1270:1437))
- (INTERCONNECT SLICE_77/F1 SLICE_54/B0 (1036:1194:1353)(1036:1194:1353))
- (INTERCONNECT SLICE_77/F1 SLICE_55/B0 (778:907:1036)(778:907:1036))
- (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (778:907:1036)(778:907:1036))
- (INTERCONNECT SLICE_58/Q0 SLICE_52/C0 (802:947:1093)(802:947:1093))
- (INTERCONNECT SLICE_58/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin
- (1339:1476:1613)(1339:1476:1613))
- (INTERCONNECT SLICE_113/F0 SLICE_52/B0 (1037:1190:1343)(1037:1190:1343))
- (INTERCONNECT SLICE_113/F0 SLICE_85/B1 (1037:1190:1343)(1037:1190:1343))
- (INTERCONNECT SLICE_102/F0 SLICE_52/A0 (1174:1336:1498)(1174:1336:1498))
- (INTERCONNECT SLICE_52/F1 SLICE_52/DI1 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_51/Q1
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (906:1001:1097)
+ (906:1001:1097))
+ (INTERCONNECT SLICE_57/Q0 SLICE_52/B1 (1509:1700:1891)(1509:1700:1891))
+ (INTERCONNECT SLICE_57/Q0 SLICE_57/A0 (479:571:663)(479:571:663))
+ (INTERCONNECT SLICE_57/Q0 SLICE_87/D1 (1267:1390:1513)(1267:1390:1513))
+ (INTERCONNECT SLICE_91/F0 SLICE_52/A1 (1005:1155:1306)(1005:1155:1306))
+ (INTERCONNECT SLICE_91/F0 SLICE_87/A0 (1332:1517:1703)(1332:1517:1703))
+ (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_97/F1 SLICE_52/A0 (999:1149:1299)(999:1149:1299))
(INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_52/Q0 SLICE_91/D0 (1296:1429:1562)(1296:1429:1562))
- (INTERCONNECT SLICE_52/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1413:1557:1701)
- (1413:1557:1701))
- (INTERCONNECT SLICE_52/Q1 SLICE_53/A0 (743:868:993)(743:868:993))
- (INTERCONNECT SLICE_52/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1014:1116:1218)
- (1014:1116:1218))
- (INTERCONNECT SLICE_71/F1 SLICE_53/D1 (964:1060:1157)(964:1060:1157))
- (INTERCONNECT SLICE_87/F1 SLICE_53/C1 (811:957:1103)(811:957:1103))
- (INTERCONNECT SLICE_87/F1 SLICE_67/A1 (745:874:1003)(745:874:1003))
- (INTERCONNECT SLICE_87/F1 SLICE_87/B0 (513:611:710)(513:611:710))
- (INTERCONNECT SLICE_87/F1 SLICE_89/A0 (1010:1166:1323)(1010:1166:1323))
- (INTERCONNECT SLICE_73/F1 SLICE_53/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_109/F1 SLICE_53/A1 (1067:1225:1383)(1067:1225:1383))
- (INTERCONNECT wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/OFX0 SLICE_53/D0 (525:581:637)
- (525:581:637))
- (INTERCONNECT wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/OFX0 SLICE_54/B1 (767:891:1015)
- (767:891:1015))
+ (INTERCONNECT SLICE_87/F0 SLICE_52/CE (539:596:653)(539:596:653))
+ (INTERCONNECT SLICE_58/F1 SLICE_52/LSR (885:985:1085)(885:985:1085))
+ (INTERCONNECT SLICE_58/F1 SLICE_57/LSR (553:615:677)(553:615:677))
+ (INTERCONNECT SLICE_58/F1 SLICE_58/C0 (545:658:771)(545:658:771))
+ (INTERCONNECT SLICE_58/F1 SLICE_59/LSR (1249:1380:1512)(1249:1380:1512))
+ (INTERCONNECT SLICE_52/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin
+ (1087:1195:1303)(1087:1195:1303))
+ (INTERCONNECT SLICE_52/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin
+ (1433:1580:1727)(1433:1580:1727))
+ (INTERCONNECT SLICE_60/F1 SLICE_53/D1 (535:598:662)(535:598:662))
+ (INTERCONNECT SLICE_60/F1 SLICE_60/B0 (767:894:1021)(767:894:1021))
+ (INTERCONNECT SLICE_60/F1 SLICE_83/D0 (525:584:643)(525:584:643))
+ (INTERCONNECT SLICE_116/F1 SLICE_53/C1 (541:653:766)(541:653:766))
+ (INTERCONNECT SLICE_99/F0 SLICE_53/B1 (508:600:693)(508:600:693))
+ (INTERCONNECT SLICE_80/F0 SLICE_53/A1 (733:854:976)(733:854:976))
+ (INTERCONNECT SLICE_80/F0 SLICE_56/C0 (537:645:753)(537:645:753))
+ (INTERCONNECT SLICE_100/F1 SLICE_53/D0 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_79/F1 SLICE_53/C0 (984:1147:1311)(984:1147:1311))
+ (INTERCONNECT SLICE_79/F1 SLICE_56/A0 (1439:1636:1834)(1439:1636:1834))
+ (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (286:377:469)(286:377:469))
+ (INTERCONNECT SLICE_79/F1 SLICE_82/A0 (739:869:1000)(739:869:1000))
+ (INTERCONNECT SLICE_79/F1 SLICE_107/A0 (742:869:997)(742:869:997))
+ (INTERCONNECT SLICE_59/Q0 SLICE_53/A0 (1436:1622:1808)(1436:1622:1808))
+ (INTERCONNECT SLICE_59/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin
+ (2034:2232:2430)(2034:2232:2430))
(INTERCONNECT SLICE_53/F1 SLICE_53/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_53/F0 SLICE_53/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_53/Q0 SLICE_73/D1 (967:1065:1164)(967:1065:1164))
+ (INTERCONNECT SLICE_53/Q0 SLICE_116/B1 (1034:1188:1343)(1034:1188:1343))
(INTERCONNECT SLICE_53/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1411:1555:1700)
- (1411:1555:1700))
- (INTERCONNECT SLICE_53/Q1 SLICE_86/B0 (765:888:1011)(765:888:1011))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (977:1082:1188)
+ (977:1082:1188))
+ (INTERCONNECT SLICE_53/Q1 SLICE_54/C0 (1170:1341:1513)(1170:1341:1513))
(INTERCONNECT SLICE_53/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (1378:1511:1645)
- (1378:1511:1645))
- (INTERCONNECT SLICE_54/Q0 SLICE_54/A1 (733:853:974)(733:853:974))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1239:1370:1501)
+ (1239:1370:1501))
+ (INTERCONNECT SLICE_54/Q0 SLICE_54/D1 (1227:1351:1476)(1227:1351:1476))
(INTERCONNECT SLICE_54/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1530:1666:1802)
- (1530:1666:1802))
- (INTERCONNECT SLICE_86/F0 SLICE_54/D0 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_67/F1 SLICE_54/C0 (800:939:1079)(800:939:1079))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (980:1084:1188)
+ (980:1084:1188))
+ (INTERCONNECT SLICE_101/F0 SLICE_54/C1 (541:653:766)(541:653:766))
+ (INTERCONNECT SLICE_60/F0 SLICE_54/B1 (762:883:1004)(762:883:1004))
+ (INTERCONNECT SLICE_72/F1 SLICE_54/D0 (526:579:632)(526:579:632))
+ (INTERCONNECT SLICE_72/F1 SLICE_55/A1 (744:867:991)(744:867:991))
+ (INTERCONNECT SLICE_72/F1 SLICE_55/A0 (744:867:991)(744:867:991))
+ (INTERCONNECT SLICE_83/F0 SLICE_54/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT SLICE_83/F0 SLICE_55/D1 (526:579:632)(526:579:632))
(INTERCONNECT SLICE_54/F1 SLICE_54/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_54/F0 SLICE_54/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_54/Q1 SLICE_85/D0 (525:581:637)(525:581:637))
+ (INTERCONNECT SLICE_54/Q1 SLICE_59/D1 (1155:1277:1399)(1155:1277:1399))
(INTERCONNECT SLICE_54/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1272:1405:1538)
- (1272:1405:1538))
- (INTERCONNECT SLICE_77/F0 SLICE_55/D1 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_66/F0 SLICE_55/C1 (541:653:766)(541:653:766))
- (INTERCONNECT SLICE_87/F0 SLICE_55/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_76/F0 SLICE_55/A1 (730:848:967)(730:848:967))
- (INTERCONNECT SLICE_85/F0 SLICE_55/D0 (523:573:623)(523:573:623))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (642:709:776)
+ (642:709:776))
+ (INTERCONNECT SLICE_55/Q0 SLICE_55/C1 (802:947:1093)(802:947:1093))
+ (INTERCONNECT SLICE_55/Q0
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1235:1371:1508)
+ (1235:1371:1508))
+ (INTERCONNECT SLICE_79/F0 SLICE_55/C0 (541:653:766)(541:653:766))
+ (INTERCONNECT SLICE_59/F1 SLICE_55/B0 (1031:1183:1336)(1031:1183:1336))
(INTERCONNECT SLICE_55/F1 SLICE_55/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_55/F0 SLICE_55/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_55/Q0 SLICE_66/D0 (863:956:1049)(863:956:1049))
- (INTERCONNECT SLICE_55/Q0
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1344:1479:1615)
- (1344:1479:1615))
- (INTERCONNECT SLICE_55/Q1 SLICE_97/A0 (1005:1155:1306)(1005:1155:1306))
+ (INTERCONNECT SLICE_55/Q1 SLICE_84/A0 (733:853:974)(733:853:974))
(INTERCONNECT SLICE_55/Q1
- ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1276:1403:1531)
- (1276:1403:1531))
- (INTERCONNECT SLICE_107/F0 SLICE_56/D0 (863:956:1049)(863:956:1049))
- (INTERCONNECT SLICE_107/F0 SLICE_57/B0 (1506:1695:1884)(1506:1695:1884))
- (INTERCONNECT SLICE_56/F1 SLICE_56/B0 (508:600:693)(508:600:693))
- (INTERCONNECT SLICE_56/Q0 SLICE_56/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_56/Q0 SLICE_92/C1 (545:657:769)(545:657:769))
- (INTERCONNECT SLICE_56/Q0 SLICE_121/D1 (534:591:648)(534:591:648))
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1014:1116:1218)
+ (1014:1116:1218))
+ (INTERCONNECT SLICE_82/F0 SLICE_56/D1 (523:573:623)(523:573:623))
+ (INTERCONNECT SLICE_69/F1 SLICE_56/B1 (762:883:1004)(762:883:1004))
+ (INTERCONNECT SLICE_88/F1 SLICE_56/A1 (736:854:973)(736:854:973))
+ (INTERCONNECT SLICE_88/F1 SLICE_88/B0 (765:889:1013)(765:889:1013))
+ (INTERCONNECT SLICE_84/F0 SLICE_56/D0 (530:587:645)(530:587:645))
+ (INTERCONNECT SLICE_70/F1 SLICE_56/B0 (513:611:710)(513:611:710))
+ (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (767:894:1021)(767:894:1021))
+ (INTERCONNECT SLICE_70/F1 SLICE_79/B0 (770:894:1018)(770:894:1018))
+ (INTERCONNECT SLICE_56/F1 SLICE_56/DI1 (0:0:0)(0:0:0))
(INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_75/F1 SLICE_57/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (765:889:1013)(765:889:1013))
- (INTERCONNECT SLICE_57/Q0 SLICE_57/A0 (479:571:663)(479:571:663))
- (INTERCONNECT SLICE_57/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin
- (993:1105:1218)(993:1105:1218))
+ (INTERCONNECT SLICE_56/Q0 SLICE_108/D0 (523:578:633)(523:578:633))
+ (INTERCONNECT SLICE_56/Q0
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1411:1555:1700)
+ (1411:1555:1700))
+ (INTERCONNECT SLICE_56/Q1 SLICE_85/C0 (806:946:1086)(806:946:1086))
+ (INTERCONNECT SLICE_56/Q1
+ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1603:1765:1928)
+ (1603:1765:1928))
+ (INTERCONNECT SLICE_103/F0 SLICE_57/A1 (733:854:976)(733:854:976))
+ (INTERCONNECT SLICE_103/F0 SLICE_63/D1 (803:891:980)(803:891:980))
+ (INTERCONNECT SLICE_103/F0 SLICE_63/D0 (803:891:980)(803:891:980))
+ (INTERCONNECT SLICE_103/F0 SLICE_71/A1 (1340:1529:1718)(1340:1529:1718))
+ (INTERCONNECT SLICE_97/F0 SLICE_57/D0 (536:594:652)(536:594:652))
+ (INTERCONNECT SLICE_97/F0 SLICE_58/D0 (863:956:1049)(863:956:1049))
+ (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (277:356:436)(277:356:436))
(INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_82/Q0 SLICE_58/C0 (1269:1444:1620)(1269:1444:1620))
- (INTERCONNECT SLICE_63/F0 SLICE_58/B0 (772:897:1023)(772:897:1023))
+ (INTERCONNECT SLICE_58/Q0 SLICE_58/A0 (479:571:663)(479:571:663))
+ (INTERCONNECT SLICE_58/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin
+ (1495:1654:1814)(1495:1654:1814))
(INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0))
- (INTERCONNECT SLICE_76/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/C1 (544:659:775)
- (544:659:775))
- (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_86/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/A1 (738:862:987)
- (738:862:987))
- (INTERCONNECT SLICE_86/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/A0 (738:862:987)
- (738:862:987))
- (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_110/F0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/B0 (768:889:1010)
- (768:889:1010))
- (INTERCONNECT SLICE_110/F0 SLICE_91/B1 (775:903:1032)(775:903:1032))
- (INTERCONNECT SLICE_80/Q1 SLICE_60/D1 (1436:1566:1696)(1436:1566:1696))
- (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_60/F1 SLICE_81/D0 (897:989:1081)(897:989:1081))
- (INTERCONNECT SLICE_74/F0 SLICE_60/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_74/F0 SLICE_61/C1 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_60/F0 SLICE_94/D1 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_61/F1 SLICE_61/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_61/F0 SLICE_94/C0 (534:639:744)(534:639:744))
- (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (545:658:771)(545:658:771))
- (INTERCONNECT SLICE_62/F1 SLICE_106/A1 (479:572:665)(479:572:665))
- (INTERCONNECT SLICE_62/F1 SLICE_106/A0 (744:867:991)(744:867:991))
- (INTERCONNECT SLICE_62/F0 SLICE_63/A0 (1326:1511:1696)(1326:1511:1696))
- (INTERCONNECT SLICE_95/F0 SLICE_63/C1 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_105/F0 SLICE_63/A1 (1174:1336:1498)(1174:1336:1498))
+ (INTERCONNECT SLICE_84/F1 SLICE_59/C1 (919:1067:1215)(919:1067:1215))
+ (INTERCONNECT SLICE_84/F1 SLICE_60/D0 (544:605:667)(544:605:667))
+ (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_84/F1 SLICE_101/D0 (544:605:667)(544:605:667))
+ (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (1113:1271:1429)(1113:1271:1429))
+ (INTERCONNECT SLICE_83/F1 SLICE_83/A0 (733:854:976)(733:854:976))
+ (INTERCONNECT SLICE_83/F1 SLICE_99/A0 (1076:1237:1399)(1076:1237:1399))
+ (INTERCONNECT SLICE_71/F1 SLICE_59/D0 (266:290:315)(266:290:315))
+ (INTERCONNECT SLICE_63/F0 SLICE_59/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0))
+ (INTERCONNECT SLICE_100/F0 SLICE_60/A1 (1174:1336:1498)(1174:1336:1498))
+ (INTERCONNECT SLICE_98/F0 SLICE_60/A0 (999:1149:1299)(999:1149:1299))
+ (INTERCONNECT SLICE_65/F1 SLICE_61/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_62/F0 SLICE_96/A0 (999:1149:1299)(999:1149:1299))
+ (INTERCONNECT SLICE_80/F1 SLICE_63/B1 (775:914:1053)(775:914:1053))
+ (INTERCONNECT SLICE_80/F1 SLICE_65/C0 (810:970:1131)(810:970:1131))
+ (INTERCONNECT SLICE_80/F1 SLICE_67/B1 (775:914:1053)(775:914:1053))
+ (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (769:899:1029)(769:899:1029))
+ (INTERCONNECT SLICE_80/F1 SLICE_85/A1 (742:872:1003)(742:872:1003))
+ (INTERCONNECT SLICE_80/F1 SLICE_101/C0 (1136:1325:1515)(1136:1325:1515))
+ (INTERCONNECT SLICE_80/F1 SLICE_107/A1 (747:879:1011)(747:879:1011))
(INTERCONNECT SLICE_63/F1 SLICE_63/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_119/F0 SLICE_64/D1 (526:579:632)(526:579:632))
- (INTERCONNECT SLICE_119/F0 SLICE_100/A0 (733:854:976)(733:854:976))
- (INTERCONNECT Din\[6\]_I/PADDI SLICE_64/C1 (2750:3044:3338)(2750:3044:3338))
- (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/C0 (2750:3044:3338)(2750:3044:3338))
- (INTERCONNECT Din\[6\]_I/PADDI SLICE_100/C1 (2380:2642:2904)(2380:2642:2904))
- (INTERCONNECT Din\[6\]_I/PADDI SLICE_119/C1 (2380:2642:2904)(2380:2642:2904))
- (INTERCONNECT Din\[6\]_I/PADDI SLICE_120/D0 (3538:3845:4153)(3538:3845:4153))
- (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (4553:4938:5324)(4553:4938:5324))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_64/C1 (2385:2647:2910)(2385:2647:2910))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_73/A0 (2922:3232:3542)(2922:3232:3542))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/C1 (2755:3049:3344)(2755:3049:3344))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/C0 (2755:3049:3344)(2755:3049:3344))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_106/A0 (2922:3232:3542)(2922:3232:3542))
+ (INTERCONNECT Din\[6\]_I/PADDI SLICE_115/C0 (2749:3043:3337)(2749:3043:3337))
+ (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (4065:4422:4779)(4065:4422:4779))
(INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (424:441:459)(424:441:459))
- (INTERCONNECT SLICE_64/F0 SLICE_80/C0 (868:1015:1163)(868:1015:1163))
- (INTERCONNECT SLICE_110/F1 SLICE_65/C1 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_70/F1 SLICE_65/A1 (730:848:967)(730:848:967))
- (INTERCONNECT SLICE_70/F0 SLICE_65/D0 (269:296:324)(269:296:324))
- (INTERCONNECT SLICE_70/F0 SLICE_70/D1 (523:579:635)(523:579:635))
- (INTERCONNECT SLICE_65/F1 SLICE_65/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_67/F0 SLICE_65/A0 (733:854:976)(733:854:976))
- (INTERCONNECT SLICE_67/F0 SLICE_67/D1 (523:579:635)(523:579:635))
- (INTERCONNECT SLICE_101/F0 SLICE_66/A0 (999:1149:1299)(999:1149:1299))
- (INTERCONNECT SLICE_104/F0 SLICE_68/C0 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_68/F1 SLICE_105/C1 (803:945:1088)(803:945:1088))
- (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_69/F1 SLICE_91/C0 (534:639:744)(534:639:744))
- (INTERCONNECT SLICE_89/F1 SLICE_70/C1 (537:645:753)(537:645:753))
- (INTERCONNECT SLICE_89/F1 SLICE_89/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_113/F1 SLICE_71/D1 (269:296:324)(269:296:324))
- (INTERCONNECT SLICE_113/F1 SLICE_73/C1 (539:653:767)(539:653:767))
- (INTERCONNECT SLICE_113/F1 SLICE_86/A1 (738:862:987)(738:862:987))
+ (INTERCONNECT SLICE_65/F0 SLICE_65/C1 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_66/F0 SLICE_86/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (476:566:656)(476:566:656))
+ (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_67/A0 (1191:1357:1524)
+ (1191:1357:1524))
+ (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_87/D0 (1672:1839:2007)
+ (1672:1839:2007))
+ (INTERCONNECT SLICE_78/F1 SLICE_68/C1 (544:659:775)(544:659:775))
+ (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT SLICE_114/F0 SLICE_68/A1 (1067:1225:1383)(1067:1225:1383))
+ (INTERCONNECT SLICE_68/F1 SLICE_92/B1 (772:897:1023)(772:897:1023))
+ (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_108/F0 SLICE_69/A1 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_70/F0 SLICE_108/A0 (730:848:967)(730:848:967))
(INTERCONNECT SLICE_71/F0 SLICE_71/C1 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_95/F1 SLICE_71/B1 (770:894:1018)(770:894:1018))
- (INTERCONNECT SLICE_95/F1 SLICE_86/B1 (777:908:1040)(777:908:1040))
- (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (282:367:453)(282:367:453))
- (INTERCONNECT SLICE_91/F1 SLICE_71/A1 (479:572:665)(479:572:665))
- (INTERCONNECT SLICE_91/F1 SLICE_91/A0 (733:854:976)(733:854:976))
- (INTERCONNECT SLICE_78/F1 SLICE_72/C1 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_72/F1 SLICE_83/B0 (765:883:1001)(765:883:1001))
- (INTERCONNECT SLICE_73/F0 SLICE_73/B1 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_74/F1 SLICE_78/D1 (533:593:654)(533:593:654))
- (INTERCONNECT SLICE_79/F1 SLICE_78/A1 (735:859:984)(735:859:984))
- (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (282:367:453)(282:367:453))
- (INTERCONNECT SLICE_79/F1 SLICE_88/A1 (745:874:1003)(745:874:1003))
- (INTERCONNECT SLICE_78/F0 nRRAS_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693))
- (INTERCONNECT SLICE_80/F1 SLICE_80/D0 (520:573:626)(520:573:626))
- (INTERCONNECT SLICE_90/F0 SLICE_81/C0 (531:639:747)(531:639:747))
- (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (765:889:1013)(765:889:1013))
- (INTERCONNECT SLICE_81/F1 SLICE_83/D0 (523:579:635)(523:579:635))
- (INTERCONNECT SLICE_108/F0 SLICE_81/A0 (1442:1633:1825)(1442:1633:1825))
- (INTERCONNECT SLICE_108/F0 SLICE_83/A0 (1442:1633:1825)(1442:1633:1825))
- (INTERCONNECT SLICE_81/F0 nRWE_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296))
- (INTERCONNECT SLICE_82/F0 SLICE_82/CE (539:596:653)(539:596:653))
- (INTERCONNECT SLICE_83/F1 SLICE_83/C0 (280:362:445)(280:362:445))
- (INTERCONNECT SLICE_83/F1 SLICE_94/C1 (917:1077:1237)(917:1077:1237))
- (INTERCONNECT SLICE_83/F0 nRCS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
- (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_84/D1 (975:1075:1176)(975:1075:1176))
- (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_84/C1 (727:855:984)(727:855:984))
- (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_84/B1 (1217:1385:1554)(1217:1385:1554))
- (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_84/A1 (1253:1427:1601)(1253:1427:1601))
- (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_84/D0 (1514:1658:1802)(1514:1658:1802))
- (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_84/C0 (1525:1724:1923)(1525:1724:1923))
- (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (508:600:693)(508:600:693))
- (INTERCONNECT SLICE_93/F0 SLICE_84/A0 (999:1149:1299)(999:1149:1299))
- (INTERCONNECT SLICE_102/F1 SLICE_85/C1 (534:645:756)(534:645:756))
- (INTERCONNECT SLICE_102/F1 SLICE_101/A0 (744:867:991)(744:867:991))
- (INTERCONNECT SLICE_102/F1 SLICE_102/A0 (744:867:991)(744:867:991))
- (INTERCONNECT SLICE_101/F1 SLICE_85/A1 (479:572:665)(479:572:665))
- (INTERCONNECT SLICE_101/F1 SLICE_101/B0 (511:606:702)(511:606:702))
- (INTERCONNECT SLICE_89/F0 SLICE_85/B0 (772:897:1023)(772:897:1023))
- (INTERCONNECT SLICE_85/F1 SLICE_85/A0 (733:854:976)(733:854:976))
- (INTERCONNECT SLICE_85/F1 SLICE_86/A0 (1070:1231:1392)(1070:1231:1392))
- (INTERCONNECT SLICE_88/F0 RA\[10\]_MGIOL/LSR (1815:1978:2141)(1815:1978:2141))
- (INTERCONNECT SLICE_90/F1 SLICE_90/B0 (508:600:693)(508:600:693))
- (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_92/B0 (1328:1501:1675)
- (1328:1501:1675))
- (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_104/A0 (1660:1862:2065)
- (1660:1862:2065))
- (INTERCONNECT SLICE_92/F1 SLICE_92/A0 (730:848:967)(730:848:967))
- (INTERCONNECT SLICE_93/F1 SLICE_93/D0 (520:573:626)(520:573:626))
- (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_93/C0 (1174:1343:1512)(1174:1343:1512))
- (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_93/B0 (2284:2517:2751)(2284:2517:2751))
- (INTERCONNECT SLICE_114/F0 SLICE_93/A0 (999:1149:1299)(999:1149:1299))
- (INTERCONNECT SLICE_94/F0 SLICE_94/A1 (476:566:656)(476:566:656))
- (INTERCONNECT SLICE_94/F1 nRCAS_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192))
- (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_72/F0 SLICE_72/C1 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_75/F0 SLICE_73/C0 (802:947:1093)(802:947:1093))
+ (INTERCONNECT SLICE_75/F0 SLICE_74/C0 (536:647:758)(536:647:758))
+ (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT SLICE_73/F1 SLICE_106/B0 (511:606:702)(511:606:702))
+ (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_75/D1 (1150:1262:1375)(1150:1262:1375))
+ (INTERCONNECT SLICE_89/F0 SLICE_75/B1 (765:883:1001)(765:883:1001))
+ (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_75/A1 (1290:1460:1631)(1290:1460:1631))
+ (INTERCONNECT SLICE_76/F1 SLICE_76/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_98/F1 SLICE_77/C1 (534:645:756)(534:645:756))
+ (INTERCONNECT SLICE_98/F1 SLICE_79/D0 (526:579:632)(526:579:632))
+ (INTERCONNECT SLICE_85/F0 SLICE_77/D0 (857:949:1042)(857:949:1042))
+ (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (1206:1370:1535)(1206:1370:1535))
+ (INTERCONNECT SLICE_88/F0 SLICE_77/A0 (1067:1225:1383)(1067:1225:1383))
+ (INTERCONNECT SLICE_78/F0 RA\[10\]_MGIOL/LSR (1558:1705:1853)(1558:1705:1853))
+ (INTERCONNECT SLICE_105/F1 SLICE_81/D1 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_92/F0 SLICE_81/C1 (537:645:753)(537:645:753))
+ (INTERCONNECT SLICE_92/F0 SLICE_92/C1 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_117/F1 SLICE_81/B1 (768:889:1010)(768:889:1010))
+ (INTERCONNECT SLICE_117/F1 SLICE_92/A1 (479:572:665)(479:572:665))
+ (INTERCONNECT SLICE_81/F0 SLICE_81/A1 (476:566:656)(476:566:656))
+ (INTERCONNECT SLICE_90/F0 SLICE_81/B0 (765:889:1013)(765:889:1013))
+ (INTERCONNECT SLICE_90/F0 SLICE_90/C1 (280:362:445)(280:362:445))
+ (INTERCONNECT SLICE_81/F1 nRCS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599))
+ (INTERCONNECT SLICE_82/F1 SLICE_82/C0 (531:639:747)(531:639:747))
+ (INTERCONNECT SLICE_94/F0 SLICE_84/D0 (520:573:626)(520:573:626))
+ (INTERCONNECT SLICE_86/F0 SLICE_85/B0 (765:883:1001)(765:883:1001))
+ (INTERCONNECT SLICE_85/F1 SLICE_85/A0 (730:848:967)(730:848:967))
+ (INTERCONNECT SLICE_87/F1 SLICE_87/B0 (762:883:1004)(762:883:1004))
+ (INTERCONNECT SLICE_109/F0 SLICE_89/D0 (530:587:645)(530:587:645))
+ (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_89/C0 (1174:1343:1512)(1174:1343:1512))
+ (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_89/B0 (2284:2517:2751)(2284:2517:2751))
+ (INTERCONNECT SLICE_89/F1 SLICE_89/A0 (1430:1615:1801)(1430:1615:1801))
+ (INTERCONNECT SLICE_90/F1 nRRAS_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120))
+ (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_92/F1 nRWE_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
+ (INTERCONNECT SLICE_93/F1 SLICE_93/C0 (277:356:436)(277:356:436))
+ (INTERCONNECT SLICE_94/F1 SLICE_94/B0 (508:600:693)(508:600:693))
+ (INTERCONNECT SLICE_95/F1 SLICE_95/B0 (508:600:693)(508:600:693))
+ (INTERCONNECT SLICE_117/F0 SLICE_96/D1 (520:573:626)(520:573:626))
(INTERCONNECT SLICE_96/F1 SLICE_96/B0 (762:883:1004)(762:883:1004))
- (INTERCONNECT SLICE_98/F1 SLICE_98/C0 (277:356:436)(277:356:436))
- (INTERCONNECT Din\[2\]_I/PADDI SLICE_99/D0 (1700:1823:1947)(1700:1823:1947))
- (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/B0 (2312:2535:2759)(2312:2535:2759))
- (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (3765:4075:4386)(3765:4075:4386))
- (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565))
- (INTERCONNECT SLICE_99/F1 SLICE_99/B0 (508:600:693)(508:600:693))
- (INTERCONNECT Din\[7\]_I/PADDI SLICE_100/A1 (2956:3261:3567)(2956:3261:3567))
- (INTERCONNECT Din\[7\]_I/PADDI SLICE_112/A1 (2956:3261:3567)(2956:3261:3567))
- (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/B1 (3315:3658:4001)(3315:3658:4001))
- (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (4110:4464:4819)(4110:4464:4819))
- (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459))
- (INTERCONNECT SLICE_112/F0 SLICE_100/D0 (266:290:315)(266:290:315))
- (INTERCONNECT SLICE_103/F1 SLICE_103/C0 (277:356:436)(277:356:436))
- (INTERCONNECT SLICE_111/F0 RDQMH_I/PADDO (1020:1147:1274)(1020:1147:1274))
- (INTERCONNECT SLICE_111/F1 RDQML_I/PADDO (1263:1400:1537)(1263:1400:1537))
- (INTERCONNECT SLICE_114/F1 RA\[6\]_I/PADDO (1433:1627:1822)(1433:1627:1822))
- (INTERCONNECT SLICE_115/F0 RA\[8\]_I/PADDO (1295:1474:1653)(1295:1474:1653))
- (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (1362:1545:1728)(1362:1545:1728))
- (INTERCONNECT SLICE_116/F0 RA\[0\]_I/PADDO (1106:1265:1425)(1106:1265:1425))
- (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (1362:1545:1728)(1362:1545:1728))
- (INTERCONNECT SLICE_117/F0 RA\[1\]_I/PADDO (1106:1265:1425)(1106:1265:1425))
- (INTERCONNECT SLICE_117/F1 RA\[5\]_I/PADDO (1362:1545:1728)(1362:1545:1728))
- (INTERCONNECT SLICE_118/F0 RA\[2\]_I/PADDO (1036:1188:1340)(1036:1188:1340))
- (INTERCONNECT SLICE_118/F1 RA\[4\]_I/PADDO (1400:1583:1767)(1400:1583:1767))
- (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/B1 (2108:2330:2553)(2108:2330:2553))
- (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
- (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (1783:1940:2098)(1783:1940:2098))
- (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_122/D1 (1406:1542:1678)
- (1406:1542:1678))
+ (INTERCONNECT SLICE_96/F0 nRCAS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
+ (INTERCONNECT SLICE_102/F0 RDQMH_I/PADDO (1346:1504:1662)(1346:1504:1662))
+ (INTERCONNECT SLICE_102/F1 RDQML_I/PADDO (1367:1504:1642)(1367:1504:1642))
+ (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_108/C1 (986:1141:1297)
+ (986:1141:1297))
+ (INTERCONNECT SLICE_109/F1 RA\[3\]_I/PADDO (1916:2133:2351)(1916:2133:2351))
+ (INTERCONNECT SLICE_110/F0 RA\[9\]_I/PADDO (1111:1225:1339)(1111:1225:1339))
+ (INTERCONNECT SLICE_110/F1 RA\[8\]_I/PADDO (1929:2148:2367)(1929:2148:2367))
+ (INTERCONNECT SLICE_111/F0 RA\[7\]_I/PADDO (1834:2056:2279)(1834:2056:2279))
+ (INTERCONNECT SLICE_111/F1 RA\[0\]_I/PADDO (1362:1545:1728)(1362:1545:1728))
+ (INTERCONNECT SLICE_112/F0 RA\[6\]_I/PADDO (1778:2009:2240)(1778:2009:2240))
+ (INTERCONNECT SLICE_112/F1 RA\[1\]_I/PADDO (1470:1661:1852)(1470:1661:1852))
+ (INTERCONNECT SLICE_113/F0 RA\[5\]_I/PADDO (1726:1940:2155)(1726:1940:2155))
+ (INTERCONNECT SLICE_113/F1 RA\[2\]_I/PADDO (1797:2023:2249)(1797:2023:2249))
+ (INTERCONNECT SLICE_114/F1 RA\[10\]_MGIOL/OPOS (1212:1320:1429)(1212:1320:1429))
+ (INTERCONNECT CROW\[0\]_I/PADDI SLICE_115/A1 (2230:2452:2674)(2230:2452:2674))
+ (INTERCONNECT SLICE_115/F0 RA\[11\]_MGIOL/OPOS (1986:2148:2310)(1986:2148:2310))
+ (INTERCONNECT SLICE_115/F1 RBA\[0\]_MGIOL/OPOS (1995:2157:2319)(1995:2157:2319))
(INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2674:2873:3073)(2674:2873:3073))
(INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (30:36:43)(30:36:43))
(INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (9:36:63)(9:36:63))
(INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (9:36:63)(9:36:63))
(INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (30:36:43)(30:36:43))
+ (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (25:77:129)(25:77:129))
(INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (9:36:63)(9:36:63))
- (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (3029:3288:3547)(3029:3288:3547))
+ (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (3098:3322:3547)(3098:3322:3547))
(INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (30:36:43)(30:36:43))
- (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2615:2816:3018)(2615:2816:3018))
+ (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2583:2787:2992)(2583:2787:2992))
(INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (30:36:43)(30:36:43))
(INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2219:2392:2565)(2219:2392:2565))
(INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (30:36:43)(30:36:43))
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo
index 88ac701..501ed17 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo
@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd
-// Netlist created on Thu Sep 21 05:39:45 2023
-// Netlist written on Thu Sep 21 05:40:12 2023
+// Netlist created on Thu Oct 19 23:50:56 2023
+// Netlist written on Thu Oct 19 23:51:19 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4
@@ -11,7 +11,8 @@
`timescale 1 ns / 1 ps
module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
- RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML );
+ RD, nRCS, RCLK, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH,
+ RDQML );
input PHI2;
input [9:0] MAin;
input [1:0] CROW;
@@ -21,7 +22,7 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
output LED;
output [1:0] RBA;
output [11:0] RA;
- output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
+ output nRCS, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
inout [7:0] RD;
wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] ,
\FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] ,
@@ -31,70 +32,66 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
\FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] ,
\FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] ,
\FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] ,
- un1_CmdEnable20_0_0_o3, \MAin_c[1] , ADSubmitted, N_524, CmdEnable17,
- CmdEnable16, ADSubmitted_r_0_0, PHI2_c, N_594, N_518, C1Submitted,
- C1Submitted_RNO, nCCAS_c, nCCAS_c_i, CASr, CASr2, CO0, \S[1] ,
- N_123_i, RASr2, N_345_i, N_593, CmdEnable, CmdEnable_0_sqmuxa,
- un1_CmdEnable20_i, CmdEnable_s, CmdLEDEN_4_u_i_0_a3_0_0, \Din_c[1] ,
- CmdLEDEN, CmdValid_2_i_o2_1_o3, LEDEN, CmdLEDEN_4_u_i_0_0, N_531,
- N_40_i, XOR8MEG18, CmdUFMShift, CmdUFMShift_3, CmdUFMWrite,
- \Din_c[0] , N_462, CmdUFMWrite_3, N_213, \Din_c[5] , \Din_c[3] ,
- \Din_c[4] , CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast,
- CmdValid_fast, Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0_0, N_38_i,
- nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, nRCS_9_u_i_0_o2_1_RNIL2K71,
- \IS[0] , N_351_i_i, N_267, \IS[1] , \IS[2] , N_348_i_i, N_344_i,
- N_360_i, \IS[3] , N_350_i_i, \IS_i[0] , N_581, InitReady3_0_a3_1,
- InitReady3, InitReady, N_757_0, \wb_dato[1] , CmdValid_RNIOOBE2,
- LEDEN_6_i_m2_i_m2, LEDENe_0, \CROW_c[0] , Ready_fast, PHI2r2, PHI2r,
- \RBAd_0[0] , PHI2r3, CBR, nCRAS_c_i_0, RASr, LED_c, nRowColSel,
- \RowA[3] , \MAin_c[3] , RASr3, \RA_c[3] , N_216, Ready,
- RCKEEN_8_u_0_0_0, RCKEEN_8_u_0_1_0, RCKEEN_8, RCKEEN, RCKE_2, RCKE_c,
- m3_0_a2_0, Ready_0_sqmuxa_0_a2_4_a3_2, N_347, N_758_0, Ready_0_sqmuxa,
- N_759_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , \RowA[1] ,
- \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \MAin_c[5] ,
- \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , \RowA[4] , \RowA[5] ,
- \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , \RowA[6] ,
- \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] ,
- \RowA[8] , \RowA[9] , XOR8MEG, N_441, XOR8MEG_3_u_0_0_a3_0_2,
- XOR8MEG_3, g1_0, N_4, n8MEGENe_1_0, n8MEGENe_0, CASr3, N_248_i_1_1,
- nRowColSel_0_0_0, nRRAS_0_sqmuxa, N_417, N_382, \wb_adr_5_i_0_0[1] ,
- N_416, \wb_adr_5_i_0_3[0] , N_383, \wb_adr_5_i_0_0[0] , N_423,
- N_229_i, N_230_i, un1_wb_rst14_i_0, \wb_adr[0] , \wb_adr[1] ,
- \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , N_210,
- \wb_adr[4] , N_385, N_384, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] ,
- N_386, \wb_adr[7] , N_214, N_471_3, wb_cyc_stb_4_iv_0_a3_0_0, N_471_2,
- N_471, un1_PHI2r3, wb_cyc_stb_4, N_178, wb_rst10, wb_cyc_stb, N_207,
- \wb_dati_5_1_iv_0_1[1] , N_578, wb_we, N_576,
- \wb_dati_5_0_iv_0_a3_1[0] , \wb_dati_5[1] , \wb_dati_5[0] ,
- \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_i_i_1[3] , N_579,
- \wb_dati_5_1_iv_i_i_0[3] , \wb_dati_5_1_iv_i_i_a3_1[3] , N_361,
- \wb_dati_5_1_iv_i_i[3] , \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] ,
- \wb_dati[4] , \wb_dati_5_1_iv_0_1[4] , \wb_dati_5_1_iv_0_0[4] ,
- \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , N_484,
- \wb_dati_5_1_iv_0_0[7] , N_488, N_486, \wb_dati_5_1_iv_0_1[6] ,
- \wb_dati_5[7] , \wb_dati_5[6] , \wb_dati[6] , \wb_dati[7] , N_92_i,
- N_31_i, wb_req, wb_reqe_0, N_515, wb_rst, wb_rste_0, CmdUFMData,
- wb_we_0_i_0_1, N_231_i, N_217, N_479, N_209, CBR_fast,
- nRCAS_0_sqmuxa_1, N_408, N_248_i_sx, un1_nRCAS_6_sqmuxa_i_0_0,
- nRCAS_r_i_0_o2_0_0, N_599, N_407, N_427, wb_we_0_i_0_a3_0_0,
- wb_we_0_i_0_0, N_539, \Din_c[6] , un1_CmdEnable20_0_0_0,
- \wb_adr_5_i_0_a3_0_1[0] , N_424, N_542, \wb_adr_5_i_0_1[0] , N_208,
- \wb_dati_5_1_iv_0_a3_0_1[7] , \ufmefb/g0_0_a3_2 , N_226,
- \wb_dati_5_1_iv_0_a3_0_1[1] , N_477, N_236, N_502, N_596, N_536,
- N_412, N_522, nRCS_9_u_i_0_o3, \wb_dati_5_1_iv_i_i_a3_3_0[3] ,
- un1_nRCAS_6_sqmuxa_i_0_0_o2_0, N_221, N_246_i,
- un1_CmdEnable20_0_0_a3_1_1, nRWE_s_i_0_tz_0, N_590, N_595, N_49_i,
- CmdUFMData_1_sqmuxa, N_248_i_1_0, N_247_i, \Bank[4] , \Bank[3] ,
- \Bank[5] , \Bank[1] , \Bank[6] , \Bank[7] , un1_CmdEnable20_0_0_o3_11,
- un1_CmdEnable20_0_0_o3_10, N_514, N_537, N_472, N_473, RA10s_i,
- nRWE_s_i_0_a3_1_0, wb_ack, wb_cyc_stb_2_sqmuxa_i_a3_0,
- un1_CmdEnable20_0_0_o3_4, \Bank[2] , \Bank[0] ,
- un1_CmdEnable20_0_0_o3_3, N_248_i_1, N_248_i, N_404, N_511,
- wb_cyc_stb_4_iv_0_a3_0_2_0, \Din_c[2] , N_505, \Din_c[7] ,
- XOR8MEG_3_u_0_0_0_a2, G_4_0_a3_0, RDQMH_c, RDQML_c, \RA_c[6] ,
- \RA_c[8] , \RA_c[9] , \RA_c[0] , \RA_c[7] , \RA_c[1] , \RA_c[5] ,
- \RA_c[2] , \RA_c[4] , \CROW_c[1] , RA11d_0, \RBAd_0[1] , \wb_dato[0] ,
- \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] ,
+ \MAin_c[1] , N_294, ADSubmitted, CmdEnable17, CmdEnable16, N_22_i,
+ ADSubmitted_r_0, PHI2_c, N_393, N_374, C1Submitted, C1Submitted_RNO,
+ nCCAS_c, nCCAS_c_i, CASr, CASr2, RASr2, \IS[3] , CO0, \S[1] , N_253_i,
+ Ready_0_sqmuxa_0_a3_2, un1_CmdEnable20_0_0, un1_CmdEnable20_0_a2_1_0,
+ CmdEnable, un1_CmdEnable20_i, CmdEnable_0_sqmuxa, CmdEnable_s,
+ CmdLEDEN_4_u_i_a2_0_0, N_140, CmdLEDEN, \Din_c[1] , CmdLEDEN_4_u_i_0,
+ N_380, LEDEN, N_284_i, XOR8MEG18, \Din_c[0] , CmdUFMData_1_sqmuxa,
+ VCC, CmdUFMData, GND, \Din_c[4] , \Din_c[7] , CmdUFMShift,
+ CmdUFMShift_3, CmdUFMWrite, N_279, CmdUFMWrite_3, N_134, \Din_c[5] ,
+ \Din_c[3] , XOR8MEG18_i, CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast,
+ CmdValid_fast, Cmdn8MEGEN, Cmdn8MEGEN_4_u_i_0, n8MEGEN, N_285_i,
+ nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, \CROW_c[1] , Ready_fast,
+ \Din_c[2] , N_381, FWEr_fast, \RBAd_0[1] , Ready, N_43, \IS[0] ,
+ N_60_i_i, N_244_i, \IS[1] , \IS[2] , N_57_i_i, N_53_i, N_58_i_i, N_49,
+ N_142, InitReady3_0_a2_2, InitReady3, InitReady, N_586_0,
+ \wb_dato[1] , LEDEN_6_i_m2, CmdValid_RNITBH02, LEDENe_0, nRowColSel,
+ \MAin_c[4] , \RowA[4] , \Bank[6] , \Bank[4] , \Bank[5] , \Bank[7] ,
+ PHI2r2, PHI2r, un1_ADWR_i_o2_11, \RA_c[4] , PHI2r3, CBR, nCRAS_c_i_0,
+ RASr, LED_c, N_133, \wb_dati_5_1_iv_0_a2_1_1[7] , RASr3,
+ wb_cyc_stb_2_sqmuxa_i_a2_3_4, N_41, RCKEEN_8_u_1, RCKEEN_8_u_0_0,
+ RCKEEN_8, RCKEEN, RCKE_c, RCKE_2, nRWE_0io_RNO_2, N_248, N_587_0,
+ Ready_0_sqmuxa, N_588_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] ,
+ \RowA[1] , \MAin_c[3] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] ,
+ \RowA[2] , \RowA[3] , \MAin_c[5] , \RowAd_0[5] , \RowAd_0[4] ,
+ \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] ,
+ \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] ,
+ \RowAd_0[8] , \RowA[8] , \RowA[9] , CBR_fast, nRCAS_0_sqmuxa_1,
+ XOR8MEG, N_274, XOR8MEG_3_u_0_a2_0_2, XOR8MEG_3, N_4, g1_0,
+ n8MEGENe_1_0, n8MEGENe_0, CASr3, N_255, nRowColSel_0_0,
+ nRRAS_0_sqmuxa, N_384, \wb_adr_5_i_i_0[1] , \wb_adr_5_i_i_5[0] ,
+ N_313, N_367, N_282, N_283, N_122, \wb_adr[0] , \wb_adr[1] ,
+ \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , N_132,
+ \wb_adr[4] , N_80, N_81, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] ,
+ \wb_adr_5_i_m2_0[6] , \wb_adr[7] , wb_req, N_330_4, N_330, un1_PHI2r3,
+ wb_cyc_stb_4, N_103, wb_rst10, wb_cyc_stb, N_226, N_302, N_303, N_233,
+ \wb_dati_5_0_iv_0_a2_0[0] , N_383, wb_we, \wb_dati_5[1] ,
+ \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , \wb_dati[2] , N_341,
+ \wb_dati_5_1_iv_0_1[3] , N_335, \wb_dati_5_1_iv_0_o2_0[5] ,
+ \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[3] , \wb_dati[4] ,
+ \wb_dati_5_1_iv_0_2[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] ,
+ \wb_dati_5[4] , \wb_dati[5] , N_345, \wb_dati_5_1_iv_0_1[7] , N_375,
+ \wb_dati_5_1_iv_0_0[6] , N_348_2, \wb_dati_5[7] , \wb_dati_5[6] ,
+ \wb_dati[6] , \wb_dati[7] , N_131, N_94_i, N_34_i, wb_reqe_0, wb_rst,
+ wb_rste_0, N_362, N_394, N_353, wb_we_0_0_0_0, wb_we_0_0_0, N_129,
+ N_223, N_428_tz, N_39, N_125, N_356, \Din_c[6] ,
+ \wb_adr_5_i_i_a2_0[1] , \wb_adr_5_i_i_a2_3_0[0] ,
+ \wb_adr_5_i_i_1_0_tz_0[0] , g0_0_a3_1, wb_ack, IS_0_sqmuxa_0_o2,
+ nRWE_0io_RNO_1, nRWE_0io_RNO_0, N_220, \wb_dati_5_1_iv_0_0[7] ,
+ \wb_dati_5_1_iv_0_a2_3_0[7] , N_143, N_137, N_382,
+ un1_CmdEnable20_0_a2_3_0, \Bank[3] , un1_ADWR_i_o2_10, \Bank[1] ,
+ N_378, \wb_adr_5_i_i_a2_6_0[0] , \wb_adr_5_i_i_1[0] , N_314, N_315,
+ RA10s_i, nRCS_0io_RNO_0, N_37_i_1, N_28_i_1, nRCS_9_u_i_0,
+ nRCS_9_u_i_0_0, N_28_i, N_376, \wb_dati_5_1_iv_0_a2_1[6] ,
+ \wb_adr_5_i_i_1_0[0] , N_307, N_295, un1_ADWR_i_o2_3, \Bank[2] ,
+ \Bank[0] , un1_ADWR_i_o2_4, N_25_i, wb_cyc_stb_2_sqmuxa_i_a2_3_3,
+ N_37_i, N_371, N_141, G_8_0_a3_0_0, nRCAS_0io_RNO_1, N_242_i_1,
+ N_242_i, RDQMH_c, RDQML_c, \wb_dato[0] , \RA_c[3] , \RA_c[9] ,
+ \RA_c[8] , \RA_c[7] , \RA_c[0] , \RA_c[6] , \RA_c[1] , \RA_c[5] ,
+ \RA_c[2] , \IS_i[0] , \CROW_c[0] , RA11d_0, \RBAd_0[0] , \RD_in[0] ,
+ \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, RCLKout_c, nRCS_c, \RD_in[7] ,
\WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] ,
\WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] ,
\WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI;
@@ -127,352 +124,329 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ),
.DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ),
.Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
- SLICE_10 SLICE_10( .D1(un1_CmdEnable20_0_0_o3), .A1(\MAin_c[1] ),
- .D0(ADSubmitted), .C0(N_524), .B0(CmdEnable17), .A0(CmdEnable16),
- .DI0(ADSubmitted_r_0_0), .CLK(PHI2_c), .F0(ADSubmitted_r_0_0),
- .Q0(ADSubmitted), .F1(N_524));
- SLICE_11 SLICE_11( .D1(N_594), .C1(N_518), .B1(\MAin_c[1] ),
- .A1(un1_CmdEnable20_0_0_o3), .D0(C1Submitted), .C0(CmdEnable16),
- .B0(\MAin_c[1] ), .A0(un1_CmdEnable20_0_0_o3), .DI0(C1Submitted_RNO),
- .CLK(PHI2_c), .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
- SLICE_12 SLICE_12( .C0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c),
+ SLICE_10 SLICE_10( .C1(\MAin_c[1] ), .A1(N_294), .D0(ADSubmitted),
+ .C0(CmdEnable17), .B0(CmdEnable16), .A0(N_22_i), .DI0(ADSubmitted_r_0),
+ .CLK(PHI2_c), .F0(ADSubmitted_r_0), .Q0(ADSubmitted), .F1(N_22_i));
+ SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_294), .B1(N_393), .A1(N_374),
+ .D0(\MAin_c[1] ), .C0(N_294), .B0(CmdEnable16), .A0(C1Submitted),
+ .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO),
+ .Q0(C1Submitted), .F1(CmdEnable16));
+ SLICE_12 SLICE_12( .D0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c),
.F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2));
- SLICE_16 SLICE_16( .D1(CO0), .A1(\S[1] ), .D0(CO0), .A0(\S[1] ),
- .DI0(N_123_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_123_i), .Q0(CO0),
- .F1(N_345_i));
- SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), .B1(N_593),
- .A1(N_518), .D0(CmdEnable), .C0(CmdEnable17), .B0(CmdEnable_0_sqmuxa),
- .A0(un1_CmdEnable20_i), .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s),
- .Q0(CmdEnable), .F1(CmdEnable17));
- SLICE_18 SLICE_18( .D1(CmdLEDEN_4_u_i_0_a3_0_0), .C1(\Din_c[1] ),
- .B1(CmdLEDEN), .A1(CmdValid_2_i_o2_1_o3), .D0(LEDEN),
- .C0(CmdLEDEN_4_u_i_0_0), .A0(N_531), .DI0(N_40_i), .CE(XOR8MEG18),
- .CLK(PHI2_c), .F0(N_40_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_0_0));
- SLICE_20 SLICE_20( .D0(CmdValid_2_i_o2_1_o3), .C0(\Din_c[1] ), .B0(N_531),
- .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(CmdUFMShift_3), .Q0(CmdUFMShift));
- SLICE_21 SLICE_21( .C1(CmdValid_2_i_o2_1_o3), .A1(CmdUFMWrite),
- .D0(\Din_c[1] ), .C0(\Din_c[0] ), .B0(N_462), .A0(N_531),
- .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3),
- .Q0(CmdUFMWrite), .F1(N_462));
- SLICE_22 SLICE_22( .D1(N_213), .C1(\Din_c[5] ), .B1(\Din_c[3] ),
- .A1(\Din_c[4] ), .C0(CmdValid_2_i_o2_1_o3), .A0(XOR8MEG18),
- .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid),
- .F1(CmdValid_2_i_o2_1_o3));
- SLICE_23 SLICE_23( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3),
- .B1(CmdEnable), .A1(\MAin_c[0] ), .D0(CmdValid_2_i_o2_1_o3),
- .B0(XOR8MEG18), .DI0(N_36_fast), .CLK(PHI2_c), .F0(N_36_fast),
- .Q0(CmdValid_fast), .F1(XOR8MEG18));
- SLICE_24 SLICE_24( .D1(Cmdn8MEGEN), .C1(CmdLEDEN_4_u_i_0_a3_0_0),
- .B1(CmdValid_2_i_o2_1_o3), .A1(\Din_c[0] ), .C0(n8MEGEN), .B0(N_531),
- .A0(Cmdn8MEGEN_4_u_i_0_0), .DI0(N_38_i), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(N_38_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0_0));
- SLICE_25 SLICE_25( .C1(nFWE_c), .B1(nCCAS_c), .C0(nFWE_c), .DI0(nFWE_c_i),
+ SLICE_16 SLICE_16( .D1(RASr2), .C1(\IS[3] ), .B1(CO0), .A1(\S[1] ),
+ .C0(\S[1] ), .B0(CO0), .DI0(N_253_i), .LSR(RASr2), .CLK(RCLK_c),
+ .F0(N_253_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
+ SLICE_17 SLICE_17( .D1(N_294), .C1(un1_CmdEnable20_0_0), .B1(C1Submitted),
+ .A1(un1_CmdEnable20_0_a2_1_0), .D0(CmdEnable), .C0(un1_CmdEnable20_i),
+ .B0(CmdEnable17), .A0(CmdEnable_0_sqmuxa), .DI0(CmdEnable_s), .CLK(PHI2_c),
+ .F0(CmdEnable_s), .Q0(CmdEnable), .F1(un1_CmdEnable20_i));
+ SLICE_18 SLICE_18( .D1(CmdLEDEN_4_u_i_a2_0_0), .C1(N_140), .B1(CmdLEDEN),
+ .A1(\Din_c[1] ), .C0(CmdLEDEN_4_u_i_0), .B0(N_380), .A0(LEDEN),
+ .DI0(N_284_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_284_i), .Q0(CmdLEDEN),
+ .F1(CmdLEDEN_4_u_i_0));
+ SLICE_19 SLICE_19( .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c),
+ .F0(VCC), .Q0(CmdUFMData), .F1(GND));
+ SLICE_20 SLICE_20( .D1(\Din_c[1] ), .C1(\Din_c[4] ), .B1(\Din_c[0] ),
+ .A1(\Din_c[7] ), .D0(\Din_c[1] ), .C0(N_380), .B0(N_140), .A0(CmdUFMShift),
+ .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3),
+ .Q0(CmdUFMShift), .F1(N_374));
+ SLICE_21 SLICE_21( .D1(N_140), .A1(CmdUFMWrite), .D0(\Din_c[0] ), .C0(N_279),
+ .B0(\Din_c[1] ), .A0(N_380), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18),
+ .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_279));
+ SLICE_22 SLICE_22( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[3] ),
+ .A1(\Din_c[4] ), .C0(XOR8MEG18_i), .B0(N_140), .DI0(CmdValid_r),
+ .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_140));
+ SLICE_23 SLICE_23( .D1(\MAin_c[0] ), .C1(CmdEnable), .B1(\MAin_c[1] ),
+ .A1(N_294), .C0(XOR8MEG18_i), .A0(N_140), .DI0(N_36_fast), .CLK(PHI2_c),
+ .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18_i));
+ SLICE_24 SLICE_24( .D1(CmdLEDEN_4_u_i_a2_0_0), .C1(\Din_c[0] ), .B1(N_140),
+ .A1(Cmdn8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .B0(n8MEGEN), .A0(N_380),
+ .DI0(N_285_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_285_i), .Q0(Cmdn8MEGEN),
+ .F1(Cmdn8MEGEN_4_u_i_0));
+ SLICE_25 SLICE_25( .D1(nFWE_c), .A1(nCCAS_c), .D0(nFWE_c), .DI0(nFWE_c_i),
.CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i));
- SLICE_26 SLICE_26( .C1(CO0), .A1(CASr2), .C0(nRCS_9_u_i_0_o2_1_RNIL2K71),
- .A0(\IS[0] ), .DI0(N_351_i_i), .CLK(RCLK_c), .F0(N_351_i_i), .Q0(\IS[0] ),
- .F1(N_267));
- SLICE_27 SLICE_27( .D1(\IS[1] ), .B1(\IS[0] ), .A1(\IS[2] ), .D0(\IS[0] ),
- .A0(\IS[1] ), .DI1(N_348_i_i), .DI0(N_344_i), .CE(N_360_i), .CLK(RCLK_c),
- .F0(N_344_i), .Q0(\IS[1] ), .F1(N_348_i_i), .Q1(\IS[2] ));
- SLICE_28 SLICE_28( .A1(\IS[0] ), .D0(\IS[1] ), .C0(\IS[0] ), .B0(\IS[3] ),
- .A0(\IS[2] ), .DI0(N_350_i_i), .CE(N_360_i), .CLK(RCLK_c), .F0(N_350_i_i),
- .Q0(\IS[3] ), .F1(\IS_i[0] ));
- SLICE_29 SLICE_29( .D1(N_581), .C1(\FS[11] ), .B1(\FS[10] ),
- .A1(InitReady3_0_a3_1), .C0(InitReady3), .A0(InitReady), .DI0(N_757_0),
- .CLK(RCLK_c), .F0(N_757_0), .Q0(InitReady), .F1(InitReady3));
- SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN),
- .C0(CmdValid_RNIOOBE2), .B0(LEDEN_6_i_m2_i_m2), .A0(LEDEN), .DI0(LEDENe_0),
- .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2_i_m2));
- SLICE_31 SLICE_31( .C0(\CROW_c[0] ), .A0(Ready_fast), .M1(PHI2r2),
- .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .Q1(PHI2r3));
- SLICE_32 SLICE_32( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c),
+ SLICE_26 SLICE_26( .C1(\CROW_c[1] ), .A1(Ready_fast), .D0(\Din_c[2] ),
+ .C0(\Din_c[5] ), .M0(nFWE_c_i), .CLK(nCRAS_c), .F0(N_381), .Q0(FWEr_fast),
+ .F1(\RBAd_0[1] ));
+ SLICE_27 SLICE_27( .B1(Ready), .A1(N_43), .C0(\IS[0] ), .B0(Ready),
+ .A0(N_43), .DI0(N_60_i_i), .CLK(RCLK_c), .F0(N_60_i_i), .Q0(\IS[0] ),
+ .F1(N_244_i));
+ SLICE_28 SLICE_28( .C1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .C0(\IS[0] ),
+ .A0(\IS[1] ), .DI1(N_57_i_i), .DI0(N_53_i), .CE(N_244_i), .CLK(RCLK_c),
+ .F0(N_53_i), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] ));
+ SLICE_29 SLICE_29( .D1(\IS[2] ), .C1(\IS[3] ), .A1(\IS[1] ), .D0(\IS[2] ),
+ .C0(\IS[3] ), .B0(\IS[0] ), .A0(\IS[1] ), .DI0(N_58_i_i), .CE(N_244_i),
+ .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_49));
+ SLICE_30 SLICE_30( .D1(N_142), .C1(\FS[14] ), .B1(\FS[13] ),
+ .A1(InitReady3_0_a2_2), .C0(InitReady3), .A0(InitReady), .DI0(N_586_0),
+ .CLK(RCLK_c), .F0(N_586_0), .Q0(InitReady), .F1(InitReady3));
+ SLICE_31 SLICE_31( .D1(InitReady), .C1(\wb_dato[1] ), .B1(CmdLEDEN),
+ .C0(LEDEN_6_i_m2), .B0(LEDEN), .A0(CmdValid_RNITBH02), .DI0(LEDENe_0),
+ .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2));
+ SLICE_32 SLICE_32( .D1(nRowColSel), .C1(\MAin_c[4] ), .B1(\RowA[4] ),
+ .D0(\Bank[6] ), .C0(\Bank[4] ), .B0(\Bank[5] ), .A0(\Bank[7] ),
+ .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), .F0(un1_ADWR_i_o2_11), .Q0(PHI2r2),
+ .F1(\RA_c[4] ), .Q1(PHI2r3));
+ SLICE_33 SLICE_33( .D1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c),
.DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr),
.F1(LED_c), .Q1(RASr2));
- SLICE_33 SLICE_33( .D1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ),
- .C0(ADSubmitted), .B0(CmdEnable16), .M0(RASr2), .CLK(RCLK_c),
- .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\RA_c[3] ));
- SLICE_34 SLICE_34( .D1(RASr2), .C1(N_216), .B1(InitReady), .A1(Ready),
- .D0(Ready), .C0(RCKEEN_8_u_0_0_0), .B0(RCKEEN_8_u_0_1_0), .A0(CBR),
+ SLICE_34 SLICE_34( .D1(\FS[1] ), .C1(\FS[5] ), .B1(\FS[2] ), .A1(\FS[4] ),
+ .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(N_133), .M0(RASr2),
+ .CLK(RCLK_c), .F0(\wb_dati_5_1_iv_0_a2_1_1[7] ), .Q0(RASr3),
+ .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_4));
+ SLICE_35 SLICE_35( .D1(InitReady), .C1(Ready), .B1(RASr2), .A1(N_41),
+ .D0(CBR), .C0(RCKEEN_8_u_1), .B0(Ready), .A0(RCKEEN_8_u_0_0),
.DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN),
- .F1(RCKEEN_8_u_0_0_0));
- SLICE_35 SLICE_35( .C1(\S[1] ), .A1(RASr2), .D0(RASr2), .C0(RCKEEN),
- .B0(RASr), .A0(RASr3), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2),
- .Q0(RCKE_c), .F1(m3_0_a2_0));
- SLICE_36 SLICE_36( .D1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(Ready),
- .C0(Ready_0_sqmuxa_0_a2_4_a3_2), .B0(N_347), .A0(InitReady), .DI0(N_758_0),
- .CLK(RCLK_c), .F0(N_758_0), .Q0(Ready), .F1(N_347));
- SLICE_37 SLICE_37( .D1(N_347), .C1(InitReady), .B1(Ready),
- .A1(Ready_0_sqmuxa_0_a2_4_a3_2), .C0(Ready_0_sqmuxa), .A0(Ready_fast),
- .DI0(N_759_0), .CLK(RCLK_c), .F0(N_759_0), .Q0(Ready_fast),
- .F1(Ready_0_sqmuxa));
- SLICE_38 SLICE_38( .B1(\MAin_c[1] ), .A1(Ready_fast), .D0(\MAin_c[0] ),
- .A0(Ready_fast), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c),
+ .F1(RCKEEN_8_u_0_0));
+ SLICE_36 SLICE_36( .D1(RASr2), .A1(RCKE_c), .D0(RASr2), .C0(RASr3),
+ .B0(RASr), .A0(RCKEEN), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2),
+ .Q0(RCKE_c), .F1(nRWE_0io_RNO_2));
+ SLICE_37 SLICE_37( .D1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ),
+ .D0(Ready_0_sqmuxa_0_a3_2), .C0(N_248), .B0(InitReady), .A0(Ready),
+ .DI0(N_587_0), .CLK(RCLK_c), .F0(N_587_0), .Q0(Ready), .F1(N_248));
+ SLICE_38 SLICE_38( .D1(N_248), .C1(Ready_0_sqmuxa_0_a3_2), .B1(InitReady),
+ .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_588_0),
+ .CLK(RCLK_c), .F0(N_588_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
+ SLICE_39 SLICE_39( .D1(Ready_fast), .B1(\MAin_c[1] ), .D0(Ready_fast),
+ .B0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c),
.F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
- SLICE_39 SLICE_39( .B1(\MAin_c[3] ), .A1(Ready_fast), .B0(\MAin_c[2] ),
- .A0(Ready_fast), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c),
+ SLICE_40 SLICE_40( .D1(\MAin_c[3] ), .B1(Ready_fast), .D0(\MAin_c[2] ),
+ .B0(Ready_fast), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c),
.F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
- SLICE_40 SLICE_40( .D1(\MAin_c[5] ), .A1(Ready_fast), .C0(\MAin_c[4] ),
- .A0(Ready_fast), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c),
+ SLICE_41 SLICE_41( .D1(Ready_fast), .A1(\MAin_c[5] ), .D0(Ready_fast),
+ .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c),
.F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
- SLICE_41 SLICE_41( .D1(\MAin_c[7] ), .A1(Ready_fast), .C0(\MAin_c[6] ),
- .A0(Ready_fast), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c),
+ SLICE_42 SLICE_42( .D1(Ready_fast), .C1(\MAin_c[7] ), .D0(Ready_fast),
+ .C0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c),
.F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
- SLICE_42 SLICE_42( .C1(Ready_fast), .A1(\MAin_c[9] ), .C0(Ready_fast),
- .B0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c),
+ SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[9] ), .C0(\MAin_c[8] ),
+ .B0(Ready_fast), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c),
.F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
- SLICE_43 SLICE_43( .D1(\S[1] ), .C1(CO0), .B1(\IS[3] ), .A1(RASr2), .B0(CO0),
- .A0(\S[1] ), .DI0(N_216), .LSR(RASr2), .CLK(RCLK_c), .F0(N_216),
- .Q0(\S[1] ), .F1(Ready_0_sqmuxa_0_a2_4_a3_2));
- SLICE_44 SLICE_44( .D1(N_213), .C1(\Din_c[5] ), .B1(XOR8MEG),
- .A1(\Din_c[4] ), .D0(LEDEN), .C0(N_441), .B0(\Din_c[1] ),
- .A0(XOR8MEG_3_u_0_0_a3_0_2), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c),
- .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_441));
- SLICE_45 SLICE_45( .D1(InitReady), .C1(g1_0), .B1(CmdValid), .A1(N_4),
- .D0(n8MEGENe_1_0), .C0(CmdValid_RNIOOBE2), .A0(n8MEGEN), .DI0(n8MEGENe_0),
- .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNIOOBE2));
- SLICE_46 SLICE_46( .D1(CASr3), .B1(FWEr), .D0(N_345_i), .C0(Ready),
- .B0(N_248_i_1_1), .A0(CBR), .DI0(nRowColSel_0_0_0), .LSR(nRRAS_0_sqmuxa),
- .CLK(RCLK_c), .F0(nRowColSel_0_0_0), .Q0(nRowColSel), .F1(N_248_i_1_1));
- SLICE_47 SLICE_47( .D1(N_417), .C1(N_382), .B1(\wb_adr_5_i_0_0[1] ),
- .A1(N_416), .D0(\wb_adr_5_i_0_3[0] ), .C0(N_383), .B0(\wb_adr_5_i_0_0[0] ),
- .A0(N_423), .DI1(N_229_i), .DI0(N_230_i), .CE(un1_wb_rst14_i_0),
- .CLK(RCLK_c), .F0(N_230_i), .Q0(\wb_adr[0] ), .F1(N_229_i),
- .Q1(\wb_adr[1] ));
- SLICE_48 SLICE_48( .B1(\wb_adr[2] ), .A1(InitReady), .D0(\wb_adr[1] ),
- .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ),
- .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] ));
- SLICE_49 SLICE_49( .D1(\FS[15] ), .C1(N_210), .B1(\wb_adr[4] ),
- .A1(InitReady), .D0(\FS[15] ), .C0(N_210), .B0(\wb_adr[3] ),
- .A0(InitReady), .DI1(N_385), .DI0(N_384), .CE(un1_wb_rst14_i_0),
- .CLK(RCLK_c), .F0(N_384), .Q0(\wb_adr[4] ), .F1(N_385), .Q1(\wb_adr[5] ));
- SLICE_50 SLICE_50( .D1(\wb_adr[6] ), .A1(InitReady), .D0(\wb_adr[5] ),
- .C0(N_210), .B0(\FS[15] ), .A0(InitReady), .DI1(\wb_adr_5[7] ),
- .DI0(N_386), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_386),
- .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] ));
- SLICE_51 SLICE_51( .D1(N_214), .C1(N_471_3), .B1(wb_cyc_stb_4_iv_0_a3_0_0),
- .A1(N_471_2), .D0(InitReady), .C0(N_471), .B0(un1_PHI2r3),
- .A0(CmdUFMWrite), .DI0(wb_cyc_stb_4), .CE(N_178), .LSR(wb_rst10),
- .CLK(RCLK_c), .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_471));
- SLICE_52 SLICE_52( .D1(N_207), .C1(\wb_dati_5_1_iv_0_1[1] ), .B1(N_578),
- .A1(\FS[11] ), .D0(InitReady), .C0(wb_we), .B0(N_576),
- .A0(\wb_dati_5_0_iv_0_a3_1[0] ), .DI1(\wb_dati_5[1] ),
- .DI0(\wb_dati_5[0] ), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c),
+ SLICE_44 SLICE_44( .D1(Ready), .C1(N_41), .B1(CBR_fast), .A1(RASr2),
+ .B0(CO0), .A0(\S[1] ), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41),
+ .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1));
+ SLICE_45 SLICE_45( .D1(\Din_c[5] ), .C1(N_134), .B1(\Din_c[4] ),
+ .A1(XOR8MEG), .D0(\Din_c[1] ), .C0(N_274), .B0(LEDEN),
+ .A0(XOR8MEG_3_u_0_a2_0_2), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c),
+ .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_274));
+ SLICE_46 SLICE_46( .D1(N_4), .C1(CmdValid), .B1(InitReady), .A1(g1_0),
+ .D0(n8MEGENe_1_0), .C0(CmdValid_RNITBH02), .A0(n8MEGEN), .DI0(n8MEGENe_0),
+ .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNITBH02));
+ SLICE_47 SLICE_47( .D1(Ready), .C1(CASr3), .B1(FWEr), .A1(CBR), .D0(Ready),
+ .C0(N_255), .B0(CO0), .A0(\S[1] ), .DI0(nRowColSel_0_0),
+ .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel),
+ .F1(N_255));
+ SLICE_48 SLICE_48( .D1(N_384), .C1(\FS[12] ), .B1(\FS[11] ),
+ .A1(\wb_adr_5_i_i_0[1] ), .D0(\wb_adr_5_i_i_5[0] ), .C0(N_313),
+ .B0(\FS[11] ), .A0(N_367), .DI1(N_282), .DI0(N_283), .CE(N_122),
+ .CLK(RCLK_c), .F0(N_283), .Q0(\wb_adr[0] ), .F1(N_282), .Q1(\wb_adr[1] ));
+ SLICE_49 SLICE_49( .D1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ),
+ .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_122),
+ .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ),
+ .Q1(\wb_adr[3] ));
+ SLICE_50 SLICE_50( .D1(N_132), .C1(InitReady), .A1(\wb_adr[4] ), .D0(N_132),
+ .C0(InitReady), .A0(\wb_adr[3] ), .DI1(N_80), .DI0(N_81), .CE(N_122),
+ .CLK(RCLK_c), .F0(N_81), .Q0(\wb_adr[4] ), .F1(N_80), .Q1(\wb_adr[5] ));
+ SLICE_51 SLICE_51( .D1(\wb_adr[6] ), .B1(InitReady), .C0(N_132),
+ .B0(InitReady), .A0(\wb_adr[5] ), .DI1(\wb_adr_5[7] ),
+ .DI0(\wb_adr_5_i_m2_0[6] ), .CE(N_122), .CLK(RCLK_c),
+ .F0(\wb_adr_5_i_m2_0[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ),
+ .Q1(\wb_adr[7] ));
+ SLICE_52 SLICE_52( .D1(\FS[0] ), .C1(N_132), .B1(wb_req), .A1(N_330_4),
+ .D0(InitReady), .C0(N_330), .B0(CmdUFMWrite), .A0(un1_PHI2r3),
+ .DI0(wb_cyc_stb_4), .CE(N_103), .LSR(wb_rst10), .CLK(RCLK_c),
+ .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_330));
+ SLICE_53 SLICE_53( .D1(N_226), .C1(N_302), .B1(N_303), .A1(N_233),
+ .D0(\wb_dati_5_0_iv_0_a2_0[0] ), .C0(N_383), .B0(InitReady), .A0(wb_we),
+ .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_122), .CLK(RCLK_c),
.F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ),
.Q1(\wb_dati[1] ));
- SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_i_i_1[3] ), .C1(N_579),
- .B1(\wb_dati_5_1_iv_i_i_0[3] ), .A1(\wb_dati_5_1_iv_i_i_a3_1[3] ),
- .D0(N_361), .B0(InitReady), .A0(\wb_dati[1] ),
- .DI1(\wb_dati_5_1_iv_i_i[3] ), .DI0(\wb_dati_5[2] ), .CE(un1_wb_rst14_i_0),
- .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ),
- .F1(\wb_dati_5_1_iv_i_i[3] ), .Q1(\wb_dati[3] ));
- SLICE_54 SLICE_54( .C1(InitReady), .B1(N_361), .A1(\wb_dati[4] ),
- .D0(\wb_dati_5_1_iv_0_1[4] ), .C0(\wb_dati_5_1_iv_0_0[4] ), .B0(N_578),
- .A0(\FS[9] ), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[4] ),
+ SLICE_54 SLICE_54( .D1(\wb_dati[2] ), .C1(N_341),
+ .B1(\wb_dati_5_1_iv_0_1[3] ), .A1(InitReady), .D0(N_335),
+ .C0(\wb_dati[1] ), .B0(\wb_dati_5_1_iv_0_o2_0[5] ), .A0(InitReady),
+ .DI1(\wb_dati_5[3] ), .DI0(\wb_dati_5[2] ), .CE(N_122), .CLK(RCLK_c),
+ .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ),
+ .Q1(\wb_dati[3] ));
+ SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_o2_0[5] ), .C1(\wb_dati[4] ),
+ .B1(InitReady), .A1(N_335), .C0(\wb_dati_5_1_iv_0_2[4] ),
+ .B0(\wb_dati_5_1_iv_0_0[4] ), .A0(N_335), .DI1(\wb_dati_5[5] ),
+ .DI0(\wb_dati_5[4] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[4] ),
.Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] ));
- SLICE_55 SLICE_55( .D1(N_484), .C1(\wb_dati_5_1_iv_0_0[7] ), .B1(N_488),
- .A1(N_486), .D0(\wb_dati_5_1_iv_0_1[6] ), .C0(\FS[11] ), .B0(N_578),
- .A0(N_207), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ),
- .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[6] ),
+ SLICE_56 SLICE_56( .D1(N_345), .C1(\wb_dati_5_1_iv_0_a2_1_1[7] ),
+ .B1(\wb_dati_5_1_iv_0_1[7] ), .A1(N_375), .D0(\wb_dati_5_1_iv_0_0[6] ),
+ .C0(N_233), .B0(N_348_2), .A0(N_383), .DI1(\wb_dati_5[7] ),
+ .DI0(\wb_dati_5[6] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[6] ),
.Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] ));
- SLICE_56 SLICE_56( .D1(\FS[17] ), .C1(\FS[16] ), .B1(InitReady), .A1(N_581),
- .D0(N_92_i), .B0(N_31_i), .A0(wb_req), .DI0(wb_reqe_0), .LSR(wb_rst10),
- .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_31_i));
- SLICE_57 SLICE_57( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[16] ),
- .A1(InitReady), .D0(wb_rst10), .C0(N_515), .B0(N_92_i), .A0(wb_rst),
+ SLICE_57 SLICE_57( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), .A1(N_131),
+ .D0(N_94_i), .C0(N_34_i), .A0(wb_req), .DI0(wb_reqe_0), .LSR(wb_rst10),
+ .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_34_i));
+ SLICE_58 SLICE_58( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ),
+ .A1(\FS[15] ), .D0(N_94_i), .C0(wb_rst10), .B0(\FS[14] ), .A0(wb_rst),
.DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10));
- SLICE_58 SLICE_58( .D1(N_210), .C1(\FS[15] ), .B1(\wb_adr[0] ),
- .A1(InitReady), .D0(N_210), .C0(CmdUFMData), .B0(wb_we_0_i_0_1),
- .A0(InitReady), .DI0(N_231_i), .CE(un1_wb_rst14_i_0), .LSR(wb_rst10),
- .CLK(RCLK_c), .F0(N_231_i), .Q0(wb_we), .F1(N_382));
- wb_dati_5_1_iv_0_o3_5__SLICE_59 \wb_dati_5_1_iv_0_o3[5]/SLICE_59 (
- .D1(N_214), .C1(N_217), .B1(\FS[12] ), .A1(N_479), .D0(N_214),
- .C0(\FS[13] ), .B0(N_209), .A0(N_479), .M0(\FS[9] ), .OFX0(N_361));
- SLICE_60 SLICE_60( .D1(CBR_fast), .C1(Ready), .B1(m3_0_a2_0), .A1(CO0),
- .D0(CO0), .C0(nRCAS_0_sqmuxa_1), .B0(N_408), .A0(\S[1] ), .F0(N_248_i_sx),
- .F1(nRCAS_0_sqmuxa_1));
- SLICE_61 SLICE_61( .D1(CO0), .C1(N_408), .B1(Ready), .A1(\S[1] ), .D0(CASr2),
- .C0(un1_nRCAS_6_sqmuxa_i_0_0), .A0(CO0), .F0(nRCAS_r_i_0_o2_0_0),
- .F1(un1_nRCAS_6_sqmuxa_i_0_0));
- SLICE_62 SLICE_62( .D1(\FS[11] ), .C1(\FS[9] ), .B1(\FS[10] ),
- .A1(InitReady), .C0(N_599), .B0(\FS[14] ), .A0(InitReady), .F0(N_407),
- .F1(N_599));
- SLICE_63 SLICE_63( .D1(\FS[12] ), .C1(N_427), .B1(N_207),
- .A1(wb_we_0_i_0_a3_0_0), .D0(\FS[12] ), .C0(wb_we_0_i_0_0), .B0(\FS[13] ),
- .A0(N_407), .F0(wb_we_0_i_0_1), .F1(wb_we_0_i_0_0));
- SLICE_64 SLICE_64( .D1(N_539), .C1(\Din_c[6] ), .B1(\Din_c[3] ),
- .A1(\MAin_c[0] ), .D0(N_518), .C0(N_594), .B0(\MAin_c[1] ),
- .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_594));
- SLICE_65 SLICE_65( .D1(\FS[9] ), .C1(\wb_adr_5_i_0_a3_0_1[0] ),
- .B1(\FS[10] ), .A1(N_424), .D0(N_542), .C0(\wb_adr_5_i_0_1[0] ),
- .B0(\FS[9] ), .A0(N_208), .F0(\wb_adr_5_i_0_3[0] ),
- .F1(\wb_adr_5_i_0_1[0] ));
- SLICE_66 SLICE_66( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ),
- .A1(\FS[15] ), .D0(\wb_dati[6] ), .C0(N_214), .B0(InitReady),
- .A0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F0(\wb_dati_5_1_iv_0_0[7] ),
- .F1(N_214));
- SLICE_67 SLICE_67( .D1(N_208), .C1(\FS[9] ), .B1(\FS[10] ), .A1(N_579),
- .D0(\FS[13] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_208),
- .F1(\wb_dati_5_1_iv_0_0[4] ));
- SLICE_68 SLICE_68( .D1(\FS[10] ), .C1(\FS[9] ), .A1(\FS[11] ), .D0(N_214),
- .C0(\ufmefb/g0_0_a3_2 ), .B0(N_226), .F0(N_4), .F1(N_226));
- SLICE_69 SLICE_69( .D1(\FS[12] ), .C1(\wb_dati_5_1_iv_0_a3_0_1[1] ),
- .B1(\FS[14] ), .A1(N_214), .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[13] ),
- .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a3_0_1[1] ), .F1(N_477));
- SLICE_70 SLICE_70( .D1(N_542), .C1(N_236), .B1(\FS[13] ), .A1(\FS[11] ),
- .D0(InitReady), .B0(\FS[12] ), .A0(\FS[14] ), .F0(N_542), .F1(N_424));
- SLICE_71 SLICE_71( .D1(N_502), .C1(N_596), .B1(N_536), .A1(N_412),
- .D0(\FS[10] ), .C0(\FS[9] ), .A0(\FS[11] ), .F0(N_596),
- .F1(\wb_dati_5_1_iv_i_i_1[3] ));
- SLICE_72 SLICE_72( .D1(nRRAS_0_sqmuxa), .C1(N_522), .B1(RCKE_c), .A1(RASr2),
- .D0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa),
- .F1(nRCS_9_u_i_0_o3));
- SLICE_73 SLICE_73( .D1(\wb_dati[2] ), .C1(N_502),
- .B1(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), .A1(InitReady), .D0(\FS[10] ),
- .C0(\FS[11] ), .B0(\FS[12] ), .A0(\FS[9] ),
- .F0(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), .F1(\wb_dati_5_1_iv_i_i_0[3] ));
- SLICE_74 SLICE_74( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[3] ), .D0(InitReady),
- .C0(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .B0(Ready), .A0(RASr2), .F0(N_408),
- .F1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0));
- SLICE_75 SLICE_75( .D1(\FS[14] ), .A1(InitReady), .D0(\FS[11] ),
- .C0(\FS[12] ), .B0(N_515), .A0(N_207), .F0(\wb_adr_5_i_0_0[1] ),
- .F1(N_515));
- SLICE_76 SLICE_76( .D1(\FS[10] ), .C1(\FS[13] ), .B1(\FS[14] ),
- .A1(\FS[11] ), .D0(N_214), .C0(N_217), .B0(\FS[9] ), .A0(\FS[12] ),
- .F0(N_486), .F1(N_217));
- SLICE_77 SLICE_77( .D1(\FS[12] ), .C1(N_214), .B1(\FS[13] ), .A1(\FS[14] ),
- .D0(\FS[10] ), .C0(\FS[11] ), .B0(N_578), .A0(\FS[9] ), .F0(N_484),
- .F1(N_578));
- SLICE_78 SLICE_78( .D1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .C1(N_216),
- .B1(\IS[0] ), .A1(N_221), .D0(nRRAS_0_sqmuxa), .C0(N_522), .B0(RCKE_c),
- .A0(RASr2), .F0(N_246_i), .F1(N_522));
- SLICE_79 SLICE_79( .C1(InitReady), .A1(RASr2), .D0(CO0), .C0(N_221),
- .B0(Ready), .A0(\S[1] ), .F0(N_360_i), .F1(N_221));
- SLICE_80 SLICE_80( .D1(\MAin_c[1] ), .B1(N_593), .A1(N_518),
- .D0(un1_CmdEnable20_0_0_a3_1_1), .C0(un1_CmdEnable20_0_0_0),
- .B0(C1Submitted), .A0(un1_CmdEnable20_0_0_o3), .M1(nCCAS_c_i),
- .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR),
- .F1(un1_CmdEnable20_0_0_a3_1_1), .Q1(CBR_fast));
- SLICE_81 SLICE_81( .D1(Ready), .C1(CBR), .A1(\S[1] ), .D0(nRCAS_0_sqmuxa_1),
- .C0(nRWE_s_i_0_tz_0), .B0(N_590), .A0(N_595), .F0(N_49_i), .F1(N_590));
- SLICE_82 SLICE_82( .D1(\Din_c[4] ), .C1(\Din_c[5] ), .B1(N_213),
- .A1(\Din_c[3] ), .C0(N_531), .B0(XOR8MEG18), .M0(\Din_c[0] ),
- .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), .F0(CmdUFMData_1_sqmuxa),
- .Q0(CmdUFMData), .F1(N_531));
- SLICE_83 SLICE_83( .D1(FWEr), .A1(CO0), .D0(N_590), .C0(N_248_i_1_0),
- .B0(nRCS_9_u_i_0_o3), .A0(N_595), .F0(N_247_i), .F1(N_248_i_1_0));
- SLICE_84 SLICE_84( .D1(\Bank[4] ), .C1(\Bank[3] ), .B1(\Bank[5] ),
- .A1(\Bank[1] ), .D0(\Bank[6] ), .C0(\Bank[7] ),
- .B0(un1_CmdEnable20_0_0_o3_11), .A0(un1_CmdEnable20_0_0_o3_10),
- .F0(un1_CmdEnable20_0_0_o3), .F1(un1_CmdEnable20_0_0_o3_11));
- SLICE_85 SLICE_85( .D1(\FS[10] ), .C1(N_514), .B1(N_576), .A1(N_537),
- .D0(\wb_dati[5] ), .C0(InitReady), .B0(N_472), .A0(N_473),
- .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_473));
- SLICE_86 SLICE_86( .D1(\FS[11] ), .C1(N_207), .B1(N_536), .A1(N_502),
- .D0(InitReady), .C0(N_479), .B0(\wb_dati[3] ), .A0(N_473),
- .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(N_479));
- SLICE_87 SLICE_87( .D1(\FS[12] ), .C1(\FS[14] ), .B1(N_214), .D0(\FS[10] ),
- .C0(\FS[11] ), .B0(N_579), .A0(\FS[13] ), .F0(N_488), .F1(N_579));
- SLICE_88 SLICE_88( .D1(CO0), .C1(\S[1] ), .B1(Ready), .A1(N_221),
- .D0(\IS[1] ), .C0(nRCS_9_u_i_0_o2_1_RNIL2K71), .B0(\IS[3] ), .A0(\IS[2] ),
- .F0(RA10s_i), .F1(nRCS_9_u_i_0_o2_1_RNIL2K71));
- SLICE_89 SLICE_89( .D1(\FS[10] ), .C1(\FS[9] ), .D0(\FS[13] ), .C0(N_236),
- .B0(\FS[11] ), .A0(N_579), .F0(N_472), .F1(N_236));
- SLICE_90 SLICE_90( .D1(\IS[1] ), .C1(nRCS_9_u_i_0_o2_1_RNIL2K71),
- .B1(\IS[2] ), .A1(\IS[0] ), .D0(RCKE_c), .C0(nRRAS_0_sqmuxa),
- .B0(nRWE_s_i_0_a3_1_0), .A0(RASr2), .F0(nRWE_s_i_0_tz_0),
- .F1(nRWE_s_i_0_a3_1_0));
- SLICE_91 SLICE_91( .D1(\FS[13] ), .C1(\FS[9] ), .B1(N_209), .A1(N_214),
- .D0(\wb_dati[0] ), .C0(N_477), .B0(InitReady), .A0(N_412),
- .F0(\wb_dati_5_1_iv_0_1[1] ), .F1(N_412));
- SLICE_92 SLICE_92( .D1(N_471_3), .C1(wb_req), .B1(\FS[0] ), .D0(N_214),
- .C0(N_471_2), .B0(wb_ack), .A0(wb_cyc_stb_2_sqmuxa_i_a3_0), .F0(N_178),
- .F1(wb_cyc_stb_2_sqmuxa_i_a3_0));
- SLICE_93 SLICE_93( .D1(\MAin_c[5] ), .C1(\MAin_c[3] ), .B1(\MAin_c[2] ),
- .A1(\MAin_c[7] ), .D0(un1_CmdEnable20_0_0_o3_4), .C0(\Bank[2] ),
- .B0(\Bank[0] ), .A0(un1_CmdEnable20_0_0_o3_3),
- .F0(un1_CmdEnable20_0_0_o3_10), .F1(un1_CmdEnable20_0_0_o3_4));
- SLICE_94 SLICE_94( .D1(N_248_i_sx), .C1(N_248_i_1_0), .B1(N_248_i_1_1),
- .A1(N_248_i_1), .D0(N_267), .C0(nRCAS_r_i_0_o2_0_0), .B0(FWEr), .A0(CBR),
- .F0(N_248_i_1), .F1(N_248_i));
- SLICE_95 SLICE_95( .D1(\FS[12] ), .B1(\FS[13] ), .D0(InitReady), .C0(N_536),
- .B0(\FS[11] ), .A0(N_207), .F0(N_427), .F1(N_536));
- SLICE_96 SLICE_96( .D1(InitReady), .A1(\FS[14] ), .D0(\FS[13] ), .C0(N_404),
- .B0(N_511), .A0(\FS[12] ), .F0(\wb_adr_5_i_0_0[0] ), .F1(N_511));
- SLICE_97 SLICE_97( .C1(\FS[16] ), .B1(\FS[17] ), .D0(InitReady), .C0(N_210),
- .B0(\FS[15] ), .A0(\wb_dati[7] ), .F0(N_383), .F1(N_210));
- SLICE_98 SLICE_98( .C1(\FS[4] ), .B1(\FS[3] ), .D0(\FS[6] ),
- .C0(wb_cyc_stb_4_iv_0_a3_0_2_0), .B0(\FS[2] ), .A0(\FS[7] ), .F0(N_471_2),
- .F1(wb_cyc_stb_4_iv_0_a3_0_2_0));
- SLICE_99 SLICE_99( .C1(\Din_c[5] ), .B1(\Din_c[3] ), .D0(\Din_c[2] ),
- .C0(\Din_c[6] ), .B0(N_505), .A0(\MAin_c[0] ), .F0(N_593), .F1(N_505));
- SLICE_100 SLICE_100( .C1(\Din_c[6] ), .A1(\Din_c[7] ),
- .D0(XOR8MEG_3_u_0_0_0_a2), .C0(N_213), .B0(\Din_c[3] ), .A0(N_539),
- .F0(XOR8MEG_3_u_0_0_a3_0_2), .F1(N_213));
- SLICE_101 SLICE_101( .B1(\FS[14] ), .A1(\FS[12] ), .D0(\FS[10] ),
- .C0(\FS[9] ), .B0(N_537), .A0(N_514), .F0(\wb_dati_5_1_iv_0_a3_0_1[7] ),
- .F1(N_537));
- SLICE_102 SLICE_102( .C1(\FS[13] ), .A1(\FS[11] ), .D0(\FS[10] ),
- .C0(\FS[14] ), .B0(\FS[12] ), .A0(N_514), .F0(\wb_dati_5_0_iv_0_a3_1[0] ),
- .F1(N_514));
- SLICE_103 SLICE_103( .C1(PHI2r3), .A1(PHI2r2), .D0(InitReady),
- .C0(G_4_0_a3_0), .B0(CmdUFMShift), .A0(CmdValid_fast),
- .F0(un1_wb_rst14_i_0), .F1(G_4_0_a3_0));
- SLICE_104 SLICE_104( .D1(\FS[13] ), .C1(\FS[14] ), .B1(\FS[12] ),
- .D0(\FS[13] ), .C0(\FS[14] ), .B0(\FS[12] ), .A0(wb_ack),
- .F0(\ufmefb/g0_0_a3_2 ), .F1(N_581));
- SLICE_105 SLICE_105( .D1(\FS[13] ), .C1(N_226), .B1(\FS[14] ),
- .A1(InitReady), .D0(\FS[13] ), .B0(\FS[14] ), .A0(InitReady),
- .F0(wb_we_0_i_0_a3_0_0), .F1(N_417));
- SLICE_106 SLICE_106( .D1(\FS[14] ), .C1(\FS[12] ), .B1(\FS[13] ), .A1(N_599),
- .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_599), .F0(N_423), .F1(N_416));
- SLICE_107 SLICE_107( .C1(PHI2r2), .B1(PHI2r3), .A1(CmdValid), .D0(InitReady),
- .C0(PHI2r2), .B0(PHI2r3), .A0(CmdValid), .M0(CASr2), .CLK(RCLK_c),
- .F0(N_92_i), .Q0(CASr3), .F1(un1_PHI2r3));
- SLICE_108 SLICE_108( .D1(CO0), .C1(FWEr), .B1(CASr2), .A1(\S[1] ), .D0(CO0),
- .C0(FWEr), .B0(CASr3), .A0(CASr2), .F0(N_595), .F1(RCKEEN_8_u_0_1_0));
- SLICE_109 SLICE_109( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ),
- .A1(\FS[9] ), .D0(\FS[10] ), .C0(\FS[11] ), .A0(\FS[9] ), .F0(N_404),
- .F1(\wb_dati_5_1_iv_i_i_a3_1[3] ));
- SLICE_110 SLICE_110( .D1(InitReady), .C1(\FS[12] ), .B1(\FS[11] ),
- .A1(\FS[13] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[10] ), .A0(\FS[11] ),
- .F0(N_209), .F1(\wb_adr_5_i_0_a3_0_1[0] ));
- SLICE_111 SLICE_111( .C1(\MAin_c[9] ), .B1(nRowColSel), .C0(\MAin_c[9] ),
- .B0(nRowColSel), .F0(RDQMH_c), .F1(RDQML_c));
- SLICE_112 SLICE_112( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ),
- .A1(\Din_c[7] ), .C0(\Din_c[4] ), .B0(\Din_c[0] ),
- .F0(XOR8MEG_3_u_0_0_0_a2), .F1(N_518));
- SLICE_113 SLICE_113( .B1(N_214), .A1(\FS[14] ), .C0(\FS[9] ), .B0(N_214),
- .F0(N_576), .F1(N_502));
- SLICE_114 SLICE_114( .C1(\MAin_c[6] ), .B1(nRowColSel), .A1(\RowA[6] ),
- .C0(\MAin_c[6] ), .B0(\MAin_c[4] ), .A0(nFWE_c),
- .F0(un1_CmdEnable20_0_0_o3_3), .F1(\RA_c[6] ));
- SLICE_115 SLICE_115( .D1(\RowA[9] ), .B1(\MAin_c[9] ), .A1(nRowColSel),
- .D0(nRowColSel), .C0(\MAin_c[8] ), .A0(\RowA[8] ), .F0(\RA_c[8] ),
- .F1(\RA_c[9] ));
- SLICE_116 SLICE_116( .D1(\RowA[7] ), .C1(\MAin_c[7] ), .B1(nRowColSel),
- .D0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ),
- .F1(\RA_c[7] ));
- SLICE_117 SLICE_117( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ),
- .D0(\MAin_c[1] ), .C0(\RowA[1] ), .B0(nRowColSel), .F0(\RA_c[1] ),
- .F1(\RA_c[5] ));
- SLICE_118 SLICE_118( .D1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ),
- .D0(nRowColSel), .C0(\RowA[2] ), .B0(\MAin_c[2] ), .F0(\RA_c[2] ),
- .F1(\RA_c[4] ));
- SLICE_119 SLICE_119( .D1(\Din_c[5] ), .C1(\Din_c[6] ), .B1(\Din_c[7] ),
- .A1(\Din_c[4] ), .C0(\Din_c[5] ), .B0(\Din_c[2] ), .F0(N_539),
- .F1(CmdLEDEN_4_u_i_0_a3_0_0));
- SLICE_120 SLICE_120( .B1(\CROW_c[1] ), .A1(Ready_fast), .D0(\Din_c[6] ),
- .C0(n8MEGEN), .B0(XOR8MEG), .A0(Ready_fast), .F0(RA11d_0),
- .F1(\RBAd_0[1] ));
- SLICE_121 SLICE_121( .D1(wb_req), .B1(\FS[0] ), .D0(\FS[5] ), .C0(\FS[8] ),
- .A0(\FS[1] ), .F0(N_471_3), .F1(wb_cyc_stb_4_iv_0_a3_0_0));
- SLICE_122 SLICE_122( .D1(\wb_dato[0] ), .C1(InitReady), .B1(Cmdn8MEGEN),
- .B0(PHI2r2), .A0(PHI2r3), .F0(g1_0), .F1(n8MEGENe_1_0));
- SLICE_123 SLICE_123( .D1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[17] ),
- .C0(\FS[16] ), .A0(\FS[15] ), .F0(InitReady3_0_a3_1), .F1(N_207));
+ SLICE_59 SLICE_59( .D1(\wb_dati[3] ), .C1(N_362), .B1(InitReady), .A1(N_394),
+ .D0(N_353), .C0(wb_we_0_0_0_0), .B0(InitReady), .A0(CmdUFMData),
+ .DI0(wb_we_0_0_0), .CE(N_122), .LSR(wb_rst10), .CLK(RCLK_c),
+ .F0(wb_we_0_0_0), .Q0(wb_we), .F1(\wb_dati_5_1_iv_0_0[4] ));
+ SLICE_60 SLICE_60( .D1(\FS[13] ), .C1(\FS[9] ), .B1(N_132), .A1(N_129),
+ .D0(N_362), .C0(\FS[13] ), .B0(N_226), .A0(N_223),
+ .F0(\wb_dati_5_1_iv_0_1[3] ), .F1(N_226));
+ SLICE_61 SLICE_61( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady),
+ .A1(\FS[15] ), .D0(N_132), .C0(\wb_adr[0] ), .B0(InitReady), .A0(N_428_tz),
+ .F0(\wb_adr_5_i_i_0[1] ), .F1(N_132));
+ SLICE_62 SLICE_62( .D1(InitReady), .C1(CO0), .B1(\S[1] ), .A1(RASr2),
+ .D0(\S[1] ), .C0(N_49), .B0(N_43), .A0(Ready), .F0(N_39), .F1(N_43));
+ SLICE_63 SLICE_63( .D1(N_131), .C1(N_142), .B1(N_125), .A1(\FS[13] ),
+ .D0(N_131), .C0(N_356), .B0(\FS[12] ), .A0(N_133), .F0(wb_we_0_0_0_0),
+ .F1(N_356));
+ SLICE_64 SLICE_64( .D1(\Din_c[3] ), .C1(\Din_c[6] ), .B1(N_381),
+ .A1(\MAin_c[0] ), .D0(\MAin_c[1] ), .C0(N_374), .B0(N_393),
+ .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0), .F1(N_393));
+ SLICE_65 SLICE_65( .D1(\FS[14] ), .C1(\wb_adr_5_i_i_a2_0[1] ), .B1(N_142),
+ .A1(\FS[13] ), .D0(\FS[11] ), .C0(N_125), .B0(\FS[12] ), .A0(\FS[13] ),
+ .F0(\wb_adr_5_i_i_a2_0[1] ), .F1(N_428_tz));
+ SLICE_66 SLICE_66( .D1(\FS[11] ), .C1(\FS[9] ), .A1(\FS[12] ), .D0(\FS[11] ),
+ .C0(\wb_adr_5_i_i_a2_3_0[0] ), .B0(\FS[10] ), .A0(\FS[13] ),
+ .F0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F1(\wb_adr_5_i_i_a2_3_0[0] ));
+ SLICE_67 SLICE_67( .D1(N_132), .C1(N_142), .B1(N_125), .A1(g0_0_a3_1),
+ .D0(\FS[14] ), .B0(\FS[13] ), .A0(wb_ack), .F0(g0_0_a3_1), .F1(N_4));
+ SLICE_68 SLICE_68( .D1(nRWE_0io_RNO_2), .C1(IS_0_sqmuxa_0_o2),
+ .B1(nRRAS_0_sqmuxa), .A1(nRWE_0io_RNO_1), .D0(Ready), .C0(\S[1] ),
+ .B0(CO0), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_0));
+ SLICE_69 SLICE_69( .D1(\FS[11] ), .C1(N_220), .B1(N_367),
+ .A1(\wb_dati_5_1_iv_0_0[7] ), .D0(\FS[9] ), .B0(\FS[12] ), .A0(\FS[10] ),
+ .F0(N_220), .F1(\wb_dati_5_1_iv_0_1[7] ));
+ SLICE_70 SLICE_70( .D1(\FS[11] ), .C1(\FS[14] ), .B1(\FS[12] ),
+ .A1(\FS[13] ), .C0(\FS[10] ), .B0(N_348_2), .A0(\FS[9] ),
+ .F0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F1(N_348_2));
+ SLICE_71 SLICE_71( .D1(\FS[14] ), .C1(N_143), .A1(N_131), .D0(\FS[10] ),
+ .C0(\FS[13] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_143), .F1(N_353));
+ SLICE_72 SLICE_72( .D1(\FS[14] ), .C1(N_137), .B1(N_132), .A1(\FS[13] ),
+ .D0(\FS[11] ), .C0(\FS[12] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_137),
+ .F1(N_335));
+ SLICE_73 SLICE_73( .D1(N_374), .C1(\Din_c[5] ), .B1(\MAin_c[1] ),
+ .A1(\Din_c[3] ), .D0(\Din_c[2] ), .C0(N_382),
+ .B0(un1_CmdEnable20_0_a2_3_0), .A0(\Din_c[6] ), .M1(nCCAS_c_i),
+ .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CmdEnable17), .Q0(CBR),
+ .F1(un1_CmdEnable20_0_a2_3_0), .Q1(CBR_fast));
+ SLICE_74 SLICE_74( .D1(N_134), .C1(\Din_c[3] ), .B1(\Din_c[4] ),
+ .A1(\Din_c[5] ), .D0(\MAin_c[1] ), .C0(N_382), .B0(N_380), .A0(CmdEnable),
+ .F0(CmdUFMData_1_sqmuxa), .F1(N_380));
+ SLICE_75 SLICE_75( .D1(\Bank[3] ), .C1(un1_ADWR_i_o2_11),
+ .B1(un1_ADWR_i_o2_10), .A1(\Bank[1] ), .D0(\MAin_c[0] ), .B0(N_294),
+ .F0(N_382), .F1(N_294));
+ SLICE_76 SLICE_76( .C1(\MAin_c[1] ), .A1(N_374), .D0(N_294),
+ .C0(ADSubmitted), .B0(N_393), .A0(N_378), .M0(CASr2), .CLK(RCLK_c),
+ .F0(CmdEnable_0_sqmuxa), .Q0(CASr3), .F1(N_378));
+ SLICE_77 SLICE_77( .D1(\FS[14] ), .C1(\wb_adr_5_i_i_a2_6_0[0] ), .B1(N_132),
+ .D0(\wb_adr_5_i_i_1[0] ), .C0(N_384), .B0(N_314), .A0(N_315),
+ .F0(\wb_adr_5_i_i_5[0] ), .F1(N_314));
+ SLICE_78 SLICE_78( .D1(Ready), .B1(N_43), .D0(\IS[2] ), .C0(\IS[1] ),
+ .B0(IS_0_sqmuxa_0_o2), .A0(\IS[3] ), .F0(RA10s_i), .F1(IS_0_sqmuxa_0_o2));
+ SLICE_79 SLICE_79( .D1(\FS[10] ), .C1(N_132), .B1(\FS[9] ),
+ .D0(\wb_adr_5_i_i_a2_6_0[0] ), .C0(N_383), .B0(N_348_2), .A0(N_367),
+ .F0(\wb_dati_5_1_iv_0_2[4] ), .F1(N_383));
+ SLICE_80 SLICE_80( .B1(\FS[9] ), .A1(\FS[10] ), .D0(N_367), .C0(\FS[11] ),
+ .B0(N_125), .A0(\FS[12] ), .F0(N_233), .F1(N_125));
+ SLICE_81 SLICE_81( .D1(nRCS_0io_RNO_0), .C1(N_37_i_1), .B1(N_28_i_1),
+ .A1(nRCS_9_u_i_0), .D0(N_49), .C0(N_43), .B0(nRCS_9_u_i_0_0), .A0(\IS[0] ),
+ .F0(nRCS_9_u_i_0), .F1(N_28_i));
+ SLICE_82 SLICE_82( .D1(\FS[12] ), .A1(\FS[11] ), .D0(\FS[13] ), .C0(N_376),
+ .B0(\FS[14] ), .A0(N_383), .F0(N_345), .F1(N_376));
+ SLICE_83 SLICE_83( .D1(\FS[11] ), .C1(\FS[9] ), .B1(\FS[12] ), .A1(\FS[10] ),
+ .D0(N_226), .C0(N_133), .B0(N_132), .A0(N_394),
+ .F0(\wb_dati_5_1_iv_0_o2_0[5] ), .F1(N_394));
+ SLICE_84 SLICE_84( .D1(N_132), .C1(\FS[14] ),
+ .D0(\wb_dati_5_1_iv_0_a2_1[6] ), .C0(N_362), .B0(InitReady),
+ .A0(\wb_dati[5] ), .F0(\wb_dati_5_1_iv_0_0[6] ), .F1(N_362));
+ SLICE_85 SLICE_85( .D1(\FS[12] ), .C1(N_132), .B1(\FS[13] ), .A1(N_125),
+ .D0(InitReady), .C0(\wb_dati[7] ), .B0(\wb_adr_5_i_i_1_0[0] ), .A0(N_307),
+ .F0(\wb_adr_5_i_i_1[0] ), .F1(N_307));
+ SLICE_86 SLICE_86( .D1(\FS[13] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(N_132),
+ .B0(N_133), .A0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F0(\wb_adr_5_i_i_1_0[0] ),
+ .F1(N_133));
+ SLICE_87 SLICE_87( .D1(wb_req), .B1(\FS[0] ), .D0(wb_ack), .C0(N_132),
+ .B0(N_295), .A0(N_330_4), .F0(N_103), .F1(N_295));
+ SLICE_88 SLICE_88( .C1(N_132), .A1(\FS[9] ), .D0(\FS[10] ), .C0(\FS[11] ),
+ .B0(N_375), .A0(\FS[13] ), .F0(N_315), .F1(N_375));
+ SLICE_89 SLICE_89( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[2] ),
+ .A1(\MAin_c[4] ), .D0(un1_ADWR_i_o2_3), .C0(\Bank[2] ), .B0(\Bank[0] ),
+ .A0(un1_ADWR_i_o2_4), .F0(un1_ADWR_i_o2_10), .F1(un1_ADWR_i_o2_4));
+ SLICE_90 SLICE_90( .D1(\IS[0] ), .C1(nRCS_9_u_i_0_0), .B1(N_43), .A1(N_49),
+ .D0(Ready), .C0(RCKE_c), .B0(N_41), .A0(RASr2), .F0(nRCS_9_u_i_0_0),
+ .F1(N_25_i));
+ SLICE_91 SLICE_91( .D1(\FS[6] ), .C1(\FS[7] ), .D0(\FS[8] ),
+ .C0(wb_cyc_stb_2_sqmuxa_i_a2_3_3), .B0(\FS[3] ),
+ .A0(wb_cyc_stb_2_sqmuxa_i_a2_3_4), .F0(N_330_4),
+ .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_3));
+ SLICE_92 SLICE_92( .D1(nRCAS_0_sqmuxa_1), .C1(N_37_i_1), .B1(nRWE_0io_RNO_0),
+ .A1(N_28_i_1), .D0(CASr3), .C0(CASr2), .B0(CO0), .A0(FWEr_fast),
+ .F0(N_37_i_1), .F1(N_37_i));
+ SLICE_93 SLICE_93( .C1(\Din_c[4] ), .A1(\Din_c[0] ), .D0(N_134), .C0(N_371),
+ .B0(N_381), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_a2_0_2), .F1(N_371));
+ SLICE_94 SLICE_94( .D1(\FS[9] ), .A1(\FS[10] ), .D0(\FS[11] ), .C0(\FS[13] ),
+ .B0(N_141), .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_a2_1[6] ), .F1(N_141));
+ SLICE_95 SLICE_95( .D1(PHI2r2), .A1(PHI2r3), .D0(CmdValid_fast),
+ .C0(InitReady), .B0(G_8_0_a3_0_0), .A0(CmdUFMShift), .F0(N_122),
+ .F1(G_8_0_a3_0_0));
+ SLICE_96 SLICE_96( .D1(nRCAS_0io_RNO_1), .C1(FWEr), .B1(CO0), .A1(CBR),
+ .D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(N_242_i_1), .A0(N_39),
+ .F0(N_242_i), .F1(N_242_i_1));
+ SLICE_97 SLICE_97( .D1(PHI2r2), .C1(CmdValid), .A1(PHI2r3), .D0(PHI2r2),
+ .C0(CmdValid), .B0(InitReady), .A0(PHI2r3), .F0(N_94_i), .F1(un1_PHI2r3));
+ SLICE_98 SLICE_98( .D1(\FS[12] ), .C1(\FS[10] ), .B1(\FS[9] ), .D0(\FS[12] ),
+ .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_223),
+ .F1(\wb_adr_5_i_i_a2_6_0[0] ));
+ SLICE_99 SLICE_99( .D1(\FS[14] ), .C1(\FS[13] ), .B1(N_132), .D0(\FS[14] ),
+ .C0(\FS[13] ), .B0(N_132), .A0(N_394), .F0(N_303), .F1(N_367));
+ SLICE_100 SLICE_100( .D1(\FS[11] ), .C1(\FS[13] ), .B1(\FS[12] ),
+ .A1(\FS[14] ), .D0(\FS[11] ), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[14] ),
+ .F0(N_129), .F1(\wb_dati_5_0_iv_0_a2_0[0] ));
+ SLICE_101 SLICE_101( .D1(\FS[11] ), .A1(\FS[12] ), .D0(N_362), .C0(N_125),
+ .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_341), .F1(N_142));
+ SLICE_102 SLICE_102( .D1(\MAin_c[9] ), .A1(nRowColSel), .D0(\MAin_c[9] ),
+ .A0(nRowColSel), .F0(RDQMH_c), .F1(RDQML_c));
+ SLICE_103 SLICE_103( .D1(\FS[10] ), .C1(\FS[17] ), .B1(\FS[16] ),
+ .A1(\FS[15] ), .D0(InitReady), .C0(\FS[17] ), .B0(\FS[16] ), .F0(N_131),
+ .F1(InitReady3_0_a2_2));
+ SLICE_104 SLICE_104( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ),
+ .A1(\Din_c[4] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .F0(N_134),
+ .F1(CmdLEDEN_4_u_i_a2_0_0));
+ SLICE_105 SLICE_105( .B1(FWEr), .A1(CO0), .D0(\S[1] ), .C0(CASr2), .B0(FWEr),
+ .A0(CO0), .F0(RCKEEN_8_u_1), .F1(nRCS_0io_RNO_0));
+ SLICE_106 SLICE_106( .D1(CmdEnable), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ),
+ .A1(N_294), .D0(\MAin_c[0] ), .C0(\Din_c[2] ),
+ .B0(un1_CmdEnable20_0_a2_3_0), .A0(\Din_c[6] ),
+ .F0(un1_CmdEnable20_0_a2_1_0), .F1(XOR8MEG18));
+ SLICE_107 SLICE_107( .D1(\FS[14] ), .C1(N_132), .B1(\FS[13] ), .A1(N_125),
+ .C0(\FS[13] ), .B0(\FS[12] ), .A0(N_383), .F0(N_313), .F1(N_384));
+ SLICE_108 SLICE_108( .D1(InitReady), .C1(\wb_dato[0] ), .A1(Cmdn8MEGEN),
+ .D0(\wb_dati[6] ), .C0(InitReady), .B0(N_132),
+ .A0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F0(\wb_dati_5_1_iv_0_0[7] ),
+ .F1(n8MEGENe_1_0));
+ SLICE_109 SLICE_109( .D1(\RowA[3] ), .C1(nRowColSel), .A1(\MAin_c[3] ),
+ .D0(\MAin_c[6] ), .C0(nFWE_c), .A0(\MAin_c[3] ), .F0(un1_ADWR_i_o2_3),
+ .F1(\RA_c[3] ));
+ SLICE_110 SLICE_110( .D1(\RowA[8] ), .C1(\MAin_c[8] ), .A1(nRowColSel),
+ .C0(nRowColSel), .B0(\MAin_c[9] ), .A0(\RowA[9] ), .F0(\RA_c[9] ),
+ .F1(\RA_c[8] ));
+ SLICE_111 SLICE_111( .D1(nRowColSel), .B1(\MAin_c[0] ), .A1(\RowA[0] ),
+ .D0(nRowColSel), .C0(\RowA[7] ), .B0(\MAin_c[7] ), .F0(\RA_c[7] ),
+ .F1(\RA_c[0] ));
+ SLICE_112 SLICE_112( .D1(nRowColSel), .C1(\RowA[1] ), .A1(\MAin_c[1] ),
+ .D0(\MAin_c[6] ), .C0(nRowColSel), .B0(\RowA[6] ), .F0(\RA_c[6] ),
+ .F1(\RA_c[1] ));
+ SLICE_113 SLICE_113( .D1(\RowA[2] ), .C1(\MAin_c[2] ), .A1(nRowColSel),
+ .D0(\RowA[5] ), .B0(\MAin_c[5] ), .A0(nRowColSel), .F0(\RA_c[5] ),
+ .F1(\RA_c[2] ));
+ SLICE_114 SLICE_114( .C1(\IS[0] ), .D0(\IS[1] ), .C0(\IS[2] ), .A0(\IS[0] ),
+ .F0(nRWE_0io_RNO_1), .F1(\IS_i[0] ));
+ SLICE_115 SLICE_115( .D1(Ready_fast), .A1(\CROW_c[0] ), .D0(Ready_fast),
+ .C0(\Din_c[6] ), .B0(n8MEGEN), .A0(XOR8MEG), .F0(RA11d_0),
+ .F1(\RBAd_0[0] ));
+ SLICE_116 SLICE_116( .D1(InitReady), .B1(\wb_dati[0] ), .C0(PHI2r3),
+ .B0(PHI2r2), .F0(g1_0), .F1(N_302));
+ SLICE_117 SLICE_117( .D1(Ready), .C1(\S[1] ), .B1(CBR_fast), .C0(CASr2),
+ .B0(CASr3), .F0(nRCAS_0io_RNO_1), .F1(N_28_i_1));
RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i),
.RD0(RD[0]));
RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ),
@@ -483,15 +457,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
- nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_248_i), .CLK(RCLK_c));
+ nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_242_i), .CLK(RCLK_c));
nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
- nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_246_i), .CLK(RCLK_c));
+ nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c));
nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
- nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_49_i), .CLK(RCLK_c));
+ nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c));
RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
+ RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout));
+ RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND),
+ .CLK(RCLK_c));
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
- nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_247_i), .CLK(RCLK_c));
+ nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c));
RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i),
.RD7(RD[7]));
RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ),
@@ -931,19 +908,19 @@ module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
endmodule
-module SLICE_10 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_10 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut4 un1_ADWR_i_i_a2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ lut4 ADSubmitted_r_0_RNO( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40003 ADSubmitted_r_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40003 ADSubmitted_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
- (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -959,12 +936,12 @@ endmodule
module lut4 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40003 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4544) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module inverter ( input I, output Z );
@@ -976,7 +953,7 @@ module SLICE_11 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
- lut40004 CmdEnable16_0_a2_1_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40004 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1003,18 +980,18 @@ endmodule
module lut40004 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40005 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFBF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hECEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_12 ( input C0, DI0, M1, CLK, output F0, Q0, Q1 );
+module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
- lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
@@ -1023,7 +1000,7 @@ module SLICE_12 ( input C0, DI0, M1, CLK, output F0, Q0, Q1 );
.LSR(GNDI), .Q(Q0));
specify
- (C0 => F0) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -1036,15 +1013,16 @@ endmodule
module lut40006 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_16 ( input D1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
+module SLICE_16 ( input D1, C1, B1, A1, C0, B0, DI0, LSR, CLK, output F0, Q0,
+ F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
- lut40007 nRowColSel_0_0_0_x2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ lut40007 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40008 \S_RNO[0] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
- lut40008 \S_RNO[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1052,9 +1030,11 @@ module SLICE_16 ( input D1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
@@ -1068,12 +1048,12 @@ endmodule
module lut40007 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40008 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q );
@@ -1086,8 +1066,7 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
- lut40010 un1_CmdEnable20_0_0_a2_0_RNI00E51( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
+ lut40010 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1114,20 +1093,20 @@ endmodule
module lut40010 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40011 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFDEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hEFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_18 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0,
+module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
- lut40012 CmdLEDEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40013 CmdLEDEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+ lut40012 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1139,8 +1118,8 @@ module SLICE_18 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0,
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
@@ -1153,33 +1132,30 @@ endmodule
module lut40012 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2F22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h7530) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40013 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
- wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+module SLICE_19 ( input M0, CE, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
- lut40014 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
+ lut40014 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40015 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
+ vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
- gnd DRIVEGND( .PWR0(GNDI));
specify
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
- $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
@@ -1187,24 +1163,30 @@ endmodule
module lut40014 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAE0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_21 ( input C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
- F1 );
- wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+module lut40015 ( input A, B, C, D, output Z );
- lut40015 CmdUFMWrite_3_u_0_0_0_a3( .A(A1), .B(GNDI), .C(C1), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40016 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
+ ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
+ F0, Q0, F1 );
+ wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+ lut40016 un1_CmdEnable20_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40017 CmdUFMShift_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+ gnd DRIVEGND( .PWR0(GNDI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -1219,21 +1201,59 @@ module SLICE_21 ( input C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
endmodule
-module lut40015 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
module lut40016 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
+module lut40017 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
+ F1 );
+ wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
+
+ lut40018 CmdUFMWrite_3_u_0_a2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40019 CmdUFMWrite_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+ endspecify
+
+endmodule
+
+module lut40018 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40017 CmdValid_2_i_o2_1_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40018 CmdValid_r( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40020 CmdValid_2_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40021 CmdValid_r( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1246,7 +1266,7 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
@@ -1255,21 +1275,21 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40017 ( input A, B, C, D, output Z );
+module lut40020 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFF75) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40018 ( input A, B, C, D, output Z );
+module lut40021 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_23 ( input D1, C1, B1, A1, D0, B0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_23 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40019 CmdUFMData_1_sqmuxa_0_a3_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40020 CmdValid_r_fast( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ lut40022 CmdEnable_RNI7PMB1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40023 CmdValid_r_fast( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1281,8 +1301,8 @@ module SLICE_23 ( input D1, C1, B1, A1, D0, B0, DI0, CLK, output F0, Q0, F1 );
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
@@ -1291,22 +1311,22 @@ module SLICE_23 ( input D1, C1, B1, A1, D0, B0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40019 ( input A, B, C, D, output Z );
+module lut40022 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40020 ( input A, B, C, D, output Z );
+module lut40023 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
- lut40021 Cmdn8MEGEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40022 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40024 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40025 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
@@ -1330,31 +1350,31 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
endmodule
-module lut40021 ( input A, B, C, D, output Z );
+module lut40024 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40022 ( input A, B, C, D, output Z );
+module lut40025 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0D0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_25 ( input C1, B1, C0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_25 ( input D1, A1, D0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
- lut40023 nCCAS_pad_RNI01SJ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40026 nCCAS_pad_RNI01SJ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40006 FWEr_RNO( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40006 nFWE_pad_RNI420B( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
@@ -1363,25 +1383,61 @@ module SLICE_25 ( input C1, B1, C0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40023 ( input A, B, C, D, output Z );
+module lut40026 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_26 ( input C1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_26 ( input C1, A1, D0, C0, M0, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly;
+
+ lut40027 \RBAd[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40028 XOR8MEG_3_u_0_a2_2( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+ vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+ endspecify
+
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40024 RCKEEN_8_u_0_0_o2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ lut40029 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
+ .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40025 \IS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40030 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
- (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -1391,23 +1447,23 @@ module SLICE_26 ( input C1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40024 ( input A, B, C, D, output Z );
+module lut40029 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40025 ( input A, B, C, D, output Z );
+module lut40030 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hA5A5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_27 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0,
+module SLICE_28 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40026 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ lut40031 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40007 IS_n1_0_x2_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+ lut40032 IS_n1_0_x2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1415,10 +1471,10 @@ module SLICE_27 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0,
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
@@ -1431,22 +1487,30 @@ module SLICE_27 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0,
endmodule
-module lut40026 ( input A, B, C, D, output Z );
+module lut40031 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+module lut40032 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h5A5A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
+ Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
- lut40027 RA10_0io_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40033 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40028 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40034 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -1461,21 +1525,21 @@ module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
endmodule
-module lut40027 ( input A, B, C, D, output Z );
+module lut40033 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40028 ( input A, B, C, D, output Z );
+module lut40034 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h6CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_29 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_30 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40029 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40030 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40035 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40036 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1496,30 +1560,30 @@ module SLICE_29 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40029 ( input A, B, C, D, output Z );
+module lut40035 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40030 ( input A, B, C, D, output Z );
+module lut40036 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_31 ( input D1, C1, B1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40031 LEDEN_6_i_m2_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40037 LEDEN_6_i_m2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40032 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40038 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -1531,21 +1595,23 @@ module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40031 ( input A, B, C, D, output Z );
+module lut40037 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40032 ( input A, B, C, D, output Z );
+module lut40038 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_31 ( input C0, A0, M1, M0, CLK, output F0, Q0, Q1 );
+module SLICE_32 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
+ F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
- lut40033 \RBAd[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40039 \un9_RA_i_m2[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
+ lut40040 un1_ADWR_i_o2_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1553,7 +1619,12 @@ module SLICE_31 ( input C0, A0, M1, M0, CLK, output F0, Q0, Q1 );
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
@@ -1565,17 +1636,22 @@ module SLICE_31 ( input C0, A0, M1, M0, CLK, output F0, Q0, Q1 );
endmodule
-module lut40033 ( input A, B, C, D, output Z );
+module lut40039 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
+module lut40040 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_33 ( input D1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
- lut40034 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40041 LED_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40027 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40042 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1583,7 +1659,7 @@ module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
.LSR(GNDI), .Q(Q0));
specify
- (C1 => F1) = (0:0:0,0:0:0);
+ (D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -1597,28 +1673,38 @@ module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
endmodule
-module lut40034 ( input A, B, C, D, output Z );
+module lut40041 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_33 ( input D1, B1, A1, C0, B0, M0, CLK, output F0, Q0, F1 );
- wire GNDI, VCCI, M0_dly, CLK_dly;
+module lut40042 ( input A, B, C, D, output Z );
- lut40035 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40036 CmdEnable_0_sqmuxa_0_a3_0_a3( .A(GNDI), .B(B0), .C(C0), .D(GNDI),
+ ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
+ F1 );
+ wire VCCI, GNDI, M0_dly, CLK_dly;
+
+ lut40043 wb_cyc_stb_2_sqmuxa_i_a2_3_4( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40044 \wb_dati_5_1_iv_0_a2_1_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0));
vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
@@ -1627,22 +1713,22 @@ module SLICE_33 ( input D1, B1, A1, C0, B0, M0, CLK, output F0, Q0, F1 );
endmodule
-module lut40035 ( input A, B, C, D, output Z );
+module lut40043 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAACC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40036 ( input A, B, C, D, output Z );
+module lut40044 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
+module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
- lut40037 RCKEEN_8_u_0_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40038 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40045 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40046 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1665,28 +1751,28 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
endmodule
-module lut40037 ( input A, B, C, D, output Z );
+module lut40045 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h444E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40038 ( input A, B, C, D, output Z );
+module lut40046 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_35 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_36 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40018 RASr2_RNI6PUF( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ lut40047 nRWE_0io_RNO_2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40039 RCKE_2_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40048 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
- (C1 => F1) = (0:0:0,0:0:0);
+ (D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -1700,18 +1786,23 @@ module SLICE_35 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40039 ( input A, B, C, D, output Z );
+module lut40047 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_36 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
+module lut40048 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hAAF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_37 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40040 Ready_0_sqmuxa_0_a2_4_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ lut40049 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40041 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40050 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1732,21 +1823,21 @@ module SLICE_36 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
endmodule
-module lut40040 ( input A, B, C, D, output Z );
+module lut40049 ( input A, B, C, D, output Z );
ROM16X1A #(16'h77FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40041 ( input A, B, C, D, output Z );
+module lut40050 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_37 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
+module SLICE_38 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40042 Ready_0_sqmuxa_0_a2_4_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40030 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40051 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40036 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1767,17 +1858,17 @@ module SLICE_37 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
endmodule
-module lut40042 ( input A, B, C, D, output Z );
+module lut40051 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_38 ( input B1, A1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_39 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40043 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40052 \RowAd[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40044 \RowAd[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+ lut40052 \RowAd[0] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1786,7 +1877,73 @@ module SLICE_38 ( input B1, A1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ (CLK => Q1) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+ $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ endspecify
+
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_40 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+ wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
+
+ lut40053 \RowAd[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40053 \RowAd[2] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+ vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ (CLK => Q1) = (0:0:0,0:0:0);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+ $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ endspecify
+
+endmodule
+
+module lut40053 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_41 ( input D1, A1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+ wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
+
+ lut40054 \RowAd[5] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40018 \RowAd[4] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+ vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+ vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
+ .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -1800,83 +1957,17 @@ module SLICE_38 ( input B1, A1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module lut40043 ( input A, B, C, D, output Z );
+module lut40054 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40044 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module SLICE_42 ( input D1, C1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40043 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40055 \RowAd[7] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40043 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
- vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
- vcc DRIVEVCC( .PWR1(VCCI));
- inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
- vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- (CLK => Q1) = (0:0:0,0:0:0);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
- $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
- endspecify
-
-endmodule
-
-module SLICE_40 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
- wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
- lut40045 \RowAd[5] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40033 \RowAd[4] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
- vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
- vcc DRIVEVCC( .PWR1(VCCI));
- inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
- vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- (CLK => Q1) = (0:0:0,0:0:0);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
- $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
- endspecify
-
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
- wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
- lut40044 \RowAd[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40033 \RowAd[6] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+ lut40055 \RowAd[6] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1886,9 +1977,9 @@ module SLICE_41 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
specify
(D1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
@@ -1899,12 +1990,17 @@ module SLICE_41 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module SLICE_42 ( input C1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
+module lut40055 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_43 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
- lut40046 \RowAd[9] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ lut40056 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40047 \RowAd[8] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40057 \RowAd[8] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -1913,7 +2009,7 @@ module SLICE_42 ( input C1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
- (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -1927,22 +2023,22 @@ module SLICE_42 ( input C1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
endmodule
-module lut40046 ( input A, B, C, D, output Z );
+module lut40056 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40047 ( input A, B, C, D, output Z );
+module lut40057 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
+module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
- lut40048 Ready_0_sqmuxa_0_a2_4_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40049 \S_0_i_o2_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+ lut40004 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40058 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
@@ -1967,22 +2063,17 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
endmodule
-module lut40048 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
+module lut40058 ( input A, B, C, D, output Z );
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
+module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
- lut40050 XOR8MEG_3_u_0_0_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40051 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40059 XOR8MEG_3_u_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40060 XOR8MEG_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2007,22 +2098,22 @@ module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
endmodule
-module lut40050 ( input A, B, C, D, output Z );
+module lut40059 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40051 ( input A, B, C, D, output Z );
+module lut40060 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF2FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0,
+module SLICE_46 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
- lut40052 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40053 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+ lut40061 CmdValid_RNITBH02( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40062 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -2044,30 +2135,31 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0,
endmodule
-module lut40052 ( input A, B, C, D, output Z );
+module lut40061 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40053 ( input A, B, C, D, output Z );
+module lut40062 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_46 ( input D1, B1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
- F1 );
- wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
+ F0, Q0, F1 );
+ wire VCCI, DI0_dly, CLK_dly, LSR_dly;
- lut40054 nRowColSel_0_0_0_a2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40055 nRowColSel_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40063 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40064 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -2083,22 +2175,22 @@ module SLICE_46 ( input D1, B1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
endmodule
-module lut40054 ( input A, B, C, D, output Z );
+module lut40063 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40055 ( input A, B, C, D, output Z );
+module lut40064 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40056 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40057 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40065 \wb_adr_5_i_i[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40066 \wb_adr_5_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2126,23 +2218,23 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40056 ( input A, B, C, D, output Z );
+module lut40065 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40057 ( input A, B, C, D, output Z );
+module lut40066 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_48 ( input B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
+module SLICE_49 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40058 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40018 \wb_adr_5[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40059 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+ lut40067 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2150,9 +2242,9 @@ module SLICE_48 ( input B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
- (B1 => F1) = (0:0:0,0:0:0);
+ (D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
@@ -2165,37 +2257,30 @@ module SLICE_48 ( input B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
endmodule
-module lut40058 ( input A, B, C, D, output Z );
+module lut40067 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40059 ( input A, B, C, D, output Z );
+module SLICE_50 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0,
+ Q0, F1, Q1 );
+ wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
- output F0, Q0, F1, Q1 );
- wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
- lut40060 \wb_adr_5_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40060 \wb_adr_5_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40068 \wb_adr_5_i_m2_0[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40068 \wb_adr_5_i_m2_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
- gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
@@ -2208,18 +2293,18 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40060 ( input A, B, C, D, output Z );
+module lut40068 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8D88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hA0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_50 ( input D1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
- Q0, F1, Q1 );
+module SLICE_51 ( input D1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
+ F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40059 \wb_adr_5[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ lut40052 \wb_adr_5[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40061 \wb_adr_5_i_m2_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40069 \wb_adr_5_i_m2_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2228,8 +2313,7 @@ module SLICE_50 ( input D1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
specify
(D1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -2244,17 +2328,17 @@ module SLICE_50 ( input D1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
endmodule
-module lut40061 ( input A, B, C, D, output Z );
+module lut40069 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAE04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h8F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
+module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
- lut40062 wb_cyc_stb_4_iv_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40063 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40070 wb_cyc_stb_4_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40071 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2280,22 +2364,22 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
endmodule
-module lut40062 ( input A, B, C, D, output Z );
+module lut40070 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40063 ( input A, B, C, D, output Z );
+module lut40071 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40064 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40065 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40072 \wb_dati_5_1_iv_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40073 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2323,72 +2407,31 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40064 ( input A, B, C, D, output Z );
+module lut40072 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40065 ( input A, B, C, D, output Z );
+module lut40073 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_53 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output
- F0, Q0, F1, Q1 );
- wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+ output F0, Q0, F1, Q1 );
+ wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40066 \wb_dati_5_1_iv_i_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40067 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
+ lut40074 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40075 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- (CLK => Q1) = (0:0:0,0:0:0);
- $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
- $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
- $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- endspecify
-
-endmodule
-
-module lut40066 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
- F0, Q0, F1, Q1 );
- wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
- lut40068 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40069 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
- .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
- vcc DRIVEVCC( .PWR1(VCCI));
- vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
- .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
- specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
@@ -2407,22 +2450,64 @@ module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
endmodule
-module lut40068 ( input A, B, C, D, output Z );
+module lut40074 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40069 ( input A, B, C, D, output Z );
+module lut40075 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF4A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
+module SLICE_55 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
+ F0, Q0, F1, Q1 );
+ wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+ lut40076 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40077 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+ vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
+ .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+ vcc DRIVEVCC( .PWR1(VCCI));
+ vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
+ .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ (CLK => Q0) = (0:0:0,0:0:0);
+ (CLK => Q1) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+ $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+ $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ endspecify
+
+endmodule
+
+module lut40076 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40077 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
- lut40070 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40071 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40078 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40079 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2450,22 +2535,22 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
endmodule
-module lut40070 ( input A, B, C, D, output Z );
+module lut40078 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFB3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40071 ( input A, B, C, D, output Z );
+module lut40079 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_56 ( input D1, C1, B1, A1, D0, B0, A0, DI0, LSR, CLK, output F0,
+module SLICE_57 ( input D1, C1, B1, A1, D0, C0, A0, DI0, LSR, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
- lut40072 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40073 wb_reqe( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ lut40080 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40081 wb_reqe( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
@@ -2477,7 +2562,7 @@ module SLICE_56 ( input D1, C1, B1, A1, D0, B0, A0, DI0, LSR, CLK, output F0,
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -2490,22 +2575,22 @@ module SLICE_56 ( input D1, C1, B1, A1, D0, B0, A0, DI0, LSR, CLK, output F0,
endmodule
-module lut40072 ( input A, B, C, D, output Z );
+module lut40080 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40073 ( input A, B, C, D, output Z );
+module lut40081 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
+module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
- lut40074 \FS_RNIHVJI_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40075 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40082 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40083 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2528,22 +2613,22 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
endmodule
-module lut40074 ( input A, B, C, D, output Z );
+module lut40082 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40075 ( input A, B, C, D, output Z );
+module lut40083 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hE222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h30AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
+module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
- lut40076 \wb_adr_5_i_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40077 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40084 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40085 wb_we_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -2569,151 +2654,20 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
endmodule
-module lut40076 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h88D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0,
- M0, output OFX0 );
- wire
- \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ,
- \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ;
-
- lut40078 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1),
- .D(D1),
- .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ));
- lut40079 \wb_dati_5_1_iv_0_o3[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ));
- selmux2 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K0K1MUX (
- .D0(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ),
- .D1(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ),
- .SD(M0), .Z(OFX0));
-
- specify
- (D1 => OFX0) = (0:0:0,0:0:0);
- (C1 => OFX0) = (0:0:0,0:0:0);
- (B1 => OFX0) = (0:0:0,0:0:0);
- (A1 => OFX0) = (0:0:0,0:0:0);
- (D0 => OFX0) = (0:0:0,0:0:0);
- (C0 => OFX0) = (0:0:0,0:0:0);
- (B0 => OFX0) = (0:0:0,0:0:0);
- (A0 => OFX0) = (0:0:0,0:0:0);
- (M0 => OFX0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
- MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40080 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40081 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hF0F1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_61 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
- wire GNDI;
-
- lut40082 un1_nRCAS_6_sqmuxa_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40083 nRCAS_r_i_0_o2_0_2_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40082 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h7772) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40083 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40084 \wb_adr_5_i_0_a2_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40085 wb_we_0_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
module lut40084 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40085 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40086 wb_we_0_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40087 wb_we_0_i_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40086 \wb_dati_5_1_iv_0_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40087 \wb_dati_5_1_iv_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2730,18 +2684,18 @@ endmodule
module lut40086 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF8FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40087 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40088 un1_CmdEnable20_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40089 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40088 wb_cyc_stb_2_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40089 \wb_adr_5_i_i_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2758,18 +2712,18 @@ endmodule
module lut40088 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40089 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40090 \wb_adr_5_i_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40091 \wb_adr_5_i_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40090 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40091 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2786,18 +2740,18 @@ endmodule
module lut40090 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hBAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40091 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h45EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40092 \FS_RNIHVJI[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40093 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40092 wb_we_0_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40093 wb_we_0_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2814,20 +2768,18 @@ endmodule
module lut40092 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40093 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40094 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40095 \wb_adr_5_i_0_o2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
+ lut40094 CmdEnable_0_sqmuxa_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40095 un1_CmdEnable20_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -2835,6 +2787,7 @@ module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
@@ -2843,53 +2796,52 @@ endmodule
module lut40094 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h53F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40095 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1199) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hC0D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_68 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
- wire GNDI;
+module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40096 \FS_RNIF2MA[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40097 \ufmefb/EFBInst_0_RNISI191 ( .A(GNDI), .B(B0), .C(C0), .D(D0),
- .Z(F0));
+ lut40096 \wb_adr_5_i_i_0_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40097 \wb_adr_5_i_i_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40096 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40097 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_66 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40098 \wb_dati_5_1_iv_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40099 \wb_dati_5_1_iv_0_a3_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
+ lut40098 \wb_adr_5_i_i_a2_3_0[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40099 \wb_adr_5_i_i_1_0_tz_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -2901,19 +2853,21 @@ endmodule
module lut40098 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40099 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_70 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
wire GNDI;
- lut40100 \wb_adr_5_i_0_a3_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40101 \FS_RNIJO0F[14] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ lut40100 wb_cyc_stb_2_sqmuxa_i_o2_RNI167R( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40101 \ufmefb/EFBInst_0_RNI8K48 ( .A(A0), .B(B0), .C(GNDI), .D(D0),
+ .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
specify
@@ -2930,20 +2884,19 @@ endmodule
module lut40100 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40101 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
+module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
- lut40102 \wb_dati_5_1_iv_i_i_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40103 \wb_dati_5_1_iv_i_i_1_RNO[3] ( .A(A0), .B(GNDI), .C(C0), .D(D0),
- .Z(F0));
+ lut40102 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40103 \S_RNICVV51[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
specify
@@ -2953,26 +2906,27 @@ module SLICE_71 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40102 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40103 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_72 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+module SLICE_69 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
wire GNDI;
- lut40104 nRCS_9_u_i_0_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40105 Ready_RNICVV51( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ lut40104 \wb_dati_5_1_iv_0_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40105 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(GNDI), .D(D0),
+ .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
specify
@@ -2989,26 +2943,28 @@ endmodule
module lut40104 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h5515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40105 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h99DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40106 \wb_dati_5_1_iv_i_i_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40107 \wb_dati_5_1_iv_i_i_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ lut40106 \wb_dati_5_1_iv_0_a2_3_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1),
+ .Z(F1));
+ lut40107 \wb_dati_5_1_iv_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
.Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
@@ -3018,26 +2974,24 @@ endmodule
module lut40106 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40107 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_71 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40108 un1_nRCAS_6_sqmuxa_i_0_0_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI),
- .Z(F1));
+ lut40108 wb_we_0_0_0_a2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40109 un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER( .A(A0), .B(B0), .C(C0),
- .D(D0), .Z(F0));
+ lut40109 wb_we_0_0_0_a2_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3049,23 +3003,24 @@ endmodule
module lut40108 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40109 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h71F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_75 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40110 \wb_adr_5_i_0_a2_0[1] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40111 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40110 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40111 \wb_dati_5_1_iv_0_a2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3077,139 +3032,31 @@ endmodule
module lut40110 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40111 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0C8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
+ Q0, F1, Q1 );
+ wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
- lut40112 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40056 \wb_dati_5_1_iv_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40112 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0251) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40113 \FS_RNIGOCT[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40114 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40113 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40114 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0C04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40115 nRCS_9_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40116 nRRAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40115 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0504) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40116 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h010F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40117 nRCS_9_u_i_0_o2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40118 nRCS_9_u_i_0_o2_1_RNIL2K71_0( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40117 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40118 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
- F1, Q1 );
- wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
-
- lut40119 un1_CmdEnable20_0_0_a3_1_1( .A(A1), .B(B1), .C(GNDI), .D(D1),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40120 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40112 un1_CmdEnable20_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40113 CmdEnable17_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
+ gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN),
.LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
@@ -3226,26 +3073,25 @@ module SLICE_80 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
endmodule
-module lut40119 ( input A, B, C, D, output Z );
+module lut40112 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40120 ( input A, B, C, D, output Z );
+module lut40113 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0405) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_81 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40121 RCKEEN_8_u_0_0_a2_2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40122 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40114 CmdUFMData_1_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40115 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3255,173 +3101,274 @@ module SLICE_81 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
-module lut40121 ( input A, B, C, D, output Z );
+module lut40114 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40122 ( input A, B, C, D, output Z );
+module lut40115 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_82 ( input D1, C1, B1, A1, C0, B0, M0, CE, CLK, output F0, Q0, F1 );
- wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
+module SLICE_75 ( input D1, C1, B1, A1, D0, B0, output F0, F1 );
+ wire GNDI;
- lut40123 CmdLEDEN_4_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40036 CmdUFMData_1_sqmuxa_0_a3( .A(GNDI), .B(B0), .C(C0), .D(GNDI),
- .Z(F0));
+ lut40090 un1_ADWR_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40116 XOR8MEG18_0_a2_0( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
- vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
- .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
- vcc DRIVEVCC( .PWR1(VCCI));
- inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40116 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_76 ( input C1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 );
+ wire GNDI, VCCI, M0_dly, CLK_dly;
+
+ lut40027 CmdEnable_0_sqmuxa_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40117 CmdEnable_0_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
+ .LSR(GNDI), .Q(Q0));
+ vcc DRIVEVCC( .PWR1(VCCI));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
- $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
- $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+ endspecify
+
+endmodule
+
+module lut40117 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40118 \wb_adr_5_i_i_a2_6[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40119 \wb_adr_5_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40118 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40119 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_78 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40120 IS_0_sqmuxa_0_o2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40121 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40120 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40121 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_79 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40103 \wb_adr_5_i_i_a2_11[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40122 \wb_dati_5_1_iv_0_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40122 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40123 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40124 \wb_dati_5_1_iv_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40123 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40124 nRCAS_r_i_0_a2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40125 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40124 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40125 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40126 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40125 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40126 un1_CmdEnable20_0_0_o3_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40127 un1_CmdEnable20_0_0_o3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h1115) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40126 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hCFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_82 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40127 \wb_dati_5_1_iv_0_a2_2[6] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40128 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40127 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40128 \wb_dati_5_1_iv_0_a3_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40129 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40128 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40129 \wb_dati_5_1_iv_0_a2_9[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40130 \wb_dati_5_1_iv_0_o2_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40129 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40130 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40131 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40130 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40131 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_87 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_84 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40132 \wb_dati_5_1_iv_i_i_a2_4[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1),
- .Z(F1));
+ lut40131 \FS_RNICHC8[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40133 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40132 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -3430,20 +3377,20 @@ module SLICE_87 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40131 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40132 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40133 ( input A, B, C, D, output Z );
+module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40134 nRCS_9_u_i_0_o2_1_RNIL2K71( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40135 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40133 \wb_adr_5_i_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40134 \wb_adr_5_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -3458,27 +3405,27 @@ module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40133 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40134 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40135 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_86 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40136 \wb_dati_5_1_iv_0_o2_0[7] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1),
+ lut40135 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40137 \wb_dati_5_1_iv_0_a3[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40136 \wb_adr_5_i_i_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -3487,25 +3434,50 @@ module SLICE_89 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40135 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40136 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFF0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0A0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_87 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40137 wb_cyc_stb_2_sqmuxa_i_o2_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40079 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40137 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_88 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40138 nRWE_s_i_0_a3_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40139 nRWE_s_i_0_tz_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40138 \wb_dati_5_1_iv_0_a2_7[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40094 \wb_adr_5_i_i_a2_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3517,19 +3489,13 @@ endmodule
module lut40138 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40139 ( input A, B, C, D, output Z );
+module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40140 \wb_dati_5_1_iv_i_i_a3_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- lut40141 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40139 un1_ADWR_i_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40140 un1_ADWR_i_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -3544,28 +3510,26 @@ module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40139 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40140 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40141 ( input A, B, C, D, output Z );
+module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_92 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40142 wb_cyc_stb_2_sqmuxa_i_a3_0( .A(GNDI), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40143 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40141 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40142 nRCS_9_u_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -3574,20 +3538,44 @@ module SLICE_92 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40141 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0C0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40142 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_91 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40028 wb_cyc_stb_2_sqmuxa_i_a2_3_3( .A(GNDI), .B(GNDI), .C(C1), .D(D1),
+ .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40143 wb_cyc_stb_2_sqmuxa_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40143 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40144 un1_CmdEnable20_0_0_o3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40145 un1_CmdEnable20_0_0_o3_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40144 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40145 nRWE_s_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
@@ -3604,23 +3592,23 @@ endmodule
module lut40144 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFF4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40145 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_93 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- lut40146 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40147 nRCAS_r_i_0_o2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40146 XOR8MEG_3_u_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40147 XOR8MEG_3_u_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
- (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3632,25 +3620,26 @@ endmodule
module lut40146 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40147 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_95 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_94 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40148 \wb_dati_5_1_iv_i_i_a2_2[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1),
+ lut40054 \wb_dati_5_1_iv_0_o2_0[6] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40149 wb_we_0_i_0_a3_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40148 \wb_dati_5_1_iv_0_a2_1_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0),
+ .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -3661,23 +3650,41 @@ endmodule
module lut40148 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h1001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_95 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40047 PHI2r3_RNIFT0I_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40149 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40149 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h8F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_96 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut4 \wb_adr_5_i_0_a2_1[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40150 \wb_adr_5_i_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40150 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40151 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3689,119 +3696,83 @@ endmodule
module lut40150 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hC800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_97 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40151 \FS_RNIH267[16] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40152 \wb_adr_5_i_0_m2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40151 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_97 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40152 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40153 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40152 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hAA0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_98 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40153 wb_cyc_stb_4_iv_0_a3_0_2_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40154 wb_cyc_stb_4_iv_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40153 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40154 \wb_adr_5_i_i_a2_6_0[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40155 \wb_dati_5_1_iv_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40154 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40047 CmdLEDEN_4_u_i_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40155 un1_CmdEnable20_0_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40155 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2A90) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_100 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+module SLICE_99 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40030 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+ lut40156 \FS_RNI1FVB[14] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40107 XOR8MEG_3_u_0_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40157 \wb_dati_5_1_iv_0_a2_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40156 \wb_dati_5_1_iv_0_a2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40157 \wb_dati_5_1_iv_0_a3_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
- .Z(F0));
-
- specify
(B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
@@ -3812,24 +3783,24 @@ endmodule
module lut40156 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40157 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_102 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
+module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
- lut40015 \wb_dati_5_0_iv_0_a2[0] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI),
+ lut40158 \wb_dati_5_0_iv_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40158 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40159 \wb_dati_5_1_iv_0_0_o2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -3841,228 +3812,210 @@ endmodule
module lut40158 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_103 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40159 PHI2r3_RNIFT0I_0( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40160 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40159 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_101 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40160 \FS_RNI7O57[11] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40161 \wb_dati_5_1_iv_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40160 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_104 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40161 \FS_RNIVOOA[14] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40162 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40161 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_102 ( input D1, A1, D0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40160 RDQML_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40135 RDQMH_pad_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+ wire GNDI;
+
+ lut40162 InitReady3_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40163 \FS_RNIQV0F[16] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40162 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_105 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40163 \wb_adr_5_i_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40164 wb_we_0_i_0_0_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40163 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_104 ( input D1, C1, B1, A1, D0, C0, output F0, F1 );
+ wire GNDI;
+
+ lut40164 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40165 XOR8MEG_3_u_0_o2_1( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40164 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_106 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40165 \wb_adr_5_i_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40166 \wb_adr_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40165 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hA022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40166 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40167 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40166 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
- F1 );
- wire GNDI, VCCI, M0_dly, CLK_dly;
-
- lut40167 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40168 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
- vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
- .LSR(GNDI), .Q(Q0));
- vcc DRIVEVCC( .PWR1(VCCI));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- (CLK => Q0) = (0:0:0,0:0:0);
- $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
- $width (posedge CLK, 0:0:0);
- $width (negedge CLK, 0:0:0);
- endspecify
-
+ ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40167 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4CBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+
+ lut40168 XOR8MEG18_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40169 un1_CmdEnable20_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40168 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40169 RCKEEN_8_u_0_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40170 nRWE_s_i_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40169 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h75A5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_107 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40170 \FS_RNITL2J[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40171 \wb_adr_5_i_i_a2_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
endmodule
module lut40170 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_109 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
- wire GNDI;
-
- lut40171 \wb_dati_5_1_iv_i_i_a3_1_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
- .Z(F1));
- lut40172 \wb_adr_5_i_0_o2_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40171 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40172 ( input A, B, C, D, output Z );
+module SLICE_108 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
- ROM16X1A #(16'hA0F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
- lut40173 \wb_adr_5_i_0_a3_0_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40174 \wb_dati_5_1_iv_i_i_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40172 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40173 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
@@ -4072,76 +4025,84 @@ module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
endmodule
+module lut40172 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h550F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
module lut40173 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40174 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_111 ( input C1, B1, C0, B0, output F0, F1 );
+module SLICE_109 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
wire GNDI;
- lut40175 RDQML_0_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40176 RDQMH_pad_RNO( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
- specify
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40175 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40176 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_112 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
- wire GNDI;
-
- lut40100 un1_CmdEnable20_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40177 XOR8MEG_3_u_0_0_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40174 \un9_RA_i_m2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
+ lut40175 un1_ADWR_i_o2_3( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
-module lut40177 ( input A, B, C, D, output Z );
+module lut40174 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_113 ( input B1, A1, C0, B0, output F0, F1 );
+module lut40175 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hF5FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_110 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
- lut40178 \FS_RNI7U6M[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+ lut40176 \un9_RA[8] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40179 \wb_dati_5_1_iv_i_i_a2_3[3] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI),
- .Z(F0));
+ lut40177 \un9_RA_i_m2[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40176 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40177 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_111 ( input D1, B1, A1, D0, C0, B0, output F0, F1 );
+ wire GNDI;
+
+ lut40178 \un9_RA_i_m2[0] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40179 \un9_RA_i_m2[7] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
@@ -4150,55 +4111,55 @@ endmodule
module lut40178 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40179 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+module SLICE_112 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
- lut40180 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40180 \un9_RA_i_m2[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40181 un1_CmdEnable20_0_0_o3_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+ lut40181 \un9_RA_i_m2[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
+ (D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40180 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40181 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_115 ( input D1, B1, A1, D0, C0, A0, output F0, F1 );
+module SLICE_113 ( input D1, C1, A1, D0, B0, A0, output F0, F1 );
wire GNDI;
- lut40182 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ lut40176 \un9_RA_i_m2[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40183 \un9_RA[8] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+ lut40182 \un9_RA_i_m2[5] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
+ (B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
@@ -4209,74 +4170,88 @@ module lut40182 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module lut40183 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_116 ( input D1, C1, B1, D0, B0, A0, output F0, F1 );
+module SLICE_114 ( input C1, D0, C0, A0, output F0, F1 );
wire GNDI;
- lut40184 \un9_RA_i_m2_i_m2[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+ lut40183 RA10_0io_RNO( .A(GNDI), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40035 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+ lut40184 nRWE_0io_RNO_1( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+
+ specify
+ (C1 => F1) = (0:0:0,0:0:0);
+ (D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
+ (A0 => F0) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module lut40183 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40184 ( input A, B, C, D, output Z );
+
+ ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_115 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+ wire GNDI;
+
+ lut40018 \RBAd[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+ gnd DRIVEGND( .PWR0(GNDI));
+ lut40185 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
+ (A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
+ (C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
-module lut40184 ( input A, B, C, D, output Z );
+module lut40185 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hF3C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h9A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_117 ( input C1, B1, A1, D0, C0, B0, output F0, F1 );
+module SLICE_116 ( input D1, B1, C0, B0, output F0, F1 );
wire GNDI;
- lut40185 \un9_RA_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+ lut40053 \wb_dati_5_1_iv_0_a2_1[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1),
+ .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40186 \un9_RA_i_m2_i_m2[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40186 PHI2r3_RNIFT0I( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
- (C1 => F1) = (0:0:0,0:0:0);
+ (D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
-module lut40185 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
module lut40186 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hFC30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
-module SLICE_118 ( input D1, B1, A1, D0, C0, B0, output F0, F1 );
+module SLICE_117 ( input D1, C1, B1, C0, B0, output F0, F1 );
wire GNDI;
- lut40035 \un9_RA_i_m2_i_m2[4] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+ lut40187 RCKEEN_8_u_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
- lut40187 \un9_RA_i_m2_i_m2[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+ lut40188 nRCAS_0io_RNO_1( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
+ (C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
@@ -4285,135 +4260,12 @@ endmodule
module lut40187 ( input A, B, C, D, output Z );
- ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_119 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
- wire GNDI;
-
- lut40188 CmdLEDEN_4_u_i_0_a3_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
- lut40153 XOR8MEG_3_u_0_0_a2_0( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
- gnd DRIVEGND( .PWR0(GNDI));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- endspecify
-
+ ROM16X1A #(16'h3000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40188 ( input A, B, C, D, output Z );
- ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_120 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40043 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40189 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
- specify
- (B1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40189 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h8288) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_121 ( input D1, B1, D0, C0, A0, output F0, F1 );
- wire GNDI;
-
- lut40190 wb_cyc_stb_4_iv_0_a3_0_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1),
- .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40191 wb_cyc_stb_4_iv_0_a3_0_3( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40190 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40191 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_122 ( input D1, C1, B1, B0, A0, output F0, F1 );
- wire GNDI;
-
- lut40192 n8MEGEN_RNO_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40193 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (C1 => F1) = (0:0:0,0:0:0);
- (B1 => F1) = (0:0:0,0:0:0);
- (B0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40192 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h303F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40193 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_123 ( input D1, A1, D0, C0, A0, output F0, F1 );
- wire GNDI;
-
- lut40194 \wb_adr_5_i_0_o2[1] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
- gnd DRIVEGND( .PWR0(GNDI));
- lut40195 InitReady3_0_a3_1( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-
- specify
- (D1 => F1) = (0:0:0,0:0:0);
- (A1 => F1) = (0:0:0,0:0:0);
- (D0 => F0) = (0:0:0,0:0:0);
- (C0 => F0) = (0:0:0,0:0:0);
- (A0 => F0) = (0:0:0,0:0:0);
- endspecify
-
-endmodule
-
-module lut40194 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40195 ( input A, B, C, D, output Z );
-
- ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+ ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 );
@@ -4462,7 +4314,7 @@ endmodule
module Dout_0_ ( input PADDO, output Dout0 );
- xo2iobuf0196 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
+ xo2iobuf0189 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
specify
(PADDO => Dout0) = (0:0:0,0:0:0);
@@ -4470,14 +4322,14 @@ module Dout_0_ ( input PADDO, output Dout0 );
endmodule
-module xo2iobuf0196 ( input I, output PAD );
+module xo2iobuf0189 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module PHI2 ( output PADDI, input PHI2 );
- xo2iobuf0197 PHI2_pad( .Z(PADDI), .PAD(PHI2));
+ xo2iobuf0190 PHI2_pad( .Z(PADDI), .PAD(PHI2));
specify
(PHI2 => PADDI) = (0:0:0,0:0:0);
@@ -4487,7 +4339,7 @@ module PHI2 ( output PADDI, input PHI2 );
endmodule
-module xo2iobuf0197 ( output Z, input PAD );
+module xo2iobuf0190 ( output Z, input PAD );
IB INST1( .I(PAD), .O(Z));
endmodule
@@ -4517,7 +4369,7 @@ endmodule
module RDQML ( input PADDO, output RDQML );
- xo2iobuf0198 RDQML_pad( .I(PADDO), .PAD(RDQML));
+ xo2iobuf0191 RDQML_pad( .I(PADDO), .PAD(RDQML));
specify
(PADDO => RDQML) = (0:0:0,0:0:0);
@@ -4525,14 +4377,14 @@ module RDQML ( input PADDO, output RDQML );
endmodule
-module xo2iobuf0198 ( input I, output PAD );
+module xo2iobuf0191 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module RDQMH ( input PADDO, output RDQMH );
- xo2iobuf0198 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
+ xo2iobuf0191 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
specify
(PADDO => RDQMH) = (0:0:0,0:0:0);
@@ -4542,7 +4394,7 @@ endmodule
module nRCAS ( input IOLDO, output nRCAS );
- xo2iobuf0198 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
+ xo2iobuf0191 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
specify
(IOLDO => nRCAS) = (0:0:0,0:0:0);
@@ -4553,7 +4405,7 @@ endmodule
module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0199 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0192 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4567,7 +4419,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
endmodule
-module mfflsre0199 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0192 ( input D0, SP, CK, LSR, output Q );
FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
@@ -4575,7 +4427,7 @@ endmodule
module nRRAS ( input IOLDO, output nRRAS );
- xo2iobuf0198 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
+ xo2iobuf0191 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
specify
(IOLDO => nRRAS) = (0:0:0,0:0:0);
@@ -4586,7 +4438,7 @@ endmodule
module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0199 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0192 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4602,7 +4454,7 @@ endmodule
module nRWE ( input IOLDO, output nRWE );
- xo2iobuf0198 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+ xo2iobuf0191 nRWE_pad( .I(IOLDO), .PAD(nRWE));
specify
(IOLDO => nRWE) = (0:0:0,0:0:0);
@@ -4613,7 +4465,7 @@ endmodule
module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0199 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0192 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4629,7 +4481,7 @@ endmodule
module RCKE ( input PADDO, output RCKE );
- xo2iobuf0198 RCKE_pad( .I(PADDO), .PAD(RCKE));
+ xo2iobuf0191 RCKE_pad( .I(PADDO), .PAD(RCKE));
specify
(PADDO => RCKE) = (0:0:0,0:0:0);
@@ -4637,9 +4489,42 @@ module RCKE ( input PADDO, output RCKE );
endmodule
+module RCLKout ( input IOLDO, output RCLKout );
+
+ xo2iobuf0189 RCLKout_pad( .I(IOLDO), .PAD(RCLKout));
+
+ specify
+ (IOLDO => RCLKout) = (0:0:0,0:0:0);
+ endspecify
+
+endmodule
+
+module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK );
+ wire GNDI, ONEG_dly, CLK_dly, OPOS_dly;
+
+ xo2oddr rck( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI),
+ .Q(IOLDO));
+ gnd DRIVEGND( .PWR0(GNDI));
+
+ specify
+ (CLK => IOLDO) = (0:0:0,0:0:0);
+ $setuphold (posedge CLK, ONEG, 0:0:0, 0:0:0,,,, CLK_dly, ONEG_dly);
+ $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+ $width (posedge CLK, 0:0:0);
+ $width (negedge CLK, 0:0:0);
+ endspecify
+
+endmodule
+
+module xo2oddr ( input D0, D1, SCLK, RST, output Q );
+
+ ODDRXE INST1( .D0(D0), .D1(D1), .SCLK(SCLK), .RST(RST), .Q(Q));
+ defparam INST1.GSR = "DISABLED";
+endmodule
+
module RCLK ( output PADDI, input RCLK );
- xo2iobuf0197 RCLK_pad( .Z(PADDI), .PAD(RCLK));
+ xo2iobuf0190 RCLK_pad( .Z(PADDI), .PAD(RCLK));
specify
(RCLK => PADDI) = (0:0:0,0:0:0);
@@ -4651,7 +4536,7 @@ endmodule
module nRCS ( input IOLDO, output nRCS );
- xo2iobuf0198 nRCS_pad( .I(IOLDO), .PAD(nRCS));
+ xo2iobuf0191 nRCS_pad( .I(IOLDO), .PAD(nRCS));
specify
(IOLDO => nRCS) = (0:0:0,0:0:0);
@@ -4662,7 +4547,7 @@ endmodule
module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
- mfflsre0199 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
+ mfflsre0192 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
@@ -4902,7 +4787,7 @@ endmodule
module RA_11_ ( input IOLDO, output RA11 );
- xo2iobuf0198 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+ xo2iobuf0191 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
specify
(IOLDO => RA11) = (0:0:0,0:0:0);
@@ -4929,7 +4814,7 @@ endmodule
module RA_10_ ( input IOLDO, output RA10 );
- xo2iobuf0198 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+ xo2iobuf0191 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
specify
(IOLDO => RA10) = (0:0:0,0:0:0);
@@ -4940,7 +4825,7 @@ endmodule
module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
wire VCCI, OPOS_dly, CLK_dly, LSR_dly;
- mfflsre0200 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
+ mfflsre0193 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
@@ -4954,7 +4839,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
endmodule
-module mfflsre0200 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0193 ( input D0, SP, CK, LSR, output Q );
FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
@@ -4962,7 +4847,7 @@ endmodule
module RA_9_ ( input PADDO, output RA9 );
- xo2iobuf0198 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
+ xo2iobuf0191 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
specify
(PADDO => RA9) = (0:0:0,0:0:0);
@@ -4972,7 +4857,7 @@ endmodule
module RA_8_ ( input PADDO, output RA8 );
- xo2iobuf0198 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
+ xo2iobuf0191 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
specify
(PADDO => RA8) = (0:0:0,0:0:0);
@@ -4982,7 +4867,7 @@ endmodule
module RA_7_ ( input PADDO, output RA7 );
- xo2iobuf0198 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
+ xo2iobuf0191 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
specify
(PADDO => RA7) = (0:0:0,0:0:0);
@@ -4992,7 +4877,7 @@ endmodule
module RA_6_ ( input PADDO, output RA6 );
- xo2iobuf0198 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
+ xo2iobuf0191 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
specify
(PADDO => RA6) = (0:0:0,0:0:0);
@@ -5002,7 +4887,7 @@ endmodule
module RA_5_ ( input PADDO, output RA5 );
- xo2iobuf0198 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
+ xo2iobuf0191 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
specify
(PADDO => RA5) = (0:0:0,0:0:0);
@@ -5012,7 +4897,7 @@ endmodule
module RA_4_ ( input PADDO, output RA4 );
- xo2iobuf0198 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
+ xo2iobuf0191 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
specify
(PADDO => RA4) = (0:0:0,0:0:0);
@@ -5022,7 +4907,7 @@ endmodule
module RA_3_ ( input PADDO, output RA3 );
- xo2iobuf0198 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+ xo2iobuf0191 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
specify
(PADDO => RA3) = (0:0:0,0:0:0);
@@ -5032,7 +4917,7 @@ endmodule
module RA_2_ ( input PADDO, output RA2 );
- xo2iobuf0198 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
+ xo2iobuf0191 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
specify
(PADDO => RA2) = (0:0:0,0:0:0);
@@ -5042,7 +4927,7 @@ endmodule
module RA_1_ ( input PADDO, output RA1 );
- xo2iobuf0198 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
+ xo2iobuf0191 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
specify
(PADDO => RA1) = (0:0:0,0:0:0);
@@ -5052,7 +4937,7 @@ endmodule
module RA_0_ ( input PADDO, output RA0 );
- xo2iobuf0198 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+ xo2iobuf0191 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
specify
(PADDO => RA0) = (0:0:0,0:0:0);
@@ -5062,7 +4947,7 @@ endmodule
module RBA_1_ ( input IOLDO, output RBA1 );
- xo2iobuf0198 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
+ xo2iobuf0191 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
specify
(IOLDO => RBA1) = (0:0:0,0:0:0);
@@ -5090,7 +4975,7 @@ endmodule
module RBA_0_ ( input IOLDO, output RBA0 );
- xo2iobuf0198 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
+ xo2iobuf0191 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
specify
(IOLDO => RBA0) = (0:0:0,0:0:0);
@@ -5118,7 +5003,7 @@ endmodule
module LED ( input PADDO, output LED );
- xo2iobuf0201 LED_pad( .I(PADDO), .PAD(LED));
+ xo2iobuf0194 LED_pad( .I(PADDO), .PAD(LED));
specify
(PADDO => LED) = (0:0:0,0:0:0);
@@ -5126,14 +5011,14 @@ module LED ( input PADDO, output LED );
endmodule
-module xo2iobuf0201 ( input I, output PAD );
+module xo2iobuf0194 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
module nFWE ( output PADDI, input nFWE );
- xo2iobuf0197 nFWE_pad( .Z(PADDI), .PAD(nFWE));
+ xo2iobuf0190 nFWE_pad( .Z(PADDI), .PAD(nFWE));
specify
(nFWE => PADDI) = (0:0:0,0:0:0);
@@ -5145,7 +5030,7 @@ endmodule
module nCRAS ( output PADDI, input nCRAS );
- xo2iobuf0197 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
+ xo2iobuf0190 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
specify
(nCRAS => PADDI) = (0:0:0,0:0:0);
@@ -5157,7 +5042,7 @@ endmodule
module nCCAS ( output PADDI, input nCCAS );
- xo2iobuf0197 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
+ xo2iobuf0190 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
specify
(nCCAS => PADDI) = (0:0:0,0:0:0);
@@ -5169,7 +5054,7 @@ endmodule
module Dout_7_ ( input PADDO, output Dout7 );
- xo2iobuf0196 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
+ xo2iobuf0189 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
specify
(PADDO => Dout7) = (0:0:0,0:0:0);
@@ -5179,7 +5064,7 @@ endmodule
module Dout_6_ ( input PADDO, output Dout6 );
- xo2iobuf0196 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
+ xo2iobuf0189 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
specify
(PADDO => Dout6) = (0:0:0,0:0:0);
@@ -5189,7 +5074,7 @@ endmodule
module Dout_5_ ( input PADDO, output Dout5 );
- xo2iobuf0196 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
+ xo2iobuf0189 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
specify
(PADDO => Dout5) = (0:0:0,0:0:0);
@@ -5199,7 +5084,7 @@ endmodule
module Dout_4_ ( input PADDO, output Dout4 );
- xo2iobuf0196 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
+ xo2iobuf0189 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
specify
(PADDO => Dout4) = (0:0:0,0:0:0);
@@ -5209,7 +5094,7 @@ endmodule
module Dout_3_ ( input PADDO, output Dout3 );
- xo2iobuf0196 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
+ xo2iobuf0189 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
specify
(PADDO => Dout3) = (0:0:0,0:0:0);
@@ -5219,7 +5104,7 @@ endmodule
module Dout_2_ ( input PADDO, output Dout2 );
- xo2iobuf0196 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
+ xo2iobuf0189 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
specify
(PADDO => Dout2) = (0:0:0,0:0:0);
@@ -5229,7 +5114,7 @@ endmodule
module Dout_1_ ( input PADDO, output Dout1 );
- xo2iobuf0196 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
+ xo2iobuf0189 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
specify
(PADDO => Dout1) = (0:0:0,0:0:0);
@@ -5239,7 +5124,7 @@ endmodule
module Din_7_ ( output PADDI, input Din7 );
- xo2iobuf0197 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+ xo2iobuf0190 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
specify
(Din7 => PADDI) = (0:0:0,0:0:0);
@@ -5268,7 +5153,7 @@ endmodule
module Din_6_ ( output PADDI, input Din6 );
- xo2iobuf0197 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+ xo2iobuf0190 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
specify
(Din6 => PADDI) = (0:0:0,0:0:0);
@@ -5297,7 +5182,7 @@ endmodule
module Din_5_ ( output PADDI, input Din5 );
- xo2iobuf0197 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+ xo2iobuf0190 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
specify
(Din5 => PADDI) = (0:0:0,0:0:0);
@@ -5326,7 +5211,7 @@ endmodule
module Din_4_ ( output PADDI, input Din4 );
- xo2iobuf0197 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+ xo2iobuf0190 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
specify
(Din4 => PADDI) = (0:0:0,0:0:0);
@@ -5355,7 +5240,7 @@ endmodule
module Din_3_ ( output PADDI, input Din3 );
- xo2iobuf0197 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+ xo2iobuf0190 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
specify
(Din3 => PADDI) = (0:0:0,0:0:0);
@@ -5384,7 +5269,7 @@ endmodule
module Din_2_ ( output PADDI, input Din2 );
- xo2iobuf0197 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+ xo2iobuf0190 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
specify
(Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5413,7 +5298,7 @@ endmodule
module Din_1_ ( output PADDI, input Din1 );
- xo2iobuf0197 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+ xo2iobuf0190 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
specify
(Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5442,7 +5327,7 @@ endmodule
module Din_0_ ( output PADDI, input Din0 );
- xo2iobuf0197 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+ xo2iobuf0190 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
specify
(Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5471,7 +5356,7 @@ endmodule
module CROW_1_ ( output PADDI, input CROW1 );
- xo2iobuf0197 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
+ xo2iobuf0190 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
specify
(CROW1 => PADDI) = (0:0:0,0:0:0);
@@ -5483,7 +5368,7 @@ endmodule
module CROW_0_ ( output PADDI, input CROW0 );
- xo2iobuf0197 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
+ xo2iobuf0190 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
specify
(CROW0 => PADDI) = (0:0:0,0:0:0);
@@ -5495,7 +5380,7 @@ endmodule
module MAin_9_ ( output PADDI, input MAin9 );
- xo2iobuf0197 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
+ xo2iobuf0190 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
specify
(MAin9 => PADDI) = (0:0:0,0:0:0);
@@ -5507,7 +5392,7 @@ endmodule
module MAin_8_ ( output PADDI, input MAin8 );
- xo2iobuf0197 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
+ xo2iobuf0190 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
specify
(MAin8 => PADDI) = (0:0:0,0:0:0);
@@ -5519,7 +5404,7 @@ endmodule
module MAin_7_ ( output PADDI, input MAin7 );
- xo2iobuf0197 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
+ xo2iobuf0190 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
specify
(MAin7 => PADDI) = (0:0:0,0:0:0);
@@ -5531,7 +5416,7 @@ endmodule
module MAin_6_ ( output PADDI, input MAin6 );
- xo2iobuf0197 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
+ xo2iobuf0190 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
specify
(MAin6 => PADDI) = (0:0:0,0:0:0);
@@ -5543,7 +5428,7 @@ endmodule
module MAin_5_ ( output PADDI, input MAin5 );
- xo2iobuf0197 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
+ xo2iobuf0190 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
specify
(MAin5 => PADDI) = (0:0:0,0:0:0);
@@ -5555,7 +5440,7 @@ endmodule
module MAin_4_ ( output PADDI, input MAin4 );
- xo2iobuf0197 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
+ xo2iobuf0190 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
specify
(MAin4 => PADDI) = (0:0:0,0:0:0);
@@ -5567,7 +5452,7 @@ endmodule
module MAin_3_ ( output PADDI, input MAin3 );
- xo2iobuf0197 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
+ xo2iobuf0190 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
specify
(MAin3 => PADDI) = (0:0:0,0:0:0);
@@ -5579,7 +5464,7 @@ endmodule
module MAin_2_ ( output PADDI, input MAin2 );
- xo2iobuf0197 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
+ xo2iobuf0190 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
specify
(MAin2 => PADDI) = (0:0:0,0:0:0);
@@ -5591,7 +5476,7 @@ endmodule
module MAin_1_ ( output PADDI, input MAin1 );
- xo2iobuf0197 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
+ xo2iobuf0190 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
specify
(MAin1 => PADDI) = (0:0:0,0:0:0);
@@ -5603,7 +5488,7 @@ endmodule
module MAin_0_ ( output PADDI, input MAin0 );
- xo2iobuf0197 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
+ xo2iobuf0190 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
specify
(MAin0 => PADDI) = (0:0:0,0:0:0);
diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
index c941887..68f0f05 100644
--- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
@@ -4,11 +4,15 @@ Starting: parse design source files
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-615,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-621,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
-Done: design load finished with (0) errors, and (0) warnings
+WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,7-46,8) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D0'
+WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,15-46,16) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D1'
+WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(47,8-47,9) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
+Done: design load finished with (0) errors, and (3) warnings