diff --git a/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb deleted file mode 100755 index a80855d..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(0).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb deleted file mode 100755 index 1a1481b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(0).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb deleted file mode 100755 index 84cfd7b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(1).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb deleted file mode 100755 index 10dc2d1..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(1).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb b/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb deleted file mode 100755 index bf025da..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(2).cnf.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb b/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb deleted file mode 100755 index 7121330..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.(2).cnf.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.asm.qmsg b/CPLD/AGM-src/db/RAM4GS.asm.qmsg deleted file mode 100755 index 4989b11..0000000 --- a/CPLD/AGM-src/db/RAM4GS.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.asm.rdb b/CPLD/AGM-src/db/RAM4GS.asm.rdb deleted file mode 100755 index 57f2d3d..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.asm.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb b/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb deleted file mode 100755 index c9b3243..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.asm_labs.ddb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.cdb b/CPLD/AGM-src/db/RAM4GS.cmp.cdb deleted file mode 100755 index 660f5e1..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.hdb b/CPLD/AGM-src/db/RAM4GS.cmp.hdb deleted file mode 100755 index 27f7c43..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.idb b/CPLD/AGM-src/db/RAM4GS.cmp.idb deleted file mode 100755 index e91cbcb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.idb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.kpt b/CPLD/AGM-src/db/RAM4GS.cmp.kpt deleted file mode 100755 index 29f003a..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.kpt and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.rdb b/CPLD/AGM-src/db/RAM4GS.cmp.rdb deleted file mode 100755 index 8974ee5..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.cmp0.ddb b/CPLD/AGM-src/db/RAM4GS.cmp0.ddb deleted file mode 100755 index db1bbdb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.cmp0.ddb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.fit.qmsg b/CPLD/AGM-src/db/RAM4GS.fit.qmsg deleted file mode 100755 index f7f2a6b..0000000 --- a/CPLD/AGM-src/db/RAM4GS.fit.qmsg +++ /dev/null @@ -1,43 +0,0 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.hif b/CPLD/AGM-src/db/RAM4GS.hif deleted file mode 100755 index 662d74f..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.hif and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.ipinfo b/CPLD/AGM-src/db/RAM4GS.ipinfo deleted file mode 100755 index 482f1be..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.ipinfo and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.rdb b/CPLD/AGM-src/db/RAM4GS.lpc.rdb deleted file mode 100755 index 2c939fb..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.lpc.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.cdb b/CPLD/AGM-src/db/RAM4GS.map.cdb deleted file mode 100755 index ca0a971..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.hdb b/CPLD/AGM-src/db/RAM4GS.map.hdb deleted file mode 100755 index 8ae41d2..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.map.qmsg b/CPLD/AGM-src/db/RAM4GS.map.qmsg deleted file mode 100755 index 543433e..0000000 --- a/CPLD/AGM-src/db/RAM4GS.map.qmsg +++ /dev/null @@ -1,26 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.map.rdb b/CPLD/AGM-src/db/RAM4GS.map.rdb deleted file mode 100755 index d27105c..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.map.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.pre_map.hdb b/CPLD/AGM-src/db/RAM4GS.pre_map.hdb deleted file mode 100755 index 6f71689..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.pre_map.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.qns b/CPLD/AGM-src/db/RAM4GS.qns deleted file mode 100755 index ef67c3e..0000000 --- a/CPLD/AGM-src/db/RAM4GS.qns +++ /dev/null @@ -1 +0,0 @@ -RAM4GS/done diff --git a/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb b/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb deleted file mode 100755 index a7aa640..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.routing.rdb b/CPLD/AGM-src/db/RAM4GS.routing.rdb deleted file mode 100755 index a1beb78..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.routing.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv.hdb b/CPLD/AGM-src/db/RAM4GS.rtlv.hdb deleted file mode 100755 index 802d93c..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb b/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb deleted file mode 100755 index 30b67ca..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv_sg.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb b/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb deleted file mode 100755 index e318de4..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.rtlv_sg_swap.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb b/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb deleted file mode 100755 index 2d31b44..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sgdiff.cdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb b/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb deleted file mode 100755 index 18597e6..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sgdiff.hdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sta.qmsg b/CPLD/AGM-src/db/RAM4GS.sta.qmsg deleted file mode 100755 index e020392..0000000 --- a/CPLD/AGM-src/db/RAM4GS.sta.qmsg +++ /dev/null @@ -1,23 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} diff --git a/CPLD/AGM-src/db/RAM4GS.sta.rdb b/CPLD/AGM-src/db/RAM4GS.sta.rdb deleted file mode 100755 index 25f87ad..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sta.rdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb b/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb deleted file mode 100755 index 8b39503..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.sta_cmp.5_slow.tdb and /dev/null differ diff --git a/CPLD/AGM-src/db/RAM4GS.vpr.ammdb b/CPLD/AGM-src/db/RAM4GS.vpr.ammdb deleted file mode 100755 index 2acc82b..0000000 Binary files a/CPLD/AGM-src/db/RAM4GS.vpr.ammdb and /dev/null differ diff --git a/CPLD/AGM-src/db/logic_util_heursitic.dat b/CPLD/AGM-src/db/logic_util_heursitic.dat deleted file mode 100755 index c3752a7..0000000 Binary files a/CPLD/AGM-src/db/logic_util_heursitic.dat and /dev/null differ diff --git a/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg b/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg deleted file mode 100755 index 715eafe..0000000 --- a/CPLD/AGM-src/db/prev_cmp_RAM4GS.qmsg +++ /dev/null @@ -1,106 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""} diff --git a/CPLD/AGM-src/greybox_tmp/cbx_args.txt b/CPLD/AGM-src/greybox_tmp/cbx_args.txt deleted file mode 100755 index b32fb07..0000000 --- a/CPLD/AGM-src/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,26 +0,0 @@ -ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=RAM4GS.mif -LPM_HINT=UNUSED -LPM_TYPE=altufm_none -OSC_FREQUENCY=180000 -PORT_ARCLKENA=PORT_UNUSED -PORT_DRCLKENA=PORT_UNUSED -PROGRAM_TIME=1600000 -WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" -CBX_AUTO_BLACKBOX=ALL -CBX_AUTO_BLACKBOX=ALL -arclk -ardin -arshft -busy -drclk -drdin -drdout -drshft -erase -osc -oscena -program -rtpbusy diff --git a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt b/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt deleted file mode 100755 index 4a04335..0000000 Binary files a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt and /dev/null differ diff --git a/CPLD/AGM-src/output_files/RAM4GS.cdf b/CPLD/AGM-src/output_files/RAM4GS.cdf deleted file mode 100755 index 43f46dc..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/CPLD/AGM-src/output_files/RAM4GS.done b/CPLD/AGM-src/output_files/RAM4GS.done deleted file mode 100755 index d7b20f4..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.done +++ /dev/null @@ -1 +0,0 @@ -Thu Jul 23 02:21:03 2020 diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.summary b/CPLD/AGM-src/output_files/RAM4GS.fit.summary deleted file mode 100755 index 530787c..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.fit.summary +++ /dev/null @@ -1,11 +0,0 @@ -Fitter Status : Successful - Thu Jul 23 02:20:50 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Device : EPM240T100C5 -Timing Models : Final -Total logic elements : 170 / 240 ( 71 % ) -Total pins : 62 / 80 ( 78 % ) -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.jdi b/CPLD/AGM-src/output_files/RAM4GS.jdi deleted file mode 100755 index 85a8d49..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.summary b/CPLD/AGM-src/output_files/RAM4GS.map.summary deleted file mode 100755 index 56e671c..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.map.summary +++ /dev/null @@ -1,9 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : RAM4GS -Top-level Entity Name : RAM4GS -Family : MAX II -Total logic elements : 178 -Total pins : 62 -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/AGM-src/output_files/RAM4GS.pof b/CPLD/AGM-src/output_files/RAM4GS.pof deleted file mode 100755 index a168b2e..0000000 Binary files a/CPLD/AGM-src/output_files/RAM4GS.pof and /dev/null differ diff --git a/CPLD/AGM-src/output_files/RAM4GS.sta.rpt b/CPLD/AGM-src/output_files/RAM4GS.sta.rpt deleted file mode 100755 index 6462353..0000000 --- a/CPLD/AGM-src/output_files/RAM4GS.sta.rpt +++ /dev/null @@ -1,1588 +0,0 @@ -TimeQuest Timing Analyzer report for RAM4GS -Thu Jul 23 02:21:02 2020 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Fmax Summary - 7. Setup Summary - 8. Hold Summary - 9. Recovery Summary - 10. Removal Summary - 11. Minimum Pulse Width Summary - 12. Setup: 'ARCLK' - 13. Setup: 'DRCLK' - 14. Setup: 'PHI2' - 15. Setup: 'RCLK' - 16. Setup: 'nCRAS' - 17. Hold: 'DRCLK' - 18. Hold: 'ARCLK' - 19. Hold: 'RCLK' - 20. Hold: 'PHI2' - 21. Hold: 'nCRAS' - 22. Minimum Pulse Width: 'ARCLK' - 23. Minimum Pulse Width: 'DRCLK' - 24. Minimum Pulse Width: 'PHI2' - 25. Minimum Pulse Width: 'RCLK' - 26. Minimum Pulse Width: 'nCCAS' - 27. Minimum Pulse Width: 'nCRAS' - 28. Setup Times - 29. Hold Times - 30. Clock to Output Times - 31. Minimum Clock to Output Times - 32. Propagation Delay - 33. Minimum Propagation Delay - 34. Output Enable Times - 35. Minimum Output Enable Times - 36. Output Disable Times - 37. Minimum Output Disable Times - 38. Setup Transfers - 39. Hold Transfers - 40. Report TCCS - 41. Report RSKM - 42. Unconstrained Paths - 43. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; RAM4GS ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+--------------------+-------------------------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; < 0.1% ; -+----------------------------+-------------+ - - -+-----------------------------------------------------+ -; SDC File List ; -+-----------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+-----------------+--------+--------------------------+ -; constraints.sdc ; OK ; Thu Jul 23 02:21:01 2020 ; -+-----------------+--------+--------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; -; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; -; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; -; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; -; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; -; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ - - -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 51.06 MHz ; 51.06 MHz ; PHI2 ; ; -; 128.87 MHz ; 128.87 MHz ; RCLK ; ; -+------------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+---------------------------------+ -; Setup Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -99.000 ; -99.000 ; -; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -9.292 ; -92.804 ; -; RCLK ; -8.365 ; -253.063 ; -; nCRAS ; -0.490 ; -0.577 ; -+-------+---------+---------------+ - - -+---------------------------------+ -; Hold Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; DRCLK ; -16.306 ; -16.306 ; -; ARCLK ; -16.272 ; -16.272 ; -; RCLK ; -0.874 ; -0.874 ; -; PHI2 ; -0.396 ; -0.396 ; -; nCRAS ; -0.125 ; -0.125 ; -+-------+---------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+---------------------------------+ -; Minimum Pulse Width Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -29.500 ; -59.000 ; -; DRCLK ; -29.500 ; -59.000 ; -; PHI2 ; -2.289 ; -2.289 ; -; RCLK ; -2.289 ; -2.289 ; -; nCCAS ; -2.289 ; -2.289 ; -; nCRAS ; -2.289 ; -2.289 ; -+-------+---------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.728 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.715 ; 2.013 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.549 ; -; -22.694 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.529 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Setup: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -9.292 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.121 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.288 ; -; -8.996 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.163 ; -; -8.949 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.949 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.116 ; -; -8.857 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.024 ; -; -8.778 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.778 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.945 ; -; -8.653 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.653 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.594 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.761 ; -; -8.514 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.514 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.681 ; -; -8.300 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.467 ; -; -8.289 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.456 ; -; -8.251 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.251 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.418 ; -; -8.118 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.285 ; -; -8.084 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.251 ; -; -8.043 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.210 ; -; -7.993 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.160 ; -; -7.957 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.957 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.124 ; -; -7.872 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.039 ; -; -7.854 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.021 ; -; -7.799 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.966 ; -; -7.747 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.914 ; -; -7.741 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.741 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.908 ; -; -7.608 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.775 ; -; -7.591 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.758 ; -; -7.456 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.456 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.623 ; -; -7.345 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.512 ; -; -7.297 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.464 ; -; -7.205 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.372 ; -; -7.081 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.248 ; -; -7.051 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.218 ; -; -7.034 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.201 ; -; -6.909 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.076 ; -; -6.870 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.870 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.037 ; -; -6.835 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.002 ; -; -6.796 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.963 ; -; -6.770 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.937 ; -; -6.745 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.912 ; -; -6.699 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.699 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.866 ; -; -6.574 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.574 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; -; -6.550 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.717 ; -; -6.507 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.674 ; -; -6.449 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.616 ; -; -6.435 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.435 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.602 ; -; -6.310 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.477 ; -; -6.213 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.380 ; -; -6.172 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.172 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.339 ; -; -6.047 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.214 ; -; -5.997 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.164 ; -; -5.878 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.878 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.045 ; -; -5.753 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.920 ; -; -5.712 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.879 ; -; -5.662 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.662 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.829 ; -; -5.537 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.704 ; -; -5.377 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.377 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.544 ; -; -5.252 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.419 ; -; -5.004 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.671 ; -; -4.046 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.046 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.713 ; -; -4.040 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.707 ; -; -4.001 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.668 ; -; -3.752 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.419 ; -; -3.694 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.861 ; -; -3.585 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.252 ; -; -2.929 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.596 ; -; -2.917 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.584 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; -8.365 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -8.365 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 5.334 ; -; -7.591 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 5.180 ; -; -7.130 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.719 ; -; -7.061 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.650 ; -; -7.017 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.986 ; -; -6.760 ; FS[5] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.760 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.427 ; -; -6.691 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.280 ; -; -6.669 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.258 ; -; -6.664 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.633 ; -; -6.612 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.612 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ; -; -6.588 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.255 ; -; -6.574 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.163 ; -; -6.549 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.549 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.216 ; -; -6.526 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 4.115 ; -; -6.502 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.502 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.169 ; -; -6.501 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.168 ; -; -6.482 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.149 ; -; -6.401 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.068 ; -; -6.399 ; FS[4] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.399 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.066 ; -; -6.395 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.062 ; -; -6.380 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.047 ; -; -6.328 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 3.297 ; -; -6.258 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.847 ; -; -6.256 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.923 ; -; -6.253 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.920 ; -; -6.232 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.899 ; -; -6.198 ; FS[6] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.198 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.865 ; -; -6.193 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.860 ; -; -6.190 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.857 ; -; -6.169 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ; -; -6.146 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.813 ; -; -6.143 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.810 ; -; -6.122 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.789 ; -; -6.070 ; UFMInitDone ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.070 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ; -; -6.044 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.633 ; -; -6.040 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.707 ; -; -6.032 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.699 ; -; -6.028 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.695 ; -; -6.022 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.689 ; -; -6.019 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.686 ; -; -5.996 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.578 ; 3.585 ; -; -5.959 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.626 ; -; -5.958 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.625 ; -; -5.954 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.621 ; -; -5.949 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.198 ; 2.918 ; -; -5.942 ; UFMReqErase ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.609 ; -; -5.915 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.582 ; -; -5.912 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.579 ; -; -5.852 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.852 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.519 ; -; -5.839 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.506 ; -; -5.835 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.502 ; -; -5.818 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.485 ; -; -5.805 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.472 ; -; -5.739 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.406 ; -; -5.733 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 2.165 ; 8.565 ; -; -5.720 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.387 ; -; -5.714 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.381 ; -; -5.711 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.711 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.378 ; -; -5.690 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.357 ; -; -5.688 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.355 ; -; -5.666 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ; -; -5.656 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.323 ; -; -5.596 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.263 ; -; -5.579 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.246 ; -; -5.563 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.230 ; -; -5.549 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.216 ; -; -5.503 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.170 ; -; -5.500 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.167 ; -; -5.487 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.154 ; -; -5.480 ; UFMInitDone ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.147 ; -; -5.479 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.146 ; -; -5.459 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.126 ; -; -5.453 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.120 ; -; -5.425 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.092 ; -; -5.420 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.087 ; -; -5.397 ; IS[2] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.064 ; -; -5.373 ; UFMInitDone ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.040 ; -; -5.363 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.030 ; -; -5.350 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.017 ; -; -5.345 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.345 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; -; -5.333 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.000 ; -; -5.312 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.312 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.979 ; -; -5.290 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.957 ; -; -5.267 ; FS[3] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.934 ; -; -5.230 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.230 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.897 ; -; -5.208 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.875 ; -; -5.206 ; IS[3] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.873 ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Setup: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.490 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 3.235 ; -; -0.087 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.832 ; -; 0.071 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.926 ; 6.022 ; -; 0.079 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.666 ; -; 0.080 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.665 ; -; 0.081 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.664 ; -; 0.082 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.663 ; -; 0.084 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.661 ; -; 0.091 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.654 ; -; 0.095 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.650 ; -; 0.099 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.646 ; -; 0.104 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.641 ; -; 0.105 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.578 ; 2.640 ; -; 0.571 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.926 ; 6.022 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.306 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.529 ; -; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.549 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.272 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.715 ; 2.013 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Hold: 'RCLK' ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.874 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 3.348 ; 3.071 ; -; -0.374 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 3.348 ; 3.071 ; -; 1.192 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.761 ; -; 1.264 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.833 ; -; 1.344 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.913 ; -; 1.400 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.621 ; -; 1.642 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.863 ; -; 1.670 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.891 ; -; 1.692 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.761 ; -; 1.695 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.916 ; -; 1.703 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.924 ; -; 1.706 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.927 ; -; 1.764 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.833 ; -; 1.844 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.913 ; -; 1.899 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.120 ; -; 1.948 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.169 ; -; 1.959 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.180 ; -; 1.976 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.197 ; -; 1.983 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.204 ; -; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; -; 2.117 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; -; 2.135 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.135 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.358 ; -; 2.141 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.362 ; -; 2.153 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.374 ; -; 2.212 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.433 ; -; 2.221 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.230 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.233 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.292 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.513 ; -; 2.332 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.553 ; -; 2.363 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.584 ; -; 2.380 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.601 ; -; 2.407 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.628 ; -; 2.522 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.743 ; -; 2.530 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.751 ; -; 2.542 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.763 ; -; 2.577 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.798 ; -; 2.582 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.803 ; -; 2.593 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.814 ; -; 2.615 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.836 ; -; 2.622 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.843 ; -; 2.837 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.058 ; -; 2.885 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.106 ; -; 2.912 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.133 ; -; 2.913 ; PHI2r3 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.134 ; -; 2.936 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.157 ; -; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; -; 2.949 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.178 ; -; 2.967 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ; -; 2.969 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.190 ; -; 3.028 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.249 ; -; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; -; 3.060 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.066 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.287 ; -; 3.068 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.289 ; -; 3.078 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.299 ; -; 3.109 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.330 ; -; 3.130 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.351 ; -; 3.159 ; S[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.380 ; -; 3.161 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.161 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.162 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.383 ; -; 3.170 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.179 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; -; 3.184 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; -; 3.241 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.462 ; -; 3.277 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.498 ; -; 3.281 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.282 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.289 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.289 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.510 ; -; 3.290 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; -; 3.296 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.517 ; -; 3.306 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.527 ; -; 3.324 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.545 ; -; 3.328 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.549 ; -; 3.381 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.602 ; -; 3.383 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.604 ; -+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Hold: 'PHI2' ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.396 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.023 ; -; 0.072 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.198 ; 2.991 ; -; 0.129 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.198 ; 3.548 ; -; 1.927 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.148 ; -; 2.681 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.902 ; -; 3.162 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.383 ; -; 3.363 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.584 ; -; 3.375 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.596 ; -; 3.825 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.546 ; -; 4.031 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.252 ; -; 4.110 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.831 ; -; 4.140 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.861 ; -; 4.198 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.419 ; -; 4.265 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.986 ; -; 4.326 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.047 ; -; 4.447 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.668 ; -; 4.486 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.707 ; -; 4.492 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.492 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.713 ; -; 4.550 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.271 ; -; 4.620 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.341 ; -; 4.766 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.487 ; -; 4.883 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.604 ; -; 5.022 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.743 ; -; 5.060 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.781 ; -; 5.064 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.785 ; -; 5.147 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.868 ; -; 5.318 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.039 ; -; 5.323 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.044 ; -; 5.349 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.070 ; -; 5.450 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.671 ; -; 5.462 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.183 ; -; 5.519 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.240 ; -; 5.565 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.286 ; -; 5.587 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.308 ; -; 5.758 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.479 ; -; 5.804 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.525 ; -; 5.859 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.580 ; -; 6.020 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.741 ; -; 6.122 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.843 ; -; 6.158 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.879 ; -; 6.261 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.982 ; -; 6.314 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.035 ; -; 6.386 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.107 ; -; 6.443 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.164 ; -; 6.557 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.278 ; -; 6.577 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.298 ; -; 6.659 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.380 ; -; 6.716 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.437 ; -; 6.841 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.562 ; -; 6.953 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.674 ; -; 7.012 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.733 ; -; 7.216 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.937 ; -; 7.242 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.963 ; -; 7.355 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.076 ; -; 7.480 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.201 ; -; 7.527 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.248 ; -; 7.651 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.372 ; -; 7.743 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.464 ; -; 7.902 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 7.902 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; -; 8.037 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.758 ; -; 8.187 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.187 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.908 ; -; 8.245 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.966 ; -; 8.300 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.021 ; -; 8.403 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.403 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.124 ; -; 8.439 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.160 ; -; 8.530 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.251 ; -; 8.564 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.285 ; -; 8.697 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.697 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.418 ; -; 8.735 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.456 ; -; 8.746 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.467 ; -; 8.960 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 8.960 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.681 ; -; 9.040 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.761 ; -; 9.099 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.099 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.224 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.224 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.945 ; -; 9.303 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.024 ; -; 9.395 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.116 ; -+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.125 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.926 ; 6.022 ; -; 0.341 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.640 ; -; 0.342 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.641 ; -; 0.347 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.646 ; -; 0.351 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.650 ; -; 0.355 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.654 ; -; 0.362 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.661 ; -; 0.364 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.663 ; -; 0.365 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.664 ; -; 0.366 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.665 ; -; 0.367 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.666 ; -; 0.375 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.926 ; 6.022 ; -; 0.533 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 2.832 ; -; 0.936 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.578 ; 3.235 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'ARCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'DRCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI2' ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI2 ; Rise ; PHI2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; ADSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; C1Submitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdDRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdEnable ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdSubmitted ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; CmdUFMPrgm ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; Cmdn8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Rise ; RA11 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; UFMOscEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI2 ; Fall ; XOR8MEG ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; ADSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Bank[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; C1Submitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRCLK|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdDRDIn|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdEnable|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdSubmitted|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMErase|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; CmdUFMPrgm|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; Cmdn8MEGEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; PHI2|combout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; RA11|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; UFMOscEN|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI2 ; Rise ; XOR8MEG|clk ; -+--------+--------------+----------------+------------------+-------+------------+------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'RCLK' ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; RCLK ; Rise ; RCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; CASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRDIn ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[14] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[15] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[16] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; FS[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; IS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; InitReady ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; PHI2r3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RA10 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RASr3 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKEEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; RCKE~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; Ready ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; S[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMD ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMInitDone ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMProgram ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; UFMReqErase ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; RCLK ; Rise ; n8MEGEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; RCLK ; Rise ; nRCAS~reg0 ; -+--------+--------------+----------------+------------------+-------+------------+-------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCCAS' ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCCAS ; Rise ; nCCAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCCAS ; Fall ; WRD[7] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; WRD[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCCAS ; Rise ; nCCAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+---------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'nCRAS' ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; nCRAS ; Rise ; nCRAS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; CBR ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; FWEr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[0]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RBA[1]~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; nCRAS ; Fall ; RowA[9] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; CBR|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; FWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[0]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RBA[1]~reg0|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[1]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[2]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[3]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[4]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[5]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[6]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[7]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[8]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; RowA[9]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; nCRAS ; Rise ; nCRAS|combout ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.100 ; 0.100 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.099 ; 0.099 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.187 ; 0.187 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.377 ; 0.377 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.181 ; 0.181 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.431 ; 0.431 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.839 ; 0.839 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; -0.141 ; -0.141 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; 6.507 ; 6.507 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 5.653 ; 5.653 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; 6.225 ; 6.225 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; 6.476 ; 6.476 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 5.332 ; 5.332 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; 7.176 ; 7.176 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; 5.239 ; 5.239 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; 5.246 ; 5.246 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 4.152 ; 4.152 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; 4.051 ; 4.051 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; 6.688 ; 6.688 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; 7.271 ; 7.271 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; 7.040 ; 7.040 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; 5.984 ; 5.984 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; 4.702 ; 4.702 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; 4.845 ; 4.845 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; 5.436 ; 5.436 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; 1.898 ; 1.898 ; Rise ; RCLK ; -; nCCAS ; RCLK ; 1.746 ; 1.746 ; Rise ; RCLK ; -; nCRAS ; RCLK ; 1.818 ; 1.818 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; -0.572 ; -0.572 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; -0.490 ; -0.490 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; -0.295 ; -0.295 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; -0.561 ; -0.561 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.097 ; 0.097 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.343 ; 0.343 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; -0.478 ; -0.478 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; -0.222 ; -0.222 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; 1.871 ; 1.871 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; 1.618 ; 1.618 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; -0.639 ; -0.639 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.450 ; 0.450 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; -0.345 ; -0.345 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.521 ; 0.521 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; -0.391 ; -0.391 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; -0.178 ; -0.178 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; -0.439 ; -0.439 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; -1.067 ; -1.067 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; -0.425 ; -0.425 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; -0.474 ; -0.474 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.429 ; 0.429 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; 2.878 ; 2.878 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; Din[*] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[0] ; PHI2 ; 0.454 ; 0.454 ; Rise ; PHI2 ; -; Din[1] ; PHI2 ; 0.455 ; 0.455 ; Rise ; PHI2 ; -; Din[2] ; PHI2 ; 0.367 ; 0.367 ; Rise ; PHI2 ; -; Din[3] ; PHI2 ; 0.177 ; 0.177 ; Rise ; PHI2 ; -; Din[4] ; PHI2 ; 0.373 ; 0.373 ; Rise ; PHI2 ; -; Din[5] ; PHI2 ; 0.123 ; 0.123 ; Rise ; PHI2 ; -; Din[6] ; PHI2 ; 0.943 ; 0.943 ; Rise ; PHI2 ; -; Din[7] ; PHI2 ; 0.695 ; 0.695 ; Rise ; PHI2 ; -; Din[*] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[0] ; PHI2 ; -0.378 ; -0.378 ; Fall ; PHI2 ; -; Din[1] ; PHI2 ; 0.138 ; 0.138 ; Fall ; PHI2 ; -; Din[2] ; PHI2 ; -0.365 ; -0.365 ; Fall ; PHI2 ; -; Din[3] ; PHI2 ; -0.419 ; -0.419 ; Fall ; PHI2 ; -; Din[4] ; PHI2 ; 0.303 ; 0.303 ; Fall ; PHI2 ; -; Din[5] ; PHI2 ; -1.686 ; -1.686 ; Fall ; PHI2 ; -; Din[6] ; PHI2 ; -1.080 ; -1.080 ; Fall ; PHI2 ; -; Din[7] ; PHI2 ; -1.052 ; -1.052 ; Fall ; PHI2 ; -; MAin[*] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[0] ; PHI2 ; 0.837 ; 0.837 ; Fall ; PHI2 ; -; MAin[1] ; PHI2 ; -0.027 ; -0.027 ; Fall ; PHI2 ; -; MAin[2] ; PHI2 ; -2.640 ; -2.640 ; Fall ; PHI2 ; -; MAin[3] ; PHI2 ; -3.223 ; -3.223 ; Fall ; PHI2 ; -; MAin[4] ; PHI2 ; -2.992 ; -2.992 ; Fall ; PHI2 ; -; MAin[5] ; PHI2 ; -1.936 ; -1.936 ; Fall ; PHI2 ; -; MAin[6] ; PHI2 ; -0.564 ; -0.564 ; Fall ; PHI2 ; -; MAin[7] ; PHI2 ; -0.704 ; -0.704 ; Fall ; PHI2 ; -; nFWE ; PHI2 ; -0.462 ; -0.462 ; Fall ; PHI2 ; -; PHI2 ; RCLK ; -1.344 ; -1.344 ; Rise ; RCLK ; -; nCCAS ; RCLK ; -1.192 ; -1.192 ; Rise ; RCLK ; -; nCRAS ; RCLK ; -1.264 ; -1.264 ; Rise ; RCLK ; -; Din[*] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[0] ; nCCAS ; 1.126 ; 1.126 ; Fall ; nCCAS ; -; Din[1] ; nCCAS ; 1.044 ; 1.044 ; Fall ; nCCAS ; -; Din[2] ; nCCAS ; 0.849 ; 0.849 ; Fall ; nCCAS ; -; Din[3] ; nCCAS ; 1.115 ; 1.115 ; Fall ; nCCAS ; -; Din[4] ; nCCAS ; 0.457 ; 0.457 ; Fall ; nCCAS ; -; Din[5] ; nCCAS ; 0.211 ; 0.211 ; Fall ; nCCAS ; -; Din[6] ; nCCAS ; 1.032 ; 1.032 ; Fall ; nCCAS ; -; Din[7] ; nCCAS ; 0.776 ; 0.776 ; Fall ; nCCAS ; -; CROW[*] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; CROW[0] ; nCRAS ; -1.317 ; -1.317 ; Fall ; nCRAS ; -; CROW[1] ; nCRAS ; -1.064 ; -1.064 ; Fall ; nCRAS ; -; MAin[*] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[0] ; nCRAS ; 1.193 ; 1.193 ; Fall ; nCRAS ; -; MAin[1] ; nCRAS ; 0.104 ; 0.104 ; Fall ; nCRAS ; -; MAin[2] ; nCRAS ; 0.899 ; 0.899 ; Fall ; nCRAS ; -; MAin[3] ; nCRAS ; 0.033 ; 0.033 ; Fall ; nCRAS ; -; MAin[4] ; nCRAS ; 0.945 ; 0.945 ; Fall ; nCRAS ; -; MAin[5] ; nCRAS ; 0.732 ; 0.732 ; Fall ; nCRAS ; -; MAin[6] ; nCRAS ; 0.993 ; 0.993 ; Fall ; nCRAS ; -; MAin[7] ; nCRAS ; 1.621 ; 1.621 ; Fall ; nCRAS ; -; MAin[8] ; nCRAS ; 0.979 ; 0.979 ; Fall ; nCRAS ; -; MAin[9] ; nCRAS ; 1.028 ; 1.028 ; Fall ; nCRAS ; -; nCCAS ; nCRAS ; 0.125 ; 0.125 ; Fall ; nCRAS ; -; nFWE ; nCRAS ; -2.324 ; -2.324 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[11] ; PHI2 ; 11.943 ; 11.943 ; Rise ; PHI2 ; -; RA[*] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RA[0] ; RCLK ; 12.101 ; 12.101 ; Rise ; RCLK ; -; RA[1] ; RCLK ; 11.881 ; 11.881 ; Rise ; RCLK ; -; RA[2] ; RCLK ; 12.068 ; 12.068 ; Rise ; RCLK ; -; RA[3] ; RCLK ; 12.421 ; 12.421 ; Rise ; RCLK ; -; RA[4] ; RCLK ; 12.287 ; 12.287 ; Rise ; RCLK ; -; RA[5] ; RCLK ; 12.220 ; 12.220 ; Rise ; RCLK ; -; RA[6] ; RCLK ; 12.186 ; 12.186 ; Rise ; RCLK ; -; RA[7] ; RCLK ; 11.890 ; 11.890 ; Rise ; RCLK ; -; RA[8] ; RCLK ; 12.150 ; 12.150 ; Rise ; RCLK ; -; RA[9] ; RCLK ; 12.269 ; 12.269 ; Rise ; RCLK ; -; RA[10] ; RCLK ; 8.927 ; 8.927 ; Rise ; RCLK ; -; RCKE ; RCLK ; 8.786 ; 8.786 ; Rise ; RCLK ; -; RDQMH ; RCLK ; 12.174 ; 12.174 ; Rise ; RCLK ; -; RDQML ; RCLK ; 12.206 ; 12.206 ; Rise ; RCLK ; -; nRCAS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRCS ; RCLK ; 8.142 ; 8.142 ; Rise ; RCLK ; -; nRRAS ; RCLK ; 7.536 ; 7.536 ; Rise ; RCLK ; -; nRWE ; RCLK ; 8.622 ; 8.622 ; Rise ; RCLK ; -; RD[*] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 19.685 ; 19.685 ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 18.806 ; 18.806 ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 17.621 ; 17.621 ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 19.528 ; 19.528 ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 18.795 ; 18.795 ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 18.802 ; 18.802 ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 18.954 ; 18.954 ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 18.801 ; 18.801 ; Fall ; nCCAS ; -; RA[*] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[0] ; nCRAS ; 13.694 ; 13.694 ; Fall ; nCRAS ; -; RA[1] ; nCRAS ; 13.338 ; 13.338 ; Fall ; nCRAS ; -; RA[2] ; nCRAS ; 13.700 ; 13.700 ; Fall ; nCRAS ; -; RA[3] ; nCRAS ; 13.894 ; 13.894 ; Fall ; nCRAS ; -; RA[4] ; nCRAS ; 13.348 ; 13.348 ; Fall ; nCRAS ; -; RA[5] ; nCRAS ; 13.282 ; 13.282 ; Fall ; nCRAS ; -; RA[6] ; nCRAS ; 13.721 ; 13.721 ; Fall ; nCRAS ; -; RA[7] ; nCRAS ; 13.003 ; 13.003 ; Fall ; nCRAS ; -; RA[8] ; nCRAS ; 14.657 ; 14.657 ; Fall ; nCRAS ; -; RA[9] ; nCRAS ; 13.207 ; 13.207 ; Fall ; nCRAS ; -; RBA[*] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[0] ; nCRAS ; 10.096 ; 10.096 ; Fall ; nCRAS ; -; RBA[1] ; nCRAS ; 10.738 ; 10.738 ; Fall ; nCRAS ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+------------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; MAin[0] ; RA[0] ; 10.124 ; ; ; 10.124 ; -; MAin[1] ; RA[1] ; 9.891 ; ; ; 9.891 ; -; MAin[2] ; RA[2] ; 8.276 ; ; ; 8.276 ; -; MAin[3] ; RA[3] ; 10.704 ; ; ; 10.704 ; -; MAin[4] ; RA[4] ; 8.824 ; ; ; 8.824 ; -; MAin[5] ; RA[5] ; 8.367 ; ; ; 8.367 ; -; MAin[6] ; RA[6] ; 10.195 ; ; ; 10.195 ; -; MAin[7] ; RA[7] ; 9.820 ; ; ; 9.820 ; -; MAin[8] ; RA[8] ; 9.678 ; ; ; 9.678 ; -; MAin[9] ; RA[9] ; 8.912 ; ; ; 8.912 ; -; MAin[9] ; RDQMH ; 8.830 ; ; ; 8.830 ; -; MAin[9] ; RDQML ; 8.862 ; ; ; 8.862 ; -; RD[0] ; Dout[0] ; 6.188 ; ; ; 6.188 ; -; RD[1] ; Dout[1] ; 6.690 ; ; ; 6.690 ; -; RD[2] ; Dout[2] ; 6.254 ; ; ; 6.254 ; -; RD[3] ; Dout[3] ; 6.845 ; ; ; 6.845 ; -; RD[4] ; Dout[4] ; 6.775 ; ; ; 6.775 ; -; RD[5] ; Dout[5] ; 6.952 ; ; ; 6.952 ; -; RD[6] ; Dout[6] ; 6.194 ; ; ; 6.194 ; -; RD[7] ; Dout[7] ; 6.725 ; ; ; 6.725 ; -; nFWE ; RD[0] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[1] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[2] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[3] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[4] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[5] ; 16.032 ; ; ; 16.032 ; -; nFWE ; RD[6] ; 17.178 ; ; ; 17.178 ; -; nFWE ; RD[7] ; 17.178 ; ; ; 17.178 ; -+------------+-------------+--------+----+----+--------+ - - -+-----------------------------------------------------------------------+ -; Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Minimum Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; RD[*] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Rise ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Rise ; nCCAS ; -; RD[*] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[0] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[1] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[2] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[3] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[4] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[5] ; nCCAS ; 13.198 ; ; Fall ; nCCAS ; -; RD[6] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -; RD[7] ; nCCAS ; 14.344 ; ; Fall ; nCCAS ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; -; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; -; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 14 ; -; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; -; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; DRCLK ; RCLK ; 2 ; 0 ; 0 ; 0 ; -; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; -; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; -; PHI2 ; RCLK ; 1 ; 11 ; 0 ; 0 ; -; RCLK ; RCLK ; 619 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 30 ; 30 ; -; Unconstrained Input Port Paths ; 231 ; 231 ; -; Unconstrained Output Ports ; 37 ; 37 ; -; Unconstrained Output Port Paths ; 75 ; 75 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Jul 23 02:20:57 2020 -Info: Command: quartus_sta RAM4GS -c RAM4GS -Info: qsta_default_script.tcl version: #1 -Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (306004): Started post-fitting delay annotation -Info (306005): Delay annotation completed successfully -Info (332104): Reading SDC File: 'constraints.sdc' -Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name DRCLK DRCLK - Info (332105): create_clock -period 1.000 -name ARCLK ARCLK - Info (332105): create_clock -period 1.000 -name RCLK RCLK - Info (332105): create_clock -period 1.000 -name nCRAS nCRAS - Info (332105): create_clock -period 1.000 -name PHI2 PHI2 - Info (332105): create_clock -period 1.000 -name nCCAS nCCAS -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -99.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -99.000 -99.000 ARCLK - Info (332119): -99.000 -99.000 DRCLK - Info (332119): -9.292 -92.804 PHI2 - Info (332119): -8.365 -253.063 RCLK - Info (332119): -0.490 -0.577 nCRAS -Info (332146): Worst-case hold slack is -16.306 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -16.306 -16.306 DRCLK - Info (332119): -16.272 -16.272 ARCLK - Info (332119): -0.874 -0.874 RCLK - Info (332119): -0.396 -0.396 PHI2 - Info (332119): -0.125 -0.125 nCRAS -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -29.500 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -29.500 -59.000 ARCLK - Info (332119): -29.500 -59.000 DRCLK - Info (332119): -2.289 -2.289 PHI2 - Info (332119): -2.289 -2.289 RCLK - Info (332119): -2.289 -2.289 nCCAS - Info (332119): -2.289 -2.289 nCRAS -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 288 megabytes - Info: Processing ended: Thu Jul 23 02:21:02 2020 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 - - diff --git a/CPLD/LCMXO/LCMXO256C/.run_manager.ini b/CPLD/LCMXO/LCMXO256C/.run_manager.ini new file mode 100644 index 0000000..be682d1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x2\xc9\0\0\x2i\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=true +isHidden=false +isExpanded=true diff --git a/CPLD/LCMXO/LCMXO256C/.setting.ini b/CPLD/LCMXO/LCMXO256C/.setting.ini new file mode 100644 index 0000000..c145fb8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=IBIS, Bitgen +Map.auto_tasks=MapEqu, MapTrace +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini b/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini b/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini new file mode 100644 index 0000000..0aa848d --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini @@ -0,0 +1,65 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Timing Preferences + +[Port%20Assignments] +Name="166,0" +Group%20By="84,1" +Pin="63,2" +BANK="62,3" +IO_TYPE="117,4" +PULLMODE="119,5" +DRIVE="67,6" +SLEWRATE="92,7" +OPENDRAIN="97,8" +Outload%20%28pF%29="103,9" +MaxSkew="87,10" +Clock%20Load%20Only="121,11" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="109,2" +Polarity="77,3" +BANK="0,4" +IO_TYPE="117,5" +Signal%20Name="123,6" +Signal%20Type="115,7" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="222,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="246,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" +Preference%20Unit="1012,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="1245,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" diff --git a/CPLD/AGM-src/constraints.sdc b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl old mode 100755 new mode 100644 similarity index 100% rename from CPLD/AGM-src/constraints.sdc rename to CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf new file mode 100644 index 0000000..0accfcf --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf new file mode 100644 index 0000000..9fa278f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf @@ -0,0 +1,226 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ; +IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ; +IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +USE PRIMARY NET "PHI2_c" ; +USE PRIMARY NET "RCLK_c" ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 16.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +USE PRIMARY NET "nCCAS_c" ; +USE PRIMARY NET "nCRAS_c" ; diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html new file mode 100644 index 0000000..ddd739c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html @@ -0,0 +1,91 @@ + +Lattice TCL Log + + +
pn210816194012
+#Start recording tcl command: 8/16/2021 19:02:08
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
+prj_project save
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_run PAR -impl impl1
+prj_run PAR -impl impl1
+prj_run Map -impl impl1
+prj_run Export -impl impl1
+prj_run PAR -impl impl1
+prj_run Map -impl impl1
+prj_run PAR -impl impl1
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 19:40:12
+
+
+
+pn210816202808
+#Start recording tcl command: 8/16/2021 20:24:10
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:28:08
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr new file mode 100644 index 0000000..c6ef2b4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr @@ -0,0 +1,17 @@ +#Start recording tcl command: 8/16/2021 19:02:08 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse" +prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" +prj_project save +prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" +prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" +prj_run PAR -impl impl1 +prj_run PAR -impl impl1 +prj_run Map -impl impl1 +prj_run Export -impl impl1 +prj_run PAR -impl impl1 +prj_run Map -impl impl1 +prj_run PAR -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/16/2021 19:40:12 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr new file mode 100644 index 0000000..fa5fbe8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/16/2021 20:24:10 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/16/2021 20:28:08 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr new file mode 100644 index 0000000..2a19da1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/16/2021 21:33:16 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +#Stop recording: 8/16/2021 21:33:22 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr new file mode 100644 index 0000000..e2e3953 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr @@ -0,0 +1,6 @@ +#Start recording tcl command: 8/16/2021 21:32:14 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceOne +#Stop recording: 8/16/2021 21:41:12 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/.build_status b/CPLD/LCMXO/LCMXO256C/impl1/.build_status new file mode 100644 index 0000000..b86a12b --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/.build_status @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb new file mode 100644 index 0000000..2ef13db Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000..fc69b95 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000..edbbbd7 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs b/CPLD/LCMXO/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs new file mode 100644 index 0000000..ef3482c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/IBIS/RAM2GS_LCMXO256C_im~.ibs @@ -0,0 +1,2156 @@ +|************************************************************************ +| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2 +| Generate date: Mon Aug 16 21:36:25 2021 +|************************************************************************ +| IBIS File machxo.ibs +| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation +| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor +| North Carolina State University, ERL, 2006 +|************************************************************************ +[IBIS ver] 3.2 +[File Name] RAM2GS_LCMXO256C_im~.ibs +[File Rev] 2.2 +[Date] Mon Sep 28 10:44:10 EDT 2009 +[Source] Lattice Semiconductor EE12 Process +[Notes] "Preliminary Version" + Lattice Semiconductor has worked hard to ensure the + models below are accurate and complete. However, the + data below was generated using simulation of the + input/output model files for the silicon. Therefore, + the data below is for reference and initial design + purposes only. +| + The data below is correlated to Spice models. + For questions regarding this data please contact + us at www.latticesemi.com. +| + Lattice Semiconductor grants permission to use this + data for use in printed circuit design using this + Lattice programmable logic device. Other use of this + code, including the selling or duplication of any + portion is strictly prohibited. +| +| NAMING CONVENTION +| + The IBIS [Model] header is limited by the specification to a + total of characters. With such a set of characters available + for naming models it becomes important to attempt to + meaningfully encode the IO standards so they fit within the + twenty character limit. It would seem that twenty characters + would provide room enough for describing IO's. However, the + PLD IO structure continues to grow more and more complex. The + complexity is making the twenty characters insuffiently + descriptive. In order to overcome this issue the naming + convention described below is implemented to resolve the issue. +| +The twenty character space is managed as follows: + bbbvvvsdddprugtcoixx +| + b = standard + v = voltage (x.xx V) + s = slew code + d = drive (xx.x ma) + p = pullup code + r = series resistance code + u = terminate to vcc code + g = terminate to gnd code + t = terminate to vtt code + c = common mode termination mode + o = diff resistor code + i = diff resistor current code + x = reserved +| +| + standard +| + LVCMOS lvc + lvcmosd lvd + LVDSE lve + LVTTL lvt + lvttld ltd + PCI pci + pcix pcx + AGP1x ag1 + agp2x ag2 + sstl_I ss1 + sstl_II ss2 + sstld_I s1d + sstld_II s2d + CTT ctt + hstl_i hs1 + hstl_ii hs2 + hstl_iii hs3 + hstl_iv hs4 + hstld_i h1d + hstld_ii h2d + gtl gtl + gtlplus gtp + lvds lvs + blvds blv + mlvds mlv + lvpecl lvp + cml cml + hypt hyp + rsds rsd + vref1 vr1 + vref2 vr2 + ref_res rer +| +| + slew + na a + fast f + slow s +| + pullmode + off a + pullup b + pulldown c + bushold d + pciclamp e + up_pciclamp f + down_pciclamp g + keeper_pciclamp h + schmitt i + up_schmitt j + down_schmitt k + keeper_schmitt l + up_pciclamp_schmitt m + down_pciclamp_schmitt n + keeper_pciclamp_schmitt o + pciclamp_schmitt p +| + impedence + off a + 25 b + 33 c + 50 d + 100 e +| + termVCC + off a + 50 b + 100 c + 120 d +| + termGND + off a + 50 b + 100 c + 120 d +| + termVTT + off a + 60 b + 75 c + 120 d + 150 e + 210 f +| + VCMT + off a + VCMT b + VTT c + DDR-2 d +| + differential resistor + off a + 120 b + 150 c + 220 d + 420 e +| + differential current + NA a + 2 b + 3.5 c + 4 d + 6 e +| + Reserved IO type + in input only + ou output + io I/O + od Open drain + on Inverting differential I/O + (signal name only) + op Non-Inverting differential I/O + (signal name only) +| + All the IO models are generated with pull mode set to UP. +| + Lattice Semiconductor Corporation + 5555 NE Moore Court + Hillsboro, OR 97214 + U.S.A +| + TEL: 1-800-Lattice (USA and Canada) + 408-826-6000 (other locations) +| + web: http://www.latticesemi.com/ + email: techsupport@latticesemi.com +| +| +| +[Disclaimer] This IBIS source code is intended as a design reference + which illustrates how the Lattice Semiconductor device operates. + It is the user's responsibility to verify their design for + consistency and functionality through the use of formal + verification methods. Lattice Semiconductor provides no warranty + regarding the use or functionality of this data. +| +[Copyright] Copyright 2009 by Lattice Semiconductor Corporation +| +| +|************************************************************************ +| Component XO +|************************************************************************ +| +[Component] MXO256_MXO640_MXO1K_MXO2K +[Manufacturer] Lattice Semiconductor Corp. +[Package] +|TQFP100 +| variable typ min max +R_pkg 70.5m 54.0m 87.0m +L_pkg 4.57nH 4.27nH 4.87nH +C_pkg .52pF .47pF .57pF +| +[Pin] signal_name model_name R_pin L_pin C_pin +32 CROW[0] lvt330fxxxaaaaaaaain +34 CROW[1] lvt330fxxxaaaaaaaain +21 Din[0] lvt330fxxxaaaaaaaain +15 Din[1] lvt330fxxxaaaaaaaain +14 Din[2] lvt330fxxxaaaaaaaain +16 Din[3] lvt330fxxxaaaaaaaain +18 Din[4] lvt330fxxxaaaaaaaain +17 Din[5] lvt330fxxxaaaaaaaain +20 Din[6] lvt330fxxxaaaaaaaain +19 Din[7] lvt330fxxxaaaaaaaain +1 Dout[0] lvt330s040aaaaaaaaio +7 Dout[1] lvt330s040aaaaaaaaio +8 Dout[2] lvt330s040aaaaaaaaio +6 Dout[3] lvt330s040aaaaaaaaio +4 Dout[4] lvt330s040aaaaaaaaio +5 Dout[5] lvt330s040aaaaaaaaio +2 Dout[6] lvt330s040aaaaaaaaio +3 Dout[7] lvt330s040aaaaaaaaio +57 LED lvt330s160aaaaaaaaio +23 MAin[0] lvt330fxxxaaaaaaaain +38 MAin[1] lvt330fxxxaaaaaaaain +37 MAin[2] lvt330fxxxaaaaaaaain +47 MAin[3] lvt330fxxxaaaaaaaain +46 MAin[4] lvt330fxxxaaaaaaaain +45 MAin[5] lvt330fxxxaaaaaaaain +49 MAin[6] lvt330fxxxaaaaaaaain +44 MAin[7] lvt330fxxxaaaaaaaain +50 MAin[8] lvt330fxxxaaaaaaaain +51 MAin[9] lvt330fxxxaaaaaaaain +39 PHI2 lvt330fxxxaaaaaaaain +98 RA[0] lvt330s040aaaaaaaaio +87 RA[10] lvt330s040aaaaaaaaio +79 RA[11] lvt330s040aaaaaaaaio +89 RA[1] lvt330s040aaaaaaaaio +94 RA[2] lvt330s040aaaaaaaaio +97 RA[3] lvt330s040aaaaaaaaio +99 RA[4] lvt330s040aaaaaaaaio +95 RA[5] lvt330s040aaaaaaaaio +91 RA[6] lvt330s040aaaaaaaaio +100 RA[7] lvt330s040aaaaaaaaio +96 RA[8] lvt330s040aaaaaaaaio +85 RA[9] lvt330s040aaaaaaaaio +63 RBA[0] lvt330s040aaaaaaaaio +83 RBA[1] lvt330s040aaaaaaaaio +82 RCKE lvt330s040aaaaaaaaio +86 RCLK lvt330fxxxaaaaaaaain +76 RDQMH lvt330s040aaaaaaaaio +61 RDQML lvt330s040aaaaaaaaio +64 RD[0] lvt330s040aaaaaaaaio +65 RD[1] lvt330s040aaaaaaaaio +66 RD[2] lvt330s040aaaaaaaaio +67 RD[3] lvt330s040aaaaaaaaio +68 RD[4] lvt330s040aaaaaaaaio +69 RD[5] lvt330s040aaaaaaaaio +70 RD[6] lvt330s040aaaaaaaaio +71 RD[7] lvt330s040aaaaaaaaio +58 UFMCLK lvt330s040aaaaaaaaio +56 UFMSDI lvt330s040aaaaaaaaio +55 UFMSDO lvt330fxxxaaaaaaaain +27 nCCAS lvt330fxxxaaaaaaaain +43 nCRAS lvt330fxxxaaaaaaaain +22 nFWE lvt330fxxxaaaaaaaain +78 nRCAS lvt330s040aaaaaaaaio +77 nRCS lvt330s040aaaaaaaaio +73 nRRAS lvt330s040aaaaaaaaio +72 nRWE lvt330s040aaaaaaaaio +53 nUFMCS lvt330s040aaaaaaaaio +|************************************************************************ +[Model] lvt330fxxxaaaaaaaain +Model_type Input +Polarity Non-Inverting +Enable Active-Low +Vinl = 0.800000V +Vinh = 2.000000V +C_comp 2.68pF 2.54pF 2.92pF +| +| +[Temperature Range] 25.000000 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2.632200V 2.956500V +| +| End [Model] lvt330s040aaaaaaaaio +|************************************************************************ +[Model] lvt330s160aaaaaaaaio +Model_type I/O +Polarity Non-Inverting +Enable Active-Low +Vinl = 0.800000V +Vinh = 2.000000V +Vmeas = 1.650000V +Cref = 0.0F +Rref = 1.000000M +Vref = 0.0V +C_comp 2.68pF 2.54pF 2.92pF +| +| +[Temperature Range] 25.000000 0.105000k -40.000000 +[Voltage Range] 3.300000V 3.140000V 3.470000V +[Pulldown] +|Voltage I(typ) I(min) I(max) +| + -3.30 -50.584550mA -43.999960mA -54.623576mA + -3.20 -50.404450mA -43.837800mA -54.427552mA + -3.10 -50.224350mA -43.675640mA -54.231528mA + -3.00 -50.044250mA -43.513480mA -54.035504mA + -2.90 -49.864150mA -43.351320mA -53.839480mA + -2.80 -49.684050mA -43.189160mA -53.643456mA + -2.70 -49.503950mA -43.027000mA -53.447432mA + -2.60 -49.323850mA -42.864840mA -53.251408mA + -2.50 -49.143750mA -42.702680mA -53.055384mA + -2.40 -48.963650mA -42.540520mA -52.859360mA + -2.30 -48.783550mA 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-4.818400uV +20.0000ns -1.206900uV 12.109000uV -4.724200uV +| +[Falling Waveform] +R_fixture= 50.000000 +V_fixture= 3.300000 +V_fixture_min= 3.140000 +V_fixture_max= 3.470000 +|time V(typ) V(min) V(max) +| +0.0S 3.300000V 3.140000V 3.470000V +0.2020ns 3.299700V 3.140000V 3.468500V +0.4040ns 3.300800V 3.139500V 3.480800V +0.6061ns 3.307700V 3.140100V 3.421400V +0.8081ns 3.288700V 3.143500V 3.119600V +1.0101ns 3.205000V 3.143800V 2.661400V +1.2121ns 3.025100V 3.145800V 2.287000V +1.4141ns 2.763000V 3.126600V 2.008100V +1.6162ns 2.525800V 3.091800V 1.804300V +1.8182ns 2.335100V 3.031500V 1.669500V +2.0202ns 2.176400V 2.950000V 1.556300V +2.2222ns 2.038500V 2.833800V 1.492000V +2.4242ns 1.931900V 2.695300V 1.454000V +2.6263ns 1.842100V 2.569900V 1.511700V +2.8283ns 1.775200V 2.465400V 1.518000V +3.0303ns 1.725800V 2.375800V 1.523200V +3.2323ns 1.686600V 2.288200V 1.528200V +3.4343ns 1.685200V 2.209700V 1.533400V +3.6364ns 1.704000V 2.138800V 1.538300V +3.8384ns 1.711300V 2.070500V 1.543000V +4.0404ns 1.712500V 2.009900V 1.547600V +4.2424ns 1.714100V 1.956200V 1.552200V +4.4444ns 1.715500V 1.910000V 1.556700V +4.6465ns 1.717000V 1.869400V 1.561200V +4.8485ns 1.718600V 1.839700V 1.565600V +5.0505ns 1.719900V 1.823800V 1.569900V +5.2525ns 1.721200V 1.826000V 1.574200V +5.4545ns 1.722500V 1.835200V 1.578400V +5.6566ns 1.723800V 1.841500V 1.582600V +5.8586ns 1.725000V 1.842800V 1.586700V +6.0606ns 1.726200V 1.841300V 1.590800V +6.2626ns 1.727400V 1.839800V 1.594800V +6.4646ns 1.728600V 1.838400V 1.598800V +6.6667ns 1.729800V 1.837000V 1.602700V +6.8687ns 1.730900V 1.835500V 1.606600V +7.0707ns 1.732000V 1.834000V 1.610400V +7.2727ns 1.733200V 1.832700V 1.614200V +7.4747ns 1.734300V 1.831300V 1.618000V +7.6768ns 1.735400V 1.829900V 1.621600V +7.8788ns 1.736400V 1.828500V 1.625300V +8.0808ns 1.737500V 1.827100V 1.628900V +8.2828ns 1.738600V 1.825800V 1.632500V +8.4848ns 1.739600V 1.824400V 1.636000V +8.6869ns 1.740600V 1.823100V 1.639400V +8.8889ns 1.741700V 1.821800V 1.642900V +9.0909ns 1.742700V 1.820400V 1.646300V +9.2929ns 1.743700V 1.819100V 1.649600V +9.4949ns 1.744700V 1.817800V 1.652900V +9.6970ns 1.745600V 1.816500V 1.656200V +9.8990ns 1.746600V 1.815200V 1.659400V +10.1010ns 1.748050V 1.813350V 1.664200V +10.3030ns 1.749400V 1.811400V 1.668900V +10.5051ns 1.750400V 1.810200V 1.672000V +10.7071ns 1.751300V 1.809000V 1.675000V +10.9091ns 1.752200V 1.807800V 1.678000V +11.1111ns 1.753100V 1.806500V 1.681000V +11.3131ns 1.753900V 1.805400V 1.684000V +11.5152ns 1.754800V 1.804200V 1.686900V +11.7172ns 1.755700V 1.803000V 1.689700V +11.9192ns 1.756500V 1.801800V 1.692600V +12.1212ns 1.757400V 1.800700V 1.695400V +12.3232ns 1.758200V 1.799500V 1.698200V +12.5253ns 1.759000V 1.798400V 1.700900V +12.7273ns 1.759800V 1.797300V 1.703600V +12.9293ns 1.760600V 1.796200V 1.706300V +13.1313ns 1.761400V 1.795100V 1.709000V +13.3333ns 1.762200V 1.794000V 1.711600V +13.5354ns 1.763000V 1.792900V 1.714200V +13.7374ns 1.763800V 1.791800V 1.716700V +13.9394ns 1.764500V 1.790800V 1.719300V +14.1414ns 1.765300V 1.789700V 1.721800V +14.3434ns 1.766000V 1.788700V 1.724200V +14.5455ns 1.766800V 1.787700V 1.726700V +14.7475ns 1.767500V 1.786600V 1.729100V +14.9495ns 1.768200V 1.785600V 1.731500V +15.1515ns 1.768900V 1.784600V 1.733900V +15.3535ns 1.769600V 1.783600V 1.736200V +15.5556ns 1.770300V 1.782700V 1.738500V +15.7576ns 1.771000V 1.781700V 1.740800V +15.9596ns 1.771700V 1.780700V 1.743100V +16.1616ns 1.772400V 1.779800V 1.745300V +16.3636ns 1.773000V 1.778800V 1.747500V +16.5657ns 1.773700V 1.777900V 1.749700V +16.7677ns 1.774300V 1.777000V 1.751900V +16.9697ns 1.775000V 1.776000V 1.754000V +17.1717ns 1.775600V 1.775100V 1.756200V +17.3737ns 1.776300V 1.774200V 1.758300V +17.5758ns 1.776900V 1.773300V 1.760300V +17.7778ns 1.777500V 1.772400V 1.762400V +17.9798ns 1.778100V 1.771600V 1.764400V +18.1818ns 1.778700V 1.770700V 1.766400V +18.3838ns 1.779300V 1.769800V 1.768400V +18.5859ns 1.779900V 1.769000V 1.770400V +18.7879ns 1.780500V 1.768100V 1.772300V +18.9899ns 1.781100V 1.767300V 1.774200V +19.1919ns 1.781600V 1.766500V 1.776200V +19.3939ns 1.782200V 1.765700V 1.778000V +19.5960ns 1.782800V 1.764900V 1.779900V +19.7980ns 1.783300V 1.764000V 1.781700V +|20.0000ns 1.783900V 1.763300V 1.783600V +40.0000ns 1.783900V 1.550000V 1.783600V +| +| End [Model] lvt330s160aaaaaaaaio +|************************************************************************ +| End [Component] +[End] diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt new file mode 100644 index 0000000..c790bb7 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep new file mode 100644 index 0000000..896bbfa --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep @@ -0,0 +1,24 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 490 (20.816%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2 9 100.0 + FD1P3AX 28 100.0 + FD1P3AY 3 100.0 + FD1P3IX 2 100.0 + FD1P3JX 1 100.0 + FD1S3AX 47 100.0 + FD1S3AY 1 100.0 + FD1S3IX 16 100.0 + FD1S3JX 4 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 114 100.0 + OB 33 100.0 + ORCALUT4 2 100.0 + PFUMX 3 100.0 + TOTAL 301 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn new file mode 100644 index 0000000..e67344f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn @@ -0,0 +1,45 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:36:25 2021 + + +Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO256C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 44 MB diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit new file mode 100644 index 0000000..2c02b6d Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd new file mode 100644 index 0000000..ea7b083 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad new file mode 100644 index 0000000..0445323 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Mon Aug 16 21:32:33 2021 + +Pinout by Port Name: ++-----------+----------+--------------+------+----------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+--------------+------+----------------------------------+ +| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | +| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | +| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | +| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | +| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | +| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | +| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | +| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | +| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | +| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | +| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | +| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | +| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | +| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | +| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | +| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | +| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | +| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | +| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | +| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | +| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | +| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | +| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | +| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | +| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | +| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | +| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | +| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | +| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | +| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | +| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | +| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | +| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | +| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | +| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | +| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | +| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | +| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | +| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | +| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | +| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | +| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | +| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | +| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | +| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | +| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | +| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | +| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | +| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | +| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | +| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | +| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | +| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | +| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | +| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | +| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | +| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | +| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | ++-----------+----------+--------------+------+----------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+--------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+--------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+--------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:33 2021 + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par new file mode 100644 index 0000000..5d8ae58 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par @@ -0,0 +1,211 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Mon Aug 16 21:32:27 2021 + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 65/128 50% used + + + +Number of Signals: 252 +Number of Connections: 618 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 4 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 13) + nCCAS_c (driver: nCCAS, clk load #: 4) + nCRAS_c (driver: nCRAS, clk load #: 7) + +No signal is selected as secondary clock. + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 586066. +Finished Placer Phase 1. REAL time: 6 secs + +Starting Placer Phase 2. +. +Placer score = 584668 +Finished Placer Phase 2. REAL time: 6 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 3 out of 80 (3%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 + + PRIMARY : 4 out of 4 (100%) + SECONDARY: 0 out of 4 (0%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 6 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 618 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 6 secs + +Start NBR router at 21:32:33 08/16/21 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:32:33 08/16/21 + +Start NBR section for initial routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 2, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 3, iteration 1 +0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 2 +4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 3 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 + +Start NBR section for re-routing at 21:32:33 08/16/21 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for post-routing at 21:32:33 08/16/21 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 2.023ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 6 secs +Total REAL time: 7 secs +Completely routed. +End of route. 618 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 2.023 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.339 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 6 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..6e5f093 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd @@ -0,0 +1,33 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 4; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 39; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; Global primary clock #2 +GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c; +GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_2_LOADNUM = 4; +; Global primary clock #3 +GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c; +GLOBAL_PRIMARY_3_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_3_LOADNUM = 7; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 0; +; I/O Bank 0 Usage +BANK_0_USED = 36; +BANK_0_AVAIL = 41; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 31; +BANK_1_AVAIL = 37; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..feb14ae --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:27 2021 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 2.023 0 0.339 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed new file mode 100644 index 0000000..b3a7f61 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed @@ -0,0 +1,977 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.0.240.2* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out 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08/16/21 21:32:26 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 65 out of 128 (51%) + SLICEs as Logic/ROM: 65 out of 128 (51%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 129 out of 256 (50%) + Number used as logic LUTs: 111 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 13 + Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs + Net RCLK_c_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net RCLK_c_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs + Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs + Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Net Ready_N_268: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net C1Submitted_N_225: 2 loads, 2 LSLICEs + Net n2299: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net LEDEN_N_88: 1 loads, 1 LSLICEs + Net n2291: 2 loads, 2 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_173: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 19 loads + Net InitReady: 17 loads + Net RASr2: 16 loads + Net nRowColSel_N_35: 14 loads + Net nRowColSel: 13 loads + Net Din_c_6: 9 loads + Net MAin_c_1: 9 loads + Net Din_c_5: 8 loads + Net FS_11: 8 loads + Net MAin_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 2 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| RD[1] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| nRRAS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| nCCAS | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_114 was merged into signal PHI2_c +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal n2302 was merged into signal nRowColSel_N_35 +Signal nRWE_N_172 was merged into signal nRWE_N_173 +Signal n2307 was merged into signal Ready +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1377 was merged into signal nRowColSel_N_34 +Signal n2306 was merged into signal nFWE_c +Signal UFMSDO_N_74 was merged into signal UFMSDO_c +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped. +Block i1962 was optimized away. +Block i1961 was optimized away. +Block i1963 was optimized away. +Block i1070_1_lut_rep_25 was optimized away. +Block nRWE_I_49_1_lut was optimized away. +Block i604_1_lut_rep_30 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1069_1_lut was optimized away. +Block i1_1_lut_rep_29 was optimized away. +Block UFMSDO_I_0_1_lut was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 29 MB + + Page 5 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +Run Time and Memory Usage (cont) +-------------------------------- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 6 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e new file mode 100644 index 0000000..c5da0e1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e @@ -0,0 +1,574 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234) +ADSubmitted.D = n1361 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_225 +n2080 = (~MAin_c_0*(~ADSubmitted*n2122)) + +comp 10: SLICE_14 (FSLICE) +n2386 = GND +C1Submitted.D = n2386 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = PHI2_N_114_enable_1 +C1Submitted.LSR = C1Submitted_N_225 +n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108))) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225) +CmdEnable.D = CmdEnable_N_236 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_114_enable_8 +CmdEnable.LSR = GND +XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1))) + +comp 12: SLICE_19 (FSLICE) +n2387\000/BUF1 = VCC +CmdSubmitted.D = n2387\000/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_114_enable_6 +CmdSubmitted.LSR = GND +n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_248 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_114_enable_6 +Cmdn8MEGEN.LSR = GND +n2296 = (~Din_c_4+(Din_c_6+Din_c_7)) + +comp 14: SLICE_25 (FSLICE) +n2387 = VCC +InitReady.D = n2387 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_6 +InitReady.LSR = GND +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) + +comp 15: SLICE_31 (FSLICE) +RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_180 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2385 = (Din_c_6+Din_c_7) + +comp 16: SLICE_33 (FSLICE) +RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116) +RCKEEN.D = RCKEEN_N_115 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308)) + +comp 17: SLICE_34 (FSLICE) +RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_128 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_178 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 18: SLICE_35 (FSLICE) +n2387\001/BUF1 = VCC +Ready.D = n2387\001/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_268 +Ready.LSR = GND +RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready))) + +comp 19: SLICE_42 (FSLICE) +UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK)) +UFMCLK_c.D = UFMCLK_N_212 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n2291 +RCLK_c_enable_6 = (n2076*FS_10) + +comp 20: SLICE_43 (FSLICE) +UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI) +UFMSDI_c.D = UFMSDI_N_219 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n2291 +n1895 = (~FS_10*(n2103*(~n2293*FS_6))) + +comp 21: SLICE_55 (FSLICE) +n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready) +n980.D = n2128 +n980.CLK = RCLK_c +n980.SP = VCC +n980.LSR = ~nRWE_N_173 +n2301 = (~InitReady+~RASr2) + +comp 22: SLICE_56 (FSLICE) +n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_94 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_7 +n8MEGEN.LSR = GND +n4 = ((~FS_11+n2300)+InitReady) + +comp 23: SLICE_58 (FSLICE) +nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287) +nRCAS_c.D = nRCAS_N_157 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND +n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR))) + +comp 24: SLICE_60 (FSLICE) +nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready) +nRCS_c.D = nRCS_N_132 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND + +comp 25: SLICE_61 (FSLICE) +n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18)) +nRRAS_c.D = n33 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND +n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND + +comp 26: SLICE_62 (FSLICE) +n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS) +nRWE_N_173.D = n705 +nRWE_N_173.CLK = RCLK_c +nRWE_N_173.SP = RCLK_c_enable_23 +nRWE_N_173.LSR = GND +nRCS_N_135.D = Ready_N_272 +nRCS_N_135.CLK = RCLK_c +nRCS_N_135.SP = RCLK_c_enable_23 +nRCS_N_135.LSR = GND + +comp 27: SLICE_63 (FSLICE) +nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174)) +nRWE_c.D = nRWE_N_167 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178) + +comp 28: SLICE_64 (FSLICE) +n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627)) +nRowColSel.D = n1368 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2299 +RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) + +comp 29: SLICE_65 (FSLICE) +n1628 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1628 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 30: SLICE_66 (FSLICE) +n1135 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1135 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34)) + +comp 31: SLICE_67 (FSLICE) +LED_N_90 = (~LEDEN+nCRAS_c) +nRowColSel_N_34.D = n1135 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n2154 = (MAin_c_4*Bank_7) + +comp 32: SLICE_68 (FSLICE) +n2168 = (FS_3*(FS_2*(FS_0*FS_1))) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n962 = (nCCAS_c+nFWE_c) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 33: SLICE_69 (FSLICE) +n1348 = (~InitReady*n2076+InitReady*n1369) +nUFMCS_c.D = n1348 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_88 +n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15))) + +comp 34: i1912/SLICE_70 (FSLICE) +n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready) + +comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE) +RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: SLICE_72 (FSLICE) +PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112))) +n702.D = n703 +n702.CLK = RCLK_c +n702.SP = RCLK_c_enable_23 +n702.LSR = GND +n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4) +n701.D = n702 +n701.CLK = RCLK_c +n701.SP = RCLK_c_enable_23 +n701.LSR = GND + +comp 37: SLICE_73 (FSLICE) +n11 = (~n2168+((~FS_11+n2300)+FS_6)) +n706.D = n707 +n706.CLK = RCLK_c +n706.SP = RCLK_c_enable_23 +n706.LSR = GND +n2300 = ((FS_16+n10)+FS_17) +n705.D = n706 +n705.CLK = RCLK_c +n705.SP = RCLK_c_enable_23 +n705.LSR = GND + +comp 38: SLICE_74 (FSLICE) +C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122))) +n710.D = n711 +n710.CLK = RCLK_c +n710.SP = RCLK_c_enable_23 +n710.LSR = GND +n2295 = (n2114*~nFWE_c) +n709.D = n710 +n709.CLK = RCLK_c +n709.SP = RCLK_c_enable_23 +n709.LSR = GND + +comp 39: SLICE_75 (FSLICE) +n2119 = (~n12*(~n11*(FS_10*n2294))) +n708.D = n709 +n708.CLK = RCLK_c +n708.SP = RCLK_c_enable_23 +n708.LSR = GND +RCLK_c_enable_25 = (n2119*(FS_5*~InitReady)) +n707.D = n708 +n707.CLK = RCLK_c +n707.SP = RCLK_c_enable_23 +n707.LSR = GND + +comp 40: SLICE_76 (FSLICE) +n2131 = ((~MAin_c_1+n1285)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26))) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 41: SLICE_77 (FSLICE) +PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290)) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098)) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 42: SLICE_78 (FSLICE) +n10 = (((FS_14+FS_13)+FS_12)+FS_15) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2294 = (((FS_16+n10)+FS_17)+FS_11) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 43: SLICE_79 (FSLICE) +n1627 = (nRowColSel_N_34+nRowColSel_N_33) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 44: SLICE_80 (FSLICE) +ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108))) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2289 = (~MAin_c_1+n1285) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 45: SLICE_81 (FSLICE) +n4_adj_1 = (n2114*(Din_c_2*~nFWE_c)) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0))) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 46: SLICE_82 (FSLICE) +n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2))) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 47: SLICE_83 (FSLICE) +n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_114_enable_7 +CmdUFMCLK.LSR = GND +Ready_N_268 = (n2245+Ready) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_114_enable_7 +CmdUFMCS.LSR = GND + +comp 48: SLICE_84 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +nRCAS_N_161.D = nRCS_N_135 +nRCAS_N_161.CLK = RCLK_c +nRCAS_N_161.SP = RCLK_c_enable_23 +nRCAS_N_161.LSR = GND +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +n703.D = nRWE_N_173 +n703.CLK = RCLK_c +n703.SP = RCLK_c_enable_23 +n703.LSR = GND + +comp 49: SLICE_85 (FSLICE) +n12 = (((~FS_4+FS_9)+FS_8)+FS_7) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8))) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 50: SLICE_86 (FSLICE) +n2291 = (~InitReady*(~n2300*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11))) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 51: SLICE_87 (FSLICE) +n2122 = (~Din_c_5*(Din_c_6*~Din_c_3)) +Ready_N_272.D = n699 +Ready_N_272.CLK = RCLK_c +Ready_N_272.SP = RCLK_c_enable_23 +Ready_N_272.LSR = GND +n2108 = (Din_c_3*(Din_c_5*~Din_c_6)) +n711.D = nRCAS_N_161 +n711.CLK = RCLK_c +n711.SP = RCLK_c_enable_23 +n711.LSR = GND + +comp 52: SLICE_88 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_114_enable_7 +CmdUFMSDI.LSR = GND +RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 53: SLICE_89 (FSLICE) +n2290 = (nFWE_c+n1285) +LEDEN.D = ~UFMSDO_c +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_25 +LEDEN.LSR = GND +PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c)) + +comp 54: SLICE_90 (FSLICE) +PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6))) +n700.D = n701 +n700.CLK = RCLK_c +n700.SP = RCLK_c_enable_23 +n700.LSR = GND +PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385))) +n699.D = n700 +n699.CLK = RCLK_c +n699.SP = RCLK_c_enable_23 +n699.LSR = GND + +comp 55: SLICE_91 (FSLICE) +n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135)) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135))) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 56: SLICE_92 (FSLICE) +RDQML_c = (~nRowColSel+~MAin_c_9) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 57: SLICE_93 (FSLICE) +n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n2293 = (~FS_11+((FS_16+n10)+FS_17)) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 58: SLICE_94 (FSLICE) +RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 59: SLICE_95 (FSLICE) +RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 60: SLICE_96 (FSLICE) +n2299 = (~Ready+nRowColSel_N_35) +XOR8MEG.D = Din_c_0 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_114_enable_2 +XOR8MEG.LSR = GND +n2297 = (~nRowColSel_N_35+nRCS_N_135) + +comp 61: SLICE_97 (FSLICE) +RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 62: SLICE_98 (FSLICE) +RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 63: SLICE_99 (FSLICE) +n2164 = (nRCAS_N_161+nRWE_N_173) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n18 = (nRowColSel_N_34*~nRowColSel_N_35) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 64: SLICE_100 (FSLICE) +n11_adj_3 = (~CASr2+nRowColSel_N_33) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n2304 = (FWEr+CBR) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd new file mode 100644 index 0000000..ea7b083 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd new file mode 100644 index 0000000..28c0d67 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 new file mode 100644 index 0000000..eb789dd --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t new file mode 100644 index 0000000..e625c68 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO256C_impl1.log" +-o "RAM2GS_LCMXO256C_impl1.csv" +-pr "RAM2GS_LCMXO256C_impl1.prf" diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad new file mode 100644 index 0000000..0445323 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Mon Aug 16 21:32:33 2021 + +Pinout by Port Name: ++-----------+----------+--------------+------+----------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+--------------+------+----------------------------------+ +| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | +| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | +| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | +| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | +| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | +| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | +| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | +| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | +| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | +| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | +| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | +| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | +| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | +| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | +| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | +| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | +| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | +| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | +| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | +| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | +| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | +| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | +| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | +| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | +| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | +| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | +| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | +| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | +| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | +| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | +| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | +| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | +| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | +| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | +| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | +| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | +| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | +| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | +| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | +| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | +| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | +| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | +| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | +| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | +| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | +| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | +| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | +| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | +| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | +| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | +| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | +| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | +| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | +| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | +| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | +| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | +| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | +| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | ++-----------+----------+--------------+------+----------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+--------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+--------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+--------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:33 2021 + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..6275f58 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,239 @@ +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:27 2021 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 2.023 0 0.339 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Mon Aug 16 21:32:27 2021 + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 65/128 50% used + + + +Number of Signals: 252 +Number of Connections: 618 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 4 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 13) + nCCAS_c (driver: nCCAS, clk load #: 4) + nCRAS_c (driver: nCRAS, clk load #: 7) + +No signal is selected as secondary clock. + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 586066. +Finished Placer Phase 1. REAL time: 6 secs + +Starting Placer Phase 2. +. +Placer score = 584668 +Finished Placer Phase 2. REAL time: 6 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 3 out of 80 (3%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 + + PRIMARY : 4 out of 4 (100%) + SECONDARY: 0 out of 4 (0%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 6 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 618 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 6 secs + +Start NBR router at 21:32:33 08/16/21 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:32:33 08/16/21 + +Start NBR section for initial routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 2, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 3, iteration 1 +0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 2 +4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 3 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 + +Start NBR section for re-routing at 21:32:33 08/16/21 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for post-routing at 21:32:33 08/16/21 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 2.023ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 6 secs +Total REAL time: 7 secs +Completely routed. +End of route. 618 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 2.023 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.339 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 6 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf new file mode 100644 index 0000000..4d03744 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf @@ -0,0 +1,165 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +PERIOD NET "PHI2_c" 350.000000 ns ; +USE PRIMARY NET "RCLK_c" ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +USE PRIMARY NET "PHI2_c" ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +USE PRIMARY NET "nCCAS_c" ; +PERIOD NET "RCLK_c" 16.000000 ns ; +USE PRIMARY NET "nCRAS_c" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +COMMERCIAL ; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 new file mode 100644 index 0000000..f728d52 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 @@ -0,0 +1,2507 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:27 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.873ns (21.6% logic, 78.4% route), 7 logic levels. + + Constraint Details: + + 12.873ns physical path delay SLICE_95 to SLICE_19 meets + 175.000ns delay constraint less + 0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_95.CLK to SLICE_95.Q1 SLICE_95 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_95.Q1 to SLICE_67.A1 Bank_7 +CTOF_DEL --- 0.371 SLICE_67.A1 to SLICE_67.F1 SLICE_67 +ROUTE 1 e 1.441 SLICE_67.F1 to SLICE_82.C1 n2154 +CTOF_DEL --- 0.371 SLICE_82.C1 to SLICE_82.F1 SLICE_82 +ROUTE 1 e 1.441 SLICE_82.F1 to SLICE_76.B1 n26 +CTOF_DEL --- 0.371 SLICE_76.B1 to SLICE_76.F1 SLICE_76 +ROUTE 4 e 1.441 SLICE_76.F1 to SLICE_89.B0 n1285 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 3 e 1.441 SLICE_89.F0 to SLICE_18.D1 n2290 +CTOF_DEL --- 0.371 SLICE_18.D1 to SLICE_18.F1 SLICE_18 +ROUTE 3 e 1.441 SLICE_18.F1 to SLICE_90.C0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 SLICE_90.C0 to SLICE_90.F0 SLICE_90 +ROUTE 2 e 1.441 SLICE_90.F0 to SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.873 (21.6% logic, 78.4% route), 7 logic levels. + +Report: 26.276ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_76 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_77 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.575ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 10.181ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.181ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 e 1.441 SLICE_7.Q0 to SLICE_78.A0 FS_14 +CTOF_DEL --- 0.371 SLICE_78.A0 to SLICE_78.F0 SLICE_78 +ROUTE 3 e 1.441 SLICE_78.F0 to SLICE_73.B1 n10 +CTOF_DEL --- 0.371 SLICE_73.B1 to SLICE_73.F1 SLICE_73 +ROUTE 4 e 0.561 SLICE_73.F1 to SLICE_73.B0 n2300 +CTOF_DEL --- 0.371 SLICE_73.B0 to SLICE_73.F0 SLICE_73 +ROUTE 1 e 1.441 SLICE_73.F0 to SLICE_75.C0 n11 +CTOF_DEL --- 0.371 SLICE_75.C0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_33.D1 n2119 +CTOF_DEL --- 0.371 SLICE_33.D1 to SLICE_33.F1 SLICE_33 +ROUTE 1 e 1.441 SLICE_33.F1 to SLICE_56.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 10.181 (23.7% logic, 76.3% route), 6 logic levels. + +Report: 10.425ns is the minimum period for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_55 and + 5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets + 12.500ns offset RCLK to RA[10] by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_55.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_55.Q0 to 87.PADDO n980 +DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[9] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.441 SLICE_88.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[8] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_95.C0 to SLICE_95.F0 SLICE_95 +ROUTE 1 e 1.441 SLICE_95.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[7] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_97.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_97.C0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[6] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_98.C0 to SLICE_98.F0 SLICE_98 +ROUTE 1 e 1.441 SLICE_98.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[5] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_98.C1 to SLICE_98.F1 SLICE_98 +ROUTE 1 e 1.441 SLICE_98.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.427ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 6.569ns (69.5% logic, 30.5% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets + 12.500ns offset RCLK to RA[4] by 3.427ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.561 SLICE_64.Q0 to SLICE_64.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 1 e 1.441 SLICE_64.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] + -------- + 6.569 (69.5% logic, 30.5% route), 3 logic levels. + +Report: 9.073ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[3] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_94.C1 to SLICE_94.F1 SLICE_94 +ROUTE 1 e 1.441 SLICE_94.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[2] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_95.C1 to SLICE_95.F1 SLICE_95 +ROUTE 1 e 1.441 SLICE_95.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[1] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_94.C0 to SLICE_94.F0 SLICE_94 +ROUTE 1 e 1.441 SLICE_94.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[0] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_92.C1 to SLICE_92.F1 SLICE_92 +ROUTE 1 e 1.441 SLICE_92.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_60 and + 5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRCS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_60.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_60.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_34 and + 5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets + 12.500ns offset RCLK to RCKE by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_34.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 e 1.441 SLICE_34.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_63 and + 5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets + 12.500ns offset RCLK to nRWE by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_63.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_63.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_61 and + 5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRRAS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_61.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 e 1.441 SLICE_61.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_58 and + 5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRCAS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_58.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_58.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets + 12.500ns offset RCLK to RDQMH by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.B0 nRowColSel +CTOF_DEL --- 0.371 SLICE_88.B0 to SLICE_88.F0 SLICE_88 +ROUTE 1 e 1.441 SLICE_88.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets + 12.500ns offset RCLK to RDQML by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.B0 nRowColSel +CTOF_DEL --- 0.371 SLICE_92.B0 to SLICE_92.F0 SLICE_92 +ROUTE 1 e 1.441 SLICE_92.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.276 ns| 7 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 10.425 ns| 6 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.073 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:27 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.485ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in ADSubmitted_380 (to PHI2_c -) + + Delay: 0.462ns (56.7% logic, 43.3% route), 2 logic levels. + + Constraint Details: + + 0.462ns physical path delay SLICE_9 to SLICE_9 meets + -0.023ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 SLICE_9.CLK to SLICE_9.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_9.Q0 to SLICE_9.C0 ADSubmitted +CTOF_DEL --- 0.092 SLICE_9.C0 to SLICE_9.F0 SLICE_9 +ROUTE 1 e 0.001 SLICE_9.F0 to SLICE_9.DI0 n1361 (to PHI2_c) + -------- + 0.462 (56.7% logic, 43.3% route), 2 logic levels. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.377ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i11 (from RCLK_c +) + Destination: FF Data in IS_FSM__i12 (to RCLK_c +) + + Delay: 0.356ns (44.1% logic, 55.9% route), 1 logic levels. + + Constraint Details: + + 0.356ns physical path delay SLICE_72 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_72.CLK to SLICE_72.Q0 SLICE_72 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_72.Q0 to SLICE_72.M1 n702 (to RCLK_c) + -------- + 0.356 (44.1% logic, 55.9% route), 1 logic levels. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_55 and + 1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets + 0.000ns hold offset RCLK to RA[10] by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_55.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_55.Q0 to 87.PADDO n980 +DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[9] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 0.515 SLICE_88.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[8] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_95.C0 to SLICE_95.F0 SLICE_95 +ROUTE 1 e 0.515 SLICE_95.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[7] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_97.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_97.C0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 0.515 SLICE_97.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[6] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_98.C0 to SLICE_98.F0 SLICE_98 +ROUTE 1 e 0.515 SLICE_98.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[5] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_98.C1 to SLICE_98.F1 SLICE_98 +ROUTE 1 e 0.515 SLICE_98.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.850ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 2.071ns (65.5% logic, 34.5% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets + 0.000ns hold offset RCLK to RA[4] by 2.850ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.199 SLICE_64.Q0 to SLICE_64.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 1 e 0.515 SLICE_64.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] + -------- + 2.071 (65.5% logic, 34.5% route), 3 logic levels. + +Report: 2.850ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[3] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_94.C1 to SLICE_94.F1 SLICE_94 +ROUTE 1 e 0.515 SLICE_94.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[2] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_95.C1 to SLICE_95.F1 SLICE_95 +ROUTE 1 e 0.515 SLICE_95.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[1] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_94.C0 to SLICE_94.F0 SLICE_94 +ROUTE 1 e 0.515 SLICE_94.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[0] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_92.C1 to SLICE_92.F1 SLICE_92 +ROUTE 1 e 0.515 SLICE_92.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_60 and + 1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRCS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_60.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_60.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_34 and + 1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets + 0.000ns hold offset RCLK to RCKE by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_34.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 e 0.515 SLICE_34.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_63 and + 1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRWE by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_63.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_63.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_61 and + 1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRRAS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_61.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 e 0.515 SLICE_61.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_58 and + 1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRCAS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_58.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_58.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RDQMH by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.B0 nRowColSel +CTOF_DEL --- 0.092 SLICE_88.B0 to SLICE_88.F0 SLICE_88 +ROUTE 1 e 0.515 SLICE_88.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RDQML by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.B0 nRowColSel +CTOF_DEL --- 0.092 SLICE_92.B0 to SLICE_92.F0 SLICE_92 +ROUTE 1 e 0.515 SLICE_92.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.850 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr new file mode 100644 index 0000000..b0d4521 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr @@ -0,0 +1,4355 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:34 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.810ns (21.7% logic, 78.3% route), 7 logic levels. + + Constraint Details: + + 12.810ns physical path delay SLICE_94 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.810 (21.7% logic, 78.3% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.655ns (22.0% logic, 78.0% route), 7 logic levels. + + Constraint Details: + + 12.655ns physical path delay SLICE_95 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.655 (22.0% logic, 78.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.326ns (22.6% logic, 77.4% route), 7 logic levels. + + Constraint Details: + + 12.326ns physical path delay SLICE_94 to SLICE_19 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.326 (22.6% logic, 77.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.319ns (22.6% logic, 77.4% route), 7 logic levels. + + Constraint Details: + + 12.319ns physical path delay SLICE_94 to SLICE_88 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.319 (22.6% logic, 77.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.171ns (22.9% logic, 77.1% route), 7 logic levels. + + Constraint Details: + + 12.171ns physical path delay SLICE_95 to SLICE_19 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.171 (22.9% logic, 77.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.164ns (22.9% logic, 77.1% route), 7 logic levels. + + Constraint Details: + + 12.164ns physical path delay SLICE_95 to SLICE_88 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.164 (22.9% logic, 77.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.129ns (23.0% logic, 77.0% route), 7 logic levels. + + Constraint Details: + + 12.129ns physical path delay SLICE_95 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q1 SLICE_95 (from PHI2_c) +ROUTE 1 1.155 R2C2C.Q1 to R5C2B.D1 Bank_7 +CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_67 +ROUTE 1 0.304 R5C2B.F1 to R5C2C.D1 n2154 +CTOF_DEL --- 0.371 R5C2C.D1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.129 (23.0% logic, 77.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.100ns (20.0% logic, 80.0% route), 6 logic levels. + + Constraint Details: + + 12.100ns physical path delay SLICE_94 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q1 SLICE_94 (from PHI2_c) +ROUTE 1 1.905 R2C3B.Q1 to R6C2B.C1 Bank_1 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_97 +ROUTE 1 1.444 R6C2B.F1 to R5C5B.C1 n2170 +CTOF_DEL --- 0.371 R5C5B.C1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.100 (20.0% logic, 80.0% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i5 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 11.867ns (23.5% logic, 76.5% route), 7 logic levels. + + Constraint Details: + + 11.867ns physical path delay SLICE_97 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2B.CLK to R6C2B.Q1 SLICE_97 (from PHI2_c) +ROUTE 1 0.700 R6C2B.Q1 to R5C2C.D0 Bank_5 +CTOF_DEL --- 0.371 R5C2C.D0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 11.867 (23.5% logic, 76.5% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R6C2B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in XOR8MEG_381 (to PHI2_c -) + + Delay: 11.849ns (23.5% logic, 76.5% route), 7 logic levels. + + Constraint Details: + + 11.849ns physical path delay SLICE_94 to SLICE_96 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_90 +ROUTE 1 1.073 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) + -------- + 11.849 (23.5% logic, 76.5% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 26.150ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_76 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_77 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 7.566ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 8.190ns (29.5% logic, 70.5% route), 6 logic levels. + + Constraint Details: + + 8.190ns physical path delay SLICE_7 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 8.190 (29.5% logic, 70.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.590ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 8.166ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.166ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 8.166 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.984ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i13 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.772ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.772ns physical path delay SLICE_8 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) +ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 +CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.772 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.008ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.748ns (31.2% logic, 68.8% route), 6 logic levels. + + Constraint Details: + + 7.748ns physical path delay SLICE_8 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) +ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 +CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.748 (31.2% logic, 68.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.123ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i12 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.633ns (31.6% logic, 68.4% route), 6 logic levels. + + Constraint Details: + + 7.633ns physical path delay SLICE_8 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) +ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 +CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.633 (31.6% logic, 68.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.147ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.609ns (31.7% logic, 68.3% route), 6 logic levels. + + Constraint Details: + + 7.609ns physical path delay SLICE_8 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) +ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 +CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.609 (31.7% logic, 68.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.262ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_389 (to RCLK_c +) + + Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. + + Constraint Details: + + 7.112ns physical path delay SLICE_7 to SLICE_42 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 +CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 +ROUTE 2 1.538 R6C4A.F0 to R7C5A.LSR n2291 (to RCLK_c) + -------- + 7.112 (23.5% logic, 76.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R7C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.262ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in UFMSDI_390 (to RCLK_c +) + + Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. + + Constraint Details: + + 7.112ns physical path delay SLICE_7 to SLICE_43 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 +CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 +ROUTE 2 1.538 R6C4A.F0 to R7C5B.LSR n2291 (to RCLK_c) + -------- + 7.112 (23.5% logic, 76.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.316ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.440ns (32.5% logic, 67.5% route), 6 logic levels. + + Constraint Details: + + 7.440ns physical path delay SLICE_7 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.440 (32.5% logic, 67.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.340ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.416ns (32.6% logic, 67.4% route), 6 logic levels. + + Constraint Details: + + 7.416ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.416 (32.6% logic, 67.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 8.434ns is the minimum period for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.904ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_55 and + 6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets + 12.500ns offset RCLK to RA[10] by 3.904ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C4B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 1.984 R2C4B.Q0 to 87.PADDO n980 +DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] + -------- + 6.180 (67.9% logic, 32.1% route), 2 logic levels. + +Report: 8.596ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets + 12.500ns offset RCLK to RA[9] by 3.734ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C1 nRowColSel +CTOF_DEL --- 0.371 R2C4A.C1 to R2C4A.F1 SLICE_88 +ROUTE 1 0.817 R2C4A.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] + -------- + 6.350 (71.9% logic, 28.1% route), 3 logic levels. + +Report: 8.766ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.604ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 6.480ns (70.5% logic, 29.5% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets + 12.500ns offset RCLK to RA[8] by 3.604ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B0 nRowColSel +CTOF_DEL --- 0.371 R2C2C.B0 to R2C2C.F0 SLICE_95 +ROUTE 1 0.817 R2C2C.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] + -------- + 6.480 (70.5% logic, 29.5% route), 3 logic levels. + +Report: 8.896ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.245ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 7.839ns (58.3% logic, 41.7% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets + 12.500ns offset RCLK to RA[7] by 2.245ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.234 R2C2A.Q0 to R6C2B.D0 nRowColSel +CTOF_DEL --- 0.371 R6C2B.D0 to R6C2B.F0 SLICE_97 +ROUTE 1 2.038 R6C2B.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] + -------- + 7.839 (58.3% logic, 41.7% route), 3 logic levels. + +Report: 10.255ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.499ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 7.585ns (60.2% logic, 39.8% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets + 12.500ns offset RCLK to RA[6] by 2.499ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C0 nRowColSel +CTOF_DEL --- 0.371 R3C2A.C0 to R3C2A.F0 SLICE_98 +ROUTE 1 2.052 R3C2A.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] + -------- + 7.585 (60.2% logic, 39.8% route), 3 logic levels. + +Report: 10.001ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.891ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 7.193ns (63.5% logic, 36.5% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets + 12.500ns offset RCLK to RA[5] by 2.891ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C1 nRowColSel +CTOF_DEL --- 0.371 R3C2A.C1 to R3C2A.F1 SLICE_98 +ROUTE 1 1.660 R3C2A.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] + -------- + 7.193 (63.5% logic, 36.5% route), 3 logic levels. + +Report: 9.609ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.996ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 6.088ns (75.0% logic, 25.0% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets + 12.500ns offset RCLK to RA[4] by 3.996ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.704 R2C2A.Q0 to R2C2A.D1 nRowColSel +CTOF_DEL --- 0.371 R2C2A.D1 to R2C2A.F1 SLICE_64 +ROUTE 1 0.817 R2C2A.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] + -------- + 6.088 (75.0% logic, 25.0% route), 3 logic levels. + +Report: 8.504ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.567ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 7.517ns (60.8% logic, 39.2% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets + 12.500ns offset RCLK to RA[3] by 2.567ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C1 nRowColSel +CTOF_DEL --- 0.371 R2C3B.C1 to R2C3B.F1 SLICE_94 +ROUTE 1 1.984 R2C3B.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] + -------- + 7.517 (60.8% logic, 39.2% route), 3 logic levels. + +Report: 9.933ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.438ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 7.646ns (59.7% logic, 40.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets + 12.500ns offset RCLK to RA[2] by 2.438ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B1 nRowColSel +CTOF_DEL --- 0.371 R2C2C.B1 to R2C2C.F1 SLICE_95 +ROUTE 1 1.983 R2C2C.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] + -------- + 7.646 (59.7% logic, 40.3% route), 3 logic levels. + +Report: 10.062ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets + 12.500ns offset RCLK to RA[1] by 3.734ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C0 nRowColSel +CTOF_DEL --- 0.371 R2C3B.C0 to R2C3B.F0 SLICE_94 +ROUTE 1 0.817 R2C3B.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] + -------- + 6.350 (71.9% logic, 28.1% route), 3 logic levels. + +Report: 8.766ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.826ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 7.258ns (62.9% logic, 37.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets + 12.500ns offset RCLK to RA[0] by 2.826ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.165 R2C2A.Q0 to R3C2B.B1 nRowColSel +CTOF_DEL --- 0.371 R3C2B.B1 to R3C2B.F1 SLICE_92 +ROUTE 1 1.526 R3C2B.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] + -------- + 7.258 (62.9% logic, 37.1% route), 3 logic levels. + +Report: 9.674ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.071ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_60 and + 5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets + 12.500ns offset RCLK to nRCS by 5.071ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C5B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 0.817 R2C5B.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS + -------- + 5.013 (83.7% logic, 16.3% route), 2 logic levels. + +Report: 7.429ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.420ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 6.664ns (63.0% logic, 37.0% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_34 and + 6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets + 12.500ns offset RCLK to RCKE by 3.420ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R5C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 2.468 R5C2A.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE + -------- + 6.664 (63.0% logic, 37.0% route), 2 logic levels. + +Report: 9.080ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.071ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_63 and + 5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets + 12.500ns offset RCLK to nRWE by 5.071ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R3C5B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 0.817 R3C5B.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE + -------- + 5.013 (83.7% logic, 16.3% route), 2 logic levels. + +Report: 7.429ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 6.199ns (67.7% logic, 32.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_61 and + 6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets + 12.500ns offset RCLK to nRRAS by 3.885ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R4C5A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 2.003 R4C5A.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS + -------- + 6.199 (67.7% logic, 32.3% route), 2 logic levels. + +Report: 8.615ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.905ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 6.179ns (67.9% logic, 32.1% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_58 and + 6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets + 12.500ns offset RCLK to nRCAS by 3.905ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C4C.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 1.983 R2C4C.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS + -------- + 6.179 (67.9% logic, 32.1% route), 2 logic levels. + +Report: 8.595ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.025ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 7.059ns (64.7% logic, 35.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets + 12.500ns offset RCLK to RDQMH by 3.025ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C0 nRowColSel +CTOF_DEL --- 0.371 R2C4A.C0 to R2C4A.F0 SLICE_88 +ROUTE 1 1.526 R2C4A.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH + -------- + 7.059 (64.7% logic, 35.3% route), 3 logic levels. + +Report: 9.475ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.023ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 8.061ns (56.7% logic, 43.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets + 12.500ns offset RCLK to RDQML by 2.023ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.954 R2C2A.Q0 to R3C2B.C0 nRowColSel +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_92 +ROUTE 1 2.540 R3C2B.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML + -------- + 8.061 (56.7% logic, 43.3% route), 3 logic levels. + +Report: 10.477ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.150 ns| 7 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 8.434 ns| 6 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.596 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.896 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.255 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.001 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.609 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.504 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.933 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.062 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.080 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.615 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.595 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.475 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.477 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:34 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.444ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in ADSubmitted_380 (to PHI2_c -) + + Delay: 0.421ns (62.2% logic, 37.8% route), 2 logic levels. + + Constraint Details: + + 0.421ns physical path delay SLICE_9 to SLICE_9 meets + -0.023ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.444ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D0 ADSubmitted +CTOF_DEL --- 0.092 R5C3A.D0 to R5C3A.F0 SLICE_9 +ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 n1361 (to PHI2_c) + -------- + 0.421 (62.2% logic, 37.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.186ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -) + + Delay: 1.157ns (30.6% logic, 69.4% route), 3 logic levels. + + Constraint Details: + + 1.157ns physical path delay SLICE_18 to SLICE_23 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.186ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 0.167 R4C4D.F0 to R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 1.157 (30.6% logic, 69.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R4C4C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.193ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_379 (from PHI2_c -) + Destination: FF Data in CmdEnable_378 (to PHI2_c -) + + Delay: 1.164ns (38.3% logic, 61.7% route), 4 logic levels. + + Constraint Details: + + 1.164ns physical path delay SLICE_14 to SLICE_18 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.193ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R6C3B.CLK to R6C3B.Q0 SLICE_14 (from PHI2_c) +ROUTE 1 0.253 R6C3B.Q0 to R6C3B.B1 C1Submitted +CTOF_DEL --- 0.092 R6C3B.B1 to R6C3B.F1 SLICE_14 +ROUTE 1 0.075 R6C3B.F1 to R6C3C.D1 n2098 +CTOF_DEL --- 0.092 R6C3C.D1 to R6C3C.F1 SLICE_77 +ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 +CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 +ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) + -------- + 1.164 (38.3% logic, 61.7% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.280ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in CmdEnable_378 (to PHI2_c -) + + Delay: 1.251ns (35.7% logic, 64.3% route), 4 logic levels. + + Constraint Details: + + 1.251ns physical path delay SLICE_9 to SLICE_18 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.280ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D1 ADSubmitted +CTOF_DEL --- 0.092 R5C3A.D1 to R5C3A.F1 SLICE_9 +ROUTE 1 0.256 R5C3A.F1 to R6C3C.A1 n2080 +CTOF_DEL --- 0.092 R6C3C.A1 to R6C3C.F1 SLICE_77 +ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 +CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 +ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) + -------- + 1.251 (35.7% logic, 64.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.286ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in XOR8MEG_381 (to PHI2_c -) + + Delay: 1.257ns (28.2% logic, 71.8% route), 3 logic levels. + + Constraint Details: + + 1.257ns physical path delay SLICE_18 to SLICE_96 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.286ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A1 to R4C4D.F1 SLICE_90 +ROUTE 1 0.267 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) + -------- + 1.257 (28.2% logic, 71.8% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.400ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 1.371ns (25.8% logic, 74.2% route), 3 logic levels. + + Constraint Details: + + 1.371ns physical path delay SLICE_18 to SLICE_88 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.400ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 0.381 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 1.371 (25.8% logic, 74.2% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R2C4A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.414ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 1.385ns (25.6% logic, 74.4% route), 3 logic levels. + + Constraint Details: + + 1.385ns physical path delay SLICE_18 to SLICE_19 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.414ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 0.395 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 1.385 (25.6% logic, 74.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C5A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.537ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 1.508ns (23.5% logic, 76.5% route), 3 logic levels. + + Constraint Details: + + 1.508ns physical path delay SLICE_18 to SLICE_83 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.537ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 0.518 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 1.508 (23.5% logic, 76.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_381 (from PHI2_c -) + Destination: FF Data in RA11_358 (to PHI2_c +) + + Delay: 0.670ns (39.1% logic, 60.9% route), 2 logic levels. + + Constraint Details: + + 0.670ns physical path delay SLICE_96 to SLICE_31 meets + -0.011ns DIN_HLD and + -175.000ns delay constraint less + 0.000ns skew requirement (totaling -175.011ns) by 175.681ns + + Physical Path Details: + + Data path SLICE_96 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R3C4B.CLK to R3C4B.Q0 SLICE_96 (from PHI2_c) +ROUTE 1 0.408 R3C4B.Q0 to R2C5A.D0 XOR8MEG +CTOF_DEL --- 0.092 R2C5A.D0 to R2C5A.F0 SLICE_31 +ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_180 (to PHI2_c) + -------- + 0.670 (39.1% logic, 60.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R2C5A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in C1Submitted_379 (to PHI2_c -) + + Delay: 1.456ns (23.4% logic, 76.6% route), 3 logic levels. + + Constraint Details: + + 1.456ns physical path delay SLICE_98 to SLICE_14 meets + -0.029ns CE_HLD and + -175.000ns delay constraint less + 0.000ns skew requirement (totaling -175.029ns) by 176.485ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R3C2A.CLK to R3C2A.Q1 SLICE_98 (from PHI2_c) +ROUTE 1 0.495 R3C2A.Q1 to R5C5B.A1 Bank_3 +CTOF_DEL --- 0.092 R5C5B.A1 to R5C5B.F1 SLICE_76 +ROUTE 4 0.459 R5C5B.F1 to R6C3A.D1 n1285 +CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_89 +ROUTE 1 0.161 R6C3A.F1 to R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c) + -------- + 1.456 (23.4% logic, 76.6% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C2A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i11 (from RCLK_c +) + Destination: FF Data in IS_FSM__i12 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_72 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q0 SLICE_72 (from RCLK_c) +ROUTE 1 0.161 R4C4A.Q0 to R4C4A.M1 n702 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_72 to SLICE_90 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_90: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q1 SLICE_72 (from RCLK_c) +ROUTE 1 0.161 R4C4A.Q1 to R4C4D.M0 n701 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i7 (from RCLK_c +) + Destination: FF Data in IS_FSM__i8 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_73 to SLICE_73 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_73 to SLICE_73: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4A.CLK to R7C4A.Q0 SLICE_73 (from RCLK_c) +ROUTE 1 0.161 R7C4A.Q0 to R7C4A.M1 n706 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i3 (from RCLK_c +) + Destination: FF Data in IS_FSM__i4 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_74 to SLICE_74 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C3B.CLK to R5C3B.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.161 R5C3B.Q0 to R5C3B.M1 n710 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_75 to SLICE_73 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_73: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q1 SLICE_75 (from RCLK_c) +ROUTE 1 0.161 R7C4B.Q1 to R7C4A.M0 n707 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i5 (from RCLK_c +) + Destination: FF Data in IS_FSM__i6 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_75 to SLICE_75 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.161 R7C4B.Q0 to R7C4B.M1 n708 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_84 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4B.CLK to R4C4B.Q1 SLICE_84 (from RCLK_c) +ROUTE 1 0.161 R4C4B.Q1 to R4C4A.M0 n703 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_87 to SLICE_74 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C3D.CLK to R5C3D.Q1 SLICE_87 (from RCLK_c) +ROUTE 1 0.161 R5C3D.Q1 to R5C3B.M0 n711 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i13 (from RCLK_c +) + Destination: FF Data in IS_FSM__i14 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_90 to SLICE_90 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_90 to SLICE_90: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4D.CLK to R4C4D.Q0 SLICE_90 (from RCLK_c) +ROUTE 1 0.161 R4C4D.Q0 to R4C4D.M1 n700 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.345ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_353 (from RCLK_c +) + Destination: FF Data in RASr3_354 (to RCLK_c +) + + Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.324ns physical path delay SLICE_93 to SLICE_93 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.345ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C5D.CLK to R7C5D.Q0 SLICE_93 (from RCLK_c) +ROUTE 16 0.167 R7C5D.Q0 to R7C5D.M1 RASr2 (to RCLK_c) + -------- + 0.324 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.220ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_55 and + 1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets + 0.000ns hold offset RCLK to RA[10] by 2.220ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C4B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 0.468 R2C4B.Q0 to 87.PADDO n980 +DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] + -------- + 1.733 (73.0% logic, 27.0% route), 2 logic levels. + +Report: 2.220ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets + 0.000ns hold offset RCLK to RA[9] by 2.284ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C1 nRowColSel +CTOF_DEL --- 0.092 R2C4A.C1 to R2C4A.F1 SLICE_88 +ROUTE 1 0.197 R2C4A.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] + -------- + 1.797 (75.5% logic, 24.5% route), 3 logic levels. + +Report: 2.284ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.316ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 1.829ns (74.2% logic, 25.8% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets + 0.000ns hold offset RCLK to RA[8] by 2.316ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B0 nRowColSel +CTOF_DEL --- 0.092 R2C2C.B0 to R2C2C.F0 SLICE_95 +ROUTE 1 0.197 R2C2C.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] + -------- + 1.829 (74.2% logic, 25.8% route), 3 logic levels. + +Report: 2.316ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.652ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets + 0.000ns hold offset RCLK to RA[7] by 2.652ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.319 R2C2A.Q0 to R6C2B.D0 nRowColSel +CTOF_DEL --- 0.092 R6C2B.D0 to R6C2B.F0 SLICE_97 +ROUTE 1 0.489 R6C2B.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] + -------- + 2.165 (62.7% logic, 37.3% route), 3 logic levels. + +Report: 2.652ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.579ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 2.092ns (64.9% logic, 35.1% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets + 0.000ns hold offset RCLK to RA[6] by 2.579ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C0 nRowColSel +CTOF_DEL --- 0.092 R3C2A.C0 to R3C2A.F0 SLICE_98 +ROUTE 1 0.492 R3C2A.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] + -------- + 2.092 (64.9% logic, 35.1% route), 3 logic levels. + +Report: 2.579ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.481ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 1.994ns (68.1% logic, 31.9% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets + 0.000ns hold offset RCLK to RA[5] by 2.481ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C1 nRowColSel +CTOF_DEL --- 0.092 R3C2A.C1 to R3C2A.F1 SLICE_98 +ROUTE 1 0.394 R3C2A.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] + -------- + 1.994 (68.1% logic, 31.9% route), 3 logic levels. + +Report: 2.481ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.219ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 1.732ns (78.3% logic, 21.7% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets + 0.000ns hold offset RCLK to RA[4] by 2.219ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.178 R2C2A.Q0 to R2C2A.D1 nRowColSel +CTOF_DEL --- 0.092 R2C2A.D1 to R2C2A.F1 SLICE_64 +ROUTE 1 0.197 R2C2A.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] + -------- + 1.732 (78.3% logic, 21.7% route), 3 logic levels. + +Report: 2.219ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.555ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 2.068ns (65.6% logic, 34.4% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets + 0.000ns hold offset RCLK to RA[3] by 2.555ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C1 nRowColSel +CTOF_DEL --- 0.092 R2C3B.C1 to R2C3B.F1 SLICE_94 +ROUTE 1 0.468 R2C3B.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] + -------- + 2.068 (65.6% logic, 34.4% route), 3 logic levels. + +Report: 2.555ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.599ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 2.112ns (64.3% logic, 35.7% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets + 0.000ns hold offset RCLK to RA[2] by 2.599ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B1 nRowColSel +CTOF_DEL --- 0.092 R2C2C.B1 to R2C2C.F1 SLICE_95 +ROUTE 1 0.480 R2C2C.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] + -------- + 2.112 (64.3% logic, 35.7% route), 3 logic levels. + +Report: 2.599ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets + 0.000ns hold offset RCLK to RA[1] by 2.284ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C0 nRowColSel +CTOF_DEL --- 0.092 R2C3B.C0 to R2C3B.F0 SLICE_94 +ROUTE 1 0.197 R2C3B.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] + -------- + 1.797 (75.5% logic, 24.5% route), 3 logic levels. + +Report: 2.284ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.492ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 2.005ns (67.7% logic, 32.3% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets + 0.000ns hold offset RCLK to RA[0] by 2.492ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.292 R2C2A.Q0 to R3C2B.B1 nRowColSel +CTOF_DEL --- 0.092 R3C2B.B1 to R3C2B.F1 SLICE_92 +ROUTE 1 0.356 R3C2B.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] + -------- + 2.005 (67.7% logic, 32.3% route), 3 logic levels. + +Report: 2.492ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 1.949ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_60 and + 1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets + 0.000ns hold offset RCLK to nRCS by 1.949ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C5B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 0.197 R2C5B.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS + -------- + 1.462 (86.5% logic, 13.5% route), 2 logic levels. + +Report: 1.949ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.363ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 1.876ns (67.4% logic, 32.6% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_34 and + 1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets + 0.000ns hold offset RCLK to RCKE by 2.363ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R5C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 0.611 R5C2A.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE + -------- + 1.876 (67.4% logic, 32.6% route), 2 logic levels. + +Report: 2.363ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 1.949ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_63 and + 1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets + 0.000ns hold offset RCLK to nRWE by 1.949ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R3C5B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 0.197 R3C5B.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE + -------- + 1.462 (86.5% logic, 13.5% route), 2 logic levels. + +Report: 1.949ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.236ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 1.749ns (72.3% logic, 27.7% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_61 and + 1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets + 0.000ns hold offset RCLK to nRRAS by 2.236ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 0.484 R4C5A.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS + -------- + 1.749 (72.3% logic, 27.7% route), 2 logic levels. + +Report: 2.236ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.232ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 1.745ns (72.5% logic, 27.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_58 and + 1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets + 0.000ns hold offset RCLK to nRCAS by 2.232ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C4C.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 0.480 R2C4C.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS + -------- + 1.745 (72.5% logic, 27.5% route), 2 logic levels. + +Report: 2.232ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.443ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 1.956ns (69.4% logic, 30.6% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets + 0.000ns hold offset RCLK to RDQMH by 2.443ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C0 nRowColSel +CTOF_DEL --- 0.092 R2C4A.C0 to R2C4A.F0 SLICE_88 +ROUTE 1 0.356 R2C4A.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH + -------- + 1.956 (69.4% logic, 30.6% route), 3 logic levels. + +Report: 2.443ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.713ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 2.226ns (61.0% logic, 39.0% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets + 0.000ns hold offset RCLK to RDQML by 2.713ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.238 R2C2A.Q0 to R3C2B.C0 nRowColSel +CTOF_DEL --- 0.092 R3C2B.C0 to R3C2B.F0 SLICE_92 +ROUTE 1 0.631 R3C2B.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML + -------- + 2.226 (61.0% logic, 39.0% route), 3 logic levels. + +Report: 2.713ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.316 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.579 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.481 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.219 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.555 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.599 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.492 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.363 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.236 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.232 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.443 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.713 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html new file mode 100644 index 0000000..0fd44c9 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + +
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:36:25 2021
+
+
+Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html new file mode 100644 index 0000000..61370c6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html @@ -0,0 +1,202 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:32:34 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.215      3       1.805     3
+CROW[1] nCRAS F    -0.050      M       2.105     3
+Din[0]  PHI2  F     5.083      3       2.097     3
+Din[0]  nCCAS F    -0.020      M       2.133     3
+Din[1]  PHI2  F     3.519      3       2.454     3
+Din[1]  nCCAS F    -0.146      M       2.462     3
+Din[2]  PHI2  F     4.416      3       2.660     3
+Din[2]  nCCAS F     0.272      3       1.853     3
+Din[3]  PHI2  F     5.627      3       2.084     3
+Din[3]  nCCAS F    -0.024      M       2.144     3
+Din[4]  PHI2  F     4.808      3       2.117     3
+Din[4]  nCCAS F     0.350      3       1.766     3
+Din[5]  PHI2  F     5.446      3       2.212     3
+Din[5]  nCCAS F     0.435      3       1.708     3
+Din[6]  PHI2  F     5.339      3       1.487     3
+Din[6]  nCCAS F    -0.140      M       2.452     3
+Din[7]  PHI2  F     4.546      3       1.555     3
+Din[7]  nCCAS F    -0.016      M       2.122     3
+MAin[0] PHI2  F     4.027      3       0.711     3
+MAin[0] nCRAS F     1.132      3       0.987     3
+MAin[1] PHI2  F     4.032      3       1.734     3
+MAin[1] nCRAS F     0.704      3       1.373     3
+MAin[2] PHI2  F    10.358      3      -0.773     M
+MAin[2] nCRAS F    -0.202      M       2.529     3
+MAin[3] PHI2  F    10.442      3      -0.829     M
+MAin[3] nCRAS F     0.186      3       1.819     3
+MAin[4] PHI2  F    10.311      3      -0.765     M
+MAin[4] nCRAS F     0.569      3       1.506     3
+MAin[5] PHI2  F     7.007      3       0.178     3
+MAin[5] nCRAS F     0.186      3       1.819     3
+MAin[6] PHI2  F     9.786      3      -0.641     M
+MAin[6] nCRAS F     0.177      3       1.829     3
+MAin[7] PHI2  F    10.008      3      -0.718     M
+MAin[7] nCRAS F    -0.092      M       2.222     3
+MAin[8] nCRAS F    -0.202      M       2.532     3
+MAin[9] nCRAS F     0.228      3       1.797     3
+PHI2    RCLK  R     5.091      3      -0.759     M
+UFMSDO  RCLK  R     2.219      3      -0.104     M
+nCCAS   RCLK  R     3.820      3      -0.611     M
+nCCAS   nCRAS F     1.538      3       0.708     3
+nCRAS   RCLK  R     4.749      3      -0.670     M
+nFWE    PHI2  F     5.301      3       1.647     3
+nFWE    nCRAS F     1.049      3       1.128     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.669         3        3.051          M
+RA[0]  RCLK  R     9.674         3        2.492          M
+RA[0]  nCRAS F    12.127         3        3.067          M
+RA[10] RCLK  R     8.596         3        2.220          M
+RA[11] PHI2  R     9.987         3        2.559          M
+RA[1]  RCLK  R     8.766         3        2.284          M
+RA[1]  nCRAS F    11.652         3        2.982          M
+RA[2]  RCLK  R    10.062         3        2.599          M
+RA[2]  nCRAS F    12.947         3        3.306          M
+RA[3]  RCLK  R     9.933         3        2.555          M
+RA[3]  nCRAS F    12.783         3        3.240          M
+RA[4]  RCLK  R     8.504         3        2.219          M
+RA[4]  nCRAS F    11.513         3        2.948          M
+RA[5]  RCLK  R     9.609         3        2.481          M
+RA[5]  nCRAS F    11.870         3        3.010          M
+RA[6]  RCLK  R    10.001         3        2.579          M
+RA[6]  nCRAS F    12.947         3        3.292          M
+RA[7]  RCLK  R    10.255         3        2.652          M
+RA[7]  nCRAS F    12.177         3        3.089          M
+RA[8]  RCLK  R     8.896         3        2.316          M
+RA[8]  nCRAS F    11.417         3        2.920          M
+RA[9]  RCLK  R     8.766         3        2.284          M
+RA[9]  nCRAS F    11.617         3        2.957          M
+RBA[0] nCRAS F     9.698         3        2.483          M
+RBA[1] nCRAS F    11.425         3        2.916          M
+RCKE   RCLK  R     9.080         3        2.363          M
+RDQMH  RCLK  R     9.475         3        2.443          M
+RDQML  RCLK  R    10.477         3        2.713          M
+RD[0]  nCCAS F    11.252         3        2.942          M
+RD[1]  nCCAS F    11.963         3        3.100          M
+RD[2]  nCCAS F    12.880         3        3.336          M
+RD[3]  nCCAS F    12.422         3        3.224          M
+RD[4]  nCCAS F    11.252         3        2.942          M
+RD[5]  nCCAS F    12.423         3        3.212          M
+RD[6]  nCCAS F    12.979         3        3.375          M
+RD[7]  nCCAS F    12.914         3        3.350          M
+UFMCLK RCLK  R     8.007         3        2.126          M
+UFMSDI RCLK  R     8.007         3        2.126          M
+nRCAS  RCLK  R     8.595         3        2.232          M
+nRCS   RCLK  R     7.429         3        1.949          M
+nRRAS  RCLK  R     8.615         3        2.236          M
+nRWE   RCLK  R     7.429         3        1.949          M
+nUFMCS RCLK  R     9.193         3        2.413          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj new file mode 100644 index 0000000..a0fe340 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO256C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" +-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" + +-ngd "RAM2GS_LCMXO256C_impl1.ngd" + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd new file mode 100644 index 0000000..c70636c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO256C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 256; +LUTS_used = 129; +FF_avail = 256; +FF_used = 102; +INPUT_LVTTL33 = 26; +OUTPUT_LVTTL33 = 33; +BIDI_LVTTL33 = 8; +IO_avail = 78; +IO_used = 67; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam new file mode 100644 index 0000000..816529f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam @@ -0,0 +1,108 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2307 Ready +n2306 nFWE_c +PHI2_N_114 PHI2_c +n2302 nRowColSel_N_35 +nRWE_N_172 nRWE_N_173 +UFMSDO_N_74 UFMSDO_c +n1377 nRowColSel_N_34 +RASr2_N_63 RASr2 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_577_add_4_14/CO0 +FS_577_add_4_16/CO0 +FS_577_add_4_12/CO0 +FS_577_add_4_2/CO0 +FS_577_add_4_4/CO0 +FS_577_add_4_6/CO0 +FS_577_add_4_18/CO1 +FS_577_add_4_18/CO0 +FS_577_add_4_8/CO0 +FS_577_add_4_10/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +PERIOD NET "PHI2_c" 350.000000 ns ; +USE PRIMARY NET "RCLK_c" ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +USE PRIMARY NET "PHI2_c" ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +USE PRIMARY NET "nCCAS_c" ; +PERIOD NET "RCLK_c" 16.000000 ns ; +USE PRIMARY NET "nCRAS_c" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr new file mode 100644 index 0000000..5a900d5 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 65.00 100.0 + LUT4 111.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd new file mode 100644 index 0000000..81a1185 Binary files /dev/null and b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd differ diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html new file mode 100644 index 0000000..e7b8ba5 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html @@ -0,0 +1,425 @@ + +Project Summary + + +

+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
+     CMXO256C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO256CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:32:26
+
+
+Design Summary
+   Number of PFU registers:   102 out of   256 (40%)
+   Number of SLICEs:        65 out of   128 (51%)
+      SLICEs as Logic/ROM:     65 out of   128 (51%)
+      SLICEs as RAM:            0 out of    64 (0%)
+      SLICEs as Carry:          9 out of   128 (7%)
+   Number of LUT4s:        129 out of   256 (50%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 78 (86%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 29 MB
+
+        
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+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html new file mode 100644 index 0000000..911c6d4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html @@ -0,0 +1,336 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO256C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.19
+
+Mon Aug 16 21:32:33 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site | Properties                       |
++-----------+----------+--------------+------+----------------------------------+
+| CROW[0]   | 32/1     | LVTTL33_IN   | PB2C | SLEW:FAST                        |
+| CROW[1]   | 34/1     | LVTTL33_IN   | PB2D | SLEW:FAST                        |
+| Din[0]    | 21/1     | LVTTL33_IN   | PL8A | SLEW:FAST                        |
+| Din[1]    | 15/1     | LVTTL33_IN   | PL6A | SLEW:FAST                        |
+| Din[2]    | 14/1     | LVTTL33_IN   | PL5D | SLEW:FAST                        |
+| Din[3]    | 16/1     | LVTTL33_IN   | PL6B | SLEW:FAST                        |
+| Din[4]    | 18/1     | LVTTL33_IN   | PL7B | SLEW:FAST                        |
+| Din[5]    | 17/1     | LVTTL33_IN   | PL7A | SLEW:FAST                        |
+| Din[6]    | 20/1     | LVTTL33_IN   | PL7D | SLEW:FAST                        |
+| Din[7]    | 19/1     | LVTTL33_IN   | PL7C | SLEW:FAST                        |
+| Dout[0]   | 1/1      | LVTTL33_OUT  | PL2A | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/1      | LVTTL33_OUT  | PL4A | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/1      | LVTTL33_OUT  | PL4B | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/1      | LVTTL33_OUT  | PL3D | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/1      | LVTTL33_OUT  | PL3B | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/1      | LVTTL33_OUT  | PL3C | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/1      | LVTTL33_OUT  | PL2B | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/1      | LVTTL33_OUT  | PL3A | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/0     | LVTTL33_OUT  | PR7B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/1     | LVTTL33_IN   | PL9A | SLEW:FAST                        |
+| MAin[1]   | 38/1     | LVTTL33_IN   | PB3C | SLEW:FAST                        |
+| MAin[2]   | 37/1     | LVTTL33_IN   | PB3B | SLEW:FAST                        |
+| MAin[3]   | 47/1     | LVTTL33_IN   | PB5A | SLEW:FAST                        |
+| MAin[4]   | 46/1     | LVTTL33_IN   | PB4D | SLEW:FAST                        |
+| MAin[5]   | 45/1     | LVTTL33_IN   | PB4C | SLEW:FAST                        |
+| MAin[6]   | 49/1     | LVTTL33_IN   | PB5C | SLEW:FAST                        |
+| MAin[7]   | 44/1     | LVTTL33_IN   | PB4B | SLEW:FAST                        |
+| MAin[8]   | 50/1     | LVTTL33_IN   | PB5D | SLEW:FAST                        |
+| MAin[9]   | 51/0     | LVTTL33_IN   | PR9B | SLEW:FAST                        |
+| PHI2      | 39/1     | LVTTL33_IN   | PB3D | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2C | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT3D | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT5A | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT3C | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3A | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2D | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2B | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT2F | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3B | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2E | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT4B | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/0     | LVTTL33_OUT  | PR5D | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT4C | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT4D | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT4A | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PR2A | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/0     | LVTTL33_OUT  | PR6A | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/0     | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/0     | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/0     | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/0     | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/0     | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/0     | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/0     | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/0     | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/0     | LVTTL33_OUT  | PR7A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/0     | LVTTL33_OUT  | PR7C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/0     | LVTTL33_IN   | PR7D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/1     | LVTTL33_IN   | PL9B | SLEW:FAST                        |
+| nCRAS     | 43/1     | LVTTL33_IN   | PB4A | SLEW:FAST                        |
+| nFWE      | 22/1     | LVTTL33_IN   | PL8B | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT5B | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT5C | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/0     | LVTTL33_OUT  | PR2B | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/0     | LVTTL33_OUT  | PR3A | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/0     | LVTTL33_OUT  | PR8B | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site | Dual Function |
++----------+---------------------+------------+--------------+------+---------------+
+| 1/1      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A |               |
+| 2/1      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2B |               |
+| 3/1      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL3A |               |
+| 4/1      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL3B |               |
+| 5/1      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3C |               |
+| 6/1      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3D |               |
+| 7/1      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL4A |               |
+| 8/1      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL4B |               |
+| 9/1      |     unused, PULL:UP |            |              | PL5A |               |
+| 11/1     |     unused, PULL:UP |            |              | PL5B |               |
+| 13/1     |     unused, PULL:UP |            |              | PL5C |               |
+| 14/1     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5D | GSR_PADN      |
+| 15/1     | Din[1]              | LOCATED    | LVTTL33_IN   | PL6A |               |
+| 16/1     | Din[3]              | LOCATED    | LVTTL33_IN   | PL6B | TSALLPAD      |
+| 17/1     | Din[5]              | LOCATED    | LVTTL33_IN   | PL7A |               |
+| 18/1     | Din[4]              | LOCATED    | LVTTL33_IN   | PL7B |               |
+| 19/1     | Din[7]              | LOCATED    | LVTTL33_IN   | PL7C |               |
+| 20/1     | Din[6]              | LOCATED    | LVTTL33_IN   | PL7D |               |
+| 21/1     | Din[0]              | LOCATED    | LVTTL33_IN   | PL8A |               |
+| 22/1     | nFWE                | LOCATED    | LVTTL33_IN   | PL8B |               |
+| 23/1     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL9A |               |
+| 27/1     | nCCAS               | LOCATED    | LVTTL33_IN   | PL9B |               |
+| 29/1     |     unused, PULL:UP |            |              | PB2A |               |
+| 30/1     |     unused, PULL:UP |            |              | PB2B |               |
+| 32/1     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB2C |               |
+| 34/1     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB2D |               |
+| 36/1     |     unused, PULL:UP |            |              | PB3A | PCLKT1_1      |
+| 37/1     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB3B |               |
+| 38/1     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB3C | PCLKT1_0      |
+| 39/1     | PHI2                | LOCATED    | LVTTL33_IN   | PB3D |               |
+| 43/1     | nCRAS               | LOCATED    | LVTTL33_IN   | PB4A |               |
+| 44/1     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB4B |               |
+| 45/1     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB4C |               |
+| 46/1     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB4D |               |
+| 47/1     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB5A |               |
+| 49/1     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB5C |               |
+| 50/1     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB5D |               |
+| 51/0     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR9B |               |
+| 52/0     |     unused, PULL:UP |            |              | PR9A |               |
+| 53/0     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR8B |               |
+| 54/0     |     unused, PULL:UP |            |              | PR8A |               |
+| 55/0     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR7D |               |
+| 56/0     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR7C |               |
+| 57/0     | LED                 | LOCATED    | LVTTL33_OUT  | PR7B |               |
+| 58/0     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR7A |               |
+| 59/0     |     unused, PULL:UP |            |              | PR6B |               |
+| 61/0     | RDQML               | LOCATED    | LVTTL33_OUT  | PR6A |               |
+| 63/0     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR5D |               |
+| 64/0     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR5C |               |
+| 65/0     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR5B |               |
+| 66/0     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5A |               |
+| 67/0     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR4B |               |
+| 68/0     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4A |               |
+| 69/0     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR3D |               |
+| 70/0     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3C |               |
+| 71/0     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B |               |
+| 72/0     | nRWE                | LOCATED    | LVTTL33_OUT  | PR3A |               |
+| 73/0     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PR2A |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT5C |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT5B |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT5A |               |
+| 80/0     |     unused, PULL:UP |            |              | PT4F |               |
+| 81/0     |     unused, PULL:UP |            |              | PT4E |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT4D |               |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT4C |               |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT4B | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT4A | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT3D |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT3C |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3B |               |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3A |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT2F |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2E |               |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2D |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2C |               |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2B |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A |               |
+| PB5B/0   |     unused, PULL:UP |            |              | PB5B |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D |               |
+| TCK/1    |                     |            |              | TCK  | TCK           |
+| TDI/1    |                     |            |              | TDI  | TDI           |
+| TDO/1    |                     |            |              | TDO  | TDO           |
+| TMS/1    |                     |            |              | TMS  | TMS           |
++----------+---------------------+------------+--------------+------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:33 2021
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html new file mode 100644 index 0000000..ce22106 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html @@ -0,0 +1,307 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:27 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            2.023        0            0.339        0            07           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Mon Aug 16 21:32:27 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             65/128          50% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 586066.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  584668
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 80 (3%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 6 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 6 secs 
+
+Start NBR router at 21:32:33 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:32:33 08/16/21
+
+Start NBR section for initial routing at 21:32:33 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:32:33 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
+
+Start NBR section for re-routing at 21:32:33 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:32:33 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 2.023ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 2.023
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html new file mode 100644 index 0000000..bb33f8f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +

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RAM2GS_LCMXO256C project summary
Module Name:RAM2GS_LCMXO256CSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO256C-3T100CDevice Family:MachXO
Device Type:LCMXO256CPackage Type:TQFP100
Performance grade:3Operating conditions:COM
Logic preference file:RAM2GS_LCMXO256C.lpf
Physical Preference file:impl1/RAM2GS_LCMXO256C_impl1.prf
Product Version:3.12.0.240.2Patch Version:
Updated:2021/08/16 21:36:29
Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1
Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf

+

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+
+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html new file mode 100644 index 0000000..01aa986 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html @@ -0,0 +1,2740 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:27 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:27 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html new file mode 100644 index 0000000..bdfe34c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html @@ -0,0 +1,4588 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.810ns  (21.7% logic, 78.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.810ns physical path delay SLICE_94 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.810   (21.7% logic, 78.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.655ns  (22.0% logic, 78.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.655ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.655   (22.0% logic, 78.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.326ns  (22.6% logic, 77.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.326ns physical path delay SLICE_94 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.326   (22.6% logic, 77.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              12.319ns  (22.6% logic, 77.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_94 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.319   (22.6% logic, 77.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.171ns  (22.9% logic, 77.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.171ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.171   (22.9% logic, 77.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              12.164ns  (22.9% logic, 77.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.164ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.164   (22.9% logic, 77.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.129ns  (23.0% logic, 77.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.129ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     1.155       R2C2C.Q1 to       R5C2B.D1 Bank_7
+CTOF_DEL    ---     0.371       R5C2B.D1 to       R5C2B.F1 SLICE_67
+ROUTE         1     0.304       R5C2B.F1 to       R5C2C.D1 n2154
+CTOF_DEL    ---     0.371       R5C2C.D1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.129   (23.0% logic, 77.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.100ns  (20.0% logic, 80.0% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.100ns physical path delay SLICE_94 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q1 SLICE_94 (from PHI2_c)
+ROUTE         1     1.905       R2C3B.Q1 to       R6C2B.C1 Bank_1
+CTOF_DEL    ---     0.371       R6C2B.C1 to       R6C2B.F1 SLICE_97
+ROUTE         1     1.444       R6C2B.F1 to       R5C5B.C1 n2170
+CTOF_DEL    ---     0.371       R5C5B.C1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.100   (20.0% logic, 80.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.867ns  (23.5% logic, 76.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.867ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C2B.CLK to       R6C2B.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     0.700       R6C2B.Q1 to       R5C2C.D0 Bank_5
+CTOF_DEL    ---     0.371       R5C2C.D0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.867   (23.5% logic, 76.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R6C2B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              11.849ns  (23.5% logic, 76.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.849ns physical path delay SLICE_94 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A1 to       R4C4D.F1 SLICE_90
+ROUTE         1     1.073       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.849   (23.5% logic, 76.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   26.150ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 7.566ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.190ns  (29.5% logic, 70.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.190ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.190   (29.5% logic, 70.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.590ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               8.166ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.166ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.166   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.984ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.772ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.772ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
+CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.772   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.008ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.748ns  (31.2% logic, 68.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.748ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
+CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.748   (31.2% logic, 68.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.123ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.633ns  (31.6% logic, 68.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.633ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.633   (31.6% logic, 68.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.147ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.609ns  (31.7% logic, 68.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.609ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.609   (31.7% logic, 68.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.262ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_389  (to RCLK_c +)
+
+   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.112ns physical path delay SLICE_7 to SLICE_42 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
+CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
+ROUTE         2     1.538       R6C4A.F0 to      R7C5A.LSR n2291 (to RCLK_c)
+                  --------
+                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R7C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.262ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_390  (to RCLK_c +)
+
+   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.112ns physical path delay SLICE_7 to SLICE_43 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
+CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
+ROUTE         2     1.538       R6C4A.F0 to      R7C5B.LSR n2291 (to RCLK_c)
+                  --------
+                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R7C5B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.316ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.440ns  (32.5% logic, 67.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.440ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
+CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.440   (32.5% logic, 67.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.340ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.416ns  (32.6% logic, 67.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.416ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
+CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.416   (32.6% logic, 67.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.434ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_55 and
+      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
+     12.500ns offset RCLK to RA[10] by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C4B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.984       R2C4B.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.734ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets
+     12.500ns offset RCLK to RA[9] by 3.734ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C1 nRowColSel
+CTOF_DEL    ---     0.371       R2C4A.C1 to       R2C4A.F1 SLICE_88
+ROUTE         1     0.817       R2C4A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
+
+Report:    8.766ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.604ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.480ns  (70.5% logic, 29.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets
+     12.500ns offset RCLK to RA[8] by 3.604ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.B0 to       R2C2C.F0 SLICE_95
+ROUTE         1     0.817       R2C2C.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.480   (70.5% logic, 29.5% route), 3 logic levels.
+
+Report:    8.896ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.245ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.839ns  (58.3% logic, 41.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets
+     12.500ns offset RCLK to RA[7] by 2.245ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.234       R2C2A.Q0 to       R6C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R6C2B.D0 to       R6C2B.F0 SLICE_97
+ROUTE         1     2.038       R6C2B.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.839   (58.3% logic, 41.7% route), 3 logic levels.
+
+Report:   10.255ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.499ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.585ns  (60.2% logic, 39.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets
+     12.500ns offset RCLK to RA[6] by 2.499ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2A.C0 to       R3C2A.F0 SLICE_98
+ROUTE         1     2.052       R3C2A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.585   (60.2% logic, 39.8% route), 3 logic levels.
+
+Report:   10.001ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.891ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.193ns  (63.5% logic, 36.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets
+     12.500ns offset RCLK to RA[5] by 2.891ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2A.C1 to       R3C2A.F1 SLICE_98
+ROUTE         1     1.660       R3C2A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.193   (63.5% logic, 36.5% route), 3 logic levels.
+
+Report:    9.609ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.996ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.088ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets
+     12.500ns offset RCLK to RA[4] by 3.996ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.704       R2C2A.Q0 to       R2C2A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.D1 to       R2C2A.F1 SLICE_64
+ROUTE         1     0.817       R2C2A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.088   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    8.504ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.567ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.517ns  (60.8% logic, 39.2% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets
+     12.500ns offset RCLK to RA[3] by 2.567ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.C1 to       R2C3B.F1 SLICE_94
+ROUTE         1     1.984       R2C3B.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.517   (60.8% logic, 39.2% route), 3 logic levels.
+
+Report:    9.933ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.438ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.646ns  (59.7% logic, 40.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets
+     12.500ns offset RCLK to RA[2] by 2.438ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.B1 to       R2C2C.F1 SLICE_95
+ROUTE         1     1.983       R2C2C.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.646   (59.7% logic, 40.3% route), 3 logic levels.
+
+Report:   10.062ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.734ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets
+     12.500ns offset RCLK to RA[1] by 3.734ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.C0 to       R2C3B.F0 SLICE_94
+ROUTE         1     0.817       R2C3B.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
+
+Report:    8.766ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.258ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets
+     12.500ns offset RCLK to RA[0] by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.165       R2C2A.Q0 to       R3C2B.B1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.B1 to       R3C2B.F1 SLICE_92
+ROUTE         1     1.526       R3C2B.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.258   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRCS by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C5B.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.420ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.664ns  (63.0% logic, 37.0% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_34 and
+      6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets
+     12.500ns offset RCLK to RCKE by 3.420ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R5C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     2.468       R5C2A.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    6.664   (63.0% logic, 37.0% route), 2 logic levels.
+
+Report:    9.080ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_63 and
+      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRWE by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R3C5B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.817       R3C5B.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_61 and
+      6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets
+     12.500ns offset RCLK to nRRAS by 3.885ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.003       R4C5A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    8.615ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.905ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_58 and
+      6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets
+     12.500ns offset RCLK to nRCAS by 3.905ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C4C.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.983       R2C4C.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.595ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.025ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.059ns  (64.7% logic, 35.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets
+     12.500ns offset RCLK to RDQMH by 3.025ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C4A.C0 to       R2C4A.F0 SLICE_88
+ROUTE         1     1.526       R2C4A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.059   (64.7% logic, 35.3% route), 3 logic levels.
+
+Report:    9.475ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.023ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     8.061ns  (56.7% logic, 43.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets
+     12.500ns offset RCLK to RDQML by 2.023ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.954       R2C2A.Q0 to       R3C2B.C0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_92
+ROUTE         1     2.540       R3C2B.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    8.061   (56.7% logic, 43.3% route), 3 logic levels.
+
+Report:   10.477ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.150 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.434 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.896 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.255 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.001 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.609 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.504 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.933 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.062 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.080 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.615 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.595 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.475 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.477 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.444ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.421ns  (62.2% logic, 37.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.421ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.444ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C3A.D0 to       R5C3A.F0 SLICE_9
+ROUTE         1     0.000       R5C3A.F0 to      R5C3A.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.421   (62.2% logic, 37.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.186ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.157ns  (30.6% logic, 69.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.157ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.186ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     0.167       R4C4D.F0 to       R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.157   (30.6% logic, 69.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R4C4C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.164ns  (38.3% logic, 61.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.164ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.193ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3B.CLK to       R6C3B.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.253       R6C3B.Q0 to       R6C3B.B1 C1Submitted
+CTOF_DEL    ---     0.092       R6C3B.B1 to       R6C3B.F1 SLICE_14
+ROUTE         1     0.075       R6C3B.F1 to       R6C3C.D1 n2098
+CTOF_DEL    ---     0.092       R6C3C.D1 to       R6C3C.F1 SLICE_77
+ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
+CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
+ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.164   (38.3% logic, 61.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.251ns  (35.7% logic, 64.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.251ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.280ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C3A.D1 to       R5C3A.F1 SLICE_9
+ROUTE         1     0.256       R5C3A.F1 to       R6C3C.A1 n2080
+CTOF_DEL    ---     0.092       R6C3C.A1 to       R6C3C.F1 SLICE_77
+ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
+CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
+ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.251   (35.7% logic, 64.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.286ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.257ns  (28.2% logic, 71.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.257ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.286ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A1 to       R4C4D.F1 SLICE_90
+ROUTE         1     0.267       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.257   (28.2% logic, 71.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.400ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.371ns  (25.8% logic, 74.2% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.371ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     0.381       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.371   (25.8% logic, 74.2% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.414ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.385ns  (25.6% logic, 74.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.385ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.414ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     0.395       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.385   (25.6% logic, 74.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.537ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.508ns  (23.5% logic, 76.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.508ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.537ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     0.518       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.508   (23.5% logic, 76.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.670ns  (39.1% logic, 60.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.670ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.681ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R3C4B.CLK to       R3C4B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.408       R3C4B.Q0 to       R2C5A.D0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C5A.D0 to       R2C5A.F0 SLICE_31
+ROUTE         1     0.000       R2C5A.F0 to      R2C5A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.670   (39.1% logic, 60.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R2C5A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.456ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.456ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.495       R3C2A.Q1 to       R5C5B.A1 Bank_3
+CTOF_DEL    ---     0.092       R5C5B.A1 to       R5C5B.F1 SLICE_76
+ROUTE         4     0.459       R5C5B.F1 to       R6C3A.D1 n1285
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_89
+ROUTE         1     0.161       R6C3A.F1 to       R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.456   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C2A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R4C4A.Q0 to       R4C4A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R4C4A.Q1 to       R4C4D.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4A.CLK to       R7C4A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R7C4A.Q0 to       R7C4A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C3B.CLK to       R5C3B.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C3B.Q0 to       R5C3B.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R7C4B.Q1 to       R7C4A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R7C4B.Q0 to       R7C4B.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4B.CLK to       R4C4B.Q1 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R4C4B.Q1 to       R4C4A.M0 n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C3D.CLK to       R5C3D.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C3D.Q1 to       R5C3B.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4D.CLK to       R4C4D.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R4C4D.Q0 to       R4C4D.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_353  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_354  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_93 to SLICE_93 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C5D.CLK to       R7C5D.Q0 SLICE_93 (from RCLK_c)
+ROUTE        16     0.167       R7C5D.Q0 to       R7C5D.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C4B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.468       R2C4B.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C1 nRowColSel
+CTOF_DEL    ---     0.092       R2C4A.C1 to       R2C4A.F1 SLICE_88
+ROUTE         1     0.197       R2C4A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
+
+Report:    2.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.316ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     1.829ns  (74.2% logic, 25.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.316ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.B0 to       R2C2C.F0 SLICE_95
+ROUTE         1     0.197       R2C2C.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    1.829   (74.2% logic, 25.8% route), 3 logic levels.
+
+Report:    2.316ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.319       R2C2A.Q0 to       R6C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R6C2B.D0 to       R6C2B.F0 SLICE_97
+ROUTE         1     0.489       R6C2B.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.092ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2A.C0 to       R3C2A.F0 SLICE_98
+ROUTE         1     0.492       R3C2A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.092   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    2.579ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.481ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     1.994ns  (68.1% logic, 31.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.481ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2A.C1 to       R3C2A.F1 SLICE_98
+ROUTE         1     0.394       R3C2A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    1.994   (68.1% logic, 31.9% route), 3 logic levels.
+
+Report:    2.481ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.219ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     1.732ns  (78.3% logic, 21.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.219ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R2C2A.Q0 to       R2C2A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.D1 to       R2C2A.F1 SLICE_64
+ROUTE         1     0.197       R2C2A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    1.732   (78.3% logic, 21.7% route), 3 logic levels.
+
+Report:    2.219ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.555ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.068ns  (65.6% logic, 34.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.555ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.C1 to       R2C3B.F1 SLICE_94
+ROUTE         1     0.468       R2C3B.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.068   (65.6% logic, 34.4% route), 3 logic levels.
+
+Report:    2.555ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.112ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.B1 to       R2C2C.F1 SLICE_95
+ROUTE         1     0.480       R2C2C.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.112   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:    2.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.C0 to       R2C3B.F0 SLICE_94
+ROUTE         1     0.197       R2C3B.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
+
+Report:    2.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.492ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.005ns  (67.7% logic, 32.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.492ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.292       R2C2A.Q0 to       R3C2B.B1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.B1 to       R3C2B.F1 SLICE_92
+ROUTE         1     0.356       R3C2B.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.005   (67.7% logic, 32.3% route), 3 logic levels.
+
+Report:    2.492ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C5B.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.611       R5C2A.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRWE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C5B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.197       R3C5B.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.484       R4C5A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
+
+Report:    2.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.232ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.232ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C4C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.480       R2C4C.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    2.232ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.443ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     1.956ns  (69.4% logic, 30.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.443ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C4A.C0 to       R2C4A.F0 SLICE_88
+ROUTE         1     0.356       R2C4A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    1.956   (69.4% logic, 30.6% route), 3 logic levels.
+
+Report:    2.443ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.713ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.226ns  (61.0% logic, 39.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.713ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.238       R2C2A.Q0 to       R3C2B.C0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.C0 to       R3C2B.F0 SLICE_92
+ROUTE         1     0.631       R3C2B.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.226   (61.0% logic, 39.0% route), 3 logic levels.
+
+Report:    2.713ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.316 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.579 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.481 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.219 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.555 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.492 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.443 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.713 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..946f96e --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 304 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..83d5ab2 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr @@ -0,0 +1,311 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Mon Aug 16 21:32:26 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 121 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMCS_385 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMCS_385 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMSDI_387 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMCLK_386 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + +Warning: 12.878 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 369 items scored, 244 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) + Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i12 to LEDEN_392 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i12 to LEDEN_392 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) +Route 3 e 1.603 FS[12] +LUT4 --- 0.390 C to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 C to Z i2_3_lut_3_lut +Route 1 e 1.220 RCLK_c_enable_25 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i12 to n8MEGEN_391 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i12 to n8MEGEN_391 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) +Route 3 e 1.603 FS[12] +LUT4 --- 0.390 C to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 D to Z i1248_4_lut +Route 1 e 1.220 RCLK_c_enable_7 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i13 (from RCLK_c +) + Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i13 to LEDEN_392 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i13 to LEDEN_392 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 B to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 C to Z i2_3_lut_3_lut +Route 1 e 1.220 RCLK_c_enable_25 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + +Warning: 11.291 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1285 | 4| 112| 30.68% + | | | +n26 | 1| 70| 19.18% + | | | +RCLK_c_enable_23 | 16| 64| 17.53% + | | | +n2290 | 3| 64| 17.53% + | | | +XOR8MEG_N_112 | 3| 54| 14.79% + | | | +n2119 | 2| 48| 13.15% + | | | +n2166 | 1| 42| 11.51% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 365 Score: 2309745 + +Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage) + + +Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..82208e7 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,376 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:32:26 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..d942735 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v @@ -0,0 +1,789 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.0.240.2 +// Netlist written on Mon Aug 16 21:32:26 2021 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14]) + input PHI2; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + input [9:0]MAin; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + input [1:0]CROW; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + input [7:0]Din; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + output [7:0]Dout; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + input nCCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + input nCRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + input nFWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) + output LED; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) + output [1:0]RBA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + output [11:0]RA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + inout [7:0]RD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + output nRCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) + input RCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + output RCKE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) + output nRWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) + output nRRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) + output nRCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) + output RDQMH; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) + output RDQML; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) + output nUFMCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) + output UFMCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) + output UFMSDI; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) + input UFMSDO; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13]) + + wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, + RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, + n2131, n33, PHI2_N_114_enable_2, n1; + wire [7:0]Bank; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980; + wire [9:0]RowA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16]) + + wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, + RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15]) + + wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, + n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, + RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, + nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, + RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, + n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, + nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, + n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, + XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, + RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, + UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, + UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, + n699, n700, n701, n702, n703, n705, n706, n707, n708, + n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, + n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, + n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, + n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, + n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, + n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, + n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, + n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, + Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, + n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, + n2297, n2154, n10, n2296, n2295; + + VHI i2 (.Z(VCC_net)); + INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r2_350.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), + .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut.init = 16'h0800; + ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_3_lut.init = 16'hfdfd; + FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r3_351.GSR = "ENABLED"; + FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr_352.GSR = "ENABLED"; + FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr2_353.GSR = "ENABLED"; + FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr3_354.GSR = "ENABLED"; + FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr_355.GSR = "ENABLED"; + FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr2_356.GSR = "ENABLED"; + FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr3_357.GSR = "ENABLED"; + FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam RA11_358.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam FWEr_362.GSR = "ENABLED"; + FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam CBR_363.GSR = "ENABLED"; + FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam ADSubmitted_380.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca; + ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut.init = 16'h8888; + CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), + .COUT1(n1878), .S0(n87), .S1(n86)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_10.INIT0 = 16'hfaaa; + defparam FS_577_add_4_10.INIT1 = 16'hfaaa; + defparam FS_577_add_4_10.INJECT1_0 = "NO"; + defparam FS_577_add_4_10.INJECT1_1 = "NO"; + FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5]) + defparam RCKE_368.GSR = "ENABLED"; + FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRCS_369.GSR = "ENABLED"; + FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRowColSel_375.GSR = "ENABLED"; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), + .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_rep_31.init = 16'h0808; + ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; + defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff; + CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), + .COUT1(n1877), .S0(n89), .S1(n88)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_8.INIT0 = 16'hfaaa; + defparam FS_577_add_4_8.INIT1 = 16'hfaaa; + defparam FS_577_add_4_8.INJECT1_0 = "NO"; + defparam FS_577_add_4_8.INJECT1_1 = "NO"; + ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), + .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1_4_lut.init = 16'h0544; + ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), + .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), + .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i4_3_lut_4_lut.init = 16'hfdff; + FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_4_lut_adj_1.init = 16'hcfee; + FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRRAS_370.GSR = "ENABLED"; + ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), + .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ; + defparam i1055_3_lut_4_lut.init = 16'hffd0; + ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37]) + defparam i2_3_lut.init = 16'hfdfd; + BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRCAS_371.GSR = "ENABLED"; + FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRWE_372.GSR = "ENABLED"; + FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam RA10_373.GSR = "ENABLED"; + FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam RCKEEN_374.GSR = "ENABLED"; + ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), + .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_4_lut.init = 16'h0008; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee; + ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), + .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1248_4_lut.init = 16'hc5c0; + ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe; + ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), + .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1437_4_lut.init = 16'hcc5c; + FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_135)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam i1_2_lut_adj_3.init = 16'hbbbb; + ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), + .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i2_4_lut_adj_4.init = 16'h0008; + FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), + .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam C1Submitted_379.GSR = "ENABLED"; + FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam nUFMCS_388.GSR = "ENABLED"; + ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), + .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i2_4_lut_adj_5.init = 16'h0800; + ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; + defparam i5_4_lut.init = 16'hfffb; + FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i0.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), + .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i2_3_lut_adj_6.init = 16'h0202; + ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46]) + defparam i1419_2_lut.init = 16'hbbbb; + ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), + .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ; + defparam n50_bdd_4_lut_1911.init = 16'h03aa; + ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i1893_2_lut.init = 16'h7777; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), + .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1858_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), + .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd; + ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), + .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i22_4_lut.init = 16'hc0ca; + ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), + .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i5_4_lut_adj_8.init = 16'h8000; + ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), + .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1889_4_lut_then_4_lut.init = 16'h0355; + ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), + .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1889_4_lut_else_4_lut.init = 16'hdfff; + CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), + .S0(n79), .S1(n78)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_18.INIT0 = 16'hfaaa; + defparam FS_577_add_4_18.INIT1 = 16'hfaaa; + defparam FS_577_add_4_18.INJECT1_0 = "NO"; + defparam FS_577_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60]) + defparam UFMSDO_I_0_1_lut.init = 16'h5555; + FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), + .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101; + ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), + .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), + .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i1884_4_lut.init = 16'h0302; + FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r_349.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1830_2_lut_rep_13.init = 16'heeee; + PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244)); + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1886_2_lut.init = 16'h4444; + ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), + .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ; + defparam n50_bdd_4_lut.init = 16'h3fbf; + ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), + .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1034_2_lut.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), + .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i2_3_lut_4_lut_adj_9.init = 16'h1000; + ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), + .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef; + FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1424_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ; + defparam i2_3_lut_adj_10.init = 16'h0404; + ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1429_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i4_4_lut.init = 16'hfffe; + ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i5_3_lut_rep_23.init = 16'hfefe; + ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), + .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1_4_lut_adj_11.init = 16'hfaee; + ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), + .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff; + ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), + .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut_adj_12.init = 16'h0040; + ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_adj_13.init = 16'heeee; + ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1420_2_lut.init = 16'heeee; + ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ; + defparam i1_1_lut_rep_29.init = 16'h5555; + ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), + .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7]) + defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5; + ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1069_1_lut.init = 16'h5555; + ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), + .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ; + defparam n2080_bdd_4_lut.init = 16'hca00; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), + .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22]) + defparam i847_2_lut_4_lut.init = 16'h0100; + ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), + .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) + defparam i1_4_lut_adj_14.init = 16'h0080; + ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16]) + defparam i1_2_lut_adj_15.init = 16'hbbbb; + FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i17.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), + .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i1_2_lut_3_lut_3_lut.init = 16'h4040; + FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i16.GSR = "ENABLED"; + FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i15.GSR = "ENABLED"; + ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), + .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6]) + defparam nRWE_I_0_428_4_lut.init = 16'hcfc5; + ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1257_3_lut.init = 16'hcaca; + ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55]) + defparam RCKE_I_0_423_4_lut.init = 16'hcfc8; + FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5]) + defparam InitReady_367.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1854_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), + .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe; + ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i1881_2_lut_rep_24.init = 16'h7777; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i1_2_lut_rep_18_2_lut.init = 16'h4444; + FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i14.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26]) + defparam i2_3_lut_3_lut.init = 16'h4040; + ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) + defparam i2_3_lut_adj_17.init = 16'h4040; + ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), + .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam i2_4_lut_adj_18.init = 16'h0020; + ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), + .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11]) + defparam i1_4_lut_adj_19.init = 16'h1044; + FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam XOR8MEG_381.GSR = "ENABLED"; + FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam n8MEGEN_391.GSR = "ENABLED"; + FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam Ready_377.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca; + FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMCLK_386.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMSDI_387.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), + .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam Cmdn8MEGEN_383.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdSubmitted_384.GSR = "ENABLED"; + CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), + .COUT1(n1876), .S0(n91), .S1(n90)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_6.INIT0 = 16'hfaaa; + defparam FS_577_add_4_6.INIT1 = 16'hfaaa; + defparam FS_577_add_4_6.INJECT1_0 = "NO"; + defparam FS_577_add_4_6.INJECT1_1 = "NO"; + FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMCS_385.GSR = "ENABLED"; + FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i13.GSR = "ENABLED"; + ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34]) + defparam i1875_2_lut.init = 16'hbbbb; + FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i12.GSR = "ENABLED"; + PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_116)); + ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), + .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1856_4_lut.init = 16'h8000; + FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i11.GSR = "ENABLED"; + ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ; + defparam i1844_2_lut.init = 16'h8888; + ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51]) + defparam RA11_I_53_3_lut.init = 16'hc6c6; + ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), + .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ; + defparam Ready_bdd_3_lut_1922.init = 16'hefef; + FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam UFMSDI_390.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca; + ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i604_1_lut_rep_30.init = 16'h5555; + FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i10.GSR = "ENABLED"; + FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i9.GSR = "ENABLED"; + FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i8.GSR = "ENABLED"; + FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i7.GSR = "ENABLED"; + FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i6.GSR = "ENABLED"; + FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i5.GSR = "ENABLED"; + FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i4.GSR = "ENABLED"; + FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i3.GSR = "ENABLED"; + FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i2.GSR = "ENABLED"; + FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i1.GSR = "ENABLED"; + FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_272)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n699)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n700)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n701)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n702)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n703)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_173)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n705)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n706)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n707)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n708)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n709)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n710)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n711)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_161)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) + defparam i1_2_lut_rep_12.init = 16'hdddd; + ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), + .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff; + ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), + .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i1_2_lut_4_lut_4_lut.init = 16'h4000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8]) + defparam nRWE_I_49_1_lut.init = 16'h5555; + BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + OB Dout_pad_7 (.I(n973), .O(Dout[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_6 (.I(n974), .O(Dout[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_5 (.I(n975), .O(Dout[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_4 (.I(n976), .O(Dout[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_3 (.I(n977), .O(Dout[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_2 (.I(n978), .O(Dout[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_1 (.I(n979), .O(Dout[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_c), .O(Dout[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB LED_pad (.I(LED_N_90), .O(LED)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_10 (.I(n980), .O(RA[10])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_9 (.I(RA_c_9), .O(RA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_8 (.I(RA_c_8), .O(RA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_7 (.I(RA_c_7), .O(RA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_6 (.I(RA_c_6), .O(RA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_5 (.I(RA_c_5), .O(RA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_4 (.I(RA_c_4), .O(RA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_3 (.I(RA_c_3), .O(RA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_2 (.I(RA_c_2), .O(RA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_1 (.I(RA_c_1), .O(RA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_0 (.I(RA_c_0), .O(RA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) + ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca; + CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), + .COUT1(n1875), .S0(n93), .S1(n92)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_4.INIT0 = 16'hfaaa; + defparam FS_577_add_4_4.INIT1 = 16'hfaaa; + defparam FS_577_add_4_4.INJECT1_0 = "NO"; + defparam FS_577_add_4_4.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam UFMCLK_389.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd; + ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), + .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe; + ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), + .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_adj_21.init = 16'hfefe; + ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca; + ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), + .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam Ready_bdd_4_lut.init = 16'hf077; + ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), + .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1366_3_lut.init = 16'hcaca; + ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), + .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30]) + defparam i1_4_lut_4_lut.init = 16'h5540; + ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), + .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_11_3_lut.init = 16'h1010; + CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n1874), .S0(n95), .S1(n94)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_2.INIT0 = 16'h0555; + defparam FS_577_add_4_2.INIT1 = 16'hfaaa; + defparam FS_577_add_4_2.INJECT1_0 = "NO"; + defparam FS_577_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), + .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0200; + ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), + .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut_1960.init = 16'h2000; + ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2245_bdd_2_lut.init = 16'heeee; + ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), + .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73; + FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam LEDEN_392.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca; + CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), + .COUT1(n1879), .S0(n85), .S1(n84)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_12.INIT0 = 16'hfaaa; + defparam FS_577_add_4_12.INIT1 = 16'hfaaa; + defparam FS_577_add_4_12.INJECT1_0 = "NO"; + defparam FS_577_add_4_12.INJECT1_1 = "NO"; + FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), + .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdEnable_378.GSR = "ENABLED"; + CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), + .COUT1(n1881), .S0(n81), .S1(n80)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_16.INIT0 = 16'hfaaa; + defparam FS_577_add_4_16.INIT1 = 16'hfaaa; + defparam FS_577_add_4_16.INJECT1_0 = "NO"; + defparam FS_577_add_4_16.INJECT1_1 = "NO"; + CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), + .COUT1(n1880), .S0(n83), .S1(n82)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_14.INIT0 = 16'hfaaa; + defparam FS_577_add_4_14.INIT1 = 16'hfaaa; + defparam FS_577_add_4_14.INJECT1_0 = "NO"; + defparam FS_577_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca; + ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1485_3_lut.init = 16'hcaca; + ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_2_lut.init = 16'h4444; + ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), + .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd; + ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam i1062_3_lut.init = 16'h3a3a; + ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca; + INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + INV i1962 (.A(PHI2_c), .Z(PHI2_N_114)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1070_1_lut_rep_25.init = 16'h5555; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), + .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1860_4_lut.init = 16'h8000; + ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ; + defparam m0_lut.init = 16'h0000; + PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf new file mode 100644 index 0000000..420deec --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf @@ -0,0 +1,89 @@ +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +COMMERCIAL ; \ No newline at end of file diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp new file mode 100644 index 0000000..fc768e6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp @@ -0,0 +1,155 @@ +VOLTAGE 3.300 V; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; +IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 new file mode 100644 index 0000000..f59c75e --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 @@ -0,0 +1,88 @@ +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 new file mode 100644 index 0000000..fc768e6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 @@ -0,0 +1,155 @@ +VOLTAGE 3.300 V; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; +IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html new file mode 100644 index 0000000..14546c8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html @@ -0,0 +1,2080 @@ + + + + + + + +
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:23:38 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.540ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
+
+   Delay:               0.517ns  (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.517ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.540ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.255       R6C3C.Q0 to R6C3C.B0       ADSubmitted
+CTOF_DEL    ---     0.092       R6C3C.B0 to       R6C3C.F0 SLICE_9
+ROUTE         1     0.000       R6C3C.F0 to R6C3C.DI0      n1355 (to PHI2_c)
+                  --------
+                    0.517   (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.089ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:               1.060ns  (33.4% logic, 66.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.060ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     0.178       R4C5A.F1 to R5C5D.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.060   (33.4% logic, 66.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R5C5D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.165ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:               1.136ns  (31.2% logic, 68.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.136ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.165ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     0.427       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.136   (31.2% logic, 68.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.212ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               1.183ns  (29.9% logic, 70.1% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.183ns physical path delay SLICE_18 to SLICE_77 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.212ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     0.301       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.183   (29.9% logic, 70.1% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.247ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:               1.218ns  (29.1% logic, 70.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.218ns physical path delay SLICE_18 to SLICE_94 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.247ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.266       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     0.424       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.218   (29.1% logic, 70.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.288ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:               1.259ns  (28.1% logic, 71.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.259ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.288ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     0.550       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.259   (28.1% logic, 71.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.392ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.363ns  (37.1% logic, 62.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.363ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4C.CLK to       R6C4C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.256       R6C4C.Q0 to R6C3D.A1       C1Submitted
+CTOOFX_DEL  ---     0.151       R6C3D.A1 to     R6C3D.OFX0 i26/SLICE_70
+ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
+CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
+ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
+CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
+ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.363   (37.1% logic, 62.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.395ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.366ns  (37.3% logic, 62.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.366ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.395ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.255       R6C3C.Q0 to R6C3D.B0       ADSubmitted
+CTOOFX_DEL  ---     0.155       R6C3D.B0 to     R6C3D.OFX0 i26/SLICE_70
+ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
+CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
+ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
+CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
+ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.366   (37.3% logic, 62.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 175.744ns (weighted slack = 351.488ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
+
+   Delay:               0.733ns  (35.7% logic, 64.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.733ns physical path delay SLICE_94 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.744ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R8C5C.CLK to       R8C5C.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     0.471       R8C5C.Q0 to R2C5A.C0       XOR8MEG
+CTOF_DEL    ---     0.092       R2C5A.C0 to       R2C5A.F0 SLICE_31
+ROUTE         1     0.000       R2C5A.F0 to R2C5A.DI0      RA11_N_180 (to PHI2_c)
+                  --------
+                    0.733   (35.7% logic, 64.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R2C5A.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 176.433ns (weighted slack = 352.866ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
+
+   Delay:               1.404ns  (24.3% logic, 75.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.404ns physical path delay SLICE_92 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.433ns
+
+ Physical Path Details:
+
+      Data path SLICE_92 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3B.CLK to       R2C3B.Q1 SLICE_92 (from PHI2_c)
+ROUTE         1     0.502       R2C3B.Q1 to R5C4B.A1       Bank_3
+CTOF_DEL    ---     0.092       R5C4B.A1 to       R5C4B.F1 SLICE_74
+ROUTE         5     0.137       R5C4B.F1 to R5C4B.C0       n1279
+CTOF_DEL    ---     0.092       R5C4B.C0 to       R5C4B.F0 SLICE_74
+ROUTE         1     0.424       R5C4B.F0 to R6C4C.CE       PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.404   (24.3% logic, 75.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_92:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R2C3B.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_101 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4C.CLK to       R5C4C.Q0 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R5C4C.Q0 to R5C4C.M1       n705 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4C.CLK to       R4C4C.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.161       R4C4C.Q0 to R4C4C.M1       n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4D.CLK to       R5C4D.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R5C4D.Q0 to R5C4D.M1       n695 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_95 to SLICE_95 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C2A.CLK to       R6C2A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.161       R6C2A.Q0 to R6C2A.M1       n699 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q1 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R5C4A.Q1 to R5C4D.M0       n696 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_96 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q0 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R5C4A.Q0 to R5C4A.M1       n697 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_344  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_345  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_97 to SLICE_88 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C3C.CLK to       R7C3C.Q1 SLICE_97 (from RCLK_c)
+ROUTE         1     0.161       R7C3C.Q1 to R7C3B.M1       PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_99 to SLICE_99 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q0 SLICE_99 (from RCLK_c)
+ROUTE         1     0.161       R3C5C.Q0 to R3C5C.M1       n693 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_345  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_346  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_88 to SLICE_97 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C3B.CLK to       R7C3B.Q1 SLICE_88 (from RCLK_c)
+ROUTE         3     0.167       R7C3B.Q1 to R7C3C.M0       PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i15  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i0  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_99 to SLICE_87 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q1 SLICE_99 (from RCLK_c)
+ROUTE         2     0.167       R3C5C.Q1 to R3C5A.M0       Ready_N_272 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.468       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.805ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.318ns  (58.5% logic, 41.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.318ns delay SLICE_64 to RA[9] (totaling 2.805ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.805ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     0.492       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.318   (58.5% logic, 41.5% route), 3 logic levels.
+
+Report:    2.805ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.476ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.989ns delay SLICE_64 to RA[8] (totaling 2.476ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.476ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.197       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
+
+Report:    2.476ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.460ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     1.973ns  (68.8% logic, 31.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.973ns delay SLICE_64 to RA[7] (totaling 2.460ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.460ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.222       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.092       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     0.394       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    1.973   (68.8% logic, 31.2% route), 3 logic levels.
+
+Report:    2.460ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.759ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.272ns  (59.7% logic, 40.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.272ns delay SLICE_64 to RA[6] (totaling 2.759ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.759ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     0.480       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.272   (59.7% logic, 40.3% route), 3 logic levels.
+
+Report:    2.759ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.516ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.029ns  (66.9% logic, 33.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.029ns delay SLICE_64 to RA[5] (totaling 2.516ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.516ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.092       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     0.394       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.029   (66.9% logic, 33.1% route), 3 logic levels.
+
+Report:    2.516ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.635ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.148ns  (63.2% logic, 36.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.148ns delay SLICE_64 to RA[4] (totaling 2.635ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.635ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     0.356       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.148   (63.2% logic, 36.8% route), 3 logic levels.
+
+Report:    2.635ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.758ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.271ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.271ns delay SLICE_64 to RA[3] (totaling 2.758ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.758ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     0.468       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.271   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    2.758ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.000ns delay SLICE_64 to RA[2] (totaling 2.487ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.487ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.197       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
+
+Report:    2.487ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.000ns delay SLICE_64 to RA[1] (totaling 2.487ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.487ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.197       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
+
+Report:    2.487ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.476ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.989ns delay SLICE_64 to RA[0] (totaling 2.476ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.476ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.197       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
+
+Report:    2.476ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.765ns  (71.7% logic, 28.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.765ns delay SLICE_34 to RCKE (totaling 2.252ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.252ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.500       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.765   (71.7% logic, 28.3% route), 2 logic levels.
+
+Report:    2.252ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRWE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.197       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.111ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.624ns  (77.9% logic, 22.1% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.624ns delay SLICE_61 to nRRAS (totaling 2.111ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.111ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.359       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.624   (77.9% logic, 22.1% route), 2 logic levels.
+
+Report:    2.111ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.733ns delay SLICE_58 to nRCAS (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.468       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.510ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.023ns  (67.1% logic, 32.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.023ns delay SLICE_64 to RDQMH (totaling 2.510ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.510ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.197       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.023   (67.1% logic, 32.9% route), 3 logic levels.
+
+Report:    2.510ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.602ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.115ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.115ns delay SLICE_64 to RDQML (totaling 2.602ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.602ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.092       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     0.480       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.115   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    2.602ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 15.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.805 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.460 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.759 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.516 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.635 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.252 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.111 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.510 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.602 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 520 paths, 6 nets, and 436 connections (70.89% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
new file mode 100644
index 0000000..267300a
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
@@ -0,0 +1,3314 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:23:38 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 162.969ns (weighted slack = 325.938ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.766ns  (23.7% logic, 76.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.766ns physical path delay SLICE_93 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.969ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.766   (23.7% logic, 76.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.029ns (weighted slack = 326.058ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.706ns  (23.8% logic, 76.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.706ns physical path delay SLICE_98 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.029ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.706   (23.8% logic, 76.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.113ns (weighted slack = 326.226ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.622ns  (24.0% logic, 76.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.622ns physical path delay SLICE_93 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.622   (24.0% logic, 76.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.562ns  (24.1% logic, 75.9% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.562ns physical path delay SLICE_98 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.173ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.562   (24.1% logic, 75.9% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.236ns (weighted slack = 326.472ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.499ns  (24.2% logic, 75.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.499ns physical path delay SLICE_90 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.236ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
+CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.499   (24.2% logic, 75.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              11.458ns  (24.3% logic, 75.7% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_93 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.458   (24.3% logic, 75.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.337ns (weighted slack = 326.674ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              11.398ns  (24.4% logic, 75.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.398ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.337ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.398   (24.4% logic, 75.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.380ns (weighted slack = 326.760ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.355ns  (24.5% logic, 75.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.355ns physical path delay SLICE_90 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.380ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
+CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.355   (24.5% logic, 75.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.430ns (weighted slack = 326.860ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:              11.305ns  (24.6% logic, 75.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.305ns physical path delay SLICE_93 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.305   (24.6% logic, 75.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:              11.245ns  (24.8% logic, 75.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.245ns physical path delay SLICE_98 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.490ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.245   (24.8% logic, 75.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   24.062ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_73
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_74
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 6.275ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.481ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.481ns physical path delay SLICE_7 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.275ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
+CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.481   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.434ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.322ns  (29.0% logic, 71.0% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.322ns physical path delay SLICE_7 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.434ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
+CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.322   (29.0% logic, 71.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.474ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.282ns  (29.2% logic, 70.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.282ns physical path delay SLICE_7 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
+CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.282   (29.2% logic, 70.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.633ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.123ns  (29.7% logic, 70.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.123ns physical path delay SLICE_7 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.633ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
+CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.123   (29.7% logic, 70.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.693ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.063ns  (30.0% logic, 70.0% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.063ns physical path delay SLICE_8 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.693ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.063   (30.0% logic, 70.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.852ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.904ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.904ns physical path delay SLICE_8 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.852ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.904   (30.6% logic, 69.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.891ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.865ns  (26.0% logic, 74.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.865ns physical path delay SLICE_4 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.891ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
+CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.865   (26.0% logic, 74.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.951ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.805ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.805ns physical path delay SLICE_5 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.951ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3A.CLK to       R8C3A.Q1 SLICE_5 (from RCLK_c)
+ROUTE         2     1.503       R8C3A.Q1 to R7C4C.A1       FS_1
+CTOF_DEL    ---     0.371       R7C4C.A1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.805   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3A.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.017ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.739ns  (31.2% logic, 68.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.739ns physical path delay SLICE_8 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 7.017ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.724       R8C4C.Q0 to R8C5D.D1       FS_12
+CTOF_DEL    ---     0.371       R8C5D.D1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.739   (31.2% logic, 68.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.050ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.706ns  (26.5% logic, 73.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.706ns physical path delay SLICE_4 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 7.050ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
+CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.706   (26.5% logic, 73.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.725ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_55 and
+      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
+     12.500ns offset RCLK to RA[10] by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.984       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_55 and
+      5.683ns delay SLICE_55 to RA[10] (totaling 7.280ns) meets
+      0.000ns hold offset RCLK to RA[10] by 7.280ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.532       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    7.280ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.684ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     8.400ns  (54.4% logic, 45.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.400ns delay SLICE_64 to RA[9] (totaling 10.816ns) meets
+     12.500ns offset RCLK to RA[9] by 1.684ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     2.052       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    8.400   (54.4% logic, 45.6% route), 3 logic levels.
+
+Report:   10.816ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.596ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.596ns delay SLICE_64 to RA[9] (totaling 9.193ns) meets
+      0.000ns hold offset RCLK to RA[9] by 9.193ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     1.610       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.596   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:    9.193ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.988ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.096ns delay SLICE_64 to RA[8] (totaling 9.512ns) meets
+     12.500ns offset RCLK to RA[8] by 2.988ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.817       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
+
+Report:    9.512ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.119ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.522ns delay SLICE_64 to RA[8] (totaling 8.119ns) meets
+      0.000ns hold offset RCLK to RA[8] by 8.119ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.646       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
+
+Report:    8.119ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.977ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.107ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.107ns delay SLICE_64 to RA[7] (totaling 9.523ns) meets
+     12.500ns offset RCLK to RA[7] by 2.977ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.880       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.371       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     1.660       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.107   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:    9.523ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.063ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     6.466ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.466ns delay SLICE_64 to RA[7] (totaling 8.063ns) meets
+      0.000ns hold offset RCLK to RA[7] by 8.063ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.726       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.301       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     1.288       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    6.466   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    8.063ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.822ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     8.262ns  (55.3% logic, 44.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.262ns delay SLICE_64 to RA[6] (totaling 10.678ns) meets
+     12.500ns offset RCLK to RA[6] by 1.822ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     1.983       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    8.262   (55.3% logic, 44.7% route), 3 logic levels.
+
+Report:   10.678ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.044ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.447ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.447ns delay SLICE_64 to RA[6] (totaling 9.044ns) meets
+      0.000ns hold offset RCLK to RA[6] by 9.044ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     1.571       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.447   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    9.044ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.738ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.346ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.346ns delay SLICE_64 to RA[5] (totaling 9.762ns) meets
+     12.500ns offset RCLK to RA[5] by 2.738ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.371       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     1.660       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.346   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.762ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     6.655ns  (66.9% logic, 33.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.655ns delay SLICE_64 to RA[5] (totaling 8.252ns) meets
+      0.000ns hold offset RCLK to RA[5] by 8.252ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.301       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     1.288       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    6.655   (66.9% logic, 33.1% route), 3 logic levels.
+
+Report:    8.252ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.279ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.805ns  (58.5% logic, 41.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.805ns delay SLICE_64 to RA[4] (totaling 10.221ns) meets
+     12.500ns offset RCLK to RA[4] by 2.279ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     1.526       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.805   (58.5% logic, 41.5% route), 3 logic levels.
+
+Report:   10.221ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.638ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.041ns  (63.2% logic, 36.8% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.041ns delay SLICE_64 to RA[4] (totaling 8.638ns) meets
+      0.000ns hold offset RCLK to RA[4] by 8.638ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     1.165       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.041   (63.2% logic, 36.8% route), 3 logic levels.
+
+Report:    8.638ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.800ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.284ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.284ns delay SLICE_64 to RA[3] (totaling 10.700ns) meets
+     12.500ns offset RCLK to RA[3] by 1.800ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     1.984       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.284   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.700ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.042ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.445ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.445ns delay SLICE_64 to RA[3] (totaling 9.042ns) meets
+      0.000ns hold offset RCLK to RA[3] by 9.042ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     1.532       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.445   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    9.042ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.967ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.117ns delay SLICE_64 to RA[2] (totaling 9.533ns) meets
+     12.500ns offset RCLK to RA[2] by 2.967ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.817       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    9.533ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.156ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.559ns delay SLICE_64 to RA[2] (totaling 8.156ns) meets
+      0.000ns hold offset RCLK to RA[2] by 8.156ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.646       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
+
+Report:    8.156ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.967ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.117ns delay SLICE_64 to RA[1] (totaling 9.533ns) meets
+     12.500ns offset RCLK to RA[1] by 2.967ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.817       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    9.533ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.156ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.559ns delay SLICE_64 to RA[1] (totaling 8.156ns) meets
+      0.000ns hold offset RCLK to RA[1] by 8.156ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.646       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
+
+Report:    8.156ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.988ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.096ns delay SLICE_64 to RA[0] (totaling 9.512ns) meets
+     12.500ns offset RCLK to RA[0] by 2.988ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.817       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
+
+Report:    9.512ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.119ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.522ns delay SLICE_64 to RA[0] (totaling 8.119ns) meets
+      0.000ns hold offset RCLK to RA[0] by 8.119ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.646       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
+
+Report:    8.119ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRCS by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.394ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_60 and
+      4.797ns delay SLICE_60 to nRCS (totaling 6.394ns) meets
+      0.000ns hold offset RCLK to nRCS by 6.394ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.646       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.394ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.806ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.278ns  (66.8% logic, 33.2% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_34 and
+      6.278ns delay SLICE_34 to RCKE (totaling 8.694ns) meets
+     12.500ns offset RCLK to RCKE by 3.806ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     2.082       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    6.278   (66.8% logic, 33.2% route), 2 logic levels.
+
+Report:    8.694ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.385ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.788ns  (71.7% logic, 28.3% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_34 and
+      5.788ns delay SLICE_34 to RCKE (totaling 7.385ns) meets
+      0.000ns hold offset RCLK to RCKE by 7.385ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     1.637       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.788   (71.7% logic, 28.3% route), 2 logic levels.
+
+Report:    7.385ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_63 and
+      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRWE by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.817       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.394ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_63 and
+      4.797ns delay SLICE_63 to nRWE (totaling 6.394ns) meets
+      0.000ns hold offset RCLK to nRWE by 6.394ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.646       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.394ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.360ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.724ns  (73.3% logic, 26.7% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_61 and
+      5.724ns delay SLICE_61 to nRRAS (totaling 8.140ns) meets
+     12.500ns offset RCLK to nRRAS by 4.360ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.528       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.724   (73.3% logic, 26.7% route), 2 logic levels.
+
+Report:    8.140ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.920ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.323ns  (78.0% logic, 22.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_61 and
+      5.323ns delay SLICE_61 to nRRAS (totaling 6.920ns) meets
+      0.000ns hold offset RCLK to nRRAS by 6.920ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.172       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.323   (78.0% logic, 22.0% route), 2 logic levels.
+
+Report:    6.920ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_58 and
+      6.180ns delay SLICE_58 to nRCAS (totaling 8.596ns) meets
+     12.500ns offset RCLK to nRCAS by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.984       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_58 and
+      5.683ns delay SLICE_58 to nRCAS (totaling 7.280ns) meets
+      0.000ns hold offset RCLK to nRCAS by 7.280ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.532       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    7.280ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.919ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.165ns  (63.7% logic, 36.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.165ns delay SLICE_64 to RDQMH (totaling 9.581ns) meets
+     12.500ns offset RCLK to RDQMH by 2.919ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.817       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.165   (63.7% logic, 36.3% route), 3 logic levels.
+
+Report:    9.581ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.229ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     6.632ns  (67.1% logic, 32.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.632ns delay SLICE_64 to RDQMH (totaling 8.229ns) meets
+      0.000ns hold offset RCLK to RDQMH by 8.229ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.646       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    6.632   (67.1% logic, 32.9% route), 3 logic levels.
+
+Report:    8.229ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.415ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.669ns  (59.6% logic, 40.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.669ns delay SLICE_64 to RDQML (totaling 10.085ns) meets
+     12.500ns offset RCLK to RDQML by 2.415ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.371       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     1.983       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.669   (59.6% logic, 40.4% route), 3 logic levels.
+
+Report:   10.085ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.535ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.938ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.938ns delay SLICE_64 to RDQML (totaling 8.535ns) meets
+      0.000ns hold offset RCLK to RDQML by 8.535ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.301       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     1.571       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.938   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    8.535ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    24.062 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 15.000000 ns  ;     |    15.000 ns|     8.725 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.816 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.193 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.063 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.678 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.044 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.762 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.252 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.221 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.638 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.700 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.042 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.694 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.385 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.140 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.920 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.581 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.229 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.085 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.535 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 538 paths, 6 nets, and 436 connections (70.89% coverage)
+
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/automake.log b/CPLD/LCMXO/LCMXO256C/impl1/automake.log
new file mode 100644
index 0000000..e197df1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/automake.log
@@ -0,0 +1,528 @@
+
+ibisgen "RAM2GS_LCMXO256C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Mon Aug 16 21:36:25 2021
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO256C_impl1.par" 
+
+bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
+ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed"  -comment "RAM2GS_LCMXO256C_impl1.alt" 
+Lattice Diamond Deployment Tool 3.12 Command Line
+
+Loading Programmer Device Database...
+
+Generating JED.....
+Device Name: LCMXO256C-XXT100
+Reading Input File: RAM2GS_LCMXO256C_impl1.bit
+Output File: RAM2GS_LCMXO256C_impl1.jed
+Comment file RAM2GS_LCMXO256C_impl1.alt.
+Generating JEDEC.....
+File RAM2GS_LCMXO256C_impl1.jed generated successfully.
+Lattice Diamond Deployment Tool has exited successfully.
+
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..0b86833
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,9 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
new file mode 100644
index 0000000..68dddcc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
@@ -0,0 +1,137 @@
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:32:34 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.215      3       1.805     3
+CROW[1] nCRAS F    -0.050      M       2.105     3
+Din[0]  PHI2  F     5.083      3       2.097     3
+Din[0]  nCCAS F    -0.020      M       2.133     3
+Din[1]  PHI2  F     3.519      3       2.454     3
+Din[1]  nCCAS F    -0.146      M       2.462     3
+Din[2]  PHI2  F     4.416      3       2.660     3
+Din[2]  nCCAS F     0.272      3       1.853     3
+Din[3]  PHI2  F     5.627      3       2.084     3
+Din[3]  nCCAS F    -0.024      M       2.144     3
+Din[4]  PHI2  F     4.808      3       2.117     3
+Din[4]  nCCAS F     0.350      3       1.766     3
+Din[5]  PHI2  F     5.446      3       2.212     3
+Din[5]  nCCAS F     0.435      3       1.708     3
+Din[6]  PHI2  F     5.339      3       1.487     3
+Din[6]  nCCAS F    -0.140      M       2.452     3
+Din[7]  PHI2  F     4.546      3       1.555     3
+Din[7]  nCCAS F    -0.016      M       2.122     3
+MAin[0] PHI2  F     4.027      3       0.711     3
+MAin[0] nCRAS F     1.132      3       0.987     3
+MAin[1] PHI2  F     4.032      3       1.734     3
+MAin[1] nCRAS F     0.704      3       1.373     3
+MAin[2] PHI2  F    10.358      3      -0.773     M
+MAin[2] nCRAS F    -0.202      M       2.529     3
+MAin[3] PHI2  F    10.442      3      -0.829     M
+MAin[3] nCRAS F     0.186      3       1.819     3
+MAin[4] PHI2  F    10.311      3      -0.765     M
+MAin[4] nCRAS F     0.569      3       1.506     3
+MAin[5] PHI2  F     7.007      3       0.178     3
+MAin[5] nCRAS F     0.186      3       1.819     3
+MAin[6] PHI2  F     9.786      3      -0.641     M
+MAin[6] nCRAS F     0.177      3       1.829     3
+MAin[7] PHI2  F    10.008      3      -0.718     M
+MAin[7] nCRAS F    -0.092      M       2.222     3
+MAin[8] nCRAS F    -0.202      M       2.532     3
+MAin[9] nCRAS F     0.228      3       1.797     3
+PHI2    RCLK  R     5.091      3      -0.759     M
+UFMSDO  RCLK  R     2.219      3      -0.104     M
+nCCAS   RCLK  R     3.820      3      -0.611     M
+nCCAS   nCRAS F     1.538      3       0.708     3
+nCRAS   RCLK  R     4.749      3      -0.670     M
+nFWE    PHI2  F     5.301      3       1.647     3
+nFWE    nCRAS F     1.049      3       1.128     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.669         3        3.051          M
+RA[0]  RCLK  R     9.674         3        2.492          M
+RA[0]  nCRAS F    12.127         3        3.067          M
+RA[10] RCLK  R     8.596         3        2.220          M
+RA[11] PHI2  R     9.987         3        2.559          M
+RA[1]  RCLK  R     8.766         3        2.284          M
+RA[1]  nCRAS F    11.652         3        2.982          M
+RA[2]  RCLK  R    10.062         3        2.599          M
+RA[2]  nCRAS F    12.947         3        3.306          M
+RA[3]  RCLK  R     9.933         3        2.555          M
+RA[3]  nCRAS F    12.783         3        3.240          M
+RA[4]  RCLK  R     8.504         3        2.219          M
+RA[4]  nCRAS F    11.513         3        2.948          M
+RA[5]  RCLK  R     9.609         3        2.481          M
+RA[5]  nCRAS F    11.870         3        3.010          M
+RA[6]  RCLK  R    10.001         3        2.579          M
+RA[6]  nCRAS F    12.947         3        3.292          M
+RA[7]  RCLK  R    10.255         3        2.652          M
+RA[7]  nCRAS F    12.177         3        3.089          M
+RA[8]  RCLK  R     8.896         3        2.316          M
+RA[8]  nCRAS F    11.417         3        2.920          M
+RA[9]  RCLK  R     8.766         3        2.284          M
+RA[9]  nCRAS F    11.617         3        2.957          M
+RBA[0] nCRAS F     9.698         3        2.483          M
+RBA[1] nCRAS F    11.425         3        2.916          M
+RCKE   RCLK  R     9.080         3        2.363          M
+RDQMH  RCLK  R     9.475         3        2.443          M
+RDQML  RCLK  R    10.477         3        2.713          M
+RD[0]  nCCAS F    11.252         3        2.942          M
+RD[1]  nCCAS F    11.963         3        3.100          M
+RD[2]  nCCAS F    12.880         3        3.336          M
+RD[3]  nCCAS F    12.422         3        3.224          M
+RD[4]  nCCAS F    11.252         3        2.942          M
+RD[5]  nCCAS F    12.423         3        3.212          M
+RD[6]  nCCAS F    12.979         3        3.375          M
+RD[7]  nCCAS F    12.914         3        3.350          M
+UFMCLK RCLK  R     8.007         3        2.126          M
+UFMSDI RCLK  R     8.007         3        2.126          M
+nRCAS  RCLK  R     8.595         3        2.232          M
+nRCS   RCLK  R     7.429         3        1.949          M
+nRRAS  RCLK  R     8.615         3        2.236          M
+nRWE   RCLK  R     7.429         3        1.949          M
+nUFMCS RCLK  R     9.193         3        2.413          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
new file mode 100644
index 0000000..7b7fee7
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 26.150 ns (350.000 ns);
+Period_1 = 2.000 ns (350.000 ns);
+Period_2 = 2.000 ns (350.000 ns);
+Period_3 = 8.434 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 8.596 ns (12.500 ns);
+Tco_17 = 8.766 ns (12.500 ns);
+Tco_18 = 8.896 ns (12.500 ns);
+Tco_19 = 10.255 ns (12.500 ns);
+Tco_20 = 10.001 ns (12.500 ns);
+Tco_21 = 9.609 ns (12.500 ns);
+Tco_22 = 8.504 ns (12.500 ns);
+Tco_23 = 9.933 ns (12.500 ns);
+Tco_24 = 10.062 ns (12.500 ns);
+Tco_25 = 8.766 ns (12.500 ns);
+Tco_26 = 9.674 ns (12.500 ns);
+Tco_27 = 7.429 ns (12.500 ns);
+Tco_28 = 9.080 ns (12.500 ns);
+Tco_29 = 7.429 ns (12.500 ns);
+Tco_30 = 8.615 ns (12.500 ns);
+Tco_31 = 8.595 ns (12.500 ns);
+Tco_32 = 9.475 ns (12.500 ns);
+Tco_33 = 10.477 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 2.220 ns (0.000 ns);
+Tco_17 = 2.284 ns (0.000 ns);
+Tco_18 = 2.316 ns (0.000 ns);
+Tco_19 = 2.652 ns (0.000 ns);
+Tco_20 = 2.579 ns (0.000 ns);
+Tco_21 = 2.481 ns (0.000 ns);
+Tco_22 = 2.219 ns (0.000 ns);
+Tco_23 = 2.555 ns (0.000 ns);
+Tco_24 = 2.599 ns (0.000 ns);
+Tco_25 = 2.284 ns (0.000 ns);
+Tco_26 = 2.492 ns (0.000 ns);
+Tco_27 = 1.949 ns (0.000 ns);
+Tco_28 = 2.363 ns (0.000 ns);
+Tco_29 = 1.949 ns (0.000 ns);
+Tco_30 = 2.236 ns (0.000 ns);
+Tco_31 = 2.232 ns (0.000 ns);
+Tco_32 = 2.443 ns (0.000 ns);
+Tco_33 = 2.713 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log b/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log
new file mode 100644
index 0000000..70a7a9b
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log
@@ -0,0 +1,239 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:25 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.406  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.530  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html b/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html
new file mode 100644
index 0000000..8faa0b2
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html
@@ -0,0 +1,304 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:25 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.406  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.530  secs
+--------------------------------------------------------------
+
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diff --git a/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..29f9161
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,252 @@
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diff --git a/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_sign_file b/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_sign_file
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index 0000000..47217b1
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+LSE_CPS_ID_235 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_236 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
+LSE_CPS_ID_237 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_238 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_239 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_240 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:288[9] 324[5]"
+LSE_CPS_ID_241 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_242 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_243 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_244 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:83[6:15]"
+LSE_CPS_ID_245 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_246 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_247 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
+LSE_CPS_ID_248 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_249 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_250 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:16[15:20]"
+LSE_CPS_ID_251 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:8[8:12]"
+LSE_CPS_ID_252 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
diff --git a/CPLD/LCMXO/LCMXO640C/.run_manager.ini b/CPLD/LCMXO/LCMXO640C/.run_manager.ini
new file mode 100644
index 0000000..8c0aa7b
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.run_manager.ini
@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/CPLD/LCMXO/LCMXO640C/.setting.ini b/CPLD/LCMXO/LCMXO640C/.setting.ini
new file mode 100644
index 0000000..c145fb8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.setting.ini
@@ -0,0 +1,4 @@
+[General]
+Export.auto_tasks=IBIS, Bitgen
+Map.auto_tasks=MapEqu, MapTrace
+PAR.auto_tasks=PARTrace, IOTiming
diff --git a/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini b/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini
new file mode 100644
index 0000000..6c511f4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini
@@ -0,0 +1,3 @@
+[General]
+COLUMN_POS_INFO_NAME_-1_0=Prioritize
+COLUMN_POS_INFO_NAME_-1_1=PIO Register
diff --git a/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini b/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini
new file mode 100644
index 0000000..54adf6f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini
@@ -0,0 +1,65 @@
+[General]
+pin_sort_type=0
+pin_sort_ascending=true
+sig_sort_type=0
+sig_sort_ascending=true
+active_Sheet=Port Assignments
+
+[Port%20Assignments]
+Name="166,0"
+Group%20By="84,1"
+Pin="56,2"
+BANK="62,3"
+IO_TYPE="131,4"
+PULLMODE="92,5"
+DRIVE="67,6"
+SLEWRATE="92,7"
+OPENDRAIN="97,8"
+Outload%20%28pF%29="103,9"
+MaxSkew="87,10"
+Clock%20Load%20Only="121,11"
+sort_columns="Name,Ascending"
+
+[Pin%20Assignments]
+Pin="90,0"
+Pad%20Name="89,1"
+Dual%20Function="109,2"
+Polarity="77,3"
+BANK="0,4"
+IO_TYPE="131,5"
+Signal%20Name="113,6"
+Signal%20Type="115,7"
+sort_columns="Pin,Ascending"
+
+[Clock%20Resource]
+Clock%20Type="100,ELLIPSIS"
+Clock%20Name="100,ELLIPSIS"
+Selection="100,ELLIPSIS"
+
+[Global%20Preferences]
+Preference%20Name="222,ELLIPSIS"
+Preference%20Value="236,ELLIPSIS"
+
+[Cell%20Mapping]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Din\Dout="100,ELLIPSIS"
+PIO%20Register="100,ELLIPSIS"
+
+[Route%20Priority]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Prioritize="100,ELLIPSIS"
+
+[Timing%20Preferences]
+Preference%20Name="246,ELLIPSIS"
+Preference%20Value="104,ELLIPSIS"
+Preference%20Unit="98,ELLIPSIS"
+
+[Group]
+Group%20Type\Name="134,ELLIPSIS"
+Value="38,ELLIPSIS"
+
+[Misc%20Preferences]
+Preference%20Name="117,ELLIPSIS"
+Preference%20Value="104,ELLIPSIS"
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
new file mode 100644
index 0000000..c625cb6
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
@@ -0,0 +1,14 @@
+
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
new file mode 100644
index 0000000..9fa278f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
@@ -0,0 +1,226 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
+IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
+IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+USE PRIMARY NET "PHI2_c" ;
+USE PRIMARY NET "RCLK_c" ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+USE PRIMARY NET "nCCAS_c" ;
+USE PRIMARY NET "nCRAS_c" ;
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
new file mode 100644
index 0000000..feec63c
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
@@ -0,0 +1,205 @@
+
+
+
+    
+    
+    
+    
+    
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+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
new file mode 100644
index 0000000..c0aa950
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
@@ -0,0 +1,75 @@
+
+Lattice TCL Log
+
+
+
    pn210816203903
+#Start recording tcl command: 8/16/2021 20:34:20
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_project save
+prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:39:03
+
+
+
+
    
+
    
+
    
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+
    
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diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
new file mode 100644
index 0000000..aada37a
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
@@ -0,0 +1,10 @@
+#Start recording tcl command: 8/16/2021 20:34:20
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_project save
+prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:39:03
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
new file mode 100644
index 0000000..3c252b4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/16/2021 21:33:25
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceOne
+#Stop recording: 8/16/2021 21:41:12
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.build_status b/CPLD/LCMXO/LCMXO640C/impl1/.build_status
new file mode 100644
index 0000000..45432b8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/.build_status
@@ -0,0 +1,46 @@
+
+
+    
+        
+            
+            
+            
+            
+        
+        
+            
+            
+            
+            
+            
+        
+        
+            
+            
+            
+        
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+            
+            
+        
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+            
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+            
+            
+            
+        
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb
new file mode 100644
index 0000000..983b4fe
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb
new file mode 100644
index 0000000..8564832
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb
new file mode 100644
index 0000000..9600020
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/dbStat.txt
new file mode 100644
index 0000000..0a575a4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/dbStat.txt
@@ -0,0 +1 @@
+RAM2GS_rtl.vdb
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs b/CPLD/LCMXO/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs
new file mode 100644
index 0000000..3823dcb
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/IBIS/RAM2GS_LCMXO640C_im~.ibs
@@ -0,0 +1,2156 @@
+|************************************************************************
+| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+| Generate date: Mon Aug 16 21:36:33 2021
+|************************************************************************
+| IBIS File machxo.ibs
+| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
+| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
+| North Carolina State University, ERL, 2006
+|************************************************************************
+[IBIS ver]       3.2
+[File Name]     RAM2GS_LCMXO640C_im~.ibs
+[File Rev]       2.2
+[Date]           Mon Sep 28 10:44:10 EDT 2009
+[Source]         Lattice Semiconductor EE12 Process
+[Notes]          "Preliminary Version"
+                 Lattice Semiconductor has worked hard to ensure the
+                 models below are accurate and complete.  However, the
+                 data below was generated using simulation of the
+                 input/output model files for the silicon.  Therefore,
+                 the data below is for reference and initial design
+                 purposes only.
+|
+                 The data below is correlated to Spice models.  
+                 For questions regarding this data please contact
+                 us at www.latticesemi.com.
+|
+                 Lattice Semiconductor grants permission to use this
+                 data for use in printed circuit design using this
+                 Lattice programmable logic device.  Other use of this
+                 code, including the selling or duplication of any
+                 portion is strictly prohibited.
+|
+|                NAMING CONVENTION
+|
+        The IBIS [Model] header is limited by the specification to a
+        total of characters.  With such a set of characters available
+        for naming models it becomes important to attempt to
+        meaningfully encode the IO standards so they fit within the
+        twenty character limit.  It would seem that twenty characters
+        would provide room enough for describing IO's.  However, the
+        PLD IO structure continues to grow more and more complex.  The
+        complexity is making the twenty characters insuffiently
+        descriptive.  In order to overcome this issue the naming
+        convention described below is implemented to resolve the issue.
+|
+The twenty character space is managed as follows:
+                 bbbvvvsdddprugtcoixx
+|
+                 b = standard
+                 v = voltage (x.xx V)
+                 s = slew code
+                 d = drive (xx.x ma)
+                 p = pullup code
+                 r = series resistance code
+                 u = terminate to vcc code
+                 g = terminate to gnd code
+                 t = terminate to vtt code
+                 c = common mode termination mode
+                 o = diff resistor code
+                 i = diff resistor current code
+                 x = reserved
+|
+|
+                 standard
+|
+                 LVCMOS                   lvc
+                 lvcmosd                  lvd
+                 LVDSE                    lve
+                 LVTTL                    lvt
+                 lvttld                   ltd
+                 PCI                      pci
+                 pcix                     pcx
+                 AGP1x                    ag1
+                 agp2x                    ag2
+                 sstl_I                   ss1
+                 sstl_II                  ss2
+                 sstld_I                  s1d
+                 sstld_II                 s2d
+                 CTT                      ctt
+                 hstl_i                   hs1
+                 hstl_ii                  hs2
+                 hstl_iii                 hs3
+                 hstl_iv                  hs4
+                 hstld_i                  h1d
+                 hstld_ii                 h2d
+                 gtl                      gtl
+                 gtlplus                  gtp
+                 lvds                     lvs
+                 blvds                    blv
+                 mlvds                    mlv
+                 lvpecl                   lvp
+                 cml                      cml
+                 hypt                     hyp
+                 rsds                     rsd
+                 vref1                    vr1
+                 vref2                    vr2
+                 ref_res                  rer
+|
+|
+                 slew
+                 na                       a
+                 fast                     f
+                 slow                     s
+|
+                 pullmode
+                 off                      a
+                 pullup                   b
+                 pulldown                 c
+                 bushold                  d
+                 pciclamp                 e
+                 up_pciclamp              f
+                 down_pciclamp            g
+                 keeper_pciclamp          h
+                 schmitt                  i
+                 up_schmitt               j
+                 down_schmitt             k
+                 keeper_schmitt           l
+                 up_pciclamp_schmitt      m
+                 down_pciclamp_schmitt    n
+                 keeper_pciclamp_schmitt  o
+                 pciclamp_schmitt         p
+|
+                 impedence
+                 off                      a
+                 25                       b
+                 33                       c
+                 50                       d
+                 100                      e
+|
+                 termVCC
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termGND
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termVTT
+                 off                      a
+                 60                       b
+                 75                       c
+                 120                      d
+                 150                      e
+                 210                      f
+|
+                 VCMT
+                 off                      a
+                 VCMT                     b
+                 VTT                      c
+                 DDR-2                    d
+|
+                 differential resistor
+                 off                      a
+                 120                      b
+                 150                      c
+                 220                      d
+                 420                      e
+|
+                 differential current
+                 NA                       a
+                 2                        b
+                 3.5                      c
+                 4                        d
+                 6                        e
+|
+                 Reserved                 IO type
+                 in                       input only
+                 ou                       output
+                 io                       I/O
+                 od                       Open drain
+                 on                       Inverting differential I/O
+                                          (signal name only)
+                 op                       Non-Inverting differential I/O
+                                          (signal name only)
+|
+   All the IO models are generated with pull mode set to UP.
+|
+                 Lattice Semiconductor Corporation
+                 5555 NE Moore Court
+                 Hillsboro, OR 97214
+                 U.S.A
+|
+                 TEL: 1-800-Lattice (USA and Canada)
+                      408-826-6000 (other locations)
+|
+                 web: http://www.latticesemi.com/
+                 email: techsupport@latticesemi.com
+|
+|
+|
+[Disclaimer]     This IBIS source code is intended as a design reference
+   which illustrates how the Lattice Semiconductor device operates.
+   It is the user's responsibility to verify their design for
+   consistency and functionality through the use of formal
+   verification methods.  Lattice Semiconductor provides no warranty
+   regarding the use or functionality of this data.
+|
+[Copyright]      Copyright 2009 by Lattice Semiconductor Corporation
+|
+|  
+|************************************************************************
+|                       Component XO
+|************************************************************************
+|  
+[Component]     MXO256_MXO640_MXO1K_MXO2K
+[Manufacturer]    Lattice Semiconductor Corp.
+[Package]
+|TQFP100
+| variable            typ              min              max
+R_pkg                 70.5m            54.0m            87.0m
+L_pkg                 4.57nH           4.27nH           4.87nH
+C_pkg                 .52pF            .47pF            .57pF
+|
+[Pin] signal_name           model_name           R_pin     L_pin     C_pin
+32            CROW[0]              lvt330fxxxaaaaaaaain
+34            CROW[1]              lvt330fxxxaaaaaaaain
+21            Din[0]               lvt330fxxxaaaaaaaain
+15            Din[1]               lvt330fxxxaaaaaaaain
+14            Din[2]               lvt330fxxxaaaaaaaain
+16            Din[3]               lvt330fxxxaaaaaaaain
+18            Din[4]               lvt330fxxxaaaaaaaain
+17            Din[5]               lvt330fxxxaaaaaaaain
+20            Din[6]               lvt330fxxxaaaaaaaain
+19            Din[7]               lvt330fxxxaaaaaaaain
+1             Dout[0]              lvt330s040aaaaaaaaio
+7             Dout[1]              lvt330s040aaaaaaaaio
+8             Dout[2]              lvt330s040aaaaaaaaio
+6             Dout[3]              lvt330s040aaaaaaaaio
+4             Dout[4]              lvt330s040aaaaaaaaio
+5             Dout[5]              lvt330s040aaaaaaaaio
+2             Dout[6]              lvt330s040aaaaaaaaio
+3             Dout[7]              lvt330s040aaaaaaaaio
+57            LED                  lvt330s160aaaaaaaaio
+23            MAin[0]              lvt330fxxxaaaaaaaain
+38            MAin[1]              lvt330fxxxaaaaaaaain
+37            MAin[2]              lvt330fxxxaaaaaaaain
+47            MAin[3]              lvt330fxxxaaaaaaaain
+46            MAin[4]              lvt330fxxxaaaaaaaain
+45            MAin[5]              lvt330fxxxaaaaaaaain
+49            MAin[6]              lvt330fxxxaaaaaaaain
+44            MAin[7]              lvt330fxxxaaaaaaaain
+50            MAin[8]              lvt330fxxxaaaaaaaain
+51            MAin[9]              lvt330fxxxaaaaaaaain
+39            PHI2                 lvt330fxxxaaaaaaaain
+98            RA[0]                lvt330s040aaaaaaaaio
+87            RA[10]               lvt330s040aaaaaaaaio
+79            RA[11]               lvt330s040aaaaaaaaio
+89            RA[1]                lvt330s040aaaaaaaaio
+94            RA[2]                lvt330s040aaaaaaaaio
+97            RA[3]                lvt330s040aaaaaaaaio
+99            RA[4]                lvt330s040aaaaaaaaio
+95            RA[5]                lvt330s040aaaaaaaaio
+91            RA[6]                lvt330s040aaaaaaaaio
+100           RA[7]                lvt330s040aaaaaaaaio
+96            RA[8]                lvt330s040aaaaaaaaio
+85            RA[9]                lvt330s040aaaaaaaaio
+63            RBA[0]               lvt330s040aaaaaaaaio
+83            RBA[1]               lvt330s040aaaaaaaaio
+82            RCKE                 lvt330s040aaaaaaaaio
+86            RCLK                 lvt330fxxxaaaaaaaain
+76            RDQMH                lvt330s040aaaaaaaaio
+61            RDQML                lvt330s040aaaaaaaaio
+64            RD[0]                lvt330s040aaaaaaaaio
+65            RD[1]                lvt330s040aaaaaaaaio
+66            RD[2]                lvt330s040aaaaaaaaio
+67            RD[3]                lvt330s040aaaaaaaaio
+68            RD[4]                lvt330s040aaaaaaaaio
+69            RD[5]                lvt330s040aaaaaaaaio
+70            RD[6]                lvt330s040aaaaaaaaio
+71            RD[7]                lvt330s040aaaaaaaaio
+58            UFMCLK               lvt330s040aaaaaaaaio
+56            UFMSDI               lvt330s040aaaaaaaaio
+55            UFMSDO               lvt330fxxxaaaaaaaain
+27            nCCAS                lvt330fxxxaaaaaaaain
+43            nCRAS                lvt330fxxxaaaaaaaain
+22            nFWE                 lvt330fxxxaaaaaaaain
+78            nRCAS                lvt330s040aaaaaaaaio
+77            nRCS                 lvt330s040aaaaaaaaio
+73            nRRAS                lvt330s040aaaaaaaaio
+72            nRWE                 lvt330s040aaaaaaaaio
+53            nUFMCS               lvt330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvt330fxxxaaaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415500nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+| End [Model] lvt330fxxxaaaaaaaain
+|************************************************************************
+[Model]           lvt330s040aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -16.264620mA      -12.195876mA         -17.211942mA
+  -3.20    -16.206900mA      -12.152073mA         -17.150026mA
+  -3.10    -16.149180mA      -12.108270mA         -17.088110mA
+  -3.00    -16.091460mA      -12.064467mA         -17.026194mA
+  -2.90    -16.033740mA      -12.020664mA         -16.964278mA
+  -2.80    -15.976020mA      -11.976862mA         -16.902362mA
+  -2.70    -15.918300mA      -11.933059mA         -16.840446mA
+  -2.60    -15.860580mA      -11.889256mA         -16.778530mA
+  -2.50    -15.802860mA      -11.845453mA         -16.716614mA
+  -2.40    -15.745140mA      -11.801650mA         -16.654698mA
+  -2.30    -15.687420mA      -11.757848mA         -16.592782mA
+  -2.20    -15.629700mA      -11.714045mA         -16.530866mA
+  -2.10    -15.571980mA      -11.670242mA         -16.468950mA
+  -2.00    -15.514260mA      -11.626439mA         -16.407034mA
+  -1.90    -15.456540mA      -11.582636mA         -16.345118mA
+  -1.80    -15.398820mA      -11.538834mA         -16.283202mA
+  -1.70    -15.341100mA      -11.495031mA         -16.221286mA
+  -1.60    -15.283380mA      -11.451228mA         -16.159370mA
+  -1.50    -15.225660mA      -11.407425mA         -16.097454mA
+  -1.40    -15.167940mA      -11.363622mA         -16.035538mA
+  -1.30    -15.110220mA      -11.319820mA         -15.973622mA
+  -1.20    -15.052500mA      -11.276017mA         -15.911706mA
+  -1.10    -14.994780mA      -11.232214mA         -15.849790mA
+  -1.00    -14.937060mA      -11.188411mA         -15.787874mA
+  -0.90    -14.879340mA      -11.144608mA         -15.725958mA
+  -0.80    -14.821620mA      -11.100806mA         -15.634000mA
+  -0.70    -14.763900mA      -11.057003mA         -15.389000mA
+  -0.60    -14.121200mA      -11.013200mA         -15.085900mA
+  -0.50    -12.312470mA      -10.252860mA         -13.892750mA
+  -0.40    -9.922051mA       -8.353886mA          -11.397898mA
+  -0.30    -7.415846mA       -6.279285mA          -8.571802mA
+  -0.20    -4.904405mA       -4.183585mA          -5.687248mA
+  -0.10    -2.422592mA       -2.084866mA          -2.809391mA
+  0.00    9.270000nA        8.640000nA           10.950000nA
+  0.10    2.215985mA        1.960397mA           2.507890mA
+  0.20    4.086375mA        3.683686mA           4.498680mA
+  0.30    5.594166mA        5.150675mA           5.952471mA
+  0.40    6.738256mA        6.352364mA           6.929962mA
+  0.50    7.557146mA        7.289853mA           7.572152mA
+  0.60    8.124436mA        7.983242mA           8.013343mA
+  0.70    8.511126mA        8.476831mA           8.337834mA
+  0.80    8.778316mA        8.826620mA           8.591424mA
+  0.90    8.972606mA        9.080609mA           8.798515mA
+  1.00    9.121395mA        9.272098mA           8.969206mA
+  1.10    9.240584mA        9.422087mA           9.101296mA
+  1.20    9.339574mA        9.543476mA           9.202186mA
+  1.30    9.424063mA        9.644765mA           9.285275mA
+  1.40    9.498053mA        9.731354mA           9.357665mA
+  1.50    9.564242mA        9.806743mA           9.423455mA
+  1.60    9.625232mA        9.873832mA           9.485944mA
+  1.70    9.684621mA        9.934821mA           9.548134mA
+  1.80    9.747011mA        9.992810mA           9.610224mA
+  1.90    9.814800mA        10.052999mA          9.670813mA
+  2.00    9.885689mA        10.122988mA          9.728603mA
+  2.10    9.955379mA        10.203977mA          9.783293mA
+  2.20    10.021968mA       10.292966mA          9.835282mA
+  2.30    10.083958mA       10.380954mA          9.884972mA
+  2.40    10.141947mA       10.464943mA          9.932861mA
+  2.50    10.196936mA       10.542932mA          9.979551mA
+  2.60    10.249926mA       10.614921mA          10.025941mA
+  2.70    10.300915mA       10.681910mA          10.071930mA
+  2.80    10.350904mA       10.744899mA          10.118920mA
+  2.90    10.400894mA       10.805888mA          10.167909mA
+  3.00    10.451883mA       10.863877mA          10.218899mA
+  3.10    10.504872mA       10.921864mA          10.273889mA
+  3.20    10.559862mA       10.978747mA          10.332878mA
+  3.30    10.618848mA       11.037379mA          10.397868mA
+  3.40    10.682725mA       11.085335mA          10.469857mA
+  3.50    10.751986mA       11.124616mA          10.550843mA
+  3.60    10.804292mA       11.163898mA          10.640599mA
+  3.70    10.840604mA       11.203179mA          10.738212mA
+  3.80    10.876916mA       11.242461mA          10.773505mA
+  3.90    10.913228mA       11.281743mA          10.808797mA
+  4.00    10.949540mA       11.321024mA          10.844090mA
+  4.10    10.985852mA       11.360306mA          10.879382mA
+  4.20    11.022164mA       11.399587mA          10.914675mA
+  4.30    11.058476mA       11.438869mA          10.949967mA
+  4.40    11.094788mA       11.478151mA          10.985259mA
+  4.50    11.131100mA       11.517432mA          11.020552mA
+  4.60    11.167412mA       11.556714mA          11.055844mA
+  4.70    11.203724mA       11.595995mA          11.091137mA
+  4.80    11.240036mA       11.635277mA          11.126429mA
+  4.90    11.276348mA       11.674559mA          11.161721mA
+  5.00    11.312660mA       11.713840mA          11.197014mA
+  5.10    11.348972mA       11.753122mA          11.232306mA
+  5.20    11.385284mA       11.792403mA          11.267599mA
+  5.30    11.421596mA       11.831685mA          11.302891mA
+  5.40    11.457908mA       11.870967mA          11.338183mA
+  5.50    11.494220mA       11.910248mA          11.373476mA
+  5.60    11.530532mA       11.949530mA          11.408768mA
+  5.70    11.566844mA       11.988811mA          11.444061mA
+  5.80    11.603156mA       12.028093mA          11.479353mA
+  5.90    11.639468mA       12.067375mA          11.514645mA
+  6.00    11.675780mA       12.106656mA          11.549938mA
+  6.10    11.712092mA       12.145938mA          11.585230mA
+  6.20    11.748404mA       12.185219mA          11.620523mA
+  6.30    11.784716mA       12.224501mA          11.655815mA
+  6.40    11.821028mA       12.263783mA          11.691107mA
+  6.50    11.857340mA       12.303064mA          11.726400mA
+  6.60    11.893652mA       12.342346mA          11.761692mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    6.260163mA        5.384933mA           7.315403mA
+  -3.20    6.239699mA        5.366401mA           7.291487mA
+  -3.10    6.219236mA        5.347870mA           7.267570mA
+  -3.00    6.198773mA        5.329339mA           7.243653mA
+  -2.90    6.178310mA        5.310808mA           7.219736mA
+  -2.80    6.157847mA        5.292277mA           7.195819mA
+  -2.70    6.137383mA        5.273745mA           7.171903mA
+  -2.60    6.116920mA        5.255214mA           7.147986mA
+  -2.50    6.096457mA        5.236683mA           7.124069mA
+  -2.40    6.075994mA        5.218152mA           7.100152mA
+  -2.30    6.055531mA        5.199621mA           7.076235mA
+  -2.20    6.035067mA        5.181089mA           7.052319mA
+  -2.10    6.014604mA        5.162558mA           7.028402mA
+  -2.00    5.994141mA        5.144027mA           7.004485mA
+  -1.90    5.973678mA        5.125496mA           6.980568mA
+  -1.80    5.953215mA        5.106965mA           6.956651mA
+  -1.70    5.932751mA        5.088433mA           6.932735mA
+  -1.60    5.912288mA        5.069902mA           6.908818mA
+  -1.50    5.891825mA        5.051371mA           6.884901mA
+  -1.40    5.871362mA        5.032840mA           6.860984mA
+  -1.30    5.850899mA        5.014309mA           6.837067mA
+  -1.20    5.830435mA        4.995777mA           6.813151mA
+  -1.10    5.809972mA        4.977246mA           6.789234mA
+  -1.00    5.789509mA        4.958715mA           6.765317mA
+  -0.90    5.769046mA        4.940184mA           6.741400mA
+  -0.80    5.748583mA        4.921653mA           6.717483mA
+  -0.70    5.728119mA        4.903121mA           6.693567mA
+  -0.60    5.707656mA        4.884590mA           6.669650mA
+  -0.50    5.687193mA        4.866059mA           6.645733mA
+  -0.40    5.666730mA        4.847528mA           6.621816mA
+  -0.30    5.646267mA        4.828997mA           6.597899mA
+  -0.20    4.435786mA        3.802115mA           5.174820mA
+  -0.10    2.131925mA        1.838548mA           2.475669mA
+  0.00    -6.170000nA       -5.460000nA          -7.060000nA
+  0.10    -1.893038mA       -1.673728mA          -2.145840mA
+  0.20    -3.512428mA       -3.164516mA          -3.900829mA
+  0.30    -4.854717mA       -4.471005mA          -5.257719mA
+  0.40    -5.916606mA       -5.591894mA          -6.209108mA
+  0.50    -6.694696mA       -6.525883mA          -6.765898mA
+  0.60    -7.186085mA       -7.271372mA          -7.127487mA
+  0.70    -7.501974mA       -7.827161mA          -7.398777mA
+  0.80    -7.747264mA       -8.192150mA          -7.614967mA
+  0.90    -7.946053mA       -8.442739mA          -7.794856mA
+  1.00    -8.112642mA       -8.647928mA          -7.949846mA
+  1.10    -8.255932mA       -8.820317mA          -8.086935mA
+  1.20    -8.381921mA       -8.968206mA          -8.210725mA
+  1.30    -8.494611mA       -9.097295mA          -8.324315mA
+  1.40    -8.596900mA       -9.211784mA          -8.430004mA
+  1.50    -8.691089mA       -9.314673mA          -8.529494mA
+  1.60    -8.778479mA       -9.407962mA          -8.623884mA
+  1.70    -8.860368mA       -9.493551mA          -8.714073mA
+  1.80    -8.937858mA       -9.572640mA          -8.800963mA
+  1.90    -9.011447mA       -9.646329mA          -8.884952mA
+  2.00    -9.081837mA       -9.715418mA          -8.966642mA
+  2.10    -9.149526mA       -9.780507mA          -9.046332mA
+  2.20    -9.214816mA       -9.842296mA          -9.124421mA
+  2.30    -9.278305mA       -9.901185mA          -9.201211mA
+  2.40    -9.340094mA       -9.957574mA          -9.277001mA
+  2.50    -9.400784mA       -10.011863mA         -9.352391mA
+  2.60    -9.460574mA       -10.063852mA         -9.427582mA
+  2.70    -9.519964mA       -10.115841mA         -9.503173mA
+  2.80    -9.579454mA       -10.165830mA         -9.579563mA
+  2.90    -9.639644mA       -10.215819mA         -9.657654mA
+  3.00    -9.701034mA       -10.264808mA         -9.737845mA
+  3.10    -9.764525mA       -10.315796mA         -9.821135mA
+  3.20    -9.830715mA       -10.367780mA         -9.908326mA
+  3.30    -9.900606mA       -10.421706mA         -10.000817mA
+  3.40    -9.975092mA       -10.478956mA         -10.098808mA
+  3.50    -10.055705mA      -10.535873mA         -10.202798mA
+  3.60    -10.141346mA      -10.578599mA         -10.316786mA
+  3.70    -10.228551mA      -10.620789mA         -10.438679mA
+  3.80    -10.281620mA      -10.662980mA         -10.570555mA
+  3.90    -10.322662mA      -10.705170mA         -10.682977mA
+  4.00    -10.363704mA      -10.747360mA         -10.725640mA
+  4.10    -10.404746mA      -10.789550mA         -10.768303mA
+  4.20    -10.445787mA      -10.831741mA         -10.810966mA
+  4.30    -10.486829mA      -10.873931mA         -10.853629mA
+  4.40    -10.527871mA      -10.916121mA         -10.896292mA
+  4.50    -10.568913mA      -10.958311mA         -10.938955mA
+  4.60    -10.609955mA      -11.000502mA         -10.981618mA
+  4.70    -10.650997mA      -11.042692mA         -11.024281mA
+  4.80    -10.692039mA      -11.084882mA         -11.066944mA
+  4.90    -10.733081mA      -11.127072mA         -11.109607mA
+  5.00    -10.774122mA      -11.169262mA         -11.152270mA
+  5.10    -10.815164mA      -11.211453mA         -11.194933mA
+  5.20    -10.856206mA      -11.253643mA         -11.237597mA
+  5.30    -10.897248mA      -11.295833mA         -11.280260mA
+  5.40    -10.938290mA      -11.338023mA         -11.322923mA
+  5.50    -10.979332mA      -11.380214mA         -11.365586mA
+  5.60    -11.020374mA      -11.422404mA         -11.408249mA
+  5.70    -11.061416mA      -11.464594mA         -11.450912mA
+  5.80    -11.102458mA      -11.506784mA         -11.493575mA
+  5.90    -11.143499mA      -11.548975mA         -11.536238mA
+  6.00    -11.184541mA      -11.591165mA         -11.578901mA
+  6.10    -11.225583mA      -11.633355mA         -11.621564mA
+  6.20    -11.266625mA      -11.675545mA         -11.664227mA
+  6.30    -11.307667mA      -11.717736mA         -11.706890mA
+  6.40    -11.348709mA      -11.759926mA         -11.749553mA
+  6.50    -11.389751mA      -11.802116mA         -11.792216mA
+  6.55    -11.410272mA      -11.823211mA         -11.813548mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.287457/0.467122n  0.301305/0.700268n  0.291706/0.349090n
+dV/dt_f  0.309900/0.449885n  0.304680/0.837003n  0.308100/0.266290n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.782900V         2.609000V            2.960100V
+0.2020ns          2.783000V         2.608900V            2.962600V
+0.4040ns          2.788300V         2.610900V            3.086900V
+0.6061ns          3.016200V         2.611900V            3.417200V
+0.8081ns          3.244000V         2.678900V            3.463300V
+1.0101ns          3.291900V         2.961800V            3.467200V
+1.2121ns          3.295700V         3.102900V            3.468900V
+1.4141ns          3.297500V         3.120100V            3.469600V
+1.6162ns          3.298700V         3.136000V            3.469800V
+1.8182ns          3.299500V         3.136600V            3.469900V
+2.0202ns          3.299700V         3.137000V            3.469900V
+2.2222ns          3.299800V         3.138000V            3.469900V
+2.4242ns          3.299900V         3.138900V            3.469200V
+2.6263ns          3.299900V         3.139400V            3.471100V
+2.8283ns          3.299900V         3.139700V            3.470500V
+3.0303ns          3.299900V         3.139800V            3.470100V
+3.2323ns          3.299900V         3.139800V            3.470000V
+3.4343ns          3.300600V         3.139900V            3.470000V
+3.6364ns          3.301100V         3.139900V            3.470000V
+3.8384ns          3.300500V         3.139900V            3.470000V
+4.0404ns          3.300200V         3.139900V            3.470000V
+4.2424ns          3.300000V         3.139900V            3.470000V
+4.4444ns          3.300000V         3.139900V            3.470000V
+4.6465ns          3.300000V         3.139900V            3.470000V
+4.8485ns          3.300000V         3.140000V            3.469900V
+5.0505ns          3.300000V         3.140800V            3.469900V
+5.2525ns          3.300000V         3.141300V            3.469900V
+5.4545ns          3.299900V         3.140700V            3.469900V
+5.6566ns          3.299900V         3.140400V            3.469900V
+5.8586ns          3.299900V         3.140200V            3.469900V
+6.0606ns          3.299900V         3.140000V            3.469900V
+6.2626ns          3.299900V         3.140000V            3.469900V
+6.4646ns          3.299900V         3.140000V            3.469900V
+6.6667ns          3.299900V         3.140000V            3.469900V
+6.8687ns          3.299900V         3.140000V            3.469900V
+7.0707ns          3.299900V         3.139900V            3.469900V
+7.2727ns          3.299900V         3.139900V            3.470000V
+7.4747ns          3.299900V         3.139900V            3.470000V
+7.6768ns          3.299900V         3.139900V            3.470000V
+7.8788ns          3.299900V         3.139900V            3.470000V
+8.0808ns          3.299900V         3.139900V            3.470000V
+8.2828ns          3.299900V         3.139900V            3.470000V
+8.4848ns          3.299900V         3.139900V            3.470000V
+8.6869ns          3.299900V         3.139900V            3.470000V
+8.8889ns          3.299900V         3.139800V            3.470000V
+9.0909ns          3.299900V         3.139800V            3.470000V
+9.2929ns          3.299900V         3.139900V            3.470000V
+9.4949ns          3.299900V         3.139900V            3.470000V
+9.6970ns          3.299900V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.139900V            3.470000V
+11.7172ns         3.300000V         3.139900V            3.470000V
+11.9192ns         3.300000V         3.139900V            3.470000V
+12.1212ns         3.300000V         3.139900V            3.470000V
+12.3232ns         3.300000V         3.139900V            3.470000V
+12.5253ns         3.300000V         3.139900V            3.470000V
+12.7273ns         3.300000V         3.139900V            3.470000V
+12.9293ns         3.300000V         3.139900V            3.470000V
+13.1313ns         3.300000V         3.139900V            3.470000V
+13.3333ns         3.300000V         3.139900V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              4.225900uV        4.920300uV           3.956100uV
+0.2020ns          -0.116230mV       2.501000uV           -0.231630mV
+0.4040ns          -1.733400mV       5.664000uV           -6.571900mV
+0.6061ns          1.816900mV        -0.405040mV          0.151930V
+0.8081ns          0.105890V         -6.434700mV          0.334290V
+1.0101ns          0.246820V         13.033000mV          0.470790V
+1.2121ns          0.360950V         89.173000mV          0.542490V
+1.4141ns          0.454430V         0.176030V            0.572640V
+1.6162ns          0.508590V         0.271450V            0.582550V
+1.8182ns          0.534420V         0.353570V            0.588040V
+2.0202ns          0.543170V         0.429910V            0.588930V
+2.2222ns          0.549780V         0.484400V            0.588840V
+2.4242ns          0.550820V         0.517300V            0.590870V
+2.6263ns          0.551300V         0.536250V            0.553540V
+2.8283ns          0.551520V         0.543010V            0.497470V
+3.0303ns          0.551620V         0.548720V            0.468060V
+3.2323ns          0.551660V         0.549820V            0.453000V
+3.4343ns          0.558640V         0.550520V            0.446500V
+3.6364ns          0.508640V         0.550950V            0.442330V
+3.8384ns          0.463860V         0.551240V            0.440380V
+4.0404ns          0.438900V         0.551370V            0.438930V
+4.2424ns          0.425590V         0.551450V            0.438730V
+4.4444ns          0.417880V         0.551520V            0.438850V
+4.6465ns          0.413990V         0.551560V            0.439830V
+4.8485ns          0.411950V         0.551690V            0.441070V
+5.0505ns          0.411060V         0.558950V            0.443300V
+5.2525ns          0.410360V         0.519020V            0.446000V
+5.4545ns          0.410640V         0.480460V            0.448850V
+5.6566ns          0.411100V         0.455460V            0.451660V
+5.8586ns          0.412570V         0.440580V            0.454380V
+6.0606ns          0.414210V         0.430510V            0.456880V
+6.2626ns          0.416980V         0.426080V            0.459280V
+6.4646ns          0.420210V         0.423650V            0.461440V
+6.6667ns          0.423660V         0.422350V            0.463510V
+6.8687ns          0.426990V         0.421790V            0.465350V
+7.0707ns          0.430100V         0.421350V            0.467110V
+7.2727ns          0.433090V         0.421520V            0.468670V
+7.4747ns          0.435900V         0.421800V            0.470160V
+7.6768ns          0.438640V         0.422560V            0.471470V
+7.8788ns          0.441270V         0.423400V            0.472730V
+8.0808ns          0.443800V         0.425080V            0.473840V
+8.2828ns          0.446130V         0.426920V            0.474900V
+8.4848ns          0.448370V         0.429830V            0.475830V
+8.6869ns          0.450420V         0.433230V            0.476730V
+8.8889ns          0.452380V         0.436930V            0.477510V
+9.0909ns          0.454180V         0.440610V            0.478270V
+9.2929ns          0.455900V         0.444280V            0.478930V
+9.4949ns          0.457470V         0.447610V            0.479560V
+9.6970ns          0.458970V         0.450880V            0.480120V
+9.8990ns          0.460340V         0.453950V            0.480650V
+10.1010ns         0.462260V         0.458380V            0.481335V
+10.3030ns         0.464000V         0.462500V            0.481950V
+10.5051ns         0.465050V         0.464970V            0.482320V
+10.7071ns         0.466050V         0.467390V            0.482650V
+10.9091ns         0.466960V         0.469580V            0.482960V
+11.1111ns         0.467830V         0.471720V            0.483240V
+11.3131ns         0.468630V         0.473660V            0.483500V
+11.5152ns         0.469380V         0.475550V            0.483730V
+11.7172ns         0.470080V         0.477260V            0.483950V
+11.9192ns         0.470740V         0.478940V            0.484140V
+12.1212ns         0.471340V         0.480450V            0.484330V
+12.3232ns         0.471910V         0.481930V            0.484490V
+12.5253ns         0.472440V         0.483270V            0.484640V
+12.7273ns         0.472930V         0.484580V            0.484780V
+12.9293ns         0.473390V         0.485750V            0.484900V
+13.1313ns         0.473820V         0.486910V            0.485020V
+13.3333ns         0.474220V         0.487950V            0.485120V
+13.5354ns         0.474590V         0.488970V            0.485220V
+13.7374ns         0.474940V         0.489880V            0.485310V
+13.9394ns         0.475260V         0.490780V            0.485390V
+14.1414ns         0.475560V         0.491590V            0.485460V
+14.3434ns         0.475840V         0.492380V            0.485530V
+14.5455ns         0.476100V         0.493090V            0.485590V
+14.7475ns         0.476340V         0.493790V            0.485640V
+14.9495ns         0.476570V         0.494420V            0.485700V
+15.1515ns         0.476780V         0.495030V            0.485740V
+15.3535ns         0.476970V         0.495580V            0.485790V
+15.5556ns         0.477160V         0.496120V            0.485820V
+15.7576ns         0.477330V         0.496610V            0.485860V
+15.9596ns         0.477490V         0.497090V            0.485890V
+16.1616ns         0.477630V         0.497510V            0.485920V
+16.3636ns         0.477770V         0.497930V            0.485950V
+16.5657ns         0.477890V         0.498290V            0.485980V
+16.7677ns         0.478010V         0.498640V            0.486000V
+16.9697ns         0.478120V         0.498990V            0.486020V
+17.1717ns         0.478230V         0.499340V            0.486040V
+17.3737ns         0.478320V         0.499630V            0.486060V
+17.5758ns         0.478410V         0.499920V            0.486070V
+17.7778ns         0.478490V         0.500160V            0.486090V
+17.9798ns         0.478570V         0.500400V            0.486100V
+18.1818ns         0.478640V         0.500630V            0.486110V
+18.3838ns         0.478710V         0.500870V            0.486120V
+18.5859ns         0.478770V         0.501070V            0.486130V
+18.7879ns         0.478830V         0.501260V            0.486140V
+18.9899ns         0.478880V         0.501430V            0.486150V
+19.1919ns         0.478930V         0.501590V            0.486160V
+19.3939ns         0.478980V         0.501750V            0.486170V
+19.5960ns         0.479020V         0.501910V            0.486170V
+19.7980ns         0.479060V         0.502040V            0.486180V
+20.0000ns         0.479100V         0.502180V            0.486180V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.479590V         0.504150V            0.486240V
+0.2020ns          0.479620V         0.504110V            0.490470V
+0.4040ns          0.474660V         0.515850V            0.338690V
+0.6061ns          0.260970V         0.518810V            49.227000mV
+0.8081ns          57.693000mV       0.442430V            5.358900mV
+1.0101ns          10.006000mV       0.270560V            1.610600mV
+1.2121ns          3.219300mV        0.116620V            0.420340mV
+1.4141ns          1.539600mV        28.455000mV          0.168590mV
+1.6162ns          0.544500mV        9.235500mV           63.243000uV
+1.8182ns          0.242750mV        4.555900mV           28.107000uV
+2.0202ns          0.152510mV        2.530000mV           3.232400uV
+2.2222ns          71.354000uV       1.674500mV           0.754660uV
+2.4242ns          30.528000uV       0.925740mV           -0.544570mV
+2.6263ns          17.219000uV       0.496800mV           -0.223670mV
+2.8283ns          7.642900uV        0.286310mV           -18.013000uV
+3.0303ns          2.754100uV        0.206810mV           -16.664000uV
+3.2323ns          3.719000uV        0.129010mV           -14.948000uV
+3.4343ns          -0.126320mV       73.076000uV          -9.356000uV
+3.6364ns          -0.242850mV       44.601000uV          -11.098000uV
+3.8384ns          -32.574000uV      27.309000uV          -9.946200uV
+4.0404ns          3.566200uV        14.959000uV          -9.483100uV
+4.2424ns          -5.306100uV       8.251900uV           -8.932600uV
+4.4444ns          -13.750000uV      4.915800uV           -8.381600uV
+4.6465ns          10.940000uV       2.652800uV           -7.820100uV
+4.8485ns          18.035000uV       -0.108180mV          -7.265300uV
+5.0505ns          2.807200uV        0.153640mV           -6.819000uV
+5.2525ns          2.502100uV        -0.230170mV          -6.373400uV
+5.4545ns          3.131600uV        -97.756000uV         -5.936700uV
+5.6566ns          2.983900uV        -12.193000uV         -5.505100uV
+5.8586ns          2.947300uV        25.147000uV          -5.155800uV
+6.0606ns          3.185500uV        13.918000uV          -4.806500uV
+6.2626ns          3.361600uV        13.732000uV          -4.457800uV
+6.4646ns          3.383800uV        15.275000uV          -4.112200uV
+6.6667ns          3.430500uV        14.174000uV          -3.816000uV
+6.8687ns          3.538200uV        13.495000uV          -3.520100uV
+7.0707ns          3.619900uV        13.582000uV          -3.230000uV
+7.2727ns          3.637500uV        13.501000uV          -2.942000uV
+7.4747ns          3.665100uV        13.116000uV          -2.688300uV
+7.6768ns          3.717300uV        12.820000uV          -2.435300uV
+7.8788ns          3.759700uV        12.684000uV          -2.191800uV
+8.0808ns          3.777800uV        12.528000uV          -1.949700uV
+8.2828ns          3.800700uV        12.338000uV          -1.731900uV
+8.4848ns          3.835100uV        12.144000uV          -1.514700uV
+8.6869ns          3.864700uV        11.942000uV          -1.308300uV
+8.8889ns          3.882800uV        11.757000uV          -1.103000uV
+9.0909ns          3.903100uV        11.601000uV          -0.916190uV
+9.2929ns          3.928900uV        11.419000uV          -0.730020uV
+9.4949ns          3.951900uV        11.189000uV          -0.554530uV
+9.6970ns          3.968200uV        10.989000uV          -0.379920uV
+9.8990ns          3.985700uV        10.842000uV          -0.219880uV
+10.1010ns         4.015950uV        10.553500uV          12.615000nV
+10.3030ns         4.039500uV        10.248000uV          0.231740uV
+10.5051ns         4.054400uV        10.116000uV          0.368100uV
+10.7071ns         4.071500uV        9.956800uV           0.504010uV
+10.9091ns         4.087100uV        9.748000uV           0.632480uV
+11.1111ns         4.098800uV        9.573200uV           0.760290uV
+11.3131ns         4.111100uV        9.460300uV           0.877400uV
+11.5152ns         4.125100uV        9.320800uV           0.994070uV
+11.7172ns         4.137800uV        9.133200uV           1.103600uV
+11.9192ns         4.147200uV        8.978700uV           1.212600uV
+12.1212ns         4.157100uV        8.884300uV           1.313000uV
+12.3232ns         4.168500uV        8.764100uV           1.413100uV
+12.5253ns         4.178700uV        8.597200uV           1.506700uV
+12.7273ns         4.186000uV        8.456400uV           1.599900uV
+12.9293ns         4.193900uV        8.362900uV           1.686000uV
+13.1313ns         4.203100uV        8.269500uV           1.771700uV
+13.3333ns         4.211200uV        8.176000uV           1.851800uV
+13.5354ns         4.216800uV        8.065600uV           1.931600uV
+13.7374ns         4.222900uV        7.924500uV           2.005300uV
+13.9394ns         4.230300uV        7.808100uV           2.078800uV
+14.1414ns         4.236700uV        7.736300uV           2.147500uV
+14.3434ns         4.240800uV        7.664500uV           2.215800uV
+14.5455ns         4.245400uV        7.592700uV           2.279000uV
+14.7475ns         4.251200uV        7.503700uV           2.342000uV
+14.9495ns         4.256200uV        7.383500uV           2.400800uV
+15.1515ns         4.259000uV        7.286500uV           2.459400uV
+15.3535ns         4.262400uV        7.231700uV           2.513600uV
+15.5556ns         4.267000uV        7.176900uV           2.567700uV
+15.7576ns         4.270800uV        7.122100uV           2.618100uV
+15.9596ns         4.272600uV        7.049900uV           2.668300uV
+16.1616ns         4.274900uV        6.946400uV           2.714800uV
+16.3636ns         4.278400uV        6.865000uV           2.761200uV
+16.5657ns         4.281200uV        6.823600uV           2.804400uV
+16.7677ns         4.282300uV        6.782200uV           2.847500uV
+16.9697ns         4.283800uV        6.740700uV           2.887400uV
+17.1717ns         4.286400uV        6.682100uV           2.927100uV
+17.3737ns         4.288400uV        6.592100uV           2.964200uV
+17.5758ns         4.288700uV        6.523200uV           3.001200uV
+17.7778ns         4.289500uV        6.492500uV           3.035400uV
+17.9798ns         4.291500uV        6.461700uV           3.069500uV
+18.1818ns         4.292800uV        6.430900uV           3.101400uV
+18.3838ns         4.292600uV        6.383000uV           3.133100uV
+18.5859ns         4.292900uV        6.304200uV           3.162500uV
+18.7879ns         4.294300uV        6.245400uV           3.191700uV
+18.9899ns         4.295100uV        6.223200uV           3.219100uV
+19.1919ns         4.294400uV        6.200900uV           3.246200uV
+19.3939ns         4.294300uV        6.178600uV           3.270600uV
+19.5960ns         4.295200uV        6.139500uV           3.294900uV
+19.7980ns         4.295400uV        6.069700uV           3.319200uV
+20.0000ns         4.294000uV        6.076600uV           3.343600uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468600V
+0.4040ns          3.300900V         3.139100V            3.483300V
+0.6061ns          3.304400V         3.140100V            3.272000V
+0.8081ns          3.179500V         3.145900V            3.030300V
+1.0101ns          3.015400V         3.136300V            2.907000V
+1.2121ns          2.895000V         3.095000V            2.856700V
+1.4141ns          2.821600V         2.995500V            2.837500V
+1.6162ns          2.781500V         2.910100V            2.829200V
+1.8182ns          2.760300V         2.834600V            2.826700V
+2.0202ns          2.751400V         2.769700V            2.825700V
+2.2222ns          2.745500V         2.722000V            2.826100V
+2.4242ns          2.743500V         2.688600V            2.830900V
+2.6263ns          2.743000V         2.667400V            2.878100V
+2.8283ns          2.742800V         2.654200V            2.895900V
+3.0303ns          2.742900V         2.645000V            2.900000V
+3.2323ns          2.743200V         2.639400V            2.902500V
+3.4343ns          2.756300V         2.636600V            2.904500V
+3.6364ns          2.776700V         2.635200V            2.906500V
+3.8384ns          2.790100V         2.634000V            2.908200V
+4.0404ns          2.792600V         2.633800V            2.909800V
+4.2424ns          2.793100V         2.633700V            2.911300V
+4.4444ns          2.793600V         2.633900V            2.912900V
+4.6465ns          2.793500V         2.634100V            2.914200V
+4.8485ns          2.793500V         2.636300V            2.915600V
+5.0505ns          2.793500V         2.635700V            2.916900V
+5.2525ns          2.793500V         2.642300V            2.918100V
+5.4545ns          2.793500V         2.652700V            2.919300V
+5.6566ns          2.793400V         2.656300V            2.920400V
+5.8586ns          2.793400V         2.655900V            2.921400V
+6.0606ns          2.793300V         2.655100V            2.922500V
+6.2626ns          2.793200V         2.654600V            2.923500V
+6.4646ns          2.793100V         2.654000V            2.924400V
+6.6667ns          2.793000V         2.653400V            2.925300V
+6.8687ns          2.792900V         2.652800V            2.926200V
+7.0707ns          2.792800V         2.652200V            2.927100V
+7.2727ns          2.792700V         2.651700V            2.928000V
+7.4747ns          2.792600V         2.651100V            2.928900V
+7.6768ns          2.792500V         2.650500V            2.929700V
+7.8788ns          2.792300V         2.650000V            2.930600V
+8.0808ns          2.792200V         2.649500V            2.931500V
+8.2828ns          2.792100V         2.648900V            2.932300V
+8.4848ns          2.791900V         2.648400V            2.933200V
+8.6869ns          2.791800V         2.647900V            2.934100V
+8.8889ns          2.791600V         2.647400V            2.935000V
+9.0909ns          2.791500V         2.647000V            2.935800V
+9.2929ns          2.791300V         2.646500V            2.936600V
+9.4949ns          2.791200V         2.646000V            2.937400V
+9.6970ns          2.791000V         2.645600V            2.938200V
+9.8990ns          2.790900V         2.645100V            2.939000V
+10.1010ns         2.790650V         2.644500V            2.940050V
+10.3030ns         2.790400V         2.643900V            2.941100V
+10.5051ns         2.790200V         2.643500V            2.941700V
+10.7071ns         2.790100V         2.643100V            2.942400V
+10.9091ns         2.789900V         2.642700V            2.943000V
+11.1111ns         2.789700V         2.642400V            2.943600V
+11.3131ns         2.789600V         2.642000V            2.944100V
+11.5152ns         2.789400V         2.641600V            2.944700V
+11.7172ns         2.789200V         2.641300V            2.945200V
+11.9192ns         2.789100V         2.641000V            2.945700V
+12.1212ns         2.788900V         2.640600V            2.946200V
+12.3232ns         2.788700V         2.640300V            2.946700V
+12.5253ns         2.788600V         2.640000V            2.947100V
+12.7273ns         2.788400V         2.639700V            2.947600V
+12.9293ns         2.788200V         2.639400V            2.948000V
+13.1313ns         2.788000V         2.639100V            2.948400V
+13.3333ns         2.787900V         2.638900V            2.948800V
+13.5354ns         2.787700V         2.638600V            2.949200V
+13.7374ns         2.787500V         2.638300V            2.949600V
+13.9394ns         2.787400V         2.638000V            2.949900V
+14.1414ns         2.787200V         2.637800V            2.950300V
+14.3434ns         2.787000V         2.637500V            2.950600V
+14.5455ns         2.786900V         2.637300V            2.950900V
+14.7475ns         2.786700V         2.637100V            2.951200V
+14.9495ns         2.786500V         2.636800V            2.951500V
+15.1515ns         2.786400V         2.636600V            2.951800V
+15.3535ns         2.786200V         2.636400V            2.952100V
+15.5556ns         2.786100V         2.636100V            2.952400V
+15.7576ns         2.785900V         2.635900V            2.952600V
+15.9596ns         2.785800V         2.635700V            2.952900V
+16.1616ns         2.785600V         2.635500V            2.953100V
+16.3636ns         2.785500V         2.635300V            2.953400V
+16.5657ns         2.785300V         2.635100V            2.953600V
+16.7677ns         2.785200V         2.634900V            2.953800V
+16.9697ns         2.785000V         2.634700V            2.954000V
+17.1717ns         2.784900V         2.634500V            2.954200V
+17.3737ns         2.784800V         2.634300V            2.954400V
+17.5758ns         2.784600V         2.634200V            2.954600V
+17.7778ns         2.784500V         2.634000V            2.954800V
+17.9798ns         2.784400V         2.633800V            2.955000V
+18.1818ns         2.784300V         2.633600V            2.955100V
+18.3838ns         2.784200V         2.633500V            2.955300V
+18.5859ns         2.784100V         2.633300V            2.955500V
+18.7879ns         2.784000V         2.633100V            2.955600V
+18.9899ns         2.783900V         2.633000V            2.955800V
+19.1919ns         2.783800V         2.632800V            2.955900V
+19.3939ns         2.783700V         2.632700V            2.956100V
+19.5960ns         2.783600V         2.632500V            2.956200V
+19.7980ns         2.783600V         2.632400V            2.956300V
+20.0000ns         2.783500V         2.632200V            2.956500V
+|  
+| End [Model] lvt330s040aaaaaaaaio
+|************************************************************************
+[Model]           lvt330s160aaaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.800000V
+Vinh =            2.000000V
+Vmeas =           1.650000V
+Cref =            0.0F
+Rref =            1.000000M
+Vref =            0.0V
+C_comp            2.68pF          2.54pF             2.92pF
+|  
+|  
+[Temperature Range]     25.000000         0.105000k            -40.000000
+[Voltage Range]         3.300000V         3.140000V            3.470000V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -50.584550mA      -43.999960mA         -54.623576mA
+  -3.20    -50.404450mA      -43.837800mA         -54.427552mA
+  -3.10    -50.224350mA      -43.675640mA         -54.231528mA
+  -3.00    -50.044250mA      -43.513480mA         -54.035504mA
+  -2.90    -49.864150mA      -43.351320mA         -53.839480mA
+  -2.80    -49.684050mA      -43.189160mA         -53.643456mA
+  -2.70    -49.503950mA      -43.027000mA         -53.447432mA
+  -2.60    -49.323850mA      -42.864840mA         -53.251408mA
+  -2.50    -49.143750mA      -42.702680mA         -53.055384mA
+  -2.40    -48.963650mA      -42.540520mA         -52.859360mA
+  -2.30    -48.783550mA      -42.378360mA         -52.663336mA
+  -2.20    -48.603450mA      -42.216200mA         -52.467312mA
+  -2.10    -48.423350mA      -42.054040mA         -52.271288mA
+  -2.00    -48.243250mA      -41.891880mA         -52.075264mA
+  -1.90    -48.063150mA      -41.729720mA         -51.879240mA
+  -1.80    -47.883050mA      -41.567560mA         -51.683216mA
+  -1.70    -47.702950mA      -41.405400mA         -51.487192mA
+  -1.60    -47.522850mA      -41.243240mA         -51.291168mA
+  -1.50    -47.342750mA      -41.081080mA         -51.095144mA
+  -1.40    -47.162650mA      -40.960000mA         -50.899120mA
+  -1.30    -46.982550mA      -40.310000mA         -50.703096mA
+  -1.20    -46.802450mA      -39.409000mA         -50.507072mA
+  -1.10    -46.622350mA      -38.410000mA         -50.311048mA
+  -1.00    -46.442250mA      -37.323000mA         -50.115024mA
+  -0.90    -46.262150mA      -36.180000mA         -49.919000mA
+  -0.80    -46.082050mA      -35.076000mA         -49.327000mA
+  -0.70    -45.748900mA      -34.427000mA         -47.994000mA
+  -0.60    -42.249200mA      -34.203200mA         -45.776900mA
+  -0.50    -36.169470mA      -30.752860mA         -40.603750mA
+  -0.40    -29.014551mA      -24.879886mA         -32.919898mA
+  -0.30    -21.670346mA      -18.677585mA         -24.687602mA
+  -0.20    -14.338705mA      -12.435585mA         -16.367748mA
+  -0.10    -7.093292mA       -6.195266mA          -8.095791mA
+  0.00    27.190000nA       25.680000nA          31.680000nA
+  0.10    6.587285mA        5.878497mA           7.387890mA
+  0.20    12.314175mA       11.156186mA          13.529180mA
+  0.30    17.106166mA       15.766175mA          18.285171mA
+  0.40    20.907156mA       19.661164mA          21.673162mA
+  0.50    23.747146mA       22.813153mA          23.968152mA
+  0.60    25.783136mA       25.234142mA          25.549143mA
+  0.70    27.212126mA       27.008131mA          26.699134mA
+  0.80    28.206116mA       28.280120mA          27.588124mA
+  0.90    28.917106mA       29.203109mA          28.308115mA
+  1.00    29.453095mA       29.892098mA          28.908106mA
+  1.10    29.875084mA       30.426087mA          29.398096mA
+  1.20    30.221074mA       30.854076mA          29.770086mA
+  1.30    30.513063mA       31.208065mA          30.064075mA
+  1.40    30.767053mA       31.507054mA          30.315065mA
+  1.50    30.993042mA       31.766043mA          30.542055mA
+  1.60    31.203032mA       31.995032mA          30.762044mA
+  1.70    31.414021mA       32.204021mA          30.983034mA
+  1.80    31.648011mA       32.407010mA          31.201024mA
+  1.90    31.903000mA       32.633999mA          31.408013mA
+  2.00    32.157989mA       32.912988mA          31.601003mA
+  2.10    32.398979mA       33.235977mA          31.780993mA
+  2.20    32.620968mA       33.562966mA          31.951982mA
+  2.30    32.826958mA       33.870954mA          32.113972mA
+  2.40    33.017947mA       34.153943mA          32.268961mA
+  2.50    33.197936mA       34.411932mA          32.419951mA
+  2.60    33.368926mA       34.647921mA          32.567941mA
+  2.70    33.532915mA       34.866910mA          32.714930mA
+  2.80    33.693904mA       35.070899mA          32.864920mA
+  2.90    33.851894mA       35.264888mA          33.017909mA
+  3.00    34.012883mA       35.450877mA          33.177899mA
+  3.10    34.176872mA       35.632864mA          33.347889mA
+  3.20    34.349862mA       35.813747mA          33.531878mA
+  3.30    34.531848mA       35.996379mA          33.730868mA
+  3.40    34.729725mA       36.157497mA          33.951857mA
+  3.50    34.942986mA       36.297102mA          34.196843mA
+  3.60    35.117958mA       36.436708mA          34.470599mA
+  3.70    35.251602mA       36.576313mA          34.772212mA
+  3.80    35.385246mA       36.715919mA          34.904053mA
+  3.90    35.518890mA       36.855525mA          35.035893mA
+  4.00    35.652534mA       36.995130mA          35.167734mA
+  4.10    35.786178mA       37.134736mA          35.299574mA
+  4.20    35.919822mA       37.274341mA          35.431414mA
+  4.30    36.053466mA       37.413947mA          35.563255mA
+  4.40    36.187110mA       37.553553mA          35.695095mA
+  4.50    36.320754mA       37.693158mA          35.826936mA
+  4.60    36.454398mA       37.832764mA          35.958776mA
+  4.70    36.588042mA       37.972369mA          36.090616mA
+  4.80    36.721686mA       38.111975mA          36.222457mA
+  4.90    36.855330mA       38.251581mA          36.354297mA
+  5.00    36.988974mA       38.391186mA          36.486138mA
+  5.10    37.122618mA       38.530792mA          36.617978mA
+  5.20    37.256262mA       38.670397mA          36.749818mA
+  5.30    37.389906mA       38.810003mA          36.881659mA
+  5.40    37.523550mA       38.949609mA          37.013499mA
+  5.50    37.657194mA       39.089214mA          37.145340mA
+  5.60    37.790838mA       39.228820mA          37.277180mA
+  5.70    37.924482mA       39.368425mA          37.409020mA
+  5.80    38.058126mA       39.508031mA          37.540861mA
+  5.90    38.191770mA       39.647637mA          37.672701mA
+  6.00    38.325414mA       39.787242mA          37.804542mA
+  6.10    38.459058mA       39.926848mA          37.936382mA
+  6.20    38.592702mA       40.066453mA          38.068222mA
+  6.30    38.726346mA       40.206059mA          38.200063mA
+  6.40    38.859990mA       40.345665mA          38.331903mA
+  6.50    38.993634mA       40.485270mA          38.463744mA
+  6.60    39.127278mA       40.624876mA          38.595584mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    66.669757mA       87.094613mA          92.797733mA
+  -3.20    66.440741mA       86.767866mA          92.515330mA
+  -3.10    66.211726mA       86.441119mA          92.232928mA
+  -3.00    65.982711mA       86.114372mA          91.950525mA
+  -2.90    65.753695mA       85.787625mA          91.668122mA
+  -2.80    65.524680mA       85.460878mA          91.385720mA
+  -2.70    65.295664mA       85.134131mA          91.103317mA
+  -2.60    65.066649mA       84.807384mA          90.820915mA
+  -2.50    64.837633mA       84.480636mA          90.538512mA
+  -2.40    64.608618mA       84.153889mA          90.256109mA
+  -2.30    64.379602mA       83.827142mA          89.973707mA
+  -2.20    64.150587mA       83.500395mA          89.691304mA
+  -2.10    63.921571mA       83.173648mA          89.408901mA
+  -2.00    63.692556mA       82.846901mA          89.126499mA
+  -1.90    63.463540mA       82.520154mA          88.844096mA
+  -1.80    63.234525mA       82.323794mA          88.561693mA
+  -1.70    63.005509mA       81.008819mA          88.279291mA
+  -1.60    62.776494mA       78.640845mA          87.996888mA
+  -1.50    62.547479mA       75.568869mA          87.714485mA
+  -1.40    62.318463mA       71.978893mA          87.432083mA
+  -1.30    62.089448mA       67.983917mA          87.149680mA
+  -1.20    61.860432mA       63.658940mA          86.867278mA
+  -1.10    61.631417mA       59.058962mA          86.584875mA
+  -1.00    61.402401mA       54.225984mA          80.067686mA
+  -0.90    61.173386mA       49.192006mA          71.275712mA
+  -0.80    54.621889mA       45.212027mA          61.996736mA
+  -0.70    47.050911mA       41.794048mA          52.900760mA
+  -0.60    39.442932mA       35.550069mA          44.185783mA
+  -0.50    32.215954mA       29.164089mA          36.006805mA
+  -0.40    25.419974mA       23.007107mA          28.393828mA
+  -0.30    17.101700mA       15.824500mA          19.002300mA
+  -0.20    12.464986mA       11.277815mA          13.918820mA
+  -0.10    6.164125mA        5.580948mA           6.877969mA
+  0.00    -18.490000nA      -17.070000nA         -20.440000nA
+  0.10    -5.904938mA       -5.394928mA          -6.530140mA
+  0.20    -11.454128mA      -10.553116mA         -12.558129mA
+  0.30    -16.640117mA      -15.473105mA         -18.069119mA
+  0.40    -21.457106mA      -20.150094mA         -23.046108mA
+  0.50    -25.896096mA      -24.583083mA         -27.475098mA
+  0.60    -29.949085mA      -28.768072mA         -31.336087mA
+  0.70    -33.609074mA      -32.702061mA         -34.612077mA
+  0.80    -36.868064mA      -36.383050mA         -37.284067mA
+  0.90    -39.717053mA      -39.806039mA         -39.346056mA
+  1.00    -42.147042mA      -42.970028mA         -40.889046mA
+  1.10    -44.149032mA      -45.870017mA         -42.089035mA
+  1.20    -45.748021mA      -48.504006mA         -43.060025mA
+  1.30    -47.028011mA      -50.866995mA         -43.869015mA
+  1.40    -48.080000mA      -52.957984mA         -44.561004mA
+  1.50    -48.964989mA      -54.770973mA         -45.164994mA
+  1.60    -49.722979mA      -56.304962mA         -45.700984mA
+  1.70    -50.383968mA      -57.595951mA         -46.184973mA
+  1.80    -50.967958mA      -58.692940mA         -46.625963mA
+  1.90    -51.489947mA      -59.638929mA         -47.033952mA
+  2.00    -51.962937mA      -60.463918mA         -47.412942mA
+  2.10    -52.394926mA      -61.192907mA         -47.768932mA
+  2.20    -52.791916mA      -61.842896mA         -48.104921mA
+  2.30    -53.159905mA      -62.426885mA         -48.424911mA
+  2.40    -53.504894mA      -62.956874mA         -48.730901mA
+  2.50    -53.827884mA      -63.439863mA         -49.025891mA
+  2.60    -54.132874mA      -63.884852mA         -49.310882mA
+  2.70    -54.422864mA      -64.295841mA         -49.587873mA
+  2.80    -54.700854mA      -64.676830mA         -49.859863mA
+  2.90    -54.966844mA      -65.033819mA         -50.128854mA
+  3.00    -55.224834mA      -65.367808mA         -50.397845mA
+  3.10    -55.477825mA      -65.682796mA         -50.669835mA
+  3.20    -55.727815mA      -65.980780mA         -50.947826mA
+  3.30    -55.978806mA      -66.265706mA         -51.235817mA
+  3.40    -56.233792mA      -66.536956mA         -51.539808mA
+  3.50    -56.497705mA      -66.792873mA         -51.862798mA
+  3.60    -56.774346mA      -66.928560mA         -52.210786mA
+  3.70    -57.054551mA      -67.195337mA         -52.589679mA
+  3.80    -57.194470mA      -67.462113mA         -53.001555mA
+  3.90    -57.422477mA      -67.728890mA         -53.392977mA
+  4.00    -57.650484mA      -67.995667mA         -53.537857mA
+  4.10    -57.878491mA      -68.262444mA         -53.750052mA
+  4.20    -58.106498mA      -68.529220mA         -53.962246mA
+  4.30    -58.334506mA      -68.795997mA         -54.174441mA
+  4.40    -58.562513mA      -69.062774mA         -54.386636mA
+  4.50    -58.790520mA      -69.329550mA         -54.598830mA
+  4.60    -59.018527mA      -69.596327mA         -54.811025mA
+  4.70    -59.246534mA      -69.863104mA         -55.023219mA
+  4.80    -59.474541mA      -70.129881mA         -55.235414mA
+  4.90    -59.702548mA      -70.396657mA         -55.447608mA
+  5.00    -59.930555mA      -70.663434mA         -55.659803mA
+  5.10    -60.158563mA      -70.930211mA         -55.871997mA
+  5.20    -60.386570mA      -71.196988mA         -56.084192mA
+  5.30    -60.614577mA      -71.463764mA         -56.296387mA
+  5.40    -60.842584mA      -71.730541mA         -56.508581mA
+  5.50    -61.070591mA      -71.997318mA         -56.720776mA
+  5.60    -61.298598mA      -72.264094mA         -56.932970mA
+  5.70    -61.526605mA      -72.530871mA         -57.145165mA
+  5.80    -61.754612mA      -72.797648mA         -57.357359mA
+  5.90    -61.982620mA      -73.064425mA         -57.569554mA
+  6.00    -62.210627mA      -73.331201mA         -57.781748mA
+  6.10    -62.438634mA      -73.597978mA         -57.993943mA
+  6.20    -62.666641mA      -73.864755mA         -58.206138mA
+  6.30    -62.894648mA      -74.131531mA         -58.418332mA
+  6.40    -63.122655mA      -74.398308mA         -58.630527mA
+  6.50    -63.350662mA      -74.665085mA         -58.842721mA
+  6.55    -63.464666mA      -74.798473mA         -58.948819mA
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.966230A        -0.950520A           -0.981210A
+  -3.22    -0.926890A        -0.911380A           -0.941720A
+  -3.14    -0.887580A        -0.872280A           -0.902250A
+  -3.06    -0.848310A        -0.833240A           -0.862810A
+  -2.98    -0.809090A        -0.794250A           -0.823400A
+  -2.90    -0.769910A        -0.755320A           -0.784030A
+  -2.82    -0.730780A        -0.716470A           -0.744690A
+  -2.74    -0.691720A        -0.677700A           -0.705410A
+  -2.66    -0.652720A        -0.639020A           -0.666170A
+  -2.58    -0.613810A        -0.600460A           -0.627000A
+  -2.50    -0.574990A        -0.562020A           -0.587900A
+  -2.42    -0.536290A        -0.523740A           -0.548880A
+  -2.34    -0.497720A        -0.485650A           -0.509970A
+  -2.26    -0.459320A        -0.447780A           -0.471180A
+  -2.18    -0.421130A        -0.410210A           -0.432540A
+  -2.10    -0.383220A        -0.373010A           -0.394110A
+  -2.02    -0.345660A        -0.336310A           -0.355940A
+  -1.94    -0.308600A        -0.300310A           -0.318140A
+  -1.86    -0.272270A        -0.265320A           -0.280870A
+  -1.78    -0.237080A        -0.231900A           -0.244460A
+  -1.70    -0.203840A        -0.201040A           -0.209550A
+  -1.62    -0.174180A        -0.174390A           -0.177650A
+  -1.54    -0.150480A        -0.153310A           -0.151870A
+  -1.46    -0.132430A        -0.136590A           -0.133020A
+  -1.38    -0.116630A        -0.121710A           -0.116640A
+  -1.30    -0.101400A        -0.107420A           -0.100700A
+  -1.22    -86.415000mA      -93.408000mA         -84.973000mA
+  -1.14    -71.663000mA      -79.635000mA         -69.550000mA
+  -1.06    -57.217000mA      -66.144000mA         -54.650000mA
+  -0.98    -43.212000mA      -53.022000mA         -40.867000mA
+  -0.90    -29.917000mA      -40.404000mA         -29.601000mA
+  -0.82    -17.964000mA      -28.506000mA         -21.040000mA
+  -0.74    -8.811200mA       -17.674000mA         -13.572000mA
+  -0.66    -3.584800mA       -8.562700mA          -7.150700mA
+  -0.58    -1.078100mA       -2.529400mA          -2.551200mA
+  -0.50    -0.216530mA       -0.395140mA          -0.485250mA
+  -0.42    -33.488000uA      -47.466000uA         -54.573000uA
+  -0.34    -4.479600uA       -6.180600uA          -4.703900uA
+  -0.26    -0.684160uA       -1.044200uA          -0.515460uA
+  -0.18    -0.256300uA       -0.340620uA          -0.232000uA
+  -0.10    -0.207580uA       -0.233950uA          -0.209060uA
+  -0.02    -0.196470uA       -0.211740uA          -0.200850uA
+  0.06    -0.188630uA       -0.201350uA          -0.193360uA
+  0.14    -0.180980uA       -0.192340uA          -0.185900uA
+  0.22    -0.173340uA       -0.183540uA          -0.178450uA
+  0.30    -0.165690uA       -0.174750uA          -0.171010uA
+  0.38    -0.158000uA       -0.165960uA          -0.163570uA
+  0.46    -0.150270uA       -0.157150uA          -0.156120uA
+  0.54    -0.142440uA       -0.148340uA          -0.148680uA
+  0.62    -0.134460uA       -0.139540uA          -0.141240uA
+  0.70    -0.126310uA       -0.130730uA          -0.133790uA
+  0.78    -0.118040uA       -0.121920uA          -0.126340uA
+  0.86    -0.109700uA       -0.113110uA          -0.118880uA
+  0.94    -0.101320uA       -0.104310uA          -0.111370uA
+  1.02    -92.914000nA      -95.498000nA         -0.103710uA
+  1.10    -84.495000nA      -86.692000nA         -95.808000nA
+  1.18    -76.063000nA      -77.885000nA         -87.731000nA
+  1.26    -67.624000nA      -69.077000nA         -79.564000nA
+  1.34    -59.178000nA      -60.269000nA         -71.346000nA
+  1.42    -50.727000nA      -51.460000nA         -63.100000nA
+  1.50    -42.271000nA      -42.651000nA         -54.834000nA
+  1.58    -33.812000nA      -33.840000nA         -46.556000nA
+  1.66    -25.349000nA      -25.028000nA         -38.268000nA
+  1.74    -16.884000nA      -16.215000nA         -29.974000nA
+  1.82    -8.415500nA       -7.400800nA          -21.675000nA
+  1.90    55.201000pA       1.415400nA           -13.371000nA
+  1.98    8.528300nA        10.233000nA          -5.065000nA
+  2.06    17.004000nA       19.054000nA          3.244100nA
+  2.14    25.482000nA       27.876000nA          11.555000nA
+  2.22    33.962000nA       36.702000nA          19.868000nA
+  2.30    42.445000nA       45.532000nA          28.183000nA
+  2.38    50.931000nA       54.365000nA          36.499000nA
+  2.46    59.420000nA       63.204000nA          44.816000nA
+  2.54    67.912000nA       72.050000nA          53.135000nA
+  2.62    76.408000nA       80.904000nA          61.455000nA
+  2.70    84.908000nA       89.768000nA          69.776000nA
+  2.78    93.413000nA       98.647000nA          78.099000nA
+  2.86    0.101920uA        0.107550uA           86.423000nA
+  2.94    0.110440uA        0.116470uA           94.749000nA
+  3.02    0.118970uA        0.125470uA           0.103080uA
+  3.10    0.127510uA        0.135560uA           0.111410uA
+  3.18    0.136060uA        0.207650uA           0.119740uA
+  3.26    0.144710uA        0.665780uA           0.128080uA
+  3.30    0.152020uA        1.620700uA           0.132250uA
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    1.922000uA        1.691900uA           2.178700uA
+  -3.26    1.903700uA        1.676200uA           2.158100uA
+  -3.22    1.885700uA        1.660600uA           2.137700uA
+  -3.18    1.867800uA        1.645300uA           2.117600uA
+  -3.14    1.850200uA        1.630100uA           2.097600uA
+  -3.10    1.832700uA        1.615000uA           2.077900uA
+  -3.06    1.815500uA        1.600200uA           2.058300uA
+  -3.02    1.798400uA        1.585500uA           2.039000uA
+  -2.98    1.781600uA        1.570900uA           2.019900uA
+  -2.94    1.764900uA        1.556500uA           2.001000uA
+  -2.90    1.748500uA        1.542300uA           1.982300uA
+  -2.86    1.732200uA        1.528200uA           1.963900uA
+  -2.82    1.716100uA        1.514300uA           1.945600uA
+  -2.78    1.700200uA        1.500500uA           1.927500uA
+  -2.74    1.684500uA        1.486900uA           1.909700uA
+  -2.70    1.668900uA        1.473400uA           1.892000uA
+  -2.66    1.653600uA        1.460100uA           1.874600uA
+  -2.62    1.638400uA        1.446900uA           1.857300uA
+  -2.58    1.623400uA        1.433900uA           1.840300uA
+  -2.54    1.608600uA        1.421000uA           1.823400uA
+  -2.50    1.594000uA        1.408300uA           1.806800uA
+  -2.46    1.579600uA        1.395600uA           1.790400uA
+  -2.42    1.565300uA        1.383200uA           1.774100uA
+  -2.38    1.551200uA        1.370800uA           1.758100uA
+  -2.34    1.537200uA        1.358700uA           1.742200uA
+  -2.30    1.523500uA        1.346600uA           1.726600uA
+  -2.26    1.509900uA        1.334700uA           1.711100uA
+  -2.22    1.496500uA        1.322900uA           1.695800uA
+  -2.18    1.483200uA        1.311200uA           1.680700uA
+  -2.14    1.470100uA        1.299600uA           1.665900uA
+  -2.10    1.457200uA        1.288200uA           1.651200uA
+  -2.06    1.444400uA        1.276900uA           1.636600uA
+  -2.02    1.431800uA        1.265700uA           1.622300uA
+  -1.98    1.419300uA        1.254700uA           1.608200uA
+  -1.94    1.407000uA        1.243700uA           1.594200uA
+  -1.90    1.394800uA        1.232900uA           1.580400uA
+  -1.86    1.382800uA        1.222200uA           1.566800uA
+  -1.82    1.370900uA        1.211600uA           1.553400uA
+  -1.78    1.359200uA        1.201100uA           1.540100uA
+  -1.74    1.347600uA        1.190700uA           1.527000uA
+  -1.70    1.336200uA        1.180500uA           1.514100uA
+  -1.66    1.324900uA        1.170300uA           1.501400uA
+  -1.62    1.313700uA        1.160200uA           1.488800uA
+  -1.58    1.302700uA        1.150200uA           1.476400uA
+  -1.54    1.291800uA        1.140400uA           1.464100uA
+  -1.50    1.281000uA        1.130600uA           1.452000uA
+  -1.46    1.270400uA        1.120900uA           1.440100uA
+  -1.42    1.259800uA        1.111300uA           1.428300uA
+  -1.38    1.249400uA        1.101800uA           1.416700uA
+  -1.34    1.239200uA        1.092400uA           1.405200uA
+  -1.30    1.229000uA        1.083000uA           1.393900uA
+  -1.26    1.218900uA        1.073800uA           1.382700uA
+  -1.22    1.209000uA        1.064600uA           1.371700uA
+  -1.18    1.199200uA        1.055500uA           1.360800uA
+  -1.14    1.189500uA        1.046500uA           1.350100uA
+  -1.10    1.179800uA        1.037600uA           1.339400uA
+  -1.06    1.170300uA        1.028700uA           1.329000uA
+  -1.02    1.160900uA        1.019900uA           1.318600uA
+  -0.98    1.151600uA        1.011200uA           1.308400uA
+  -0.94    1.142400uA        1.002500uA           1.298300uA
+  -0.90    1.133300uA        0.993900uA           1.288300uA
+  -0.86    1.124200uA        0.985360uA           1.278400uA
+  -0.82    1.115300uA        0.976890uA           1.268700uA
+  -0.78    1.106400uA        0.968470uA           1.259000uA
+  -0.74    1.097600uA        0.960110uA           1.249500uA
+  -0.70    1.088900uA        0.951810uA           1.240100uA
+  -0.66    1.080300uA        0.943560uA           1.230800uA
+  -0.62    1.071700uA        0.935380uA           1.221600uA
+  -0.58    1.063200uA        0.927260uA           1.212500uA
+  -0.54    1.054800uA        0.919220uA           1.203400uA
+  -0.50    1.046400uA        0.911290uA           1.194500uA
+  -0.46    1.038100uA        0.903530uA           1.185600uA
+  -0.42    1.029800uA        0.896100uA           1.176600uA
+  -0.38    1.021500uA        0.889460uA           1.167600uA
+  -0.34    1.017292uA        0.887043uA           1.162691uA
+  -0.30    1.017269uA        0.887023uA           1.162665uA
+  -0.26    1.017176uA        0.886942uA           1.162558uA
+  -0.22    1.016803uA        0.886617uA           1.162132uA
+  -0.18    1.015313uA        0.885317uA           1.160429uA
+  -0.14    1.009352uA        0.880120uA           1.153616uA
+  -0.10    0.985509uA        0.859330uA           1.126366uA
+  -0.06    0.890137uA        0.776169uA           1.017362uA
+  -0.02    1.500000pA        1.200000pA           1.800000pA
+  0.00    0.0A              0.0A                 0.0A
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  1.322279/1.397370n  1.285979/1.830494n  1.312139/1.075717n
+dV/dt_f  0.909660/0.907875n  0.826020/1.758264n  1.011840/0.527820n
+R_load = 50.000000
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.726300V         1.546200V            1.899700V
+0.2020ns          1.726800V         1.546200V            1.904800V
+0.4040ns          1.737400V         1.550000V            2.017500V
+0.6061ns          1.942100V         1.551600V            2.912500V
+0.8081ns          2.634400V         1.596800V            3.407200V
+1.0101ns          3.187200V         1.875300V            3.460800V
+1.2121ns          3.279100V         2.359700V            3.465800V
+1.4141ns          3.292700V         2.847800V            3.467100V
+1.6162ns          3.295600V         3.089900V            3.467600V
+1.8182ns          3.296700V         3.123600V            3.467900V
+2.0202ns          3.297300V         3.130900V            3.468200V
+2.2222ns          3.297500V         3.134300V            3.468700V
+2.4242ns          3.297700V         3.135700V            3.468900V
+2.6263ns          3.297900V         3.136600V            3.470800V
+2.8283ns          3.298100V         3.137000V            3.470300V
+3.0303ns          3.298400V         3.137300V            3.470100V
+3.2323ns          3.299000V         3.137500V            3.470000V
+3.4343ns          3.300800V         3.137600V            3.470000V
+3.6364ns          3.300800V         3.137800V            3.470000V
+3.8384ns          3.300300V         3.137900V            3.469900V
+4.0404ns          3.300200V         3.138000V            3.469900V
+4.2424ns          3.300000V         3.138200V            3.469900V
+4.4444ns          3.300000V         3.138400V            3.469900V
+4.6465ns          3.300000V         3.138600V            3.469900V
+4.8485ns          3.300000V         3.138900V            3.469900V
+5.0505ns          3.300000V         3.139200V            3.469900V
+5.2525ns          3.300000V         3.140400V            3.469900V
+5.4545ns          3.299900V         3.140300V            3.469900V
+5.6566ns          3.299900V         3.140100V            3.469900V
+5.8586ns          3.299900V         3.140100V            3.470000V
+6.0606ns          3.299900V         3.140000V            3.470000V
+6.2626ns          3.299900V         3.140000V            3.470000V
+6.4646ns          3.299900V         3.140000V            3.470000V
+6.6667ns          3.299900V         3.140000V            3.470000V
+6.8687ns          3.299900V         3.140000V            3.470000V
+7.0707ns          3.299900V         3.140000V            3.470000V
+7.2727ns          3.299900V         3.140000V            3.470000V
+7.4747ns          3.299900V         3.140000V            3.470000V
+7.6768ns          3.299900V         3.140000V            3.470000V
+7.8788ns          3.300000V         3.140000V            3.470000V
+8.0808ns          3.300000V         3.140000V            3.470000V
+8.2828ns          3.300000V         3.140000V            3.470000V
+8.4848ns          3.300000V         3.140000V            3.470000V
+8.6869ns          3.300000V         3.139900V            3.470000V
+8.8889ns          3.300000V         3.139900V            3.470000V
+9.0909ns          3.300000V         3.139900V            3.470000V
+9.2929ns          3.300000V         3.139900V            3.470000V
+9.4949ns          3.300000V         3.139900V            3.470000V
+9.6970ns          3.300000V         3.139900V            3.470000V
+9.8990ns          3.300000V         3.139900V            3.470000V
+10.1010ns         3.300000V         3.139900V            3.470000V
+10.3030ns         3.300000V         3.139900V            3.470000V
+10.5051ns         3.300000V         3.139900V            3.470000V
+10.7071ns         3.300000V         3.139900V            3.470000V
+10.9091ns         3.300000V         3.139900V            3.470000V
+11.1111ns         3.300000V         3.139900V            3.470000V
+11.3131ns         3.300000V         3.139900V            3.470000V
+11.5152ns         3.300000V         3.140000V            3.470000V
+11.7172ns         3.300000V         3.140000V            3.470000V
+11.9192ns         3.300000V         3.140000V            3.470000V
+12.1212ns         3.300000V         3.140000V            3.470000V
+12.3232ns         3.300000V         3.140000V            3.470000V
+12.5253ns         3.300000V         3.140000V            3.470000V
+12.7273ns         3.300000V         3.140000V            3.470000V
+12.9293ns         3.300000V         3.140000V            3.470000V
+13.1313ns         3.300000V         3.140000V            3.470000V
+13.3333ns         3.300000V         3.140000V            3.470000V
+13.5354ns         3.300000V         3.140000V            3.470000V
+13.7374ns         3.300000V         3.140000V            3.470000V
+13.9394ns         3.300000V         3.140000V            3.470000V
+14.1414ns         3.300000V         3.140000V            3.470000V
+14.3434ns         3.300000V         3.140000V            3.470000V
+14.5455ns         3.300000V         3.140000V            3.470000V
+14.7475ns         3.300000V         3.140000V            3.470000V
+14.9495ns         3.300000V         3.140000V            3.470000V
+15.1515ns         3.300000V         3.140000V            3.470000V
+15.3535ns         3.300000V         3.140000V            3.470000V
+15.5556ns         3.300000V         3.140000V            3.470000V
+15.7576ns         3.300000V         3.140000V            3.470000V
+15.9596ns         3.300000V         3.140000V            3.470000V
+16.1616ns         3.300000V         3.140000V            3.470000V
+16.3636ns         3.300000V         3.140000V            3.470000V
+16.5657ns         3.300000V         3.140000V            3.470000V
+16.7677ns         3.300000V         3.140000V            3.470000V
+16.9697ns         3.300000V         3.140000V            3.470000V
+17.1717ns         3.300000V         3.140000V            3.470000V
+17.3737ns         3.300000V         3.140000V            3.470000V
+17.5758ns         3.300000V         3.140000V            3.470000V
+17.7778ns         3.300000V         3.140000V            3.470000V
+17.9798ns         3.300000V         3.140000V            3.470000V
+18.1818ns         3.300000V         3.140000V            3.470000V
+18.3838ns         3.300000V         3.140000V            3.470000V
+18.5859ns         3.300000V         3.140000V            3.470000V
+18.7879ns         3.300000V         3.140000V            3.470000V
+18.9899ns         3.300000V         3.140000V            3.470000V
+19.1919ns         3.300000V         3.140000V            3.470000V
+19.3939ns         3.300000V         3.140000V            3.470000V
+19.5960ns         3.300000V         3.140000V            3.470000V
+19.7980ns         3.300000V         3.140000V            3.470000V
+20.0000ns         3.300000V         3.140000V            3.470000V
+|  
+[Rising Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.860000uV        2.247100uV           1.679700uV
+0.2020ns          -0.129790mV       4.669400uV           -0.320790mV
+0.4040ns          -1.716600mV       0.272540uV           -4.681500mV
+0.6061ns          1.221000mV        -0.447820mV          0.186680V
+0.8081ns          0.107030V         -5.196400mV          0.507800V
+1.0101ns          0.361420V         7.872900mV           0.782610V
+1.2121ns          0.574160V         63.086000mV          1.032400V
+1.4141ns          0.778920V         0.229510V            1.269500V
+1.6162ns          0.975680V         0.410340V            1.497800V
+1.8182ns          1.166800V         0.562960V            1.717900V
+2.0202ns          1.353800V         0.714380V            1.916400V
+2.2222ns          1.533600V         0.865340V            2.085800V
+2.4242ns          1.705400V         1.012700V            2.201900V
+2.6263ns          1.865600V         1.157800V            2.206500V
+2.8283ns          2.002800V         1.297100V            2.148000V
+3.0303ns          2.119800V         1.433900V            2.116300V
+3.2323ns          2.194200V         1.564200V            2.100900V
+3.4343ns          2.242600V         1.684200V            2.095200V
+3.6364ns          2.206600V         1.795900V            2.092100V
+3.8384ns          2.175600V         1.885300V            2.093400V
+4.0404ns          2.158100V         1.961700V            2.097900V
+4.2424ns          2.149800V         2.017100V            2.104000V
+4.4444ns          2.145000V         2.058100V            2.111400V
+4.6465ns          2.142500V         2.090000V            2.119600V
+4.8485ns          2.141700V         2.113000V            2.127800V
+5.0505ns          2.141900V         2.137500V            2.135200V
+5.2525ns          2.142800V         2.134100V            2.141000V
+5.4545ns          2.144700V         2.126700V            2.146000V
+5.6566ns          2.148900V         2.121500V            2.150700V
+5.8586ns          2.153600V         2.118100V            2.154700V
+6.0606ns          2.158200V         2.116400V            2.158400V
+6.2626ns          2.162900V         2.115100V            2.161600V
+6.4646ns          2.167200V         2.114600V            2.164500V
+6.6667ns          2.171000V         2.114400V            2.167000V
+6.8687ns          2.174500V         2.114500V            2.169300V
+7.0707ns          2.177500V         2.114600V            2.171300V
+7.2727ns          2.180300V         2.114800V            2.173100V
+7.4747ns          2.182800V         2.115200V            2.174700V
+7.6768ns          2.185100V         2.115600V            2.176100V
+7.8788ns          2.187100V         2.116000V            2.177400V
+8.0808ns          2.188900V         2.116500V            2.178500V
+8.2828ns          2.190500V         2.117100V            2.179500V
+8.4848ns          2.191900V         2.117700V            2.180300V
+8.6869ns          2.193200V         2.118500V            2.181100V
+8.8889ns          2.194300V         2.119600V            2.181800V
+9.0909ns          2.195300V         2.121000V            2.182400V
+9.2929ns          2.196300V         2.122600V            2.182900V
+9.4949ns          2.197100V         2.124200V            2.183400V
+9.6970ns          2.197800V         2.125900V            2.183800V
+9.8990ns          2.198500V         2.127400V            2.184200V
+10.1010ns         2.199350V         2.129450V            2.184650V
+10.3030ns         2.200000V         2.131300V            2.185000V
+10.5051ns         2.200500V         2.132300V            2.185200V
+10.7071ns         2.200800V         2.133300V            2.185400V
+10.9091ns         2.201200V         2.134200V            2.185600V
+11.1111ns         2.201500V         2.135100V            2.185800V
+11.3131ns         2.201700V         2.135800V            2.185900V
+11.5152ns         2.202000V         2.136500V            2.186000V
+11.7172ns         2.202200V         2.137100V            2.186100V
+11.9192ns         2.202400V         2.137700V            2.186200V
+12.1212ns         2.202500V         2.138200V            2.186300V
+12.3232ns         2.202700V         2.138700V            2.186400V
+12.5253ns         2.202800V         2.139100V            2.186400V
+12.7273ns         2.202900V         2.139500V            2.186500V
+12.9293ns         2.203000V         2.139900V            2.186500V
+13.1313ns         2.203100V         2.140200V            2.186600V
+13.3333ns         2.203200V         2.140500V            2.186600V
+13.5354ns         2.203300V         2.140700V            2.186600V
+13.7374ns         2.203300V         2.141000V            2.186700V
+13.9394ns         2.203400V         2.141200V            2.186700V
+14.1414ns         2.203400V         2.141400V            2.186700V
+14.3434ns         2.203500V         2.141600V            2.186700V
+14.5455ns         2.203500V         2.141800V            2.186700V
+14.7475ns         2.203600V         2.141900V            2.186800V
+14.9495ns         2.203600V         2.142000V            2.186800V
+15.1515ns         2.203600V         2.142200V            2.186800V
+15.3535ns         2.203600V         2.142300V            2.186800V
+15.5556ns         2.203700V         2.142400V            2.186800V
+15.7576ns         2.203700V         2.142500V            2.186800V
+15.9596ns         2.203700V         2.142600V            2.186800V
+16.1616ns         2.203700V         2.142600V            2.186800V
+16.3636ns         2.203700V         2.142700V            2.186800V
+16.5657ns         2.203700V         2.142800V            2.186900V
+16.7677ns         2.203700V         2.142800V            2.186900V
+16.9697ns         2.203800V         2.142900V            2.186900V
+17.1717ns         2.203800V         2.142900V            2.186900V
+17.3737ns         2.203800V         2.143000V            2.186900V
+17.5758ns         2.203800V         2.143000V            2.186900V
+17.7778ns         2.203800V         2.143000V            2.186900V
+17.9798ns         2.203800V         2.143100V            2.186900V
+18.1818ns         2.203800V         2.143100V            2.186900V
+18.3838ns         2.203800V         2.143100V            2.186900V
+18.5859ns         2.203800V         2.143100V            2.186900V
+18.7879ns         2.203800V         2.143200V            2.186900V
+18.9899ns         2.203800V         2.143200V            2.186900V
+19.1919ns         2.203800V         2.143200V            2.186900V
+19.3939ns         2.203800V         2.143200V            2.186900V
+19.5960ns         2.203800V         2.143200V            2.186900V
+19.7980ns         2.203800V         2.143200V            2.186900V
+20.0000ns         2.203800V         2.143300V            2.186900V
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.203900V         2.143400V            2.187000V
+0.2020ns          2.204000V         2.143400V            2.193500V
+0.4040ns          2.222800V         2.147700V            2.032600V
+0.6061ns          2.041300V         2.152800V            1.329800V
+0.8081ns          1.561500V         2.146100V            0.689440V
+1.0101ns          1.011100V         2.097000V            0.210050V
+1.2121ns          0.595520V         1.931200V            16.668000mV
+1.4141ns          0.291310V         1.573700V            3.287100mV
+1.6162ns          80.606000mV       1.160800V            1.540100mV
+1.8182ns          13.976000mV       0.816650V            0.795800mV
+2.0202ns          3.438200mV        0.556260V            0.249100mV
+2.2222ns          2.674800mV        0.354310V            0.141130mV
+2.4242ns          1.686600mV        0.200190V            -0.655480mV
+2.6263ns          0.612530mV        87.872000mV          -2.068600uV
+2.8283ns          0.572400mV        33.061000mV          -22.091000uV
+3.0303ns          0.375060mV        11.834000mV          -24.867000uV
+3.2323ns          0.241800mV        4.814600mV           -26.956000uV
+3.4343ns          -0.105830mV       3.354200mV           -15.925000uV
+3.6364ns          -75.323000uV      2.452700mV           -21.116000uV
+3.8384ns          4.162200uV        1.747000mV           -21.198000uV
+4.0404ns          -9.814400uV       1.397500mV           -20.735000uV
+4.2424ns          -8.341900uV       1.108100mV           -20.330000uV
+4.4444ns          -6.866100uV       0.872660mV           -19.920000uV
+4.6465ns          -5.387100uV       0.692450mV           -19.527000uV
+4.8485ns          -8.072400uV       0.289700mV           -19.137000uV
+5.0505ns          -7.958300uV       0.244360mV           -18.776000uV
+5.2525ns          -7.769600uV       -77.493000uV         -18.423000uV
+5.4545ns          -7.625700uV       -0.105340mV          -18.079000uV
+5.6566ns          -7.474800uV       -54.805000uV         -17.737000uV
+5.8586ns          -7.290100uV       10.015000uV          -17.420000uV
+6.0606ns          -7.095100uV       31.098000uV          -17.110000uV
+6.2626ns          -6.941900uV       27.849000uV          -16.798000uV
+6.4646ns          -6.801300uV       26.843000uV          -16.485000uV
+6.6667ns          -6.644700uV       25.837000uV          -16.193000uV
+6.8687ns          -6.483200uV       24.821000uV          -15.906000uV
+7.0707ns          -6.356800uV       23.930000uV          -15.617000uV
+7.2727ns          -6.241000uV       23.931000uV          -15.328000uV
+7.4747ns          -6.109700uV       23.867000uV          -15.057000uV
+7.6768ns          -5.973800uV       23.333000uV          -14.790000uV
+7.8788ns          -5.859500uV       22.861000uV          -14.523000uV
+8.0808ns          -5.751700uV       22.831000uV          -14.256000uV
+8.2828ns          -5.632300uV       22.765000uV          -14.004000uV
+8.4848ns          -5.509400uV       22.433000uV          -13.756000uV
+8.6869ns          -5.401200uV       22.127000uV          -13.508000uV
+8.8889ns          -5.297500uV       22.000000uV          -13.261000uV
+9.0909ns          -5.186800uV       21.856000uV          -13.026000uV
+9.2929ns          -5.073900uV       21.583000uV          -12.795000uV
+9.4949ns          -4.971400uV       21.321000uV          -12.566000uV
+9.6970ns          -4.872100uV       21.138000uV          -12.337000uV
+9.8990ns          -4.768700uV       20.948000uV          -12.119000uV
+10.1010ns         -4.615700uV       20.580000uV          -11.796500uV
+10.3030ns         -4.472500uV       20.255000uV          -11.478000uV
+10.5051ns         -4.375700uV       20.048000uV          -11.275000uV
+10.7071ns         -4.278400uV       19.819000uV          -11.074000uV
+10.9091ns         -4.186900uV       19.593000uV          -10.876000uV
+11.1111ns         -4.097100uV       19.385000uV          -10.679000uV
+11.3131ns         -4.006500uV       19.177000uV          -10.490000uV
+11.5152ns         -3.915700uV       18.963000uV          -10.303000uV
+11.7172ns         -3.829500uV       18.751000uV          -10.119000uV
+11.9192ns         -3.744700uV       18.550000uV          -9.935200uV
+12.1212ns         -3.659800uV       18.348000uV          -9.758900uV
+12.3232ns         -3.575000uV       18.147000uV          -9.584400uV
+12.5253ns         -3.493900uV       17.946000uV          -9.412900uV
+12.7273ns         -3.413900uV       17.750000uV          -9.242200uV
+12.9293ns         -3.334400uV       17.555000uV          -9.077700uV
+13.1313ns         -3.255000uV       17.367000uV          -8.914800uV
+13.3333ns         -3.178700uV       17.180000uV          -8.754900uV
+13.5354ns         -3.103400uV       16.992000uV          -8.595700uV
+13.7374ns         -3.028800uV       16.805000uV          -8.442200uV
+13.9394ns         -2.954500uV       16.625000uV          -8.290100uV
+14.1414ns         -2.882800uV       16.446000uV          -8.140800uV
+14.3434ns         -2.811900uV       16.271000uV          -7.992300uV
+14.5455ns         -2.741900uV       16.096000uV          -7.848800uV
+14.7475ns         -2.672100uV       15.921000uV          -7.706700uV
+14.9495ns         -2.604700uV       15.747000uV          -7.567200uV
+15.1515ns         -2.538000uV       15.582000uV          -7.428400uV
+15.3535ns         -2.472300uV       15.417000uV          -7.294300uV
+15.5556ns         -2.406900uV       15.254000uV          -7.161400uV
+15.7576ns         -2.343500uV       15.091000uV          -7.031000uV
+15.9596ns         -2.280700uV       14.928000uV          -6.901100uV
+16.1616ns         -2.219000uV       14.767000uV          -6.775700uV
+16.3636ns         -2.157500uV       14.614000uV          -6.651300uV
+16.5657ns         -2.097900uV       14.461000uV          -6.529200uV
+16.7677ns         -2.038900uV       14.310000uV          -6.407700uV
+16.9697ns         -1.980900uV       14.158000uV          -6.290200uV
+17.1717ns         -1.923100uV       14.007000uV          -6.173700uV
+17.3737ns         -1.867100uV       13.856000uV          -6.059300uV
+17.5758ns         -1.811500uV       13.715000uV          -5.945500uV
+17.7778ns         -1.756900uV       13.574000uV          -5.835400uV
+17.9798ns         -1.702700uV       13.433000uV          -5.726200uV
+18.1818ns         -1.649900uV       13.292000uV          -5.619000uV
+18.3838ns         -1.597600uV       13.151000uV          -5.512200uV
+18.5859ns         -1.546300uV       13.011000uV          -5.409000uV
+18.7879ns         -1.495300uV       12.881000uV          -5.306700uV
+18.9899ns         -1.445600uV       12.750000uV          -5.206100uV
+19.1919ns         -1.396400uV       12.619000uV          -5.105900uV
+19.3939ns         -1.348100uV       12.488000uV          -5.009100uV
+19.5960ns         -1.300200uV       12.357000uV          -4.913100uV
+19.7980ns         -1.253400uV       12.227000uV          -4.818400uV
+20.0000ns         -1.206900uV       12.109000uV          -4.724200uV
+|  
+[Falling Waveform] 
+R_fixture=       50.000000
+V_fixture=       3.300000
+V_fixture_min=   3.140000
+V_fixture_max=   3.470000
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.300000V         3.140000V            3.470000V
+0.2020ns          3.299700V         3.140000V            3.468500V
+0.4040ns          3.300800V         3.139500V            3.480800V
+0.6061ns          3.307700V         3.140100V            3.421400V
+0.8081ns          3.288700V         3.143500V            3.119600V
+1.0101ns          3.205000V         3.143800V            2.661400V
+1.2121ns          3.025100V         3.145800V            2.287000V
+1.4141ns          2.763000V         3.126600V            2.008100V
+1.6162ns          2.525800V         3.091800V            1.804300V
+1.8182ns          2.335100V         3.031500V            1.669500V
+2.0202ns          2.176400V         2.950000V            1.556300V
+2.2222ns          2.038500V         2.833800V            1.492000V
+2.4242ns          1.931900V         2.695300V            1.454000V
+2.6263ns          1.842100V         2.569900V            1.511700V
+2.8283ns          1.775200V         2.465400V            1.518000V
+3.0303ns          1.725800V         2.375800V            1.523200V
+3.2323ns          1.686600V         2.288200V            1.528200V
+3.4343ns          1.685200V         2.209700V            1.533400V
+3.6364ns          1.704000V         2.138800V            1.538300V
+3.8384ns          1.711300V         2.070500V            1.543000V
+4.0404ns          1.712500V         2.009900V            1.547600V
+4.2424ns          1.714100V         1.956200V            1.552200V
+4.4444ns          1.715500V         1.910000V            1.556700V
+4.6465ns          1.717000V         1.869400V            1.561200V
+4.8485ns          1.718600V         1.839700V            1.565600V
+5.0505ns          1.719900V         1.823800V            1.569900V
+5.2525ns          1.721200V         1.826000V            1.574200V
+5.4545ns          1.722500V         1.835200V            1.578400V
+5.6566ns          1.723800V         1.841500V            1.582600V
+5.8586ns          1.725000V         1.842800V            1.586700V
+6.0606ns          1.726200V         1.841300V            1.590800V
+6.2626ns          1.727400V         1.839800V            1.594800V
+6.4646ns          1.728600V         1.838400V            1.598800V
+6.6667ns          1.729800V         1.837000V            1.602700V
+6.8687ns          1.730900V         1.835500V            1.606600V
+7.0707ns          1.732000V         1.834000V            1.610400V
+7.2727ns          1.733200V         1.832700V            1.614200V
+7.4747ns          1.734300V         1.831300V            1.618000V
+7.6768ns          1.735400V         1.829900V            1.621600V
+7.8788ns          1.736400V         1.828500V            1.625300V
+8.0808ns          1.737500V         1.827100V            1.628900V
+8.2828ns          1.738600V         1.825800V            1.632500V
+8.4848ns          1.739600V         1.824400V            1.636000V
+8.6869ns          1.740600V         1.823100V            1.639400V
+8.8889ns          1.741700V         1.821800V            1.642900V
+9.0909ns          1.742700V         1.820400V            1.646300V
+9.2929ns          1.743700V         1.819100V            1.649600V
+9.4949ns          1.744700V         1.817800V            1.652900V
+9.6970ns          1.745600V         1.816500V            1.656200V
+9.8990ns          1.746600V         1.815200V            1.659400V
+10.1010ns         1.748050V         1.813350V            1.664200V
+10.3030ns         1.749400V         1.811400V            1.668900V
+10.5051ns         1.750400V         1.810200V            1.672000V
+10.7071ns         1.751300V         1.809000V            1.675000V
+10.9091ns         1.752200V         1.807800V            1.678000V
+11.1111ns         1.753100V         1.806500V            1.681000V
+11.3131ns         1.753900V         1.805400V            1.684000V
+11.5152ns         1.754800V         1.804200V            1.686900V
+11.7172ns         1.755700V         1.803000V            1.689700V
+11.9192ns         1.756500V         1.801800V            1.692600V
+12.1212ns         1.757400V         1.800700V            1.695400V
+12.3232ns         1.758200V         1.799500V            1.698200V
+12.5253ns         1.759000V         1.798400V            1.700900V
+12.7273ns         1.759800V         1.797300V            1.703600V
+12.9293ns         1.760600V         1.796200V            1.706300V
+13.1313ns         1.761400V         1.795100V            1.709000V
+13.3333ns         1.762200V         1.794000V            1.711600V
+13.5354ns         1.763000V         1.792900V            1.714200V
+13.7374ns         1.763800V         1.791800V            1.716700V
+13.9394ns         1.764500V         1.790800V            1.719300V
+14.1414ns         1.765300V         1.789700V            1.721800V
+14.3434ns         1.766000V         1.788700V            1.724200V
+14.5455ns         1.766800V         1.787700V            1.726700V
+14.7475ns         1.767500V         1.786600V            1.729100V
+14.9495ns         1.768200V         1.785600V            1.731500V
+15.1515ns         1.768900V         1.784600V            1.733900V
+15.3535ns         1.769600V         1.783600V            1.736200V
+15.5556ns         1.770300V         1.782700V            1.738500V
+15.7576ns         1.771000V         1.781700V            1.740800V
+15.9596ns         1.771700V         1.780700V            1.743100V
+16.1616ns         1.772400V         1.779800V            1.745300V
+16.3636ns         1.773000V         1.778800V            1.747500V
+16.5657ns         1.773700V         1.777900V            1.749700V
+16.7677ns         1.774300V         1.777000V            1.751900V
+16.9697ns         1.775000V         1.776000V            1.754000V
+17.1717ns         1.775600V         1.775100V            1.756200V
+17.3737ns         1.776300V         1.774200V            1.758300V
+17.5758ns         1.776900V         1.773300V            1.760300V
+17.7778ns         1.777500V         1.772400V            1.762400V
+17.9798ns         1.778100V         1.771600V            1.764400V
+18.1818ns         1.778700V         1.770700V            1.766400V
+18.3838ns         1.779300V         1.769800V            1.768400V
+18.5859ns         1.779900V         1.769000V            1.770400V
+18.7879ns         1.780500V         1.768100V            1.772300V
+18.9899ns         1.781100V         1.767300V            1.774200V
+19.1919ns         1.781600V         1.766500V            1.776200V
+19.3939ns         1.782200V         1.765700V            1.778000V
+19.5960ns         1.782800V         1.764900V            1.779900V
+19.7980ns         1.783300V         1.764000V            1.781700V
+|20.0000ns         1.783900V         1.763300V            1.783600V
+40.0000ns         1.783900V         1.550000V            1.783600V
+|  
+| End [Model] lvt330s160aaaaaaaaio
+|************************************************************************
+| End [Component]
+[End]
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt
new file mode 100644
index 0000000..036ae2c
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt
@@ -0,0 +1,75 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Mon Aug 16 21:36:33 2021 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[7] : 71 : inout *
+NOTE PINS RD[6] : 70 : inout *
+NOTE PINS RD[5] : 69 : inout *
+NOTE PINS RD[4] : 68 : inout *
+NOTE PINS RD[3] : 67 : inout *
+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RD[0] : 64 : inout *
+NOTE PINS Dout[7] : 3 : out *
+NOTE PINS Dout[6] : 2 : out *
+NOTE PINS Dout[5] : 5 : out *
+NOTE PINS Dout[4] : 4 : out *
+NOTE PINS Dout[3] : 6 : out *
+NOTE PINS Dout[2] : 8 : out *
+NOTE PINS Dout[1] : 7 : out *
+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS LED : 57 : out *
+NOTE PINS RBA[1] : 83 : out *
+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
+NOTE PINS RA[9] : 85 : out *
+NOTE PINS RA[8] : 96 : out *
+NOTE PINS RA[7] : 100 : out *
+NOTE PINS RA[6] : 91 : out *
+NOTE PINS RA[5] : 95 : out *
+NOTE PINS RA[4] : 99 : out *
+NOTE PINS RA[3] : 97 : out *
+NOTE PINS RA[2] : 94 : out *
+NOTE PINS RA[1] : 89 : out *
+NOTE PINS RA[0] : 98 : out *
+NOTE PINS nRCS : 77 : out *
+NOTE PINS RCKE : 82 : out *
+NOTE PINS nRWE : 72 : out *
+NOTE PINS nRRAS : 73 : out *
+NOTE PINS nRCAS : 78 : out *
+NOTE PINS RDQMH : 76 : out *
+NOTE PINS RDQML : 61 : out *
+NOTE PINS nUFMCS : 53 : out *
+NOTE PINS UFMCLK : 58 : out *
+NOTE PINS UFMSDI : 56 : out *
+NOTE PINS PHI2 : 39 : in *
+NOTE PINS MAin[9] : 51 : in *
+NOTE PINS MAin[8] : 50 : in *
+NOTE PINS MAin[7] : 44 : in *
+NOTE PINS MAin[6] : 49 : in *
+NOTE PINS MAin[5] : 45 : in *
+NOTE PINS MAin[4] : 46 : in *
+NOTE PINS MAin[3] : 47 : in *
+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE PINS CROW[1] : 34 : in *
+NOTE PINS CROW[0] : 32 : in *
+NOTE PINS Din[7] : 19 : in *
+NOTE PINS Din[6] : 20 : in *
+NOTE PINS Din[5] : 17 : in *
+NOTE PINS Din[4] : 18 : in *
+NOTE PINS Din[3] : 16 : in *
+NOTE PINS Din[2] : 14 : in *
+NOTE PINS Din[1] : 15 : in *
+NOTE PINS Din[0] : 21 : in *
+NOTE PINS nCCAS : 27 : in *
+NOTE PINS nCRAS : 43 : in *
+NOTE PINS nFWE : 22 : in *
+NOTE PINS RCLK : 86 : in *
+NOTE PINS UFMSDO : 55 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep
new file mode 100644
index 0000000..e05ef5e
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep
@@ -0,0 +1,24 @@
+----------------------------------------------------------------------
+Report for cell RAM2GS.TECH
+Register bits:  102 of 862 (11.833%)
+I/O cells:      67
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                                 BB         8          100.0
+                               CCU2         9          100.0
+                            FD1P3AX        28          100.0
+                            FD1P3AY         3          100.0
+                            FD1P3IX         2          100.0
+                            FD1P3JX         1          100.0
+                            FD1S3AX        47          100.0
+                            FD1S3AY         1          100.0
+                            FD1S3IX        16          100.0
+                            FD1S3JX         4          100.0
+                                GSR         1          100.0
+                                 IB        26          100.0
+                                INV         3          100.0
+                               LUT4       114          100.0
+                                 OB        33          100.0
+                           ORCALUT4         2          100.0
+                              PFUMX         3          100.0
+                              TOTAL       301
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn
new file mode 100644
index 0000000..d89f059
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn
@@ -0,0 +1,45 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:36:33 2021
+
+
+Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit
new file mode 100644
index 0000000..e85f680
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd
new file mode 100644
index 0000000..fa3d127
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
new file mode 100644
index 0000000..bcb27b5
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
@@ -0,0 +1,353 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Mon Aug 16 21:33:36 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | Properties                       |
++-----------+----------+--------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVTTL33_IN   | PB4C  | SLEW:FAST                        |
+| CROW[1]   | 34/2     | LVTTL33_IN   | PB4E  | SLEW:FAST                        |
+| Din[0]    | 21/3     | LVTTL33_IN   | PL10C | SLEW:FAST                        |
+| Din[1]    | 15/3     | LVTTL33_IN   | PL7B  | SLEW:FAST                        |
+| Din[2]    | 14/3     | LVTTL33_IN   | PL5B  | SLEW:FAST                        |
+| Din[3]    | 16/3     | LVTTL33_IN   | PL8C  | SLEW:FAST                        |
+| Din[4]    | 18/3     | LVTTL33_IN   | PL9A  | SLEW:FAST                        |
+| Din[5]    | 17/3     | LVTTL33_IN   | PL8D  | SLEW:FAST                        |
+| Din[6]    | 20/3     | LVTTL33_IN   | PL10A | SLEW:FAST                        |
+| Din[7]    | 19/3     | LVTTL33_IN   | PL9C  | SLEW:FAST                        |
+| Dout[0]   | 1/3      | LVTTL33_OUT  | PL2A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/3      | LVTTL33_OUT  | PL3C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/3      | LVTTL33_OUT  | PL3D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/3      | LVTTL33_OUT  | PL3B  | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/3      | LVTTL33_OUT  | PL2D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/3      | LVTTL33_OUT  | PL3A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/3      | LVTTL33_OUT  | PL2C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/3      | LVTTL33_OUT  | PL2B  | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/1     | LVTTL33_OUT  | PR10B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVTTL33_IN   | PL11C | SLEW:FAST                        |
+| MAin[1]   | 38/2     | LVTTL33_IN   | PB6B  | SLEW:FAST                        |
+| MAin[2]   | 37/2     | LVTTL33_IN   | PB5D  | SLEW:FAST                        |
+| MAin[3]   | 47/2     | LVTTL33_IN   | PB9C  | SLEW:FAST                        |
+| MAin[4]   | 46/2     | LVTTL33_IN   | PB9A  | SLEW:FAST                        |
+| MAin[5]   | 45/2     | LVTTL33_IN   | PB8D  | SLEW:FAST                        |
+| MAin[6]   | 49/2     | LVTTL33_IN   | PB9D  | SLEW:FAST                        |
+| MAin[7]   | 44/2     | LVTTL33_IN   | PB8C  | SLEW:FAST                        |
+| MAin[8]   | 50/2     | LVTTL33_IN   | PB9F  | SLEW:FAST                        |
+| MAin[9]   | 51/1     | LVTTL33_IN   | PR11D | SLEW:FAST                        |
+| PHI2      | 39/2     | LVTTL33_IN   | PB6C  | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVTTL33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT5B  | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVTTL33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVTTL33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVTTL33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVTTL33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVTTL33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVTTL33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVTTL33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVTTL33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVTTL33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVTTL33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVTTL33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVTTL33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVTTL33_IN   | PB2C  | SLEW:FAST                        |
+| nCRAS     | 43/2     | LVTTL33_IN   | PB8B  | SLEW:FAST                        |
+| nFWE      | 22/3     | LVTTL33_IN   | PL11A | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVTTL33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVTTL33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVTTL33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site  | Dual Function |
++----------+---------------------+------------+--------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |              | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |              | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |              | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVTTL33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVTTL33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVTTL33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVTTL33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVTTL33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVTTL33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVTTL33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVTTL33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVTTL33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |              | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVTTL33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVTTL33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |              | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |              | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVTTL33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |              | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVTTL33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVTTL33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |              | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |              | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |              | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |              | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |              | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |              | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |              | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |              | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |              | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |              | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |              | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |              | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |              | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |              | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |              | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |              | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |              | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |              | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |              | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |              | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |              | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |              | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |              | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |              | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |              | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |              | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |              | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |              | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |              | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |              | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |              | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |              | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |              | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |              | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |              | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |              | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |              | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |              | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |              | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |              | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |              | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |              | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |              | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |              | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |              | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |              | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |              | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |              | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |              | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |              | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |              | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |              | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |              | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |              | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |              | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |              | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |              | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |              | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |              | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |              | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |              | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |              | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |              | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |              | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |              | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |              | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |              | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |              | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |              | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |              | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |              | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |              | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |              | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |              | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |              | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |              | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |              | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |              | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |              | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |              | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |              | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |              | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |              | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |              | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |              | PT9D  |               |
+| TCK/2    |                     |            |              | TCK   | TCK           |
+| TDI/2    |                     |            |              | TDI   | TDID0         |
+| TDO/2    |                     |            |              | TDO   | TDO           |
+| TMS/2    |                     |            |              | TMS   | TMS           |
++----------+---------------------+------------+--------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:36 2021
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
new file mode 100644
index 0000000..b5bdccb
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
@@ -0,0 +1,219 @@
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Mon Aug 16 21:33:31 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             65/320          20% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.......
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 1105164.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1103986
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 160 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PB2C)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 21:33:36 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:33:36 08/16/21
+
+Start NBR section for initial routing at 21:33:36 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.339
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
new file mode 100644
index 0000000..878d798
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
@@ -0,0 +1,45 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 4;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 39;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 13;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c;
+GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_2_LOADNUM = 4;
+; Global primary clock #3
+GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c;
+GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_3_LOADNUM = 7;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 18;
+BANK_0_AVAIL = 18;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+BANK_0_VREF2 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 18;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+BANK_1_VREF2 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 13;
+BANK_2_AVAIL = 14;
+BANK_2_VCCIO = NA;
+BANK_2_VREF1 = NA;
+BANK_2_VREF2 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 18;
+BANK_3_AVAIL = 21;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
+BANK_3_VREF2 = NA;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
new file mode 100644
index 0000000..8bf94bf
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:31 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.213        0            0.339        0            06           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
new file mode 100644
index 0000000..149b5cf
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
@@ -0,0 +1,1745 @@
+
+*
+NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
+NOTE Version:         Diamond (64-bit) 3.12.0.240.2*
+NOTE Readback:       Off*
+NOTE Security:      Off*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Mon Aug 16 21:36:33 2021 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[7] : 71 : inout *
+NOTE PINS RD[6] : 70 : inout *
+NOTE PINS RD[5] : 69 : inout *
+NOTE PINS RD[4] : 68 : inout *
+NOTE PINS RD[3] : 67 : inout *
+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RD[0] : 64 : inout *
+NOTE PINS Dout[7] : 3 : out *
+NOTE PINS Dout[6] : 2 : out *
+NOTE PINS Dout[5] : 5 : out *
+NOTE PINS Dout[4] : 4 : out *
+NOTE PINS Dout[3] : 6 : out *
+NOTE PINS Dout[2] : 8 : out *
+NOTE PINS Dout[1] : 7 : out *
+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS LED : 57 : out *
+NOTE PINS RBA[1] : 83 : out *
+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
+NOTE PINS RA[9] : 85 : out *
+NOTE PINS RA[8] : 96 : out *
+NOTE PINS RA[7] : 100 : out *
+NOTE PINS RA[6] : 91 : out *
+NOTE PINS RA[5] : 95 : out *
+NOTE PINS RA[4] : 99 : out *
+NOTE PINS RA[3] : 97 : out *
+NOTE PINS RA[2] : 94 : out *
+NOTE PINS RA[1] : 89 : out *
+NOTE PINS RA[0] : 98 : out *
+NOTE PINS nRCS : 77 : out *
+NOTE PINS RCKE : 82 : out *
+NOTE PINS nRWE : 72 : out *
+NOTE PINS nRRAS : 73 : out *
+NOTE PINS nRCAS : 78 : out *
+NOTE PINS RDQMH : 76 : out *
+NOTE PINS RDQML : 61 : out *
+NOTE PINS nUFMCS : 53 : out *
+NOTE PINS UFMCLK : 58 : out *
+NOTE PINS UFMSDI : 56 : out *
+NOTE PINS PHI2 : 39 : in *
+NOTE PINS MAin[9] : 51 : in *
+NOTE PINS MAin[8] : 50 : in *
+NOTE PINS MAin[7] : 44 : in *
+NOTE PINS MAin[6] : 49 : in *
+NOTE PINS MAin[5] : 45 : in *
+NOTE PINS MAin[4] : 46 : in *
+NOTE PINS MAin[3] : 47 : in *
+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE PINS CROW[1] : 34 : in *
+NOTE PINS CROW[0] : 32 : in *
+NOTE PINS Din[7] : 19 : in *
+NOTE PINS Din[6] : 20 : in *
+NOTE PINS Din[5] : 17 : in *
+NOTE PINS Din[4] : 18 : in *
+NOTE PINS Din[3] : 16 : in *
+NOTE PINS Din[2] : 14 : in *
+NOTE PINS Din[1] : 15 : in *
+NOTE PINS Din[0] : 21 : in *
+NOTE PINS nCCAS : 27 : in *
+NOTE PINS nCRAS : 43 : in *
+NOTE PINS nFWE : 22 : in *
+NOTE PINS RCLK : 86 : in *
+NOTE PINS UFMSDO : 55 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
+
+
+QF130036*
+G0*
+F0*
+L000000
+11111111001011111111011110111100101111111101111011110010111111110111101111111111
+11111111111011111111111111111111101111111111111111111110111111111111111111111011
+1111111111111111111011110010100100111101111011001010010011110111011111111111
+11111111111111111111111110111111111111111111111011111111111111111111101111111111
+11111111111011110010111111110111101111111111111111111110111100101111111101111011
+1111111111111111111011110010100100111101110111001010010011110111101111111111
+11111111001011111111011110111100101111111101111011110010111111110111101111001011
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+1111111111111111111011110010100100111101110111001010010011110111011111111111
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+1101001111111111111111110100111101111111011101011111111111111101111111111001
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+11111111111111111111111110111100101001001111001111111111111111111111101111111111
+11111111111011111111111111111111101111111111111111111110111111111111111111111011
+1111111111111111111011111111111111111111101111111111111111111110111111111111
+11111111111111111111111110111100101100110111011101110010100100111100111111111111
+11111111111011110010100100111101111011001100010011110110101100110001001111001011
+1100110001001111011010110011000100111101101011001010010011110111011111111111
+11111111001010010011110111101100101001001111001111111111111111111111101111111111
+11111111111011111111111111111111101111001100010011110110101111111111111111111011
+1111111111111111111011111111111111111111101111111111111111111110111111111111
+11111111001011111111011110111100110111111101111011111111111111111111101111111111
+11111111111011111111111111111111101111111111111111111110111100110001001111011010
+1100110001001111011010110011000100111101101011001010010011110111011111111111
+*
+C489E*
+N User Electronic Signature Data*
+U00000000000000000000000000000000*
+46DE
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
new file mode 100644
index 0000000..d0353b8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
new file mode 100644
index 0000000..2743d95
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 200.000000 MHz;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
new file mode 100644
index 0000000..f0b54bc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
@@ -0,0 +1,5981 @@
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
new file mode 100644
index 0000000..279152d
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
@@ -0,0 +1,402 @@
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
+     CMXO640C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:33:30
+
+Design Summary
+--------------
+
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        65 out of   320 (20%)
+      SLICEs as Logic/ROM:     65 out of   320 (20%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        129 out of   640 (20%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+Design Summary (cont)
+---------------------
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+Removed logic
+-------------
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+
+                                    Page 5
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+Run Time and Memory Usage (cont)
+--------------------------------
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+                                    Page 6
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
new file mode 100644
index 0000000..2d70ad1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
@@ -0,0 +1,9 @@
+-v
+1
+
+
+-gt
+
+
+-mapchkpnt 0
+-sethld
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
new file mode 100644
index 0000000..c5da0e1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
@@ -0,0 +1,574 @@
+
+comp 0: SLICE_0 (FSLICE)
+
+comp 1: SLICE_1 (FSLICE)
+
+comp 2: SLICE_2 (FSLICE)
+
+comp 3: SLICE_3 (FSLICE)
+
+comp 4: SLICE_4 (FSLICE)
+
+comp 5: SLICE_5 (FSLICE)
+
+comp 6: SLICE_6 (FSLICE)
+
+comp 7: SLICE_7 (FSLICE)
+
+comp 8: SLICE_8 (FSLICE)
+
+comp 9: SLICE_9 (FSLICE)
+n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234)
+ADSubmitted.D = n1361
+ADSubmitted.CLK = ~PHI2_c
+ADSubmitted.SP = VCC
+ADSubmitted.LSR = C1Submitted_N_225
+n2080 = (~MAin_c_0*(~ADSubmitted*n2122))
+
+comp 10: SLICE_14 (FSLICE)
+n2386 = GND
+C1Submitted.D = n2386
+C1Submitted.CLK = ~PHI2_c
+C1Submitted.SP = PHI2_N_114_enable_1
+C1Submitted.LSR = C1Submitted_N_225
+n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108)))
+
+comp 11: SLICE_18 (FSLICE)
+CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225)
+CmdEnable.D = CmdEnable_N_236
+CmdEnable.CLK = ~PHI2_c
+CmdEnable.SP = PHI2_N_114_enable_8
+CmdEnable.LSR = GND
+XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1)))
+
+comp 12: SLICE_19 (FSLICE)
+n2387\000/BUF1 = VCC
+CmdSubmitted.D = n2387\000/BUF1
+CmdSubmitted.CLK = ~PHI2_c
+CmdSubmitted.SP = PHI2_N_114_enable_6
+CmdSubmitted.LSR = GND
+n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3))
+
+comp 13: SLICE_23 (FSLICE)
+Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN)
+Cmdn8MEGEN.D = Cmdn8MEGEN_N_248
+Cmdn8MEGEN.CLK = ~PHI2_c
+Cmdn8MEGEN.SP = PHI2_N_114_enable_6
+Cmdn8MEGEN.LSR = GND
+n2296 = (~Din_c_4+(Din_c_6+Din_c_7))
+
+comp 14: SLICE_25 (FSLICE)
+n2387 = VCC
+InitReady.D = n2387
+InitReady.CLK = RCLK_c
+InitReady.SP = RCLK_c_enable_6
+InitReady.LSR = GND
+RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3)))
+
+comp 15: SLICE_31 (FSLICE)
+RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG)
+RA_c.D = RA11_N_180
+RA_c.CLK = PHI2_c
+RA_c.SP = VCC
+RA_c.LSR = ~Ready
+n2385 = (Din_c_6+Din_c_7)
+
+comp 16: SLICE_33 (FSLICE)
+RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116)
+RCKEEN.D = RCKEEN_N_115
+RCKEEN.CLK = RCLK_c
+RCKEEN.SP = RCLK_c_enable_4
+RCKEEN.LSR = GND
+RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308))
+
+comp 17: SLICE_34 (FSLICE)
+RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN))
+RCKE_c.D = RCKE_N_128
+RCKE_c.CLK = RCLK_c
+RCKE_c.SP = VCC
+RCKE_c.LSR = GND
+nRWE_N_178 = (~RCKE_c+RASr2)
+CASr2.D = CASr
+CASr2.CLK = RCLK_c
+CASr2.SP = VCC
+CASr2.LSR = GND
+
+comp 18: SLICE_35 (FSLICE)
+n2387\001/BUF1 = VCC
+Ready.D = n2387\001/BUF1
+Ready.CLK = RCLK_c
+Ready.SP = Ready_N_268
+Ready.LSR = GND
+RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready)))
+
+comp 19: SLICE_42 (FSLICE)
+UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK))
+UFMCLK_c.D = UFMCLK_N_212
+UFMCLK_c.CLK = RCLK_c
+UFMCLK_c.SP = RCLK_c_enable_24
+UFMCLK_c.LSR = n2291
+RCLK_c_enable_6 = (n2076*FS_10)
+
+comp 20: SLICE_43 (FSLICE)
+UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI)
+UFMSDI_c.D = UFMSDI_N_219
+UFMSDI_c.CLK = RCLK_c
+UFMSDI_c.SP = RCLK_c_enable_24
+UFMSDI_c.LSR = n2291
+n1895 = (~FS_10*(n2103*(~n2293*FS_6)))
+
+comp 21: SLICE_55 (FSLICE)
+n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready)
+n980.D = n2128
+n980.CLK = RCLK_c
+n980.SP = VCC
+n980.LSR = ~nRWE_N_173
+n2301 = (~InitReady+~RASr2)
+
+comp 22: SLICE_56 (FSLICE)
+n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN)
+n8MEGEN.D = n8MEGEN_N_94
+n8MEGEN.CLK = RCLK_c
+n8MEGEN.SP = RCLK_c_enable_7
+n8MEGEN.LSR = GND
+n4 = ((~FS_11+n2300)+InitReady)
+
+comp 23: SLICE_58 (FSLICE)
+nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287)
+nRCAS_c.D = nRCAS_N_157
+nRCAS_c.CLK = RCLK_c
+nRCAS_c.SP = RCLK_c_enable_4
+nRCAS_c.LSR = GND
+n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR)))
+
+comp 24: SLICE_60 (FSLICE)
+nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready)
+nRCS_c.D = nRCS_N_132
+nRCS_c.CLK = RCLK_c
+nRCS_c.SP = RCLK_c_enable_4
+nRCS_c.LSR = GND
+
+comp 25: SLICE_61 (FSLICE)
+n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18))
+nRRAS_c.D = n33
+nRRAS_c.CLK = RCLK_c
+nRRAS_c.SP = VCC
+nRRAS_c.LSR = GND
+n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32)
+RASr.D = ~nCRAS_c
+RASr.CLK = RCLK_c
+RASr.SP = VCC
+RASr.LSR = GND
+
+comp 26: SLICE_62 (FSLICE)
+n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS)
+nRWE_N_173.D = n705
+nRWE_N_173.CLK = RCLK_c
+nRWE_N_173.SP = RCLK_c_enable_23
+nRWE_N_173.LSR = GND
+nRCS_N_135.D = Ready_N_272
+nRCS_N_135.CLK = RCLK_c
+nRCS_N_135.SP = RCLK_c_enable_23
+nRCS_N_135.LSR = GND
+
+comp 27: SLICE_63 (FSLICE)
+nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174))
+nRWE_c.D = nRWE_N_167
+nRWE_c.CLK = RCLK_c
+nRWE_c.SP = RCLK_c_enable_3
+nRWE_c.LSR = GND
+nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178)
+
+comp 28: SLICE_64 (FSLICE)
+n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627))
+nRowColSel.D = n1368
+nRowColSel.CLK = RCLK_c
+nRowColSel.SP = VCC
+nRowColSel.LSR = n2299
+RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4)
+
+comp 29: SLICE_65 (FSLICE)
+n1628 = (nRowColSel_N_32+nRowColSel_N_33)
+nRowColSel_N_32.D = n1628
+nRowColSel_N_32.CLK = RCLK_c
+nRowColSel_N_32.SP = VCC
+nRowColSel_N_32.LSR = ~RASr2
+RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33)
+
+comp 30: SLICE_66 (FSLICE)
+n1135 = (RASr2*~nRowColSel_N_32)
+nRowColSel_N_33.D = n1135
+nRowColSel_N_33.CLK = RCLK_c
+nRowColSel_N_33.SP = VCC
+nRowColSel_N_33.LSR = ~nRowColSel_N_34
+n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34))
+
+comp 31: SLICE_67 (FSLICE)
+LED_N_90 = (~LEDEN+nCRAS_c)
+nRowColSel_N_34.D = n1135
+nRowColSel_N_34.CLK = RCLK_c
+nRowColSel_N_34.SP = VCC
+nRowColSel_N_34.LSR = ~nRowColSel_N_35
+n2154 = (MAin_c_4*Bank_7)
+
+comp 32: SLICE_68 (FSLICE)
+n2168 = (FS_3*(FS_2*(FS_0*FS_1)))
+nRowColSel_N_35.D = ~RASr2
+nRowColSel_N_35.CLK = RCLK_c
+nRowColSel_N_35.SP = VCC
+nRowColSel_N_35.LSR = GND
+n962 = (nCCAS_c+nFWE_c)
+CASr3.D = CASr2
+CASr3.CLK = RCLK_c
+CASr3.SP = VCC
+CASr3.LSR = GND
+
+comp 33: SLICE_69 (FSLICE)
+n1348 = (~InitReady*n2076+InitReady*n1369)
+nUFMCS_c.D = n1348
+nUFMCS_c.CLK = RCLK_c
+nUFMCS_c.SP = VCC
+nUFMCS_c.LSR = LEDEN_N_88
+n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15)))
+
+comp 34: i1912/SLICE_70 (FSLICE)
+n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready)
+
+comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE)
+RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35)
+
+comp 36: SLICE_72 (FSLICE)
+PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112)))
+n702.D = n703
+n702.CLK = RCLK_c
+n702.SP = RCLK_c_enable_23
+n702.LSR = GND
+n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4)
+n701.D = n702
+n701.CLK = RCLK_c
+n701.SP = RCLK_c_enable_23
+n701.LSR = GND
+
+comp 37: SLICE_73 (FSLICE)
+n11 = (~n2168+((~FS_11+n2300)+FS_6))
+n706.D = n707
+n706.CLK = RCLK_c
+n706.SP = RCLK_c_enable_23
+n706.LSR = GND
+n2300 = ((FS_16+n10)+FS_17)
+n705.D = n706
+n705.CLK = RCLK_c
+n705.SP = RCLK_c_enable_23
+n705.LSR = GND
+
+comp 38: SLICE_74 (FSLICE)
+C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122)))
+n710.D = n711
+n710.CLK = RCLK_c
+n710.SP = RCLK_c_enable_23
+n710.LSR = GND
+n2295 = (n2114*~nFWE_c)
+n709.D = n710
+n709.CLK = RCLK_c
+n709.SP = RCLK_c_enable_23
+n709.LSR = GND
+
+comp 39: SLICE_75 (FSLICE)
+n2119 = (~n12*(~n11*(FS_10*n2294)))
+n708.D = n709
+n708.CLK = RCLK_c
+n708.SP = RCLK_c_enable_23
+n708.LSR = GND
+RCLK_c_enable_25 = (n2119*(FS_5*~InitReady))
+n707.D = n708
+n707.CLK = RCLK_c
+n707.SP = RCLK_c_enable_23
+n707.LSR = GND
+
+comp 40: SLICE_76 (FSLICE)
+n2131 = ((~MAin_c_1+n1285)+MAin_c_0)
+WRD_0.D = Din_c_0
+WRD_0.CLK = ~nCCAS_c
+WRD_0.SP = VCC
+WRD_0.LSR = GND
+n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26)))
+WRD_1.D = Din_c_1
+WRD_1.CLK = ~nCCAS_c
+WRD_1.SP = VCC
+WRD_1.LSR = GND
+
+comp 41: SLICE_77 (FSLICE)
+PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290))
+RowA_2.D = MAin_c_2
+RowA_2.CLK = ~nCRAS_c
+RowA_2.SP = VCC
+RowA_2.LSR = ~Ready
+n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098))
+RowA_3.D = MAin_c_3
+RowA_3.CLK = ~nCRAS_c
+RowA_3.SP = VCC
+RowA_3.LSR = ~Ready
+
+comp 42: SLICE_78 (FSLICE)
+n10 = (((FS_14+FS_13)+FS_12)+FS_15)
+CASr.D = ~nCCAS_c
+CASr.CLK = RCLK_c
+CASr.SP = VCC
+CASr.LSR = GND
+n2294 = (((FS_16+n10)+FS_17)+FS_11)
+PHI2r2.D = PHI2r
+PHI2r2.CLK = RCLK_c
+PHI2r2.SP = VCC
+PHI2r2.LSR = GND
+
+comp 43: SLICE_79 (FSLICE)
+n1627 = (nRowColSel_N_34+nRowColSel_N_33)
+WRD_2.D = Din_c_2
+WRD_2.CLK = ~nCCAS_c
+WRD_2.SP = VCC
+WRD_2.LSR = GND
+RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35)
+WRD_3.D = Din_c_3
+WRD_3.CLK = ~nCCAS_c
+WRD_3.SP = VCC
+WRD_3.LSR = GND
+
+comp 44: SLICE_80 (FSLICE)
+ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108)))
+WRD_6.D = Din_c_6
+WRD_6.CLK = ~nCCAS_c
+WRD_6.SP = VCC
+WRD_6.LSR = GND
+n2289 = (~MAin_c_1+n1285)
+WRD_7.D = Din_c_7
+WRD_7.CLK = ~nCCAS_c
+WRD_7.SP = VCC
+WRD_7.LSR = GND
+
+comp 45: SLICE_81 (FSLICE)
+n4_adj_1 = (n2114*(Din_c_2*~nFWE_c))
+RowA_8.D = MAin_c_8
+RowA_8.CLK = ~nCRAS_c
+RowA_8.SP = VCC
+RowA_8.LSR = ~Ready
+n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0)))
+RowA_9.D = MAin_c_9
+RowA_9.CLK = ~nCRAS_c
+RowA_9.SP = VCC
+RowA_9.LSR = ~Ready
+
+comp 46: SLICE_82 (FSLICE)
+n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0)))
+RowA_0.D = MAin_c_0
+RowA_0.CLK = ~nCRAS_c
+RowA_0.SP = VCC
+RowA_0.LSR = ~Ready
+n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2)))
+RowA_1.D = MAin_c_1
+RowA_1.CLK = ~nCRAS_c
+RowA_1.SP = VCC
+RowA_1.LSR = ~Ready
+
+comp 47: SLICE_83 (FSLICE)
+n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32)))
+CmdUFMCLK.D = Din_c_1
+CmdUFMCLK.CLK = ~PHI2_c
+CmdUFMCLK.SP = PHI2_N_114_enable_7
+CmdUFMCLK.LSR = GND
+Ready_N_268 = (n2245+Ready)
+CmdUFMCS.D = Din_c_2
+CmdUFMCS.CLK = ~PHI2_c
+CmdUFMCS.SP = PHI2_N_114_enable_7
+CmdUFMCS.LSR = GND
+
+comp 48: SLICE_84 (FSLICE)
+nRowColSel_N_28 = ((~FWEr+CASr3)+CBR)
+nRCAS_N_161.D = nRCS_N_135
+nRCAS_N_161.CLK = RCLK_c
+nRCAS_N_161.SP = RCLK_c_enable_23
+nRCAS_N_161.LSR = GND
+n1 = (~CASr3*(CASr2*(FWEr*~CBR)))
+n703.D = nRWE_N_173
+n703.CLK = RCLK_c
+n703.SP = RCLK_c_enable_23
+n703.LSR = GND
+
+comp 49: SLICE_85 (FSLICE)
+n12 = (((~FS_4+FS_9)+FS_8)+FS_7)
+PHI2r3.D = PHI2r2
+PHI2r3.CLK = RCLK_c
+PHI2r3.SP = VCC
+PHI2r3.LSR = GND
+n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8)))
+PHI2r.D = PHI2_c
+PHI2r.CLK = RCLK_c
+PHI2r.SP = VCC
+PHI2r.LSR = GND
+
+comp 50: SLICE_86 (FSLICE)
+n2291 = (~InitReady*(~n2300*~FS_11))
+RowA_6.D = MAin_c_6
+RowA_6.CLK = ~nCRAS_c
+RowA_6.SP = VCC
+RowA_6.LSR = ~Ready
+LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11)))
+RowA_7.D = MAin_c_7
+RowA_7.CLK = ~nCRAS_c
+RowA_7.SP = VCC
+RowA_7.LSR = ~Ready
+
+comp 51: SLICE_87 (FSLICE)
+n2122 = (~Din_c_5*(Din_c_6*~Din_c_3))
+Ready_N_272.D = n699
+Ready_N_272.CLK = RCLK_c
+Ready_N_272.SP = RCLK_c_enable_23
+Ready_N_272.LSR = GND
+n2108 = (Din_c_3*(Din_c_5*~Din_c_6))
+n711.D = nRCAS_N_161
+n711.CLK = RCLK_c
+n711.SP = RCLK_c_enable_23
+n711.LSR = GND
+
+comp 52: SLICE_88 (FSLICE)
+RDQMH_c = (~nRowColSel+MAin_c_9)
+CmdUFMSDI.D = Din_c_0
+CmdUFMSDI.CLK = ~PHI2_c
+CmdUFMSDI.SP = PHI2_N_114_enable_7
+CmdUFMSDI.LSR = GND
+RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9)
+
+comp 53: SLICE_89 (FSLICE)
+n2290 = (nFWE_c+n1285)
+LEDEN.D = ~UFMSDO_c
+LEDEN.CLK = RCLK_c
+LEDEN.SP = RCLK_c_enable_25
+LEDEN.LSR = GND
+PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c))
+
+comp 54: SLICE_90 (FSLICE)
+PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6)))
+n700.D = n701
+n700.CLK = RCLK_c
+n700.SP = RCLK_c_enable_23
+n700.LSR = GND
+PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385)))
+n699.D = n700
+n699.CLK = RCLK_c
+n699.SP = RCLK_c_enable_23
+n699.LSR = GND
+
+comp 55: SLICE_91 (FSLICE)
+n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135))
+CBR.D = ~nCCAS_c
+CBR.CLK = ~nCRAS_c
+CBR.SP = VCC
+CBR.LSR = GND
+n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135)))
+FWEr.D = ~nFWE_c
+FWEr.CLK = ~nCRAS_c
+FWEr.SP = VCC
+FWEr.LSR = GND
+
+comp 56: SLICE_92 (FSLICE)
+RDQML_c = (~nRowColSel+~MAin_c_9)
+RowA_4.D = MAin_c_4
+RowA_4.CLK = ~nCRAS_c
+RowA_4.SP = VCC
+RowA_4.LSR = ~Ready
+RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0)
+RowA_5.D = MAin_c_5
+RowA_5.CLK = ~nCRAS_c
+RowA_5.SP = VCC
+RowA_5.LSR = ~Ready
+
+comp 57: SLICE_93 (FSLICE)
+n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14)))
+RASr2.D = RASr
+RASr2.CLK = RCLK_c
+RASr2.SP = VCC
+RASr2.LSR = GND
+n2293 = (~FS_11+((FS_16+n10)+FS_17))
+RASr3.D = RASr2
+RASr3.CLK = RCLK_c
+RASr3.SP = VCC
+RASr3.LSR = GND
+
+comp 58: SLICE_94 (FSLICE)
+RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1)
+Bank_0.D = Din_c_0
+Bank_0.CLK = PHI2_c
+Bank_0.SP = VCC
+Bank_0.LSR = GND
+RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3)
+Bank_1.D = Din_c_1
+Bank_1.CLK = PHI2_c
+Bank_1.SP = VCC
+Bank_1.LSR = GND
+
+comp 59: SLICE_95 (FSLICE)
+RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8)
+Bank_6.D = Din_c_6
+Bank_6.CLK = PHI2_c
+Bank_6.SP = VCC
+Bank_6.LSR = GND
+RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2)
+Bank_7.D = Din_c_7
+Bank_7.CLK = PHI2_c
+Bank_7.SP = VCC
+Bank_7.LSR = GND
+
+comp 60: SLICE_96 (FSLICE)
+n2299 = (~Ready+nRowColSel_N_35)
+XOR8MEG.D = Din_c_0
+XOR8MEG.CLK = ~PHI2_c
+XOR8MEG.SP = PHI2_N_114_enable_2
+XOR8MEG.LSR = GND
+n2297 = (~nRowColSel_N_35+nRCS_N_135)
+
+comp 61: SLICE_97 (FSLICE)
+RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7)
+Bank_4.D = Din_c_4
+Bank_4.CLK = PHI2_c
+Bank_4.SP = VCC
+Bank_4.LSR = GND
+n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7)))
+Bank_5.D = Din_c_5
+Bank_5.CLK = PHI2_c
+Bank_5.SP = VCC
+Bank_5.LSR = GND
+
+comp 62: SLICE_98 (FSLICE)
+RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6)
+Bank_2.D = Din_c_2
+Bank_2.CLK = PHI2_c
+Bank_2.SP = VCC
+Bank_2.LSR = GND
+RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5)
+Bank_3.D = Din_c_3
+Bank_3.CLK = PHI2_c
+Bank_3.SP = VCC
+Bank_3.LSR = GND
+
+comp 63: SLICE_99 (FSLICE)
+n2164 = (nRCAS_N_161+nRWE_N_173)
+RBA_c_0.D = CROW_c_0
+RBA_c_0.CLK = ~nCRAS_c
+RBA_c_0.SP = VCC
+RBA_c_0.LSR = ~Ready
+n18 = (nRowColSel_N_34*~nRowColSel_N_35)
+RBA_c_1.D = CROW_c_1
+RBA_c_1.CLK = ~nCRAS_c
+RBA_c_1.SP = VCC
+RBA_c_1.LSR = ~Ready
+
+comp 64: SLICE_100 (FSLICE)
+n11_adj_3 = (~CASr2+nRowColSel_N_33)
+WRD_4.D = Din_c_4
+WRD_4.CLK = ~nCCAS_c
+WRD_4.SP = VCC
+WRD_4.LSR = GND
+n2304 = (FWEr+CBR)
+WRD_5.D = Din_c_5
+WRD_5.CLK = ~nCCAS_c
+WRD_5.SP = VCC
+WRD_5.LSR = GND
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd
new file mode 100644
index 0000000..fa3d127
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd
new file mode 100644
index 0000000..94dd6bf
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t
new file mode 100644
index 0000000..16daf53
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t
@@ -0,0 +1,9 @@
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t
new file mode 100644
index 0000000..221332e
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "RAM2GS_LCMXO640C_impl1.log"
+-o "RAM2GS_LCMXO640C_impl1.csv"
+-pr "RAM2GS_LCMXO640C_impl1.prf"
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
new file mode 100644
index 0000000..bcb27b5
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
@@ -0,0 +1,353 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Mon Aug 16 21:33:36 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | Properties                       |
++-----------+----------+--------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVTTL33_IN   | PB4C  | SLEW:FAST                        |
+| CROW[1]   | 34/2     | LVTTL33_IN   | PB4E  | SLEW:FAST                        |
+| Din[0]    | 21/3     | LVTTL33_IN   | PL10C | SLEW:FAST                        |
+| Din[1]    | 15/3     | LVTTL33_IN   | PL7B  | SLEW:FAST                        |
+| Din[2]    | 14/3     | LVTTL33_IN   | PL5B  | SLEW:FAST                        |
+| Din[3]    | 16/3     | LVTTL33_IN   | PL8C  | SLEW:FAST                        |
+| Din[4]    | 18/3     | LVTTL33_IN   | PL9A  | SLEW:FAST                        |
+| Din[5]    | 17/3     | LVTTL33_IN   | PL8D  | SLEW:FAST                        |
+| Din[6]    | 20/3     | LVTTL33_IN   | PL10A | SLEW:FAST                        |
+| Din[7]    | 19/3     | LVTTL33_IN   | PL9C  | SLEW:FAST                        |
+| Dout[0]   | 1/3      | LVTTL33_OUT  | PL2A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/3      | LVTTL33_OUT  | PL3C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/3      | LVTTL33_OUT  | PL3D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/3      | LVTTL33_OUT  | PL3B  | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/3      | LVTTL33_OUT  | PL2D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/3      | LVTTL33_OUT  | PL3A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/3      | LVTTL33_OUT  | PL2C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/3      | LVTTL33_OUT  | PL2B  | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/1     | LVTTL33_OUT  | PR10B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVTTL33_IN   | PL11C | SLEW:FAST                        |
+| MAin[1]   | 38/2     | LVTTL33_IN   | PB6B  | SLEW:FAST                        |
+| MAin[2]   | 37/2     | LVTTL33_IN   | PB5D  | SLEW:FAST                        |
+| MAin[3]   | 47/2     | LVTTL33_IN   | PB9C  | SLEW:FAST                        |
+| MAin[4]   | 46/2     | LVTTL33_IN   | PB9A  | SLEW:FAST                        |
+| MAin[5]   | 45/2     | LVTTL33_IN   | PB8D  | SLEW:FAST                        |
+| MAin[6]   | 49/2     | LVTTL33_IN   | PB9D  | SLEW:FAST                        |
+| MAin[7]   | 44/2     | LVTTL33_IN   | PB8C  | SLEW:FAST                        |
+| MAin[8]   | 50/2     | LVTTL33_IN   | PB9F  | SLEW:FAST                        |
+| MAin[9]   | 51/1     | LVTTL33_IN   | PR11D | SLEW:FAST                        |
+| PHI2      | 39/2     | LVTTL33_IN   | PB6C  | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVTTL33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT5B  | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVTTL33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVTTL33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVTTL33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVTTL33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVTTL33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVTTL33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVTTL33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVTTL33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVTTL33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVTTL33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVTTL33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVTTL33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVTTL33_IN   | PB2C  | SLEW:FAST                        |
+| nCRAS     | 43/2     | LVTTL33_IN   | PB8B  | SLEW:FAST                        |
+| nFWE      | 22/3     | LVTTL33_IN   | PL11A | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVTTL33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVTTL33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVTTL33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site  | Dual Function |
++----------+---------------------+------------+--------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |              | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |              | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |              | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVTTL33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVTTL33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVTTL33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVTTL33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVTTL33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVTTL33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVTTL33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVTTL33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVTTL33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |              | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVTTL33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVTTL33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |              | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |              | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVTTL33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |              | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVTTL33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVTTL33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |              | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |              | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |              | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |              | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |              | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |              | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |              | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |              | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |              | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |              | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |              | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |              | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |              | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |              | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |              | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |              | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |              | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |              | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |              | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |              | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |              | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |              | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |              | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |              | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |              | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |              | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |              | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |              | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |              | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |              | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |              | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |              | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |              | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |              | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |              | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |              | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |              | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |              | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |              | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |              | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |              | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |              | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |              | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |              | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |              | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |              | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |              | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |              | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |              | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |              | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |              | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |              | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |              | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |              | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |              | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |              | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |              | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |              | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |              | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |              | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |              | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |              | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |              | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |              | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |              | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |              | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |              | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |              | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |              | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |              | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |              | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |              | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |              | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |              | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |              | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |              | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |              | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |              | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |              | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |              | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |              | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |              | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |              | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |              | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |              | PT9D  |               |
+| TCK/2    |                     |            |              | TCK   | TCK           |
+| TDI/2    |                     |            |              | TDI   | TDID0         |
+| TDO/2    |                     |            |              | TDO   | TDO           |
+| TMS/2    |                     |            |              | TMS   | TMS           |
++----------+---------------------+------------+--------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:36 2021
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
new file mode 100644
index 0000000..e8b79d9
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
@@ -0,0 +1,247 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:31 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.213        0            0.339        0            06           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Mon Aug 16 21:33:31 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             65/320          20% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.......
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 1105164.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1103986
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 160 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PB2C)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 21:33:36 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:33:36 08/16/21
+
+Start NBR section for initial routing at 21:33:36 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.339
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
new file mode 100644
index 0000000..8dceb1f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
@@ -0,0 +1,165 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
new file mode 100644
index 0000000..916dbc3
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 3
+-sphld m
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
new file mode 100644
index 0000000..aa05f83
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
@@ -0,0 +1,2 @@
+
+-g ES:No
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
new file mode 100644
index 0000000..21ca4c4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
@@ -0,0 +1,2507 @@
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
new file mode 100644
index 0000000..546895c
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
@@ -0,0 +1,4338 @@
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.373ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.790ns physical path delay SLICE_95 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.774ns physical path delay SLICE_95 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_18 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
+ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_9 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.025ns physical path delay SLICE_97 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   27.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 6.557ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.262ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.246ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.866ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.890ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
+CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.963ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.856ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.979ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.840ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.065ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.691ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
+CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.472ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
+CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.601ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.155ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
+CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.732ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.087ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.748ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.071ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    9.443ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.088ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
+     12.500ns offset RCLK to RA[9] by 2.088ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:   10.412ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.035ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
+     12.500ns offset RCLK to RA[8] by 2.035ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:   10.465ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.583ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
+     12.500ns offset RCLK to RA[7] by 2.583ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:    9.917ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[6] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[5] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.742ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
+     12.500ns offset RCLK to RA[4] by 1.742ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
+
+Report:   10.758ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.725ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
+     12.500ns offset RCLK to RA[3] by 1.725ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.775ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.643ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
+     12.500ns offset RCLK to RA[2] by 1.643ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
+
+Report:   10.857ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.417ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
+     12.500ns offset RCLK to RA[1] by 1.417ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
+
+Report:   11.083ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.213ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
+     12.500ns offset RCLK to RA[0] by 1.213ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
+
+Report:   11.287ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
+     12.500ns offset RCLK to nRWE by 3.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
+
+Report:    9.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.325ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
+     12.500ns offset RCLK to nRRAS by 3.325ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
+
+Report:    9.175ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
+     12.500ns offset RCLK to RDQMH by 2.669ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.831ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
+     12.500ns offset RCLK to RDQML by 3.383ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    9.117ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.113ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.118ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.089ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.270ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.241ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
+ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
+CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.276ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.247ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.299ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.270ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
+CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
+ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
+CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.779ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.455ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
+CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
+ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
+CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
+ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_85 to SLICE_78 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_85 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
+ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_78 to SLICE_85 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
+ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.668ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.668ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    2.668ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.689ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.689ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
+
+Report:    2.689ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.572ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.572ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.572ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.776ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.776ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
+
+Report:    2.776ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.772ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.772ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
+
+Report:    2.772ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.787ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.787ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
+
+Report:    2.787ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:    2.855ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.893ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.893ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
+
+Report:    2.893ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.356ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.356ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    2.356ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.523ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.523ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
+
+Report:    2.523ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.351ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
+
+Report:    2.351ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
new file mode 100644
index 0000000..b9ec128
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
@@ -0,0 +1,111 @@
+
+Bitgen Report
+
+
+
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:36:33 2021
+
+
+Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+
+
+
    
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+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
new file mode 100644
index 0000000..4d7032d
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
@@ -0,0 +1,202 @@
+
+I/O Timing Report
+
+
+
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:33:38 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.474      3       1.625     3
+CROW[1] nCRAS F     0.104      3       1.925     3
+Din[0]  PHI2  F     6.682      3       1.613     3
+Din[0]  nCCAS F    -0.028      M       2.082     3
+Din[1]  PHI2  F     6.886      3       2.631     3
+Din[1]  nCCAS F    -0.025      M       2.074     3
+Din[2]  PHI2  F     5.426      3       1.921     3
+Din[2]  nCCAS F     1.175      3       1.003     3
+Din[3]  PHI2  F     5.699      3       1.852     3
+Din[3]  nCCAS F     0.331      3       1.707     3
+Din[4]  PHI2  F     6.556      3       1.438     3
+Din[4]  nCCAS F     0.706      3       1.406     3
+Din[5]  PHI2  F     6.281      3       1.959     3
+Din[5]  nCCAS F     0.246      3       1.807     3
+Din[6]  PHI2  F     5.585      3       1.441     3
+Din[6]  nCCAS F     0.799      3       1.341     3
+Din[7]  PHI2  F     7.980      3       1.725     3
+Din[7]  nCCAS F     0.333      3       1.707     3
+MAin[0] PHI2  F     4.994      3       1.265     3
+MAin[0] nCRAS F     0.662      3       1.471     3
+MAin[1] PHI2  F     6.056      3       1.867     3
+MAin[1] nCRAS F     1.180      3       0.990     3
+MAin[2] PHI2  F    10.634      3      -1.183     M
+MAin[2] nCRAS F    -0.218      M       2.631     3
+MAin[3] PHI2  F    10.902      3      -1.260     M
+MAin[3] nCRAS F     0.208      3       1.826     3
+MAin[4] PHI2  F    10.204      3      -1.072     M
+MAin[4] nCRAS F    -0.218      M       2.628     3
+MAin[5] PHI2  F     7.043      3      -0.270     M
+MAin[5] nCRAS F     0.123      3       1.925     3
+MAin[6] PHI2  F     9.465      3      -0.885     M
+MAin[6] nCRAS F     0.584      3       1.522     3
+MAin[7] PHI2  F     9.683      3      -0.938     M
+MAin[7] nCRAS F    -0.218      M       2.628     3
+MAin[8] nCRAS F     0.316      3       1.758     3
+MAin[9] nCRAS F    -0.058      M       2.185     3
+PHI2    RCLK  R     1.456      3       0.038     3
+UFMSDO  RCLK  R     2.953      3      -0.147     M
+nCCAS   RCLK  R     2.435      3      -0.244     M
+nCCAS   nCRAS F     0.156      3       1.902     3
+nCRAS   RCLK  R     5.307      3      -0.787     M
+nFWE    PHI2  F     5.614      3       1.072     3
+nFWE    nCRAS F    -0.101      M       2.317     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.635         3        3.019          M
+RA[0]  RCLK  R    11.287         3        2.893          M
+RA[0]  nCRAS F    15.323         3        3.902          M
+RA[10] RCLK  R     7.501         3        1.949          M
+RA[11] PHI2  R     9.747         3        2.487          M
+RA[1]  RCLK  R    11.083         3        2.855          M
+RA[1]  nCRAS F    12.034         3        3.047          M
+RA[2]  RCLK  R    10.857         3        2.787          M
+RA[2]  nCRAS F    13.411         3        3.403          M
+RA[3]  RCLK  R    10.775         3        2.772          M
+RA[3]  nCRAS F    12.977         3        3.296          M
+RA[4]  RCLK  R    10.758         3        2.776          M
+RA[4]  nCRAS F    14.192         3        3.619          M
+RA[5]  RCLK  R    10.334         3        2.652          M
+RA[5]  nCRAS F    13.484         3        3.424          M
+RA[6]  RCLK  R    10.334         3        2.652          M
+RA[6]  nCRAS F    12.972         3        3.291          M
+RA[7]  RCLK  R     9.917         3        2.572          M
+RA[7]  nCRAS F    12.327         3        3.147          M
+RA[8]  RCLK  R    10.465         3        2.689          M
+RA[8]  nCRAS F    12.559         3        3.170          M
+RA[9]  RCLK  R    10.412         3        2.668          M
+RA[9]  nCRAS F    14.019         3        3.564          M
+RBA[0] nCRAS F    11.063         3        2.809          M
+RBA[1] nCRAS F    11.902         3        3.028          M
+RCKE   RCLK  R     7.501         3        1.949          M
+RDQMH  RCLK  R     9.831         3        2.523          M
+RDQML  RCLK  R     9.117         3        2.351          M
+RD[0]  nCCAS F    12.575         3        3.249          M
+RD[1]  nCCAS F    13.016         3        3.365          M
+RD[2]  nCCAS F    11.602         3        2.993          M
+RD[3]  nCCAS F    10.893         3        2.834          M
+RD[4]  nCCAS F    12.063         3        3.116          M
+RD[5]  nCCAS F    12.555         3        3.242          M
+RD[6]  nCCAS F    12.537         3        3.240          M
+RD[7]  nCCAS F    12.524         3        3.239          M
+UFMCLK RCLK  R     8.079         3        2.126          M
+UFMSDI RCLK  R     8.079         3        2.126          M
+nRCAS  RCLK  R     7.501         3        1.949          M
+nRCS   RCLK  R     7.501         3        1.949          M
+nRRAS  RCLK  R     9.175         3        2.363          M
+nRWE   RCLK  R     9.141         3        2.356          M
+nUFMCS RCLK  R     8.804         3        2.290          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
new file mode 100644
index 0000000..f265fc9
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
@@ -0,0 +1,41 @@
+-a "MachXO"
+-d LCMXO640C
+-t TQFP100
+-s 3
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
+-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+-top RAM2GS
+
+
+-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
+
+-ngd "RAM2GS_LCMXO640C_impl1.ngd"
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
new file mode 100644
index 0000000..a946767
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
@@ -0,0 +1,13 @@
+[ActiveSupport MAP]
+Device = LCMXO640C;
+Package = TQFP100;
+Performance = 3;
+LUTS_avail = 640;
+LUTS_used = 129;
+FF_avail = 640;
+FF_used = 102;
+INPUT_LVTTL33 = 26;
+OUTPUT_LVTTL33 = 33;
+BIDI_LVTTL33 = 8;
+IO_avail = 74;
+IO_used = 67;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
new file mode 100644
index 0000000..4787547
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
@@ -0,0 +1,108 @@
+[ START MERGED ]
+nCRAS_N_9 nCRAS_c
+nCCAS_N_3 nCCAS_c
+n2307 Ready
+n2306 nFWE_c
+PHI2_N_114 PHI2_c
+n2302 nRowColSel_N_35
+nRWE_N_172 nRWE_N_173
+UFMSDO_N_74 UFMSDO_c
+n1377 nRowColSel_N_34
+RASr2_N_63 RASr2
+[ END MERGED ]
+[ START CLIPPED ]
+GND_net
+VCC_net
+FS_577_add_4_14/CO0
+FS_577_add_4_16/CO0
+FS_577_add_4_12/CO0
+FS_577_add_4_2/CO0
+FS_577_add_4_4/CO0
+FS_577_add_4_6/CO0
+FS_577_add_4_18/CO1
+FS_577_add_4_18/CO0
+FS_577_add_4_8/CO0
+FS_577_add_4_10/CO0
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
new file mode 100644
index 0000000..5a900d5
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
@@ -0,0 +1,10 @@
+---------------------------------------------------
+Report for cell RAM2GS
+   Instance path: RAM2GS
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      65.00        100.0
+                                  LUT4	     111.00        100.0
+                                 IOBUF	         67        100.0
+                                PFUREG	        102        100.0
+                                RIPPLE	          9        100.0
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd
new file mode 100644
index 0000000..f4f2deb
Binary files /dev/null and b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd differ
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
new file mode 100644
index 0000000..cee33ff
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
@@ -0,0 +1,425 @@
+
+Project Summary
+
+
+
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
+     CMXO640C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:33:30
+
+
+Design Summary
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        65 out of   320 (20%)
+      SLICEs as Logic/ROM:     65 out of   320 (20%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        129 out of   640 (20%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+
+        
+
+
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+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
new file mode 100644
index 0000000..ab78925
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
@@ -0,0 +1,418 @@
+
+PAD Specification File
+
+
+
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Mon Aug 16 21:33:36 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | Properties                       |
++-----------+----------+--------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVTTL33_IN   | PB4C  | SLEW:FAST                        |
+| CROW[1]   | 34/2     | LVTTL33_IN   | PB4E  | SLEW:FAST                        |
+| Din[0]    | 21/3     | LVTTL33_IN   | PL10C | SLEW:FAST                        |
+| Din[1]    | 15/3     | LVTTL33_IN   | PL7B  | SLEW:FAST                        |
+| Din[2]    | 14/3     | LVTTL33_IN   | PL5B  | SLEW:FAST                        |
+| Din[3]    | 16/3     | LVTTL33_IN   | PL8C  | SLEW:FAST                        |
+| Din[4]    | 18/3     | LVTTL33_IN   | PL9A  | SLEW:FAST                        |
+| Din[5]    | 17/3     | LVTTL33_IN   | PL8D  | SLEW:FAST                        |
+| Din[6]    | 20/3     | LVTTL33_IN   | PL10A | SLEW:FAST                        |
+| Din[7]    | 19/3     | LVTTL33_IN   | PL9C  | SLEW:FAST                        |
+| Dout[0]   | 1/3      | LVTTL33_OUT  | PL2A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/3      | LVTTL33_OUT  | PL3C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/3      | LVTTL33_OUT  | PL3D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/3      | LVTTL33_OUT  | PL3B  | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/3      | LVTTL33_OUT  | PL2D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/3      | LVTTL33_OUT  | PL3A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/3      | LVTTL33_OUT  | PL2C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/3      | LVTTL33_OUT  | PL2B  | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/1     | LVTTL33_OUT  | PR10B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVTTL33_IN   | PL11C | SLEW:FAST                        |
+| MAin[1]   | 38/2     | LVTTL33_IN   | PB6B  | SLEW:FAST                        |
+| MAin[2]   | 37/2     | LVTTL33_IN   | PB5D  | SLEW:FAST                        |
+| MAin[3]   | 47/2     | LVTTL33_IN   | PB9C  | SLEW:FAST                        |
+| MAin[4]   | 46/2     | LVTTL33_IN   | PB9A  | SLEW:FAST                        |
+| MAin[5]   | 45/2     | LVTTL33_IN   | PB8D  | SLEW:FAST                        |
+| MAin[6]   | 49/2     | LVTTL33_IN   | PB9D  | SLEW:FAST                        |
+| MAin[7]   | 44/2     | LVTTL33_IN   | PB8C  | SLEW:FAST                        |
+| MAin[8]   | 50/2     | LVTTL33_IN   | PB9F  | SLEW:FAST                        |
+| MAin[9]   | 51/1     | LVTTL33_IN   | PR11D | SLEW:FAST                        |
+| PHI2      | 39/2     | LVTTL33_IN   | PB6C  | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVTTL33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT5B  | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVTTL33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVTTL33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVTTL33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVTTL33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVTTL33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVTTL33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVTTL33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVTTL33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVTTL33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVTTL33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVTTL33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVTTL33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVTTL33_IN   | PB2C  | SLEW:FAST                        |
+| nCRAS     | 43/2     | LVTTL33_IN   | PB8B  | SLEW:FAST                        |
+| nFWE      | 22/3     | LVTTL33_IN   | PL11A | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVTTL33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVTTL33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVTTL33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site  | Dual Function |
++----------+---------------------+------------+--------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |              | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |              | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |              | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVTTL33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVTTL33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVTTL33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVTTL33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVTTL33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVTTL33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVTTL33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVTTL33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVTTL33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |              | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVTTL33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVTTL33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |              | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |              | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVTTL33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |              | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVTTL33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVTTL33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |              | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |              | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |              | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |              | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |              | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |              | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |              | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |              | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |              | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |              | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |              | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |              | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |              | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |              | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |              | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |              | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |              | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |              | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |              | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |              | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |              | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |              | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |              | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |              | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |              | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |              | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |              | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |              | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |              | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |              | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |              | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |              | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |              | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |              | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |              | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |              | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |              | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |              | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |              | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |              | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |              | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |              | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |              | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |              | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |              | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |              | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |              | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |              | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |              | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |              | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |              | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |              | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |              | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |              | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |              | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |              | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |              | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |              | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |              | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |              | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |              | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |              | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |              | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |              | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |              | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |              | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |              | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |              | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |              | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |              | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |              | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |              | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |              | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |              | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |              | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |              | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |              | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |              | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |              | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |              | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |              | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |              | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |              | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |              | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |              | PT9D  |               |
+| TCK/2    |                     |            |              | TCK   | TCK           |
+| TDI/2    |                     |            |              | TDI   | TDID0         |
+| TDO/2    |                     |            |              | TDO   | TDO           |
+| TMS/2    |                     |            |              | TMS   | TMS           |
++----------+---------------------+------------+--------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:36 2021
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
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+
    
+
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
new file mode 100644
index 0000000..ec4ec76
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
@@ -0,0 +1,315 @@
+
+Place & Route Report
+
+
+
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:31 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.213        0            0.339        0            06           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Mon Aug 16 21:33:31 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             65/320          20% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.......
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 1105164.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1103986
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 160 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PB2C)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 21:33:36 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:33:36 08/16/21
+
+Start NBR section for initial routing at 21:33:36 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 1.213ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.213
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
new file mode 100644
index 0000000..07ed1c1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
+
+
    
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    RAM2GS_LCMXO640C project summary
    Module Name:RAM2GS_LCMXO640CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO640C-3T100CDevice Family:MachXO
    Device Type:LCMXO640CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO640C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO640C_impl1.prf
    Product Version:3.12.0.240.2Patch Version:
    Updated:2021/08/16 21:36:37
    Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1
    Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
new file mode 100644
index 0000000..bdf2b16
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
@@ -0,0 +1,2740 @@
+
+Lattice Map TRACE Report
+
+
+
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
new file mode 100644
index 0000000..1e50adc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
@@ -0,0 +1,4571 @@
+
+Lattice TRACE Report
+
+
+
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.373ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.790ns physical path delay SLICE_95 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.774ns physical path delay SLICE_95 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_18 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
+ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_9 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.025ns physical path delay SLICE_97 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   27.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 6.557ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.262ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.246ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.866ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.890ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
+CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.963ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.856ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.979ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.840ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.065ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.691ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
+CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.472ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
+CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.601ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.155ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
+CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.732ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.087ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.748ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.071ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    9.443ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.088ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
+     12.500ns offset RCLK to RA[9] by 2.088ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:   10.412ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.035ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
+     12.500ns offset RCLK to RA[8] by 2.035ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:   10.465ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.583ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
+     12.500ns offset RCLK to RA[7] by 2.583ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:    9.917ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[6] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[5] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.742ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
+     12.500ns offset RCLK to RA[4] by 1.742ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
+
+Report:   10.758ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.725ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
+     12.500ns offset RCLK to RA[3] by 1.725ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.775ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.643ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
+     12.500ns offset RCLK to RA[2] by 1.643ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
+
+Report:   10.857ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.417ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
+     12.500ns offset RCLK to RA[1] by 1.417ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
+
+Report:   11.083ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.213ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
+     12.500ns offset RCLK to RA[0] by 1.213ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
+
+Report:   11.287ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
+     12.500ns offset RCLK to nRWE by 3.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
+
+Report:    9.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.325ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
+     12.500ns offset RCLK to nRRAS by 3.325ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
+
+Report:    9.175ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
+     12.500ns offset RCLK to RDQMH by 2.669ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.831ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
+     12.500ns offset RCLK to RDQML by 3.383ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    9.117ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.113ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.118ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.089ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.270ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.241ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
+ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
+CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.276ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.247ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.299ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.270ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
+CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
+ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
+CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.779ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.455ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
+CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
+ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
+CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
+ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_85 to SLICE_78 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_85 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
+ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_78 to SLICE_85 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
+ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.668ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.668ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    2.668ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.689ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.689ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
+
+Report:    2.689ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.572ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.572ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.572ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.776ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.776ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
+
+Report:    2.776ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.772ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.772ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
+
+Report:    2.772ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.787ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.787ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
+
+Report:    2.787ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:    2.855ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.893ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.893ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
+
+Report:    2.893ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.356ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.356ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    2.356ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.523ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.523ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
+
+Report:    2.523ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.351ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
+
+Report:    2.351ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
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+
    
+
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
new file mode 100644
index 0000000..7932ec0
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
@@ -0,0 +1,15 @@
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+    304 blocks expanded
+completed the first expansion
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
new file mode 100644
index 0000000..0779fdc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
@@ -0,0 +1,311 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:33:30 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
new file mode 100644
index 0000000..93ec74e
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
@@ -0,0 +1,376 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:33:30 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
new file mode 100644
index 0000000..9cec3ba
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
@@ -0,0 +1,789 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
+// Netlist written on Mon Aug 16 21:33:30 2021
+//
+// Verilog Description of module RAM2GS
+//
+
+module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
+            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
+            nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14])
+    input PHI2;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    input [9:0]MAin;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    input [1:0]CROW;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    input [7:0]Din;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    output [7:0]Dout;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    input nCCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    input nCRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    input nFWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
+    output LED;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
+    output [1:0]RBA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    output [11:0]RA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    inout [7:0]RD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    output nRCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
+    input RCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    output RCKE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
+    output nRWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
+    output nRRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
+    output nRCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
+    output RDQMH;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
+    output RDQML;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
+    output nUFMCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
+    output UFMCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
+    output UFMSDI;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
+    input UFMSDO;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
+    
+    wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    wire nCCAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    wire nCRAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13])
+    
+    wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, 
+        RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, 
+        Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, 
+        n2131, n33, PHI2_N_114_enable_2, n1;
+    wire [7:0]Bank;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16])
+    
+    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
+        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
+        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
+        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980;
+    wire [9:0]RowA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16])
+    
+    wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, 
+        RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
+    wire [7:0]WRD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15])
+    
+    wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, 
+        CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, 
+        CmdUFMCS, InitReady, Ready;
+    wire [17:0]FS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15])
+    
+    wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, 
+        n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, 
+        RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, 
+        nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, 
+        RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, 
+        n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, 
+        nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, 
+        n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, 
+        XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, 
+        RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, 
+        UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, 
+        UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, 
+        n699, n700, n701, n702, n703, n705, n706, n707, n708, 
+        n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, 
+        n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, 
+        n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, 
+        n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, 
+        n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, 
+        n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, 
+        n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, 
+        n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, 
+        Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, 
+        n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, 
+        n2297, n2154, n10, n2296, n2295;
+    
+    VHI i2 (.Z(VCC_net));
+    INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r2_350.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), 
+            .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
+    defparam i2_3_lut_4_lut.init = 16'h0800;
+    ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_3_lut.init = 16'hfdfd;
+    FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r3_351.GSR = "ENABLED";
+    FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr_352.GSR = "ENABLED";
+    FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr2_353.GSR = "ENABLED";
+    FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr3_354.GSR = "ENABLED";
+    FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr_355.GSR = "ENABLED";
+    FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr2_356.GSR = "ENABLED";
+    FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr3_357.GSR = "ENABLED";
+    FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam RA11_358.GSR = "ENABLED";
+    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i0.GSR = "ENABLED";
+    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i0.GSR = "ENABLED";
+    FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam FWEr_362.GSR = "ENABLED";
+    FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam CBR_363.GSR = "ENABLED";
+    FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), 
+            .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam ADSubmitted_380.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
+            .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca;
+    ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut.init = 16'h8888;
+    CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), 
+         .COUT1(n1878), .S0(n87), .S1(n86));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_10.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_10.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_10.INJECT1_0 = "NO";
+    defparam FS_577_add_4_10.INJECT1_1 = "NO";
+    FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5])
+    defparam RCKE_368.GSR = "ENABLED";
+    FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRCS_369.GSR = "ENABLED";
+    FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRowColSel_375.GSR = "ENABLED";
+    ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), 
+            .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
+    defparam n1_bdd_4_lut.init = 16'hf0dd;
+    ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
+            .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
+    defparam i2_3_lut_rep_31.init = 16'h0808;
+    ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
+            .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ;
+    defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff;
+    CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), 
+         .COUT1(n1877), .S0(n89), .S1(n88));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_8.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_8.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_8.INJECT1_0 = "NO";
+    defparam FS_577_add_4_8.INJECT1_1 = "NO";
+    ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), 
+            .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1_4_lut.init = 16'h0544;
+    ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), 
+            .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut.init = 16'h0040;
+    ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), 
+            .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i4_3_lut_4_lut.init = 16'hfdff;
+    FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i2.GSR = "ENABLED";
+    ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), 
+            .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_4_lut_adj_1.init = 16'hcfee;
+    FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRRAS_370.GSR = "ENABLED";
+    ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), 
+            .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ;
+    defparam i1055_3_lut_4_lut.init = 16'hffd0;
+    ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37])
+    defparam i2_3_lut.init = 16'hfdfd;
+    BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRCAS_371.GSR = "ENABLED";
+    FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), 
+            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRWE_372.GSR = "ENABLED";
+    FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam RA10_373.GSR = "ENABLED";
+    FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(RCKEEN));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam RCKEEN_374.GSR = "ENABLED";
+    ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), 
+            .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
+    defparam i2_4_lut.init = 16'h0008;
+    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RBA__i1.GSR = "ENABLED";
+    ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee;
+    ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), 
+            .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1248_4_lut.init = 16'hc5c0;
+    ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), 
+            .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe;
+    ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), 
+            .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1437_4_lut.init = 16'hcc5c;
+    FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRCS_N_135));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i0.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam i1_2_lut_adj_3.init = 16'hbbbb;
+    ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), 
+            .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i2_4_lut_adj_4.init = 16'h0008;
+    FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), 
+            .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam C1Submitted_379.GSR = "ENABLED";
+    FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam nUFMCS_388.GSR = "ENABLED";
+    ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
+    defparam m1_lut.init = 16'hffff;
+    ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), 
+            .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
+    defparam i2_4_lut_adj_5.init = 16'h0800;
+    ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
+    defparam i5_4_lut.init = 16'hfffb;
+    FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i0.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), 
+            .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
+    defparam i2_3_lut_adj_6.init = 16'h0202;
+    ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46])
+    defparam i1419_2_lut.init = 16'hbbbb;
+    ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), 
+            .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ;
+    defparam n50_bdd_4_lut_1911.init = 16'h03aa;
+    ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i1893_2_lut.init = 16'h7777;
+    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i0.GSR = "ENABLED";
+    ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), 
+            .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1858_4_lut.init = 16'h8000;
+    ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), 
+            .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
+    defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd;
+    ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), 
+            .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i22_4_lut.init = 16'hc0ca;
+    ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), 
+            .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i5_4_lut_adj_8.init = 16'h8000;
+    ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), 
+            .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1889_4_lut_then_4_lut.init = 16'h0355;
+    ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), 
+            .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1889_4_lut_else_4_lut.init = 16'hdfff;
+    CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), 
+         .S0(n79), .S1(n78));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_18.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_18.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_18.INJECT1_0 = "NO";
+    defparam FS_577_add_4_18.INJECT1_1 = "NO";
+    ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60])
+    defparam UFMSDO_I_0_1_lut.init = 16'h5555;
+    FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i3.GSR = "ENABLED";
+    ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), 
+            .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101;
+    ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), 
+            .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001;
+    ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), 
+            .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ;
+    defparam i1884_4_lut.init = 16'h0302;
+    FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r_349.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
+            .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe;
+    ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1830_2_lut_rep_13.init = 16'heeee;
+    PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244));
+    FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i1.GSR = "ENABLED";
+    ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1886_2_lut.init = 16'h4444;
+    ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), 
+            .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ;
+    defparam n50_bdd_4_lut.init = 16'h3fbf;
+    ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), 
+            .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1034_2_lut.init = 16'heeee;
+    ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), 
+            .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i2_3_lut_4_lut_adj_9.init = 16'h1000;
+    ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), 
+            .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef;
+    FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i4.GSR = "ENABLED";
+    ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1424_2_lut_rep_27.init = 16'heeee;
+    ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
+    defparam i2_3_lut_adj_10.init = 16'h0404;
+    ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
+    defparam i1429_2_lut_3_lut.init = 16'h1f1f;
+    ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), 
+            .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i4_4_lut.init = 16'hfffe;
+    ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i5_3_lut_rep_23.init = 16'hfefe;
+    ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), 
+            .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1_4_lut_adj_11.init = 16'hfaee;
+    ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
+            .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff;
+    ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), 
+            .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_12.init = 16'h0040;
+    ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), 
+            .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_adj_13.init = 16'heeee;
+    ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1420_2_lut.init = 16'heeee;
+    ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ;
+    defparam i1_1_lut_rep_29.init = 16'h5555;
+    ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), 
+            .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7])
+    defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5;
+    ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1069_1_lut.init = 16'h5555;
+    ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), 
+            .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
+    defparam n2080_bdd_4_lut.init = 16'hca00;
+    ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46])
+    defparam RASr2_I_0_1_lut.init = 16'h5555;
+    ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), 
+            .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22])
+    defparam i847_2_lut_4_lut.init = 16'h0100;
+    ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), 
+            .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
+    defparam i1_4_lut_adj_14.init = 16'h0080;
+    ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16])
+    defparam i1_2_lut_adj_15.init = 16'hbbbb;
+    FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i17.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), 
+            .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
+    defparam i1_2_lut_3_lut_3_lut.init = 16'h4040;
+    FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i16.GSR = "ENABLED";
+    FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i15.GSR = "ENABLED";
+    ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), 
+            .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6])
+    defparam nRWE_I_0_428_4_lut.init = 16'hcfc5;
+    ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1257_3_lut.init = 16'hcaca;
+    ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), 
+            .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55])
+    defparam RCKE_I_0_423_4_lut.init = 16'hcfc8;
+    FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
+            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5])
+    defparam InitReady_367.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), 
+            .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_adj_16.init = 16'heeee;
+    ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1854_2_lut.init = 16'heeee;
+    ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
+            .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe;
+    ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i1881_2_lut_rep_24.init = 16'h7777;
+    GSR GSR_INST (.GSR(VCC_net));
+    ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ;
+    defparam i1_2_lut_rep_18_2_lut.init = 16'h4444;
+    FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i14.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26])
+    defparam i2_3_lut_3_lut.init = 16'h4040;
+    ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
+    defparam i2_3_lut_adj_17.init = 16'h4040;
+    ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), 
+            .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam i2_4_lut_adj_18.init = 16'h0020;
+    ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), 
+            .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11])
+    defparam i1_4_lut_adj_19.init = 16'h1044;
+    FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), 
+            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam XOR8MEG_381.GSR = "ENABLED";
+    FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), 
+            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam n8MEGEN_391.GSR = "ENABLED";
+    FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam Ready_377.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
+            .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca;
+    FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMCLK_386.GSR = "ENABLED";
+    FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMSDI_387.GSR = "ENABLED";
+    FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), 
+            .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam Cmdn8MEGEN_383.GSR = "ENABLED";
+    FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), 
+            .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdSubmitted_384.GSR = "ENABLED";
+    CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), 
+         .COUT1(n1876), .S0(n91), .S1(n90));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_6.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_6.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_6.INJECT1_0 = "NO";
+    defparam FS_577_add_4_6.INJECT1_1 = "NO";
+    FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMCS_385.GSR = "ENABLED";
+    FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i13.GSR = "ENABLED";
+    ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34])
+    defparam i1875_2_lut.init = 16'hbbbb;
+    FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i12.GSR = "ENABLED";
+    PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), 
+          .Z(RCKEEN_N_116));
+    ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), 
+            .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1856_4_lut.init = 16'h8000;
+    FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i11.GSR = "ENABLED";
+    ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1844_2_lut.init = 16'h8888;
+    ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51])
+    defparam RA11_I_53_3_lut.init = 16'hc6c6;
+    ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), 
+            .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ;
+    defparam Ready_bdd_3_lut_1922.init = 16'hefef;
+    FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), 
+            .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam UFMSDI_390.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
+            .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca;
+    ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i604_1_lut_rep_30.init = 16'h5555;
+    FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i10.GSR = "ENABLED";
+    FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i9.GSR = "ENABLED";
+    FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i8.GSR = "ENABLED";
+    FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i7.GSR = "ENABLED";
+    FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i6.GSR = "ENABLED";
+    FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i5.GSR = "ENABLED";
+    FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i4.GSR = "ENABLED";
+    FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i3.GSR = "ENABLED";
+    FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i2.GSR = "ENABLED";
+    FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i1.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(Ready_N_272));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i15.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n699));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i14.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n700));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i13.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n701));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i12.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n702));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i11.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n703));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i10.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRWE_N_173));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i9.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n705));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i8.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n706));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i7.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n707));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i6.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n708));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i5.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n709));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i4.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n710));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n711));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i2.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRCAS_N_161));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i1.GSR = "ENABLED";
+    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RBA__i2.GSR = "ENABLED";
+    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i7.GSR = "ENABLED";
+    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i6.GSR = "ENABLED";
+    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i5.GSR = "ENABLED";
+    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i4.GSR = "ENABLED";
+    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i3.GSR = "ENABLED";
+    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i1.GSR = "ENABLED";
+    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i9.GSR = "ENABLED";
+    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i8.GSR = "ENABLED";
+    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i7.GSR = "ENABLED";
+    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i6.GSR = "ENABLED";
+    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i5.GSR = "ENABLED";
+    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i4.GSR = "ENABLED";
+    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i3.GSR = "ENABLED";
+    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i2.GSR = "ENABLED";
+    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i1.GSR = "ENABLED";
+    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i7.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
+    defparam i1_2_lut_rep_12.init = 16'hdddd;
+    ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
+            .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff;
+    ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), 
+            .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i1_2_lut_4_lut_4_lut.init = 16'h4000;
+    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i6.GSR = "ENABLED";
+    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i5.GSR = "ENABLED";
+    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i4.GSR = "ENABLED";
+    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i3.GSR = "ENABLED";
+    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i2.GSR = "ENABLED";
+    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i1.GSR = "ENABLED";
+    BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8])
+    defparam nRWE_I_49_1_lut.init = 16'h5555;
+    BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    OB Dout_pad_7 (.I(n973), .O(Dout[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_6 (.I(n974), .O(Dout[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_5 (.I(n975), .O(Dout[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_4 (.I(n976), .O(Dout[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_3 (.I(n977), .O(Dout[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_2 (.I(n978), .O(Dout[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_1 (.I(n979), .O(Dout[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_0 (.I(Dout_c), .O(Dout[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB LED_pad (.I(LED_N_90), .O(LED));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
+    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_10 (.I(n980), .O(RA[10]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_9 (.I(RA_c_9), .O(RA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_8 (.I(RA_c_8), .O(RA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_7 (.I(RA_c_7), .O(RA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_6 (.I(RA_c_6), .O(RA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_5 (.I(RA_c_5), .O(RA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_4 (.I(RA_c_4), .O(RA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_3 (.I(RA_c_3), .O(RA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_2 (.I(RA_c_2), .O(RA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_1 (.I(RA_c_1), .O(RA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_0 (.I(RA_c_0), .O(RA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
+    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
+    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
+    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
+    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
+    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
+    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
+    OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
+    OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
+    OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
+    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
+    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
+    ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
+            .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca;
+    CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), 
+         .COUT1(n1875), .S0(n93), .S1(n92));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_4.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_4.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_4.INJECT1_0 = "NO";
+    defparam FS_577_add_4_4.INJECT1_1 = "NO";
+    ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), 
+            .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd;
+    FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), 
+            .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam UFMCLK_389.GSR = "ENABLED";
+    ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd;
+    ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), 
+            .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe;
+    ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), 
+            .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_adj_21.init = 16'hfefe;
+    ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
+            .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca;
+    ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), 
+            .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ;
+    defparam Ready_bdd_4_lut.init = 16'hf077;
+    ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), 
+            .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1366_3_lut.init = 16'hcaca;
+    ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), 
+            .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i6_4_lut.init = 16'h8000;
+    ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), 
+            .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30])
+    defparam i1_4_lut_4_lut.init = 16'h5540;
+    ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), 
+            .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
+    defparam i1_2_lut_rep_11_3_lut.init = 16'h1010;
+    CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), 
+         .COUT1(n1874), .S0(n95), .S1(n94));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_2.INIT0 = 16'h0555;
+    defparam FS_577_add_4_2.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_2.INJECT1_0 = "NO";
+    defparam FS_577_add_4_2.INJECT1_1 = "NO";
+    ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), 
+            .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
+    defparam i3_4_lut_adj_22.init = 16'h0200;
+    ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), 
+            .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
+    defparam Ready_bdd_4_lut_1960.init = 16'h2000;
+    ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam n2245_bdd_2_lut.init = 16'heeee;
+    ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), 
+            .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ;
+    defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73;
+    FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), 
+            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam LEDEN_392.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
+            .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca;
+    ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
+            .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca;
+    CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), 
+         .COUT1(n1879), .S0(n85), .S1(n84));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_12.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_12.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_12.INJECT1_0 = "NO";
+    defparam FS_577_add_4_12.INJECT1_1 = "NO";
+    FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), 
+            .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdEnable_378.GSR = "ENABLED";
+    CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), 
+         .COUT1(n1881), .S0(n81), .S1(n80));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_16.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_16.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_16.INJECT1_0 = "NO";
+    defparam FS_577_add_4_16.INJECT1_1 = "NO";
+    CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), 
+         .COUT1(n1880), .S0(n83), .S1(n82));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_14.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_14.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_14.INJECT1_0 = "NO";
+    defparam FS_577_add_4_14.INJECT1_1 = "NO";
+    ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
+            .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca;
+    ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1485_3_lut.init = 16'hcaca;
+    ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_2_lut.init = 16'h4444;
+    ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
+            .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd;
+    ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam i1062_3_lut.init = 16'h3a3a;
+    ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
+            .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca;
+    ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
+            .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca;
+    INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    INV i1962 (.A(PHI2_c), .Z(PHI2_N_114));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    VLO i1 (.Z(GND_net));
+    TSALL TSALL_INST (.TSALL(GND_net));
+    ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1070_1_lut_rep_25.init = 16'h5555;
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), 
+            .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
+    defparam i13_4_lut.init = 16'hdfff;
+    ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), 
+            .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
+    defparam i12_4_lut.init = 16'hbfff;
+    ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), 
+            .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1860_4_lut.init = 16'h8000;
+    ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
+    defparam m0_lut.init = 16'h0000;
+    PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132));
+    
+endmodule
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
new file mode 100644
index 0000000..15d3b42
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
@@ -0,0 +1,89 @@
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
new file mode 100644
index 0000000..0f2c679
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
@@ -0,0 +1,155 @@
+VOLTAGE 3.300 V;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
new file mode 100644
index 0000000..3564159
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
@@ -0,0 +1,88 @@
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
new file mode 100644
index 0000000..0f2c679
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
@@ -0,0 +1,155 @@
+VOLTAGE 3.300 V;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
new file mode 100644
index 0000000..5e379e0
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
@@ -0,0 +1,2080 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:38:58 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.447ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R4C5C.Q0 to R4C5C.A0       ADSubmitted
+CTOF_DEL    ---     0.092       R4C5C.A0 to       R4C5C.F0 SLICE_9
+ROUTE         1     0.000       R4C5C.F0 to R4C5C.DI0      n1355 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.244ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.215ns  (41.6% logic, 58.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.215ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.244ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5A.CLK to       R4C5A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.222       R4C5A.Q0 to R4C6C.C1       C1Submitted
+CTOOFX_DEL  ---     0.151       R4C6C.C1 to     R4C6C.OFX0 i26/SLICE_70
+ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
+CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
+ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
+CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
+ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.215   (41.6% logic, 58.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.249ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:               1.220ns  (29.0% logic, 71.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.220ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.249ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
+ROUTE         2     0.463       R4C5B.F0 to R7C7C.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.220   (29.0% logic, 71.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R7C7C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.287ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.258ns  (40.5% logic, 59.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.258ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.287ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.261       R4C5C.Q0 to R4C6C.A0       ADSubmitted
+CTOOFX_DEL  ---     0.155       R4C6C.A0 to     R4C6C.OFX0 i26/SLICE_70
+ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
+CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
+ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
+CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
+ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.258   (40.5% logic, 59.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.372ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:               1.343ns  (26.4% logic, 73.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.343ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.372ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
+ROUTE         2     0.586       R4C5B.F0 to R6C6A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.343   (26.4% logic, 73.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R6C6A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.447ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:               1.418ns  (25.0% logic, 75.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.418ns physical path delay SLICE_18 to SLICE_94 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.383       R4C5B.F1 to R7C6D.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R7C6D.C0 to       R7C6D.F0 SLICE_97
+ROUTE         1     0.410       R7C6D.F0 to R8C9B.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.418   (25.0% logic, 75.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.656ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               1.627ns  (21.8% logic, 78.2% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.627ns physical path delay SLICE_18 to SLICE_77 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.656ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     0.667       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.627   (21.8% logic, 78.2% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.779ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:               1.750ns  (20.2% logic, 79.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.750ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.779ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     0.790       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.750   (20.2% logic, 79.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 175.792ns (weighted slack = 351.584ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
+
+   Delay:               0.781ns  (33.5% logic, 66.5% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.781ns physical path delay SLICE_94 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.792ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R8C9B.CLK to       R8C9B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     0.519       R8C9B.Q0 to R2C9A.B0       XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to R2C9A.DI0      RA11_N_180 (to PHI2_c)
+                  --------
+                    0.781   (33.5% logic, 66.5% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R2C9A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 176.113ns (weighted slack = 352.226ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
+
+   Delay:               1.084ns  (31.5% logic, 68.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_92 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_92 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_92 (from PHI2_c)
+ROUTE         1     0.344       R2C3A.Q1 to R2C5C.A1       Bank_3
+CTOF_DEL    ---     0.092       R2C5C.A1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.132       R2C5C.F1 to R2C5C.C0       n1279
+CTOF_DEL    ---     0.092       R2C5C.C0 to       R2C5C.F0 SLICE_74
+ROUTE         1     0.267       R2C5C.F0 to R4C5A.CE       PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.084   (31.5% logic, 68.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_92:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_101 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q0 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R2C6C.Q0 to R2C6C.M1       n705 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q1 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R2C6C.Q1 to R2C6B.M0       n704 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C6D.CLK to       R4C6D.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.161       R4C6D.Q0 to R4C6D.M1       n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6B.CLK to       R2C6B.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.161       R2C6B.Q0 to R2C6B.M1       n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R2C5B.Q0 to R2C5B.M1       n695 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_95 to SLICE_95 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R8C9C.CLK to       R8C9C.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.161       R8C9C.Q0 to R8C9C.M1       n699 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_96 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C7A.CLK to       R4C7A.Q0 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R4C7A.Q0 to R4C7A.M1       n697 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_99 to SLICE_99 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7B.CLK to       R2C7B.Q0 SLICE_99 (from RCLK_c)
+ROUTE         1     0.161       R2C7B.Q0 to R2C7B.M1       n693 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_348  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_349  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_61 to SLICE_29 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q1 SLICE_61 (from RCLK_c)
+ROUTE        16     0.167       R4C9B.Q1 to R4C9D.M1       RASr2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C9D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C9A.CLK to       R6C9A.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.167       R6C9A.Q0 to R6C9A.M1       nRCS_N_135 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.844ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.357ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.357ns delay SLICE_64 to RA[9] (totaling 2.844ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.844ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     0.527       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.357   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:    2.844ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.088ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.088ns delay SLICE_64 to RA[8] (totaling 2.575ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.575ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     0.356       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.088   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    2.575ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.673ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.186ns  (62.1% logic, 37.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.186ns delay SLICE_64 to RA[7] (totaling 2.673ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.673ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.226       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     0.603       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.186   (62.1% logic, 37.9% route), 3 logic levels.
+
+Report:    2.673ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.687ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.200ns  (61.7% logic, 38.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.200ns delay SLICE_64 to RA[6] (totaling 2.687ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.687ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     0.468       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.200   (61.7% logic, 38.3% route), 3 logic levels.
+
+Report:    2.687ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.915ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.428ns  (55.9% logic, 44.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.428ns delay SLICE_64 to RA[5] (totaling 2.915ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.915ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     0.624       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.428   (55.9% logic, 44.1% route), 3 logic levels.
+
+Report:    2.915ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.574ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.087ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.087ns delay SLICE_64 to RA[4] (totaling 2.574ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.574ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     0.355       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.087   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    2.574ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.135ns delay SLICE_64 to RA[3] (totaling 2.622ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.622ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     0.468       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    2.622ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.698ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.211ns  (61.4% logic, 38.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.211ns delay SLICE_64 to RA[2] (totaling 2.698ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.698ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     0.479       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.211   (61.4% logic, 38.6% route), 3 logic levels.
+
+Report:    2.698ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.135ns delay SLICE_64 to RA[1] (totaling 2.622ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.622ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     0.468       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    2.622ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.086ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.086ns delay SLICE_64 to RA[0] (totaling 2.573ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     0.354       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.086   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.232ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.745ns delay SLICE_63 to nRWE (totaling 2.232ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.232ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.480       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    2.232ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.484       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
+
+Report:    2.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.711ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.224ns  (61.0% logic, 39.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.224ns delay SLICE_64 to RDQMH (totaling 2.711ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.711ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     0.394       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.224   (61.0% logic, 39.0% route), 3 logic levels.
+
+Report:    2.711ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.488ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.001ns  (67.8% logic, 32.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.001ns delay SLICE_64 to RDQML (totaling 2.488ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.488ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.197       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.001   (67.8% logic, 32.2% route), 3 logic levels.
+
+Report:    2.488ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.844 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.575 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.673 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.687 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.915 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.574 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.698 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.711 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.488 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 520 paths, 6 nets, and 440 connections (71.54% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
new file mode 100644
index 0000000..9090020
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
@@ -0,0 +1,3314 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:38:58 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.810ns  (25.8% logic, 74.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.810ns physical path delay SLICE_98 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.925ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
+CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.810   (25.8% logic, 74.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.114ns (weighted slack = 328.228ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.621ns  (26.2% logic, 73.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.621ns physical path delay SLICE_98 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.114ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
+ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
+CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.621   (26.2% logic, 73.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.237ns (weighted slack = 328.474ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.498ns  (23.0% logic, 77.0% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.498ns physical path delay SLICE_90 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.237ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
+ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
+CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.498   (23.0% logic, 77.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.307ns (weighted slack = 328.614ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.428ns  (26.7% logic, 73.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.428ns physical path delay SLICE_90 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
+CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.428   (26.7% logic, 73.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.317ns (weighted slack = 328.634ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.418ns  (26.7% logic, 73.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.418ns physical path delay SLICE_93 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.317ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.626       R2C2C.Q0 to R2C2B.D1       Bank_0
+CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.418   (26.7% logic, 73.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.386ns (weighted slack = 328.772ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.349ns  (26.9% logic, 73.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.349ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.386ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
+CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.349   (26.9% logic, 73.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.575ns (weighted slack = 329.150ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.160ns  (27.4% logic, 72.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.160ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
+ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
+CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.160   (27.4% logic, 72.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.629ns (weighted slack = 329.258ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.106ns  (23.9% logic, 76.1% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.106ns physical path delay SLICE_93 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.629ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     1.251       R2C2C.Q1 to R2C6C.D0       Bank_1
+CTOF_DEL    ---     0.371       R2C6C.D0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.106   (23.9% logic, 76.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.698ns (weighted slack = 329.396ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.037ns  (24.1% logic, 75.9% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.037ns physical path delay SLICE_90 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.698ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
+ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
+CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.037   (24.1% logic, 75.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.768ns (weighted slack = 329.536ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               9.967ns  (28.0% logic, 72.0% route), 7 logic levels.
+
+ Constraint Details:
+
+      9.967ns physical path delay SLICE_90 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.768ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
+CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    9.967   (28.0% logic, 72.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   22.150ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_73
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_74
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 7.341ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.415ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.415ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.415   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.520ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.236ns  (29.3% logic, 70.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.236ns physical path delay SLICE_7 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.520ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.236   (29.3% logic, 70.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.549ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.207ns  (29.4% logic, 70.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.207ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.549ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
+CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.207   (29.4% logic, 70.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.728ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.028ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.028ns physical path delay SLICE_7 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.728ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
+CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.028   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.768ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.988ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.988ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.768ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.988   (30.2% logic, 69.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.947ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.809ns  (30.9% logic, 69.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.809ns physical path delay SLICE_8 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.947ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.809   (30.9% logic, 69.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.079ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.677ns  (26.6% logic, 73.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.677ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.079ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     0.989       R8C9D.F1 to R8C9B.A1       n10
+CTOF_DEL    ---     0.371       R8C9B.A1 to       R8C9B.F1 SLICE_94
+ROUTE         1     1.384       R8C9B.F1 to R9C9A.A1       n2292
+CTOF_DEL    ---     0.371       R9C9A.A1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.677   (26.6% logic, 73.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.092ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.664ns  (31.5% logic, 68.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.664ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.092ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.724       R8C8C.Q0 to R8C9D.D1       FS_12
+CTOF_DEL    ---     0.371       R8C9D.D1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.664   (31.5% logic, 68.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.177ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.579ns  (27.0% logic, 73.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.579ns physical path delay SLICE_5 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.177ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C7A.CLK to       R8C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE         2     1.108       R8C7A.Q1 to R7C7D.B1       FS_1
+CTOF_DEL    ---     0.371       R7C7D.B1 to       R7C7D.F1 SLICE_68
+ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
+CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.579   (27.0% logic, 73.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C7A.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.243ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.513ns  (27.2% logic, 72.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.513ns physical path delay SLICE_4 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.243ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C7B.CLK to       R8C7B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.042       R8C7B.Q0 to R7C7D.A1       FS_2
+CTOF_DEL    ---     0.371       R7C7D.A1 to       R7C7D.F1 SLICE_68
+ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
+CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.513   (27.2% logic, 72.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C7B.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.659ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_55 and
+      4.797ns delay SLICE_55 to RA[10] (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to RA[10] by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.646       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.477ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     8.535ns  (53.5% logic, 46.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.535ns delay SLICE_64 to RA[9] (totaling 11.023ns) meets
+     12.500ns offset RCLK to RA[9] by 1.477ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     2.172       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    8.535   (53.5% logic, 46.5% route), 3 logic levels.
+
+Report:   11.023ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.323ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.724ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.724ns delay SLICE_64 to RA[9] (totaling 9.323ns) meets
+      0.000ns hold offset RCLK to RA[9] by 9.323ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     1.723       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.724   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:    9.323ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.460ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.552ns  (60.5% logic, 39.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.552ns delay SLICE_64 to RA[8] (totaling 10.040ns) meets
+     12.500ns offset RCLK to RA[8] by 2.460ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     1.526       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.552   (60.5% logic, 39.5% route), 3 logic levels.
+
+Report:   10.040ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.446ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.847ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.847ns delay SLICE_64 to RA[8] (totaling 8.446ns) meets
+      0.000ns hold offset RCLK to RA[8] by 8.446ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     1.165       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.847   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    8.446ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.906ns  (57.8% logic, 42.2% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.906ns delay SLICE_64 to RA[7] (totaling 10.394ns) meets
+     12.500ns offset RCLK to RA[7] by 2.106ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.895       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     2.444       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.906   (57.8% logic, 42.2% route), 3 logic levels.
+
+Report:   10.394ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.766ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.167ns  (62.1% logic, 37.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.167ns delay SLICE_64 to RA[7] (totaling 8.766ns) meets
+      0.000ns hold offset RCLK to RA[7] by 8.766ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.741       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     1.974       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.167   (62.1% logic, 37.9% route), 3 logic levels.
+
+Report:    8.766ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.002ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     8.010ns  (57.0% logic, 43.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.010ns delay SLICE_64 to RA[6] (totaling 10.498ns) meets
+     12.500ns offset RCLK to RA[6] by 2.002ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     1.984       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    8.010   (57.0% logic, 43.0% route), 3 logic levels.
+
+Report:   10.498ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.813ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.214ns  (61.7% logic, 38.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.214ns delay SLICE_64 to RA[6] (totaling 8.813ns) meets
+      0.000ns hold offset RCLK to RA[6] by 8.813ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     1.532       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.214   (61.7% logic, 38.3% route), 3 logic levels.
+
+Report:    8.813ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.141ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.871ns  (51.5% logic, 48.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.871ns delay SLICE_64 to RA[5] (totaling 11.359ns) meets
+     12.500ns offset RCLK to RA[5] by 1.141ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     2.568       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    8.871   (51.5% logic, 48.5% route), 3 logic levels.
+
+Report:   11.359ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.960ns  (55.9% logic, 44.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.960ns delay SLICE_64 to RA[5] (totaling 9.559ns) meets
+      0.000ns hold offset RCLK to RA[5] by 9.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.301       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     2.042       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.960   (55.9% logic, 44.1% route), 3 logic levels.
+
+Report:    9.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.458ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.554ns  (60.5% logic, 39.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.554ns delay SLICE_64 to RA[4] (totaling 10.042ns) meets
+     12.500ns offset RCLK to RA[4] by 2.458ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     1.528       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.554   (60.5% logic, 39.5% route), 3 logic levels.
+
+Report:   10.042ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.445ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.846ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.846ns delay SLICE_64 to RA[4] (totaling 8.445ns) meets
+      0.000ns hold offset RCLK to RA[4] by 8.445ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     1.164       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.846   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    8.445ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.216ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.796ns delay SLICE_64 to RA[3] (totaling 10.284ns) meets
+     12.500ns offset RCLK to RA[3] by 2.216ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     1.984       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:   10.284ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.000ns delay SLICE_64 to RA[3] (totaling 8.599ns) meets
+      0.000ns hold offset RCLK to RA[3] by 8.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     1.532       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    8.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.013ns  (57.0% logic, 43.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.013ns delay SLICE_64 to RA[2] (totaling 10.501ns) meets
+     12.500ns offset RCLK to RA[2] by 1.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     1.987       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.013   (57.0% logic, 43.0% route), 3 logic levels.
+
+Report:   10.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.849ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.250ns  (61.4% logic, 38.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.250ns delay SLICE_64 to RA[2] (totaling 8.849ns) meets
+      0.000ns hold offset RCLK to RA[2] by 8.849ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     1.568       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.250   (61.4% logic, 38.6% route), 3 logic levels.
+
+Report:    8.849ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.216ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.796ns delay SLICE_64 to RA[1] (totaling 10.284ns) meets
+     12.500ns offset RCLK to RA[1] by 2.216ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     1.984       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:   10.284ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.000ns delay SLICE_64 to RA[1] (totaling 8.599ns) meets
+      0.000ns hold offset RCLK to RA[1] by 8.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     1.532       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    8.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.454ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.558ns  (60.4% logic, 39.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.558ns delay SLICE_64 to RA[0] (totaling 10.046ns) meets
+     12.500ns offset RCLK to RA[0] by 2.454ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     1.532       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.558   (60.4% logic, 39.6% route), 3 logic levels.
+
+Report:   10.046ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.442ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     6.843ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.843ns delay SLICE_64 to RA[0] (totaling 8.442ns) meets
+      0.000ns hold offset RCLK to RA[0] by 8.442ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     1.161       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    6.843   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    8.442ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_60 and
+      4.797ns delay SLICE_60 to nRCS (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to nRCS by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.646       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_34 and
+      4.797ns delay SLICE_34 to RCKE (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to RCKE by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.646       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.833ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.179ns delay SLICE_63 to nRWE (totaling 8.667ns) meets
+     12.500ns offset RCLK to nRWE by 3.833ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     1.983       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.667ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.321ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.722ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_63 and
+      5.722ns delay SLICE_63 to nRWE (totaling 7.321ns) meets
+      0.000ns hold offset RCLK to nRWE by 7.321ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     1.571       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.722   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    7.321ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.813ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.199ns delay SLICE_61 to nRRAS (totaling 8.687ns) meets
+     12.500ns offset RCLK to nRRAS by 3.813ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.003       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    8.687ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.334ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.735ns  (72.4% logic, 27.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_61 and
+      5.735ns delay SLICE_61 to nRRAS (totaling 7.334ns) meets
+      0.000ns hold offset RCLK to nRRAS by 7.334ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.584       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.735   (72.4% logic, 27.6% route), 2 logic levels.
+
+Report:    7.334ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_58 and
+      4.797ns delay SLICE_58 to nRCAS (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to nRCAS by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.646       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.989ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     8.023ns  (56.9% logic, 43.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.023ns delay SLICE_64 to RDQMH (totaling 10.511ns) meets
+     12.500ns offset RCLK to RDQMH by 1.989ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     1.660       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    8.023   (56.9% logic, 43.1% route), 3 logic levels.
+
+Report:   10.511ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.888ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.289ns  (61.1% logic, 38.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.289ns delay SLICE_64 to RDQMH (totaling 8.888ns) meets
+      0.000ns hold offset RCLK to RDQMH by 8.888ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     1.288       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.289   (61.1% logic, 38.9% route), 3 logic levels.
+
+Report:    8.888ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.892ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.120ns  (64.1% logic, 35.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.120ns delay SLICE_64 to RDQML (totaling 9.608ns) meets
+     12.500ns offset RCLK to RDQML by 2.892ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.817       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.120   (64.1% logic, 35.9% route), 3 logic levels.
+
+Report:    9.608ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.163ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.564ns  (67.8% logic, 32.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.564ns delay SLICE_64 to RDQML (totaling 8.163ns) meets
+      0.000ns hold offset RCLK to RDQML by 8.163ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.301       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.646       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.564   (67.8% logic, 32.2% route), 3 logic levels.
+
+Report:    8.163ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    22.150 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.659 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.023 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.323 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.040 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.446 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.394 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.498 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.813 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.359 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.042 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.445 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.501 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.849 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.046 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.442 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.667 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.321 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.687 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.334 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.511 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.888 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.163 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 538 paths, 6 nets, and 440 connections (71.54% coverage)
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/automake.log b/CPLD/LCMXO/LCMXO640C/impl1/automake.log
new file mode 100644
index 0000000..1165506
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/automake.log
@@ -0,0 +1,528 @@
+
+ibisgen "RAM2GS_LCMXO640C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Mon Aug 16 21:36:33 2021
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO640C\impl1\IBIS\RAM2GS_LCMXO640C_im~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO640C_impl1.par" 
+
+bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed"  -comment "RAM2GS_LCMXO640C_impl1.alt" 
+Lattice Diamond Deployment Tool 3.12 Command Line
+
+Loading Programmer Device Database...
+
+Generating JED.....
+Device Name: LCMXO640C-XXT100
+Reading Input File: RAM2GS_LCMXO640C_impl1.bit
+Output File: RAM2GS_LCMXO640C_impl1.jed
+Comment file RAM2GS_LCMXO640C_impl1.alt.
+Generating JEDEC.....
+File RAM2GS_LCMXO640C_impl1.jed generated successfully.
+Lattice Diamond Deployment Tool has exited successfully.
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..ef94b54
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,9 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
new file mode 100644
index 0000000..4473ca1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
@@ -0,0 +1,137 @@
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:33:38 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.474      3       1.625     3
+CROW[1] nCRAS F     0.104      3       1.925     3
+Din[0]  PHI2  F     6.682      3       1.613     3
+Din[0]  nCCAS F    -0.028      M       2.082     3
+Din[1]  PHI2  F     6.886      3       2.631     3
+Din[1]  nCCAS F    -0.025      M       2.074     3
+Din[2]  PHI2  F     5.426      3       1.921     3
+Din[2]  nCCAS F     1.175      3       1.003     3
+Din[3]  PHI2  F     5.699      3       1.852     3
+Din[3]  nCCAS F     0.331      3       1.707     3
+Din[4]  PHI2  F     6.556      3       1.438     3
+Din[4]  nCCAS F     0.706      3       1.406     3
+Din[5]  PHI2  F     6.281      3       1.959     3
+Din[5]  nCCAS F     0.246      3       1.807     3
+Din[6]  PHI2  F     5.585      3       1.441     3
+Din[6]  nCCAS F     0.799      3       1.341     3
+Din[7]  PHI2  F     7.980      3       1.725     3
+Din[7]  nCCAS F     0.333      3       1.707     3
+MAin[0] PHI2  F     4.994      3       1.265     3
+MAin[0] nCRAS F     0.662      3       1.471     3
+MAin[1] PHI2  F     6.056      3       1.867     3
+MAin[1] nCRAS F     1.180      3       0.990     3
+MAin[2] PHI2  F    10.634      3      -1.183     M
+MAin[2] nCRAS F    -0.218      M       2.631     3
+MAin[3] PHI2  F    10.902      3      -1.260     M
+MAin[3] nCRAS F     0.208      3       1.826     3
+MAin[4] PHI2  F    10.204      3      -1.072     M
+MAin[4] nCRAS F    -0.218      M       2.628     3
+MAin[5] PHI2  F     7.043      3      -0.270     M
+MAin[5] nCRAS F     0.123      3       1.925     3
+MAin[6] PHI2  F     9.465      3      -0.885     M
+MAin[6] nCRAS F     0.584      3       1.522     3
+MAin[7] PHI2  F     9.683      3      -0.938     M
+MAin[7] nCRAS F    -0.218      M       2.628     3
+MAin[8] nCRAS F     0.316      3       1.758     3
+MAin[9] nCRAS F    -0.058      M       2.185     3
+PHI2    RCLK  R     1.456      3       0.038     3
+UFMSDO  RCLK  R     2.953      3      -0.147     M
+nCCAS   RCLK  R     2.435      3      -0.244     M
+nCCAS   nCRAS F     0.156      3       1.902     3
+nCRAS   RCLK  R     5.307      3      -0.787     M
+nFWE    PHI2  F     5.614      3       1.072     3
+nFWE    nCRAS F    -0.101      M       2.317     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.635         3        3.019          M
+RA[0]  RCLK  R    11.287         3        2.893          M
+RA[0]  nCRAS F    15.323         3        3.902          M
+RA[10] RCLK  R     7.501         3        1.949          M
+RA[11] PHI2  R     9.747         3        2.487          M
+RA[1]  RCLK  R    11.083         3        2.855          M
+RA[1]  nCRAS F    12.034         3        3.047          M
+RA[2]  RCLK  R    10.857         3        2.787          M
+RA[2]  nCRAS F    13.411         3        3.403          M
+RA[3]  RCLK  R    10.775         3        2.772          M
+RA[3]  nCRAS F    12.977         3        3.296          M
+RA[4]  RCLK  R    10.758         3        2.776          M
+RA[4]  nCRAS F    14.192         3        3.619          M
+RA[5]  RCLK  R    10.334         3        2.652          M
+RA[5]  nCRAS F    13.484         3        3.424          M
+RA[6]  RCLK  R    10.334         3        2.652          M
+RA[6]  nCRAS F    12.972         3        3.291          M
+RA[7]  RCLK  R     9.917         3        2.572          M
+RA[7]  nCRAS F    12.327         3        3.147          M
+RA[8]  RCLK  R    10.465         3        2.689          M
+RA[8]  nCRAS F    12.559         3        3.170          M
+RA[9]  RCLK  R    10.412         3        2.668          M
+RA[9]  nCRAS F    14.019         3        3.564          M
+RBA[0] nCRAS F    11.063         3        2.809          M
+RBA[1] nCRAS F    11.902         3        3.028          M
+RCKE   RCLK  R     7.501         3        1.949          M
+RDQMH  RCLK  R     9.831         3        2.523          M
+RDQML  RCLK  R     9.117         3        2.351          M
+RD[0]  nCCAS F    12.575         3        3.249          M
+RD[1]  nCCAS F    13.016         3        3.365          M
+RD[2]  nCCAS F    11.602         3        2.993          M
+RD[3]  nCCAS F    10.893         3        2.834          M
+RD[4]  nCCAS F    12.063         3        3.116          M
+RD[5]  nCCAS F    12.555         3        3.242          M
+RD[6]  nCCAS F    12.537         3        3.240          M
+RD[7]  nCCAS F    12.524         3        3.239          M
+UFMCLK RCLK  R     8.079         3        2.126          M
+UFMSDI RCLK  R     8.079         3        2.126          M
+nRCAS  RCLK  R     7.501         3        1.949          M
+nRCS   RCLK  R     7.501         3        1.949          M
+nRRAS  RCLK  R     9.175         3        2.363          M
+nRWE   RCLK  R     9.141         3        2.356          M
+nUFMCS RCLK  R     8.804         3        2.290          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
new file mode 100644
index 0000000..735293f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 27.276 ns (350.000 ns);
+Period_1 = 2.000 ns (350.000 ns);
+Period_2 = 2.000 ns (350.000 ns);
+Period_3 = 9.443 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 7.501 ns (12.500 ns);
+Tco_17 = 10.412 ns (12.500 ns);
+Tco_18 = 10.465 ns (12.500 ns);
+Tco_19 = 9.917 ns (12.500 ns);
+Tco_20 = 10.334 ns (12.500 ns);
+Tco_21 = 10.334 ns (12.500 ns);
+Tco_22 = 10.758 ns (12.500 ns);
+Tco_23 = 10.775 ns (12.500 ns);
+Tco_24 = 10.857 ns (12.500 ns);
+Tco_25 = 11.083 ns (12.500 ns);
+Tco_26 = 11.287 ns (12.500 ns);
+Tco_27 = 7.501 ns (12.500 ns);
+Tco_28 = 7.501 ns (12.500 ns);
+Tco_29 = 9.141 ns (12.500 ns);
+Tco_30 = 9.175 ns (12.500 ns);
+Tco_31 = 7.501 ns (12.500 ns);
+Tco_32 = 9.831 ns (12.500 ns);
+Tco_33 = 9.117 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 1.949 ns (0.000 ns);
+Tco_17 = 2.668 ns (0.000 ns);
+Tco_18 = 2.689 ns (0.000 ns);
+Tco_19 = 2.572 ns (0.000 ns);
+Tco_20 = 2.652 ns (0.000 ns);
+Tco_21 = 2.652 ns (0.000 ns);
+Tco_22 = 2.776 ns (0.000 ns);
+Tco_23 = 2.772 ns (0.000 ns);
+Tco_24 = 2.787 ns (0.000 ns);
+Tco_25 = 2.855 ns (0.000 ns);
+Tco_26 = 2.893 ns (0.000 ns);
+Tco_27 = 1.949 ns (0.000 ns);
+Tco_28 = 1.949 ns (0.000 ns);
+Tco_29 = 2.356 ns (0.000 ns);
+Tco_30 = 2.363 ns (0.000 ns);
+Tco_31 = 1.949 ns (0.000 ns);
+Tco_32 = 2.523 ns (0.000 ns);
+Tco_33 = 2.351 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log b/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log
new file mode 100644
index 0000000..f808002
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log
@@ -0,0 +1,239 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:29 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.699  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.515  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html b/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html
new file mode 100644
index 0000000..23a4fc7
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html
@@ -0,0 +1,304 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:29 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.699  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.515  secs
+--------------------------------------------------------------
+
+
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..29f9161
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,252 @@
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file
new file mode 100644
index 0000000..47217b1
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+LSE_CPS_ID_228 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
+LSE_CPS_ID_229 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:147[9] 285[5]"
+LSE_CPS_ID_230 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_231 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_232 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_233 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:84[6:11]"
+LSE_CPS_ID_234 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:214[26:30]"
+LSE_CPS_ID_235 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_236 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
+LSE_CPS_ID_237 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_238 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_239 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_240 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:288[9] 324[5]"
+LSE_CPS_ID_241 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_242 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
+LSE_CPS_ID_243 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_244 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:83[6:15]"
+LSE_CPS_ID_245 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_246 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
+LSE_CPS_ID_247 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
+LSE_CPS_ID_248 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_249 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
+LSE_CPS_ID_250 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:16[15:20]"
+LSE_CPS_ID_251 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:8[8:12]"
+LSE_CPS_ID_252 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
diff --git a/CPLD/RAM4GS-ExtSPI.v b/CPLD/LCMXO/RAM2GS-LCMXO.v
old mode 100755
new mode 100644
similarity index 91%
rename from CPLD/RAM4GS-ExtSPI.v
rename to CPLD/LCMXO/RAM2GS-LCMXO.v
index 9e7da5e..fce50cf
--- a/CPLD/RAM4GS-ExtSPI.v
+++ b/CPLD/LCMXO/RAM2GS-LCMXO.v
@@ -1,5 +1,5 @@
-module RAM4GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE,
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
+			  nCCAS, nCRAS, nFWE, LED,
 			  RBA, RA, RD, nRCS, RCLK, RCKE,
 			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
 			  nUFMCS, UFMCLK, UFMSDI, UFMSDO);
@@ -7,6 +7,11 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 	/* 65816 Phase 2 Clock */
 	input PHI2;
 
+	/* Activity LED */
+	reg LEDEN = 0;
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
+
 	/* Async. DRAM Control Inputs */
 	input nCCAS, nCRAS;
 
@@ -19,7 +24,8 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* 65816 Data */
 	input [7:0] Din;
-	output [7:0] Dout = RD[7:0];
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
 
 	/* Latched 65816 Bank Address */
 	reg [7:0] Bank;
@@ -47,8 +53,9 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 	assign RA[11] = RA11;
 	assign RA[10] = RA10;
 	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
 	reg [7:0] WRD;
 	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
@@ -63,6 +70,7 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 	reg ADSubmitted = 0;
 	reg CmdEnable = 0;
 	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
 	reg Cmdn8MEGEN = 0;
 	reg CmdUFMCLK = 0;
 	reg CmdUFMSDI = 0;
@@ -302,9 +310,11 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 			if (Din[7:4]==4'h0) begin
 				XOR8MEG <= Din[0];
 			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
 				Cmdn8MEGEN <= ~Din[0];
 				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3) begin
+			end else if (Din[7:4]==4'h3 && ~Din[3]) begin
+				CmdLEDEN <= LEDEN;
 				Cmdn8MEGEN <= n8MEGEN;
 				CmdUFMCS <= Din[2];
 				CmdUFMCLK <= Din[1];
@@ -363,13 +373,18 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 			endcase
 		end else if (~InitReady && FS[17:10]==8'h03) begin
 			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
+			UFMCLK <= FS[4];
 			UFMSDI <= 1'b0;
-			// Latch n8MEGEN
-			if (FS[9:4]==6'h00 && FS[3:0]==4'hF) n8MEGEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+			// Latch n8MEGEN and LEDEN
+			if (FS[9:5]==5'h00 && FS[4:0]==5'h1F) n8MEGEN <= ~UFMSDO;
+			if (FS[9:5]==5'h01 && FS[4:0]==5'h1F) LEDEN <= ~UFMSDO;
+		end else if (~InitReady && FS[17:10]==8'h04) begin
 			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
+			UFMCLK <= FS[4];
+			UFMSDI <= 1'b0;
+		end else if (~InitReady && FS[17:10]==8'h05) begin
+			nUFMCS <= 1'b1;
+			UFMCLK <= FS[4];
 			UFMSDI <= 1'b0;
 		end else if (~InitReady) begin
 			nUFMCS <= 1'b1;
@@ -377,7 +392,8 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 			UFMSDI <= 1'b0;
 		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
 			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
+			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
+			LEDEN <= CmdLEDEN;
 			n8MEGEN <= Cmdn8MEGEN;
 			nUFMCS <= ~CmdUFMCS;
 			UFMCLK <= CmdUFMCLK;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini b/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini
new file mode 100644
index 0000000..8c0aa7b
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini
@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini
new file mode 100644
index 0000000..449a648
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini
@@ -0,0 +1,4 @@
+[General]
+Map.auto_tasks=MapTrace
+Export.auto_tasks=IBIS, Bitgen, Jedecgen
+PAR.auto_tasks=PARTrace, IOTiming
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn b/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn
new file mode 100644
index 0000000..13d44b1
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn
@@ -0,0 +1,550 @@
+(edif EFB
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2021 8 17 5 48 29)
+      (program "SCUBA" (version "Diamond (64-bit) 3.12.0.240.2"))))
+      (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell EFB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port WBCLKI
+            (direction INPUT))
+          (port WBRSTI
+            (direction INPUT))
+          (port WBCYCI
+            (direction INPUT))
+          (port WBSTBI
+            (direction INPUT))
+          (port WBWEI
+            (direction INPUT))
+          (port WBADRI7
+            (direction INPUT))
+          (port WBADRI6
+            (direction INPUT))
+          (port WBADRI5
+            (direction INPUT))
+          (port WBADRI4
+            (direction INPUT))
+          (port WBADRI3
+            (direction INPUT))
+          (port WBADRI2
+            (direction INPUT))
+          (port WBADRI1
+            (direction INPUT))
+          (port WBADRI0
+            (direction INPUT))
+          (port WBDATI7
+            (direction INPUT))
+          (port WBDATI6
+            (direction INPUT))
+          (port WBDATI5
+            (direction INPUT))
+          (port WBDATI4
+            (direction INPUT))
+          (port WBDATI3
+            (direction INPUT))
+          (port WBDATI2
+            (direction INPUT))
+          (port WBDATI1
+            (direction INPUT))
+          (port WBDATI0
+            (direction INPUT))
+          (port PLL0DATI7
+            (direction INPUT))
+          (port PLL0DATI6
+            (direction INPUT))
+          (port PLL0DATI5
+            (direction INPUT))
+          (port PLL0DATI4
+            (direction INPUT))
+          (port PLL0DATI3
+            (direction INPUT))
+          (port PLL0DATI2
+            (direction INPUT))
+          (port PLL0DATI1
+            (direction INPUT))
+          (port PLL0DATI0
+            (direction INPUT))
+          (port PLL0ACKI
+            (direction INPUT))
+          (port PLL1DATI7
+            (direction INPUT))
+          (port PLL1DATI6
+            (direction INPUT))
+          (port PLL1DATI5
+            (direction INPUT))
+          (port PLL1DATI4
+            (direction INPUT))
+          (port PLL1DATI3
+            (direction INPUT))
+          (port PLL1DATI2
+            (direction INPUT))
+          (port PLL1DATI1
+            (direction INPUT))
+          (port PLL1DATI0
+            (direction INPUT))
+          (port PLL1ACKI
+            (direction INPUT))
+          (port I2C1SCLI
+            (direction INPUT))
+          (port I2C1SDAI
+            (direction INPUT))
+          (port I2C2SCLI
+            (direction INPUT))
+          (port I2C2SDAI
+            (direction INPUT))
+          (port SPISCKI
+            (direction INPUT))
+          (port SPIMISOI
+            (direction INPUT))
+          (port SPIMOSII
+            (direction INPUT))
+          (port SPISCSN
+            (direction INPUT))
+          (port TCCLKI
+            (direction INPUT))
+          (port TCRSTN
+            (direction INPUT))
+          (port TCIC
+            (direction INPUT))
+          (port UFMSN
+            (direction INPUT))
+          (port WBDATO7
+            (direction OUTPUT))
+          (port WBDATO6
+            (direction OUTPUT))
+          (port WBDATO5
+            (direction OUTPUT))
+          (port WBDATO4
+            (direction OUTPUT))
+          (port WBDATO3
+            (direction OUTPUT))
+          (port WBDATO2
+            (direction OUTPUT))
+          (port WBDATO1
+            (direction OUTPUT))
+          (port WBDATO0
+            (direction OUTPUT))
+          (port WBACKO
+            (direction OUTPUT))
+          (port PLLCLKO
+            (direction OUTPUT))
+          (port PLLRSTO
+            (direction OUTPUT))
+          (port PLL0STBO
+            (direction OUTPUT))
+          (port PLL1STBO
+            (direction OUTPUT))
+          (port PLLWEO
+            (direction OUTPUT))
+          (port PLLADRO4
+            (direction OUTPUT))
+          (port PLLADRO3
+            (direction OUTPUT))
+          (port PLLADRO2
+            (direction OUTPUT))
+          (port PLLADRO1
+            (direction OUTPUT))
+          (port PLLADRO0
+            (direction OUTPUT))
+          (port PLLDATO7
+            (direction OUTPUT))
+          (port PLLDATO6
+            (direction OUTPUT))
+          (port PLLDATO5
+            (direction OUTPUT))
+          (port PLLDATO4
+            (direction OUTPUT))
+          (port PLLDATO3
+            (direction OUTPUT))
+          (port PLLDATO2
+            (direction OUTPUT))
+          (port PLLDATO1
+            (direction OUTPUT))
+          (port PLLDATO0
+            (direction OUTPUT))
+          (port I2C1SCLO
+            (direction OUTPUT))
+          (port I2C1SCLOEN
+            (direction OUTPUT))
+          (port I2C1SDAO
+            (direction OUTPUT))
+          (port I2C1SDAOEN
+            (direction OUTPUT))
+          (port I2C2SCLO
+            (direction OUTPUT))
+          (port I2C2SCLOEN
+            (direction OUTPUT))
+          (port I2C2SDAO
+            (direction OUTPUT))
+          (port I2C2SDAOEN
+            (direction OUTPUT))
+          (port I2C1IRQO
+            (direction OUTPUT))
+          (port I2C2IRQO
+            (direction OUTPUT))
+          (port SPISCKO
+            (direction OUTPUT))
+          (port SPISCKEN
+            (direction OUTPUT))
+          (port SPIMISOO
+            (direction OUTPUT))
+          (port SPIMISOEN
+            (direction OUTPUT))
+          (port SPIMOSIO
+            (direction OUTPUT))
+          (port SPIMOSIEN
+            (direction OUTPUT))
+          (port SPIMCSN7
+            (direction OUTPUT))
+          (port SPIMCSN6
+            (direction OUTPUT))
+          (port SPIMCSN5
+            (direction OUTPUT))
+          (port SPIMCSN4
+            (direction OUTPUT))
+          (port SPIMCSN3
+            (direction OUTPUT))
+          (port SPIMCSN2
+            (direction OUTPUT))
+          (port SPIMCSN1
+            (direction OUTPUT))
+          (port SPIMCSN0
+            (direction OUTPUT))
+          (port SPICSNEN
+            (direction OUTPUT))
+          (port SPIIRQO
+            (direction OUTPUT))
+          (port TCINT
+            (direction OUTPUT))
+          (port TCOC
+            (direction OUTPUT))
+          (port WBCUFMIRQ
+            (direction OUTPUT))
+          (port CFGWAKE
+            (direction OUTPUT))
+          (port CFGSTDBY
+            (direction OUTPUT)))))
+    (cell EFB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port wb_clk_i
+            (direction INPUT))
+          (port wb_rst_i
+            (direction INPUT))
+          (port wb_cyc_i
+            (direction INPUT))
+          (port wb_stb_i
+            (direction INPUT))
+          (port wb_we_i
+            (direction INPUT))
+          (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
+            (direction OUTPUT))
+          (port wb_ack_o
+            (direction OUTPUT))
+          (port wbc_ufm_irq
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance EFBInst_0
+            (viewRef view1 
+              (cellRef EFB))
+            (property UFM_INIT_FILE_FORMAT
+              (string "HEX"))
+            (property UFM_INIT_FILE_NAME
+              (string "NONE"))
+            (property UFM_INIT_ALL_ZEROS
+              (string "ENABLED"))
+            (property UFM_INIT_START_PAGE
+              (string "190"))
+            (property UFM_INIT_PAGES
+              (string "1"))
+            (property DEV_DENSITY
+              (string "640L"))
+            (property EFB_UFM
+              (string "ENABLED"))
+            (property TC_ICAPTURE
+              (string "DISABLED"))
+            (property TC_OVERFLOW
+              (string "DISABLED"))
+            (property TC_ICR_INT
+              (string "OFF"))
+            (property TC_OCR_INT
+              (string "OFF"))
+            (property TC_OV_INT
+              (string "OFF"))
+            (property TC_TOP_SEL
+              (string "OFF"))
+            (property TC_RESETN
+              (string "ENABLED"))
+            (property TC_OC_MODE
+              (string "TOGGLE"))
+            (property TC_OCR_SET
+              (string "32767"))
+            (property TC_TOP_SET
+              (string "65535"))
+            (property GSR
+              (string "ENABLED"))
+            (property TC_CCLK_SEL
+              (string "1"))
+            (property TC_MODE
+              (string "CTCM"))
+            (property TC_SCLK_SEL
+              (string "PCLOCK"))
+            (property EFB_TC_PORTMODE
+              (string "WB"))
+            (property EFB_TC
+              (string "DISABLED"))
+            (property SPI_WAKEUP
+              (string "DISABLED"))
+            (property SPI_INTR_RXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_TXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_RXRDY
+              (string "DISABLED"))
+            (property SPI_INTR_TXRDY
+              (string "DISABLED"))
+            (property SPI_SLAVE_HANDSHAKE
+              (string "DISABLED"))
+            (property SPI_PHASE_ADJ
+              (string "DISABLED"))
+            (property SPI_CLK_INV
+              (string "DISABLED"))
+            (property SPI_LSB_FIRST
+              (string "DISABLED"))
+            (property SPI_CLK_DIVIDER
+              (string "1"))
+            (property SPI_MODE
+              (string "MASTER"))
+            (property EFB_SPI
+              (string "DISABLED"))
+            (property I2C2_WAKEUP
+              (string "DISABLED"))
+            (property I2C2_GEN_CALL
+              (string "DISABLED"))
+            (property I2C2_CLK_DIVIDER
+              (string "1"))
+            (property I2C2_BUS_PERF
+              (string "100kHz"))
+            (property I2C2_SLAVE_ADDR
+              (string "0b1000010"))
+            (property I2C2_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C2
+              (string "DISABLED"))
+            (property I2C1_WAKEUP
+              (string "DISABLED"))
+            (property I2C1_GEN_CALL
+              (string "DISABLED"))
+            (property I2C1_CLK_DIVIDER
+              (string "1"))
+            (property I2C1_BUS_PERF
+              (string "100kHz"))
+            (property I2C1_SLAVE_ADDR
+              (string "0b1000001"))
+            (property I2C1_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C1
+              (string "DISABLED"))
+            (property EFB_WB_CLK_FREQ
+              (string "16.0")))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef UFMSN (instanceRef EFBInst_0))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef PLL1DATI7 (instanceRef EFBInst_0))
+              (portRef PLL1DATI6 (instanceRef EFBInst_0))
+              (portRef PLL1DATI5 (instanceRef EFBInst_0))
+              (portRef PLL1DATI4 (instanceRef EFBInst_0))
+              (portRef PLL1DATI3 (instanceRef EFBInst_0))
+              (portRef PLL1DATI2 (instanceRef EFBInst_0))
+              (portRef PLL1DATI1 (instanceRef EFBInst_0))
+              (portRef PLL1DATI0 (instanceRef EFBInst_0))
+              (portRef PLL1ACKI (instanceRef EFBInst_0))
+              (portRef PLL0DATI7 (instanceRef EFBInst_0))
+              (portRef PLL0DATI6 (instanceRef EFBInst_0))
+              (portRef PLL0DATI5 (instanceRef EFBInst_0))
+              (portRef PLL0DATI4 (instanceRef EFBInst_0))
+              (portRef PLL0DATI3 (instanceRef EFBInst_0))
+              (portRef PLL0DATI2 (instanceRef EFBInst_0))
+              (portRef PLL0DATI1 (instanceRef EFBInst_0))
+              (portRef PLL0DATI0 (instanceRef EFBInst_0))
+              (portRef PLL0ACKI (instanceRef EFBInst_0))
+              (portRef TCIC (instanceRef EFBInst_0))
+              (portRef TCRSTN (instanceRef EFBInst_0))
+              (portRef TCCLKI (instanceRef EFBInst_0))
+              (portRef SPISCSN (instanceRef EFBInst_0))
+              (portRef SPIMOSII (instanceRef EFBInst_0))
+              (portRef SPIMISOI (instanceRef EFBInst_0))
+              (portRef SPISCKI (instanceRef EFBInst_0))
+              (portRef I2C2SDAI (instanceRef EFBInst_0))
+              (portRef I2C2SCLI (instanceRef EFBInst_0))
+              (portRef I2C1SDAI (instanceRef EFBInst_0))
+              (portRef I2C1SCLI (instanceRef EFBInst_0))))
+          (net wbc_ufm_irq
+            (joined
+              (portRef wbc_ufm_irq)
+              (portRef WBCUFMIRQ (instanceRef EFBInst_0))))
+          (net wb_ack_o
+            (joined
+              (portRef wb_ack_o)
+              (portRef WBACKO (instanceRef EFBInst_0))))
+          (net wb_dat_o7
+            (joined
+              (portRef (member wb_dat_o 0))
+              (portRef WBDATO7 (instanceRef EFBInst_0))))
+          (net wb_dat_o6
+            (joined
+              (portRef (member wb_dat_o 1))
+              (portRef WBDATO6 (instanceRef EFBInst_0))))
+          (net wb_dat_o5
+            (joined
+              (portRef (member wb_dat_o 2))
+              (portRef WBDATO5 (instanceRef EFBInst_0))))
+          (net wb_dat_o4
+            (joined
+              (portRef (member wb_dat_o 3))
+              (portRef WBDATO4 (instanceRef EFBInst_0))))
+          (net wb_dat_o3
+            (joined
+              (portRef (member wb_dat_o 4))
+              (portRef WBDATO3 (instanceRef EFBInst_0))))
+          (net wb_dat_o2
+            (joined
+              (portRef (member wb_dat_o 5))
+              (portRef WBDATO2 (instanceRef EFBInst_0))))
+          (net wb_dat_o1
+            (joined
+              (portRef (member wb_dat_o 6))
+              (portRef WBDATO1 (instanceRef EFBInst_0))))
+          (net wb_dat_o0
+            (joined
+              (portRef (member wb_dat_o 7))
+              (portRef WBDATO0 (instanceRef EFBInst_0))))
+          (net wb_dat_i7
+            (joined
+              (portRef (member wb_dat_i 0))
+              (portRef WBDATI7 (instanceRef EFBInst_0))))
+          (net wb_dat_i6
+            (joined
+              (portRef (member wb_dat_i 1))
+              (portRef WBDATI6 (instanceRef EFBInst_0))))
+          (net wb_dat_i5
+            (joined
+              (portRef (member wb_dat_i 2))
+              (portRef WBDATI5 (instanceRef EFBInst_0))))
+          (net wb_dat_i4
+            (joined
+              (portRef (member wb_dat_i 3))
+              (portRef WBDATI4 (instanceRef EFBInst_0))))
+          (net wb_dat_i3
+            (joined
+              (portRef (member wb_dat_i 4))
+              (portRef WBDATI3 (instanceRef EFBInst_0))))
+          (net wb_dat_i2
+            (joined
+              (portRef (member wb_dat_i 5))
+              (portRef WBDATI2 (instanceRef EFBInst_0))))
+          (net wb_dat_i1
+            (joined
+              (portRef (member wb_dat_i 6))
+              (portRef WBDATI1 (instanceRef EFBInst_0))))
+          (net wb_dat_i0
+            (joined
+              (portRef (member wb_dat_i 7))
+              (portRef WBDATI0 (instanceRef EFBInst_0))))
+          (net wb_adr_i7
+            (joined
+              (portRef (member wb_adr_i 0))
+              (portRef WBADRI7 (instanceRef EFBInst_0))))
+          (net wb_adr_i6
+            (joined
+              (portRef (member wb_adr_i 1))
+              (portRef WBADRI6 (instanceRef EFBInst_0))))
+          (net wb_adr_i5
+            (joined
+              (portRef (member wb_adr_i 2))
+              (portRef WBADRI5 (instanceRef EFBInst_0))))
+          (net wb_adr_i4
+            (joined
+              (portRef (member wb_adr_i 3))
+              (portRef WBADRI4 (instanceRef EFBInst_0))))
+          (net wb_adr_i3
+            (joined
+              (portRef (member wb_adr_i 4))
+              (portRef WBADRI3 (instanceRef EFBInst_0))))
+          (net wb_adr_i2
+            (joined
+              (portRef (member wb_adr_i 5))
+              (portRef WBADRI2 (instanceRef EFBInst_0))))
+          (net wb_adr_i1
+            (joined
+              (portRef (member wb_adr_i 6))
+              (portRef WBADRI1 (instanceRef EFBInst_0))))
+          (net wb_adr_i0
+            (joined
+              (portRef (member wb_adr_i 7))
+              (portRef WBADRI0 (instanceRef EFBInst_0))))
+          (net wb_we_i
+            (joined
+              (portRef wb_we_i)
+              (portRef WBWEI (instanceRef EFBInst_0))))
+          (net wb_stb_i
+            (joined
+              (portRef wb_stb_i)
+              (portRef WBSTBI (instanceRef EFBInst_0))))
+          (net wb_cyc_i
+            (joined
+              (portRef wb_cyc_i)
+              (portRef WBCYCI (instanceRef EFBInst_0))))
+          (net wb_rst_i
+            (joined
+              (portRef wb_rst_i)
+              (portRef WBRSTI (instanceRef EFBInst_0))))
+          (net wb_clk_i
+            (joined
+              (portRef wb_clk_i)
+              (portRef WBCLKI (instanceRef EFBInst_0))))))))
+  (design EFB
+    (cellRef EFB
+      (libraryRef ORCLIB)))
+)
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx b/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx
new file mode 100644
index 0000000..0954007
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx
@@ -0,0 +1,8 @@
+
+
+  
+		
+		
+		
+  
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc b/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc
new file mode 100644
index 0000000..ae74b18
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc
@@ -0,0 +1,141 @@
+[Device]
+Family=machxo2
+PartType=LCMXO2-640HC
+PartName=LCMXO2-640HC-4TG100C
+SpeedGrade=4
+Package=TQFP100
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=EFB
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=08/17/2021
+Time=05:48:29
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+ufm0=0
+ufm1=0
+ufm2=0
+ufm3=0
+ufm_cfg0=0
+ufm_cfg1=0
+wb_clk_freq=16
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=190
+ufm_remain=
+mem_size=1
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+ufm0_ebr=
+mem_size0=1
+ufm0_init=0
+memfile0=
+ufm0_dt=hex
+ufm1_ebr=
+mem_size1=1
+ufm1_init=0
+memfile1=
+ufm1_dt=hex
+ufm2_ebr=
+mem_size2=1
+ufm2_init=0
+memfile2=
+ufm2_dt=hex
+ufm3_ebr=
+mem_size3=1
+ufm3_init=0
+memfile3=
+ufm3_dt=hex
+ufm_cfg0_ebr=
+mem_size_cfg0=1
+ufm_cfg0_init=0
+memfile_cfg0=
+ufm_cfg0_dt=hex
+ufm_cfg1_ebr=
+mem_size_cfg1=1
+ufm_cfg1_init=0
+memfile_cfg1=
+ufm_cfg1_dt=hex
+wb=1
+boot_option=Internal
+efb_ufm=0
+boot_option_internal=Single Boot
+internal_ufm0=0
+internal_ufm1=0
+efb_ufm_boot=
+tamperdr=0
+t_pwd=0
+t_lockflash=0
+t_manmode=0
+t_jtagport=0
+t_sspiport=0
+t_sic2port=0
+t_wbport=0
+t_portlock=0
+
+[Command]
+cmd_line= -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf b/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf
new file mode 100644
index 0000000..bf6d243
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf
@@ -0,0 +1,31 @@
+wb_clk_i  i
+wb_rst_i  i
+wb_cyc_i  i
+wb_stb_i  i
+wb_we_i  i
+wb_adr_i[7]  i
+wb_adr_i[6]  i
+wb_adr_i[5]  i
+wb_adr_i[4]  i
+wb_adr_i[3]  i
+wb_adr_i[2]  i
+wb_adr_i[1]  i
+wb_adr_i[0]  i
+wb_dat_i[7]  i
+wb_dat_i[6]  i
+wb_dat_i[5]  i
+wb_dat_i[4]  i
+wb_dat_i[3]  i
+wb_dat_i[2]  i
+wb_dat_i[1]  i
+wb_dat_i[0]  i
+wb_dat_o[7]  o
+wb_dat_o[6]  o
+wb_dat_o[5]  o
+wb_dat_o[4]  o
+wb_dat_o[3]  o
+wb_dat_o[2]  o
+wb_dat_o[1]  o
+wb_dat_o[0]  o
+wb_ack_o  o
+wbc_ufm_irq  o
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort
new file mode 100644
index 0000000..8437cdd
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort
@@ -0,0 +1 @@
+EFB.v
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp b/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp
new file mode 100644
index 0000000..650b29b
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 05:48:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : EFB
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
+	Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
+    I/O buffer       : not inserted
+    EDIF output      : EFB.edn
+    Verilog output   : EFB.v
+    Verilog template : EFB_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : EFB.srp
+    Element Usage    :
+            EFB : 1
+    Estimated Resource Usage:
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.sym b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sym
new file mode 100644
index 0000000..98635d3
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sym differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.v b/CPLD/LCMXO2/LCMXO2-640HC/EFB.v
new file mode 100644
index 0000000..132b8b1
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.v
@@ -0,0 +1,113 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
+/* Module Version: 1.2 */
+/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640  */
+/* Tue Aug 17 05:48:29 2021 */
+
+
+`timescale 1 ns / 1 ps
+module EFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, 
+    wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
+    input wire wb_clk_i;
+    input wire wb_rst_i;
+    input wire wb_cyc_i;
+    input wire wb_stb_i;
+    input wire wb_we_i;
+    input wire [7:0] wb_adr_i;
+    input wire [7:0] wb_dat_i;
+    output wire [7:0] wb_dat_o;
+    output wire wb_ack_o;
+    output wire wbc_ufm_irq;
+
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
+    defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
+    defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
+    defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
+    defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
+    defparam EFBInst_0.DEV_DENSITY = "640L" ;
+    defparam EFBInst_0.EFB_UFM = "ENABLED" ;
+    defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
+    defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
+    defparam EFBInst_0.TC_ICR_INT = "OFF" ;
+    defparam EFBInst_0.TC_OCR_INT = "OFF" ;
+    defparam EFBInst_0.TC_OV_INT = "OFF" ;
+    defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
+    defparam EFBInst_0.TC_RESETN = "ENABLED" ;
+    defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
+    defparam EFBInst_0.TC_OCR_SET = 32767 ;
+    defparam EFBInst_0.TC_TOP_SET = 65535 ;
+    defparam EFBInst_0.GSR = "ENABLED" ;
+    defparam EFBInst_0.TC_CCLK_SEL = 1 ;
+    defparam EFBInst_0.TC_MODE = "CTCM" ;
+    defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
+    defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
+    defparam EFBInst_0.EFB_TC = "DISABLED" ;
+    defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
+    defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
+    defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
+    defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
+    defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
+    defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
+    defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
+    defparam EFBInst_0.SPI_MODE = "MASTER" ;
+    defparam EFBInst_0.EFB_SPI = "DISABLED" ;
+    defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
+    defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
+    defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
+    defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
+    defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
+    defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
+    defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
+    defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
+    defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
+    defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
+    defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
+    defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
+    defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
+    defparam EFBInst_0.EFB_WB_CLK_FREQ = "16.0" ;
+    EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), 
+        .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), 
+        .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), 
+        .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), 
+        .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), 
+        .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), 
+        .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), 
+        .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), 
+        .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), 
+        .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), 
+        .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), 
+        .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), 
+        .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), 
+        .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), 
+        .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo), 
+        .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), 
+        .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), 
+        .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), 
+        .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), 
+        .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), 
+        .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), 
+        .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), 
+        .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), 
+        .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), 
+        .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(), 
+        .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(), 
+        .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), 
+        .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), 
+        .WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
+
+
+
+    // exemplar begin
+    // exemplar end
+
+endmodule
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB_generate.log b/CPLD/LCMXO2/LCMXO2-640HC/EFB_generate.log
new file mode 100644
index 0000000..2296034
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB_generate.log
@@ -0,0 +1,44 @@
+Starting process: Module
+
+Starting process: 
+
+SCUBA, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 05:48:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : EFB
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
+	Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
+    I/O buffer       : not inserted
+    EDIF output      : EFB.edn
+    Verilog output   : EFB.v
+    Verilog template : EFB_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : EFB.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: EFB.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB_tmpl.v b/CPLD/LCMXO2/LCMXO2-640HC/EFB_tmpl.v
new file mode 100644
index 0000000..659ce82
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB_tmpl.v
@@ -0,0 +1,8 @@
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
+/* Module Version: 1.2 */
+/* Tue Aug 17 05:48:29 2021 */
+
+/* parameterized module instance */
+EFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), 
+    .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), 
+    .wbc_ufm_irq( ));
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
new file mode 100644
index 0000000..c494afe
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
@@ -0,0 +1,14 @@
+
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
new file mode 100644
index 0000000..746bae4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
@@ -0,0 +1,215 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
+IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+USE PRIMARY NET "PHI2_c" ;
+USE PRIMARY NET "RCLK_c" ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+USE PRIMARY NET "nCCAS_c" ;
+USE PRIMARY NET "nCRAS_c" ;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
new file mode 100644
index 0000000..feec63c
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
@@ -0,0 +1,205 @@
+
+
+
+    
+    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
new file mode 100644
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+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
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+
+Lattice TCL Log
+
+
+
    pn210817003052
+#Start recording tcl command: 8/16/2021 23:26:11
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+prj_project save
+#Stop recording: 8/17/2021 00:30:52
+
+
+
+pn210817054927
+#Start recording tcl command: 8/17/2021 00:30:55
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/17/2021 05:49:27
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr
new file mode 100644
index 0000000..ffbaf5f
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/16/2021 23:26:11
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+prj_project save
+#Stop recording: 8/17/2021 00:30:52
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr
new file mode 100644
index 0000000..76d8b28
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr
@@ -0,0 +1,9 @@
+#Start recording tcl command: 8/17/2021 00:30:55
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/17/2021 05:49:27
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr
new file mode 100644
index 0000000..9f6f1a8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr
@@ -0,0 +1,24 @@
+#Start recording tcl command: 8/17/2021 05:49:30
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Synthesis -impl impl1
+prj_run Synthesis -impl impl1 -forceOne
+prj_run Map -impl impl1 -forceOne
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceOne
+#Stop recording: 8/17/2021 06:23:20
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd b/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd
new file mode 100644
index 0000000..ad185b2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd
@@ -0,0 +1,2574 @@
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, 
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package defines a standard for designers to use in
+--              describing VHDL models that make use of common REAL constants
+--              and common REAL elementary mathematical functions.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076-
+--              1993.
+--
+-- Notes:
+--              No declarations or definitions shall be included in, or
+--              excluded from, this package.
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to provide a guideline for implementations to
+--              verify their implementation of MATH_REAL.  Tool developers may
+--              choose to implement the package body in the most efficient
+--              manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package MATH_REAL is
+    constant CopyRightNotice: STRING
+      := "Copyright 1996 IEEE. All rights reserved.";
+
+    --
+    -- Constant Definitions
+    --
+    constant  MATH_E : REAL := 2.71828_18284_59045_23536;
+                                                      -- Value of e
+    constant  MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
+                                                      -- Value of 1/e
+    constant  MATH_PI : REAL := 3.14159_26535_89793_23846;
+                                                      -- Value of pi
+    constant  MATH_2_PI : REAL := 6.28318_53071_79586_47693;
+                                                      -- Value of 2*pi
+    constant  MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
+                                                      -- Value of 1/pi
+    constant  MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
+                                                      -- Value of pi/2
+    constant  MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
+                                                      -- Value of pi/3
+    constant  MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
+                                                      -- Value of pi/4
+    constant  MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
+                                                      -- Value 3*pi/2
+    constant  MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
+                                                      -- Natural log of 2
+    constant  MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
+                                                      -- Natural log of 10
+    constant  MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
+                                                      -- Log base 2 of e
+    constant  MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
+                                                      -- Log base 10 of e
+    constant  MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
+                                                      -- square root of 2
+    constant  MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
+                                                      -- square root of 1/2
+    constant  MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
+                                                      -- square root of pi
+    constant  MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
+                                     -- Conversion factor from degree to radian
+    constant  MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
+                                     -- Conversion factor from radian to degree
+
+    --
+    -- Function Declarations
+    --
+    function SIGN (X: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIGN(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function CEIL (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns smallest INTEGER value (as REAL) not less than X
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CEIL(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function FLOOR (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns largest INTEGER value (as REAL) not greater than X
+        -- Special values:
+        --         FLOOR(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         FLOOR(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function ROUND (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Rounds X to the nearest integer value (as real). If X is
+        --         halfway between two integers, rounding is away from 0.0
+        -- Special values:
+        --         ROUND(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ROUND(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function TRUNC (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Truncates X towards 0.0 and returns truncated value
+        -- Special values:
+        --         TRUNC(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         TRUNC(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function "MOD" (X, Y: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns floating point modulus of X/Y, with the same sign as
+        --         Y, and absolute value less than the absolute value of Y, and
+        --         for some INTEGER value N the result satisfies the relation
+        --         X = Y*N + MOD(X,Y)
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL; Y in REAL and Y /= 0.0
+        -- Error conditions:
+        --         Error if Y = 0.0
+        -- Range:
+        --         ABS(MOD(X,Y)) < ABS(Y)
+        -- Notes:
+        --         None
+
+    function REALMAX (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically larger of X and Y
+        -- Special values:
+        --         REALMAX(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMAX(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    function REALMIN (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically smaller of X and Y
+        -- Special values:
+        --         REALMIN(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMIN(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
+        -- Purpose:
+        --         Returns, in X, a pseudo-random number with uniform
+        --         distribution in the open interval (0.0, 1.0).
+        -- Special values:
+        --         None
+        -- Domain:
+        --         1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
+        -- Error conditions:
+        --         Error if SEED1 or SEED2 outside of valid domain
+        -- Range:
+        --         0.0 < X < 1.0
+        -- Notes:
+        --         a) The semantics for this function are described by the
+        --            algorithm published by Pierre L'Ecuyer in "Communications
+        --            of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
+        --            The algorithm is based on the combination of two
+        --            multiplicative linear congruential generators for 32-bit
+        --            platforms.
+        --
+        --         b) Before the first call to UNIFORM, the seed values
+        --            (SEED1, SEED2) have to be initialized to values in the range
+        --            [1, 2147483562] and [1, 2147483398] respectively.  The
+        --            seed values are modified after each call to UNIFORM.
+        --
+        --         c) This random number generator is portable for 32-bit
+        --            computers, and it has a period of ~2.30584*(10**18) for each
+        --            set of seed values.
+        --
+        --         d) For information on spectral tests for the algorithm, refer
+        --            to the L'Ecuyer article.
+
+    function SQRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns square root of X
+        -- Special values:
+        --         SQRT(0.0) = 0.0
+        --         SQRT(1.0) = 1.0
+        -- Domain:
+        --         X >= 0.0
+        -- Error conditions:
+        --         Error if X < 0.0
+        -- Range:
+        --         SQRT(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of SQRT is
+        --            approximately given by:
+        --                SQRT(X) <= SQRT(REAL'HIGH)
+
+    function CBRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cube root of X
+        -- Special values:
+        --         CBRT(0.0) = 0.0
+        --         CBRT(1.0) = 1.0
+        --         CBRT(-1.0) = -1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CBRT(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of CBRT is approximately given by:
+        --                ABS(CBRT(X)) <= CBRT(REAL'HIGH)
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0
+        --         0**Y = 0.0; Y > 0.0
+        --         X**1.0 = REAL(X); X >= 0
+        --         1**Y = 1.0
+        -- Domain:
+        --         X > 0
+        --         X = 0 for Y > 0.0
+        --         X < 0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0 and Y /= 0.0
+        --         Error if X = 0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function "**" (X : in REAL; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0.0
+        --         0.0**Y = 0.0; Y > 0.0
+        --         X**1.0 = X; X >= 0.0
+        --         1.0**Y = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         X = 0.0 for Y > 0.0
+        --         X < 0.0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0.0 and Y /= 0.0
+        --         Error if X = 0.0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function EXP (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns e**X; where e = MATH_E
+        -- Special values:
+        --         EXP(0.0) = 1.0
+        --         EXP(1.0) = MATH_E
+        --         EXP(-1.0) = MATH_1_OVER_E
+        --         EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
+        -- Domain:
+        --         X in REAL such that EXP(X) <= REAL'HIGH
+        -- Error conditions:
+        --         Error if X > LOG(REAL'HIGH)
+        -- Range:
+        --         EXP(X) >= 0.0
+        -- Notes:
+        --         a) The usable domain of EXP is approximately given by:
+        --                X <= LOG(REAL'HIGH)
+
+    function LOG (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns natural logarithm of X
+        -- Special values:
+        --         LOG(1.0) = 0.0
+        --         LOG(MATH_E) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG is approximately given by:
+        --                LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
+
+    function LOG2 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 2 of X
+        -- Special values:
+        --         LOG2(1.0) = 0.0
+        --         LOG2(2.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG2(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG2 is approximately given by:
+        --                LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
+
+    function LOG10 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 10 of X
+        -- Special values:
+        --         LOG10(1.0) = 0.0
+        --         LOG10(10.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG10(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG10 is approximately given by:
+        --                LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL;
+        -- Purpose:
+        --         Returns logarithm base BASE of X
+        -- Special values:
+        --         LOG(1.0, BASE) = 0.0
+        --         LOG(BASE, BASE) = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         BASE > 0.0
+        --         BASE /= 1.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        --         Error if BASE <= 0.0
+        --         Error if BASE = 1.0
+        -- Range:
+        --         LOG(X, BASE) is mathematically unbounded
+        -- Notes:
+        --         a) When BASE > 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
+        --         b) When 0.0 < BASE < 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
+
+    function  SIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns sine of X; X in radians
+        -- Special values:
+        --         SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        --         SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        --         SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIN(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  COS ( X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cosine of X; X in radians
+        -- Special values:
+        --         COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                            INTEGER
+        --         COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
+        --         COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(COS(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  TAN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns tangent of X; X in radians
+        -- Special values:
+        --         TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL and
+        --         X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
+        -- Error conditions:
+        --         Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
+        --                                                           INTEGER
+        -- Range:
+        --         TAN(X) is mathematically unbounded
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  ARCSIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse sine of X
+        -- Special values:
+        --         ARCSIN(0.0) = 0.0
+        --         ARCSIN(1.0) = MATH_PI_OVER_2
+        --         ARCSIN(-1.0) = -MATH_PI_OVER_2
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         ABS(ARCSIN(X) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCCOS (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse cosine of X
+        -- Special values:
+        --         ARCCOS(1.0) = 0.0
+        --         ARCCOS(0.0) = MATH_PI_OVER_2
+        --         ARCCOS(-1.0) = MATH_PI
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         0.0 <= ARCCOS(X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the value of the angle in radians of the point
+        --        (1.0, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0) = 0.0
+        -- Domain:
+        --         Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL; X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the principal value of the angle in radians of
+        --         the point (X, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0, X) = 0.0 if X > 0.0
+        --         ARCTAN(0.0, X) = MATH_PI if X < 0.0
+        --         ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
+        --         ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
+        -- Domain:
+        --         Y in REAL
+        --         X in REAL, X /= 0.0 when Y = 0.0
+        -- Error conditions:
+        --         Error if X = 0.0 and Y = 0.0
+        -- Range:
+        --         -MATH_PI < ARCTAN(Y,X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function SINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic sine of X
+        -- Special values:
+        --         SINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         SINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The usable domain of SINH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+
+    function COSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic cosine of X
+        -- Special values:
+        --         COSH(0.0) = 1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         COSH(X) >= 1.0
+        -- Notes:
+        --         a) The usable domain of COSH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+    function TANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic tangent of X
+        -- Special values:
+        --         TANH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(TANH(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function ARCSINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic sine of X
+        -- Special values:
+        --         ARCSINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ARCSINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCSINH is approximately given by:
+        --                ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
+
+    function ARCCOSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic cosine of X
+        -- Special values:
+        --         ARCCOSH(1.0) = 0.0
+        -- Domain:
+        --         X >= 1.0
+        -- Error conditions:
+        --         Error if X < 1.0
+        -- Range:
+        --         ARCCOSH(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of ARCCOSH is
+        --            approximately given by:   ARCCOSH(X) <= LOG(REAL'HIGH)
+
+    function ARCTANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic tangent of X
+        -- Special values:
+        --         ARCTANH(0.0) = 0.0
+        -- Domain:
+        --         ABS(X) < 1.0
+        -- Error conditions:
+        --         Error if ABS(X) >= 1.0
+        -- Range:
+        --         ARCTANH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCTANH is approximately given by:
+        --                ABS(ARCTANH(X)) < LOG(REAL'HIGH)
+
+end  MATH_REAL;
+
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+
+-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package body is a nonnormative implementation of the 
+--              functionality defined in the MATH_REAL package declaration.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076
+--              -1993.
+--
+-- Notes:
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to clarify such semantics and provide a
+--              guideline for implementations to verify their implementation
+--              of MATH_REAL.  Tool developers may choose to implement
+--              the package body in the most efficient manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package body MATH_REAL is
+
+    --
+    -- Local Constants for Use in the Package Body Only
+    --
+    constant  MATH_E_P2 :  REAL := 7.38905_60989_30650;   -- e**2
+    constant  MATH_E_P10 :  REAL := 22026.46579_48067_17; -- e**10
+    constant  MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
+    constant  MAX_ITER:  INTEGER := 27;  -- Maximum precision factor for cordic
+    constant  MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
+    constant  BASE_EPS: REAL := 0.00001;  -- Factor for convergence criteria
+    constant  KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
+
+    --
+    -- Local Type Declarations for Cordic Operations
+    --
+    type REAL_VECTOR is array (NATURAL range <>) of REAL;
+    type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
+    subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
+    subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
+    subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
+    subtype QUADRANT is INTEGER range 0 to 3;
+    type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
+
+    --
+    -- Auxiliary Functions for Cordic Algorithms
+    --
+    function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
+                NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
+        -- Description:
+        --        Returns power of two for a vector of values
+        -- Notes:
+        --        None
+        --
+        variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
+        variable TEMP : REAL := INITIAL_VALUE;
+        variable FLAG : BOOLEAN := TRUE;
+    begin
+              for I in 0 to NUMBER_OF_VALUES loop
+                 V(I) := TEMP;
+                 for P in D'RANGE loop
+                            if I = D(P) then
+                                FLAG := FALSE;
+                                exit;
+                            end if;
+                 end loop;
+                 if FLAG then
+                            TEMP := TEMP/2.0;
+                 end if;
+                 FLAG := TRUE;
+              end loop;
+              return V;
+    end POWER_OF_2_SERIES;
+
+
+    constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
+                                               NATURAL_VECTOR'(100, 90),1.0,
+                                                                  MAX_ITER);
+
+    constant EPSILON : REAL_VECTOR_N := (
+                                        7.8539816339744827e-01,
+                                        4.6364760900080606e-01,
+                                        2.4497866312686413e-01,
+                                        1.2435499454676144e-01,
+                                        6.2418809995957351e-02,
+                                        3.1239833430268277e-02,
+                                        1.5623728620476830e-02,
+                                        7.8123410601011116e-03,
+                                        3.9062301319669717e-03,
+                                        1.9531225164788189e-03,
+                                        9.7656218955931937e-04,
+                                        4.8828121119489829e-04,
+                                        2.4414062014936175e-04,
+                                        1.2207031189367021e-04,
+                                        6.1035156174208768e-05,
+                                        3.0517578115526093e-05,
+                                        1.5258789061315760e-05,
+                                        7.6293945311019699e-06,
+                                        3.8146972656064960e-06,
+                                        1.9073486328101870e-06,
+                                        9.5367431640596080e-07,
+                                        4.7683715820308876e-07,
+                                        2.3841857910155801e-07,
+                                        1.1920928955078067e-07,
+                                        5.9604644775390553e-08,
+                                        2.9802322387695303e-08,
+                                        1.4901161193847654e-08,
+                                        7.4505805969238281e-09
+                                       );
+
+    function CORDIC ( X0 : in REAL;
+                      Y0 : in REAL;
+                      Z0 : in REAL;
+                      N : in NATURAL;                 --  Precision factor
+            CORDIC_MODE : in CORDIC_MODE_TYPE         --  Rotation (Z -> 0)
+                                                      --  or vectoring (Y -> 0)
+                    ) return REAL_ARR_3 is
+        -- Description:
+        --        Compute cordic values
+        -- Notes:
+        --         None
+             variable X : REAL := X0;
+             variable Y : REAL := Y0;
+             variable Z : REAL := Z0;
+             variable X_TEMP : REAL;
+    begin
+       if CORDIC_MODE = ROTATION then
+           for K in 0 to N loop
+                      X_TEMP := X;
+                      if ( Z >= 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                      else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                      end if;
+            end loop;
+        else
+            for K in 0 to N loop
+                    X_TEMP := X;
+                    if ( Y < 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                    else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                    end if;
+            end loop;
+        end if;
+        return REAL_ARR_3'(X, Y, Z);
+    end CORDIC;
+
+    --
+    -- Bodies for Global Mathematical Functions Start Here
+    --
+    function SIGN (X: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        None
+    begin
+           if  ( X > 0.0 )  then
+                return 1.0;
+           elsif ( X < 0.0 )  then
+                return -1.0;
+           else
+                return 0.0;
+           end if;
+    end SIGN;
+
+    function CEIL (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is X <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+         if ABS(X) >= LARGE then
+               return X;
+         end if;
+
+         RD := REAL ( INTEGER(X));
+         if RD = X then
+            return X;
+         end if;
+
+            if X > 0.0 then
+                       if RD >= X then
+                                  return RD;
+                       else
+                                  return RD + 1.0;
+                       end if;
+            elsif  X = 0.0  then
+                return 0.0;
+            else
+                       if RD <= X then
+                                  return RD + 1.0;
+                       else
+                                  return RD;
+                       end if;
+            end if;
+    end CEIL;
+
+    function FLOOR (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is ABS(X) <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+        if ABS( X ) >= LARGE then
+                    return X;
+        end if;
+
+        RD := REAL ( INTEGER(X));
+        if RD = X then
+                return X;
+        end if;
+
+        if X > 0.0 then
+                      if RD <= X then
+                                  return RD;
+                       else
+                                  return RD - 1.0;
+                       end if;
+        elsif  X = 0.0  then
+                return 0.0;
+        else
+                   if RD >= X then
+                                  return RD - 1.0;
+                   else
+                                  return RD;
+                   end if;
+        end if;
+    end FLOOR;
+
+    function ROUND (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X + 0.5) if X > 0
+        --         c) Returns CEIL(X - 0.5) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X + 0.5);
+           elsif  X < 0.0  then
+                return CEIL( X - 0.5);
+           else
+                return 0.0;
+           end if;
+    end ROUND;
+
+    function TRUNC (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X) if X > 0
+        --         c) Returns CEIL(X) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X);
+           elsif  X < 0.0  then
+                return CEIL( X);
+           else
+                return 0.0;
+           end if;
+    end TRUNC;
+
+
+
+
+    function "MOD" (X, Y: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+
+        variable XNEGATIVE : BOOLEAN := X < 0.0;
+        variable YNEGATIVE : BOOLEAN := Y < 0.0;
+        variable VALUE : REAL;
+    begin
+        -- Check validity of input arguments
+            if (Y = 0.0) then
+                 assert FALSE
+                        report "MOD(X, 0.0) is undefined"
+                        severity ERROR;
+                 return 0.0;
+              end if;
+
+        -- Compute value
+        if ( XNEGATIVE ) then
+                if ( YNEGATIVE ) then
+                        VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        else
+                if ( YNEGATIVE ) then
+                        VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        end if;
+
+        return VALUE;
+    end "MOD";
+
+
+    function REALMAX (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMAX(X,Y) = X when X = Y
+        --
+    begin
+        if X >= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMAX;
+
+    function REALMIN (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMIN(X,Y) = X when X = Y
+        --
+    begin
+        if X <= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMIN;
+
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
+                                                                         is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+        --
+        variable Z, K: INTEGER;
+        variable TSEED1 : INTEGER := INTEGER'(SEED1);
+        variable TSEED2 : INTEGER := INTEGER'(SEED2);
+    begin
+        -- Check validity of arguments
+        if SEED1 > 2147483562 then
+                assert FALSE
+                        report "SEED1 > 2147483562 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        if SEED2 > 2147483398 then
+                assert FALSE
+                        report "SEED2 > 2147483398 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        -- Compute new seed values and pseudo-random number
+        K := TSEED1/53668;
+        TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
+
+        if TSEED1 < 0  then
+                TSEED1 := TSEED1 + 2147483563;
+        end if;
+
+        K := TSEED2/52774;
+        TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
+
+        if TSEED2 < 0  then
+                TSEED2 := TSEED2 + 2147483399;
+        end if;
+
+        Z := TSEED1 - TSEED2;
+        if Z < 1 then
+                Z := Z + 2147483562;
+        end if;
+
+        -- Get output values
+        SEED1 := POSITIVE'(TSEED1);
+        SEED2 := POSITIVE'(TSEED2);
+        X :=  REAL(Z)*4.656613e-10;
+    end UNIFORM;
+
+
+
+    function SQRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = 0.5*[F(n) + x/F(n)]
+        --        b) Returns 0.0 on error
+        --
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
+
+        variable INIVAL: REAL;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+        -- Check validity of argument
+        if ( X < 0.0 ) then
+                assert FALSE
+                        report "X < 0.0 in SQRT(X)"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get the square root for special cases
+        if X = 0.0 then
+                  return 0.0;
+        else
+                if ( X = 1.0 ) then
+                        return 1.0;
+                end if;
+        end if;
+
+        -- Get the square root for general cases
+        INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+
+        -- Check for  relative and absolute error and max count
+        while  ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                   (COUNT < MAX_COUNT) )  loop
+                OLDVAL := NEWVAL;
+                NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+                COUNT := COUNT + 1;
+        end loop;
+        return NEWVAL;
+    end SQRT;
+
+    function CBRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+        variable INIVAL: REAL;
+        variable XLOCAL : REAL := X;
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+
+        -- Compute root for special cases
+        if X = 0.0 then
+                return 0.0;
+        elsif ( X = 1.0 ) then
+                return 1.0;
+        else
+                if X = -1.0 then
+                        return -1.0;
+                end if;
+        end if;
+
+        -- Compute root for general cases
+        if NEGATIVE then
+                XLOCAL := -X;
+        end if;
+
+        INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
+                                          -- imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+
+        -- Check for relative and absolute errors and max count
+        while ( (  (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS ) )  AND
+                   ( COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+                COUNT := COUNT + 1;
+        end loop;
+
+        if NEGATIVE then
+                NEWVAL := -NEWVAL;
+        end if;
+
+        return NEWVAL;
+    end CBRT;
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (REAL(X));
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (REAL(X)));
+    end "**";
+
+    function "**" (X : in REAL; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0.0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0.0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0.0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0.0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0.0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (X);
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (X));
+    end "**";
+
+    function EXP  (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) This function computes the exponential using the following
+        --           series:
+        --                exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
+        --           and reduces argument X to take advantage of exp(x+y) =
+        --           exp(x)*exp(y)
+        --
+        --        b) This implementation limits X to be less than LOG(REAL'HIGH)
+        --           to avoid overflow.  Returns REAL'HIGH when X reaches that
+        --           limit
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
+
+            variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
+            variable XLOCAL : REAL := ABS(X);       -- Use positive value
+            variable OLDVAL: REAL ;
+            variable COUNT: INTEGER ;
+            variable NEWVAL: REAL ;
+            variable LAST_TERM: REAL ;
+        variable FACTOR : REAL := 1.0;
+
+     begin
+            -- Compute value for special cases
+        if X = 0.0 then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = 1.0  then
+                if RECIPROCAL then
+                        return MATH_1_OVER_E;
+                else
+                        return MATH_E;
+                end if;
+        end if;
+
+        if  XLOCAL = 2.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P2;
+                else
+                        return MATH_E_P2;
+                end if;
+        end if;
+
+        if  XLOCAL = 10.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P10;
+                else
+                        return MATH_E_P10;
+                end if;
+        end if;
+
+        if XLOCAL > LOG(REAL'HIGH) then
+                if RECIPROCAL then
+                        return 0.0;
+                else
+                        assert FALSE
+                                report "X > LOG(REAL'HIGH) in EXP(X)"
+                                severity NOTE;
+                        return REAL'HIGH;
+                end if;
+        end if;
+
+        -- Reduce argument to ABS(X) < 1.0
+        while XLOCAL > 10.0 loop
+                XLOCAL := XLOCAL - 10.0;
+                FACTOR := FACTOR*MATH_E_P10;
+        end loop;
+
+        while XLOCAL > 1.0 loop
+                XLOCAL := XLOCAL - 1.0;
+                FACTOR := FACTOR*MATH_E;
+        end loop;
+
+        -- Compute value for case 0 < XLOCAL < 1
+        OLDVAL := 1.0;
+        LAST_TERM := XLOCAL;
+        NEWVAL:= OLDVAL + LAST_TERM;
+        COUNT := 2;
+
+        -- Check for relative and absolute errors and max count
+        while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
+                  (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                  (COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
+                NEWVAL := OLDVAL + LAST_TERM;
+                COUNT := COUNT + 1;
+        end loop;
+
+        -- Compute final value using exp(x+y) = exp(x)*exp(y)
+        NEWVAL := NEWVAL*FACTOR;
+
+        if RECIPROCAL then
+                NEWVAL := 1.0/NEWVAL;
+        end if;
+
+        return NEWVAL;
+     end EXP;
+
+
+    --
+    -- Auxiliary Functions to Compute LOG
+    --
+    function ILOGB(X: in REAL) return INTEGER IS
+        -- Description:
+        --        Returns n such that -1 <= ABS(X)/2^n < 2
+        -- Notes:
+        --        None
+
+        variable N: INTEGER := 0;
+        variable Y: REAL := ABS(X);
+
+    begin
+        if(Y = 1.0 or Y = 0.0) then
+                return 0;
+        end if;
+
+        if( Y > 1.0) then
+                while Y >= 2.0 loop
+                        Y := Y/2.0;
+                        N := N+1;
+                end loop;
+                return N;
+        end if;
+
+        -- O < Y < 1
+        while Y < 1.0 loop
+                Y := Y*2.0;
+                N := N -1;
+        end loop;
+        return N;
+    end ILOGB;
+
+    function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
+        -- Description:
+        --        Returns X*2^n
+        -- Notes:
+        --         None
+    begin
+        return X*(2.0 ** N);
+    end LDEXP;
+
+    function LOG (X : in REAL ) return REAL IS
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        --
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+        --
+        -- Copyright (c) 1992 Regents of the University of California.
+        -- All rights reserved.
+        --
+        -- Redistribution and use in source and binary forms, with or without
+        -- modification, are permitted provided that the following conditions
+        -- are met:
+        -- 1. Redistributions of source code must retain the above copyright
+        -- notice, this list of conditions and the following disclaimer.
+        -- 2. Redistributions in binary form must reproduce the above copyright
+        -- notice, this list of conditions and the following disclaimer in the
+        -- documentation and/or other materials provided with the distribution.
+        -- 3. All advertising materials mentioning features or use of this
+        -- software must display the following acknowledgement:
+        -- This product includes software developed by the University of
+        -- California, Berkeley and its contributors.
+        -- 4. Neither the name of the University nor the names of its
+        -- contributors may be used to endorse or promote products derived
+        -- from this software without specific prior written permission.
+        --
+        -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+        -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+        -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+        -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
+        -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+        -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+        -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+        -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+        -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+        -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+        -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+        -- DAMAGE.
+        --
+        -- NOTE: This VHDL version was generated using the C version of the
+        --         original function by the IEEE VHDL Mathematical Package
+        --         Working Group (CS/JT)
+
+        constant N: INTEGER := 128;
+
+        -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
+        -- Used for generation of extend precision logarithms.
+        -- The constant 35184372088832 is 2^45, so the divide is exact.
+        -- It ensures correct reading of logF_head, even for inaccurate
+        -- decimal-to-binary conversion routines. (Everybody gets the
+        -- right answer for INTEGERs less than 2^53.)
+        -- Values for LOG(F) were generated using error < 10^-57 absolute
+        -- with the bc -l package.
+
+        type REAL_VECTOR is array (NATURAL range <>) of REAL;
+
+        constant A1:REAL := 0.08333333333333178827;
+        constant A2:REAL := 0.01250000000377174923;
+        constant A3:REAL := 0.002232139987919447809;
+        constant A4:REAL := 0.0004348877777076145742;
+
+        constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
+                0.0,
+                0.007782140442060381246,
+                0.015504186535963526694,
+                0.023167059281547608406,
+                0.030771658666765233647,
+                0.038318864302141264488,
+                0.045809536031242714670,
+                0.053244514518837604555,
+                0.060624621816486978786,
+                0.067950661908525944454,
+                0.075223421237524235039,
+                0.082443669210988446138,
+                0.089612158689760690322,
+                0.096729626458454731618,
+                0.103796793681567578460,
+                0.110814366340264314203,
+                0.117783035656430001836,
+                0.124703478501032805070,
+                0.131576357788617315236,
+                0.138402322859292326029,
+                0.145182009844575077295,
+                0.151916042025732167530,
+                0.158605030176659056451,
+                0.165249572895390883786,
+                0.171850256926518341060,
+                0.178407657472689606947,
+                0.184922338493834104156,
+                0.191394852999565046047,
+                0.197825743329758552135,
+                0.204215541428766300668,
+                0.210564769107350002741,
+                0.216873938300523150246,
+                0.223143551314024080056,
+                0.229374101064877322642,
+                0.235566071312860003672,
+                0.241719936886966024758,
+                0.247836163904594286577,
+                0.253915209980732470285,
+                0.259957524436686071567,
+                0.265963548496984003577,
+                0.271933715484010463114,
+                0.277868451003087102435,
+                0.283768173130738432519,
+                0.289633292582948342896,
+                0.295464212893421063199,
+                0.301261330578199704177,
+                0.307025035294827830512,
+                0.312755710004239517729,
+                0.318453731118097493890,
+                0.324119468654316733591,
+                0.329753286372579168528,
+                0.335355541920762334484,
+                0.340926586970454081892,
+                0.346466767346100823488,
+                0.351976423156884266063,
+                0.357455888922231679316,
+                0.362905493689140712376,
+                0.368325561158599157352,
+                0.373716409793814818840,
+                0.379078352934811846353,
+                0.384411698910298582632,
+                0.389716751140440464951,
+                0.394993808240542421117,
+                0.400243164127459749579,
+                0.405465108107819105498,
+                0.410659924985338875558,
+                0.415827895143593195825,
+                0.420969294644237379543,
+                0.426084395310681429691,
+                0.431173464818130014464,
+                0.436236766774527495726,
+                0.441274560805140936281,
+                0.446287102628048160113,
+                0.451274644139630254358,
+                0.456237433481874177232,
+                0.461175715122408291790,
+                0.466089729924533457960,
+                0.470979715219073113985,
+                0.475845904869856894947,
+                0.480688529345570714212,
+                0.485507815781602403149,
+                0.490303988045525329653,
+                0.495077266798034543171,
+                0.499827869556611403822,
+                0.504556010751912253908,
+                0.509261901790523552335,
+                0.513945751101346104405,
+                0.518607764208354637958,
+                0.523248143765158602036,
+                0.527867089620485785417,
+                0.532464798869114019908,
+                0.537041465897345915436,
+                0.541597282432121573947,
+                0.546132437597407260909,
+                0.550647117952394182793,
+                0.555141507540611200965,
+                0.559615787935399566777,
+                0.564070138285387656651,
+                0.568504735352689749561,
+                0.572919753562018740922,
+                0.577315365035246941260,
+                0.581691739635061821900,
+                0.586049045003164792433,
+                0.590387446602107957005,
+                0.594707107746216934174,
+                0.599008189645246602594,
+                0.603290851438941899687,
+                0.607555250224322662688,
+                0.611801541106615331955,
+                0.616029877215623855590,
+                0.620240409751204424537,
+                0.624433288012369303032,
+                0.628608659422752680256,
+                0.632766669570628437213,
+                0.636907462236194987781,
+                0.641031179420679109171,
+                0.645137961373620782978,
+                0.649227946625615004450,
+                0.653301272011958644725,
+                0.657358072709030238911,
+                0.661398482245203922502,
+                0.665422632544505177065,
+                0.669430653942981734871,
+                0.673422675212350441142,
+                0.677398823590920073911,
+                0.681359224807238206267,
+                0.685304003098281100392,
+                0.689233281238557538017,
+                0.693147180560117703862);
+
+        constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
+                0.0,
+                -0.00000000000000543229938420049,
+                0.00000000000000172745674997061,
+                -0.00000000000001323017818229233,
+                -0.00000000000001154527628289872,
+                -0.00000000000000466529469958300,
+                0.00000000000005148849572685810,
+                -0.00000000000002532168943117445,
+                -0.00000000000005213620639136504,
+                -0.00000000000001819506003016881,
+                0.00000000000006329065958724544,
+                0.00000000000008614512936087814,
+                -0.00000000000007355770219435028,
+                0.00000000000009638067658552277,
+                0.00000000000007598636597194141,
+                0.00000000000002579999128306990,
+                -0.00000000000004654729747598444,
+                -0.00000000000007556920687451336,
+                0.00000000000010195735223708472,
+                -0.00000000000017319034406422306,
+                -0.00000000000007718001336828098,
+                0.00000000000010980754099855238,
+                -0.00000000000002047235780046195,
+                -0.00000000000008372091099235912,
+                0.00000000000014088127937111135,
+                0.00000000000012869017157588257,
+                0.00000000000017788850778198106,
+                0.00000000000006440856150696891,
+                0.00000000000016132822667240822,
+                -0.00000000000007540916511956188,
+                -0.00000000000000036507188831790,
+                0.00000000000009120937249914984,
+                0.00000000000018567570959796010,
+                -0.00000000000003149265065191483,
+                -0.00000000000009309459495196889,
+                0.00000000000017914338601329117,
+                -0.00000000000001302979717330866,
+                0.00000000000023097385217586939,
+                0.00000000000023999540484211737,
+                0.00000000000015393776174455408,
+                -0.00000000000036870428315837678,
+                0.00000000000036920375082080089,
+                -0.00000000000009383417223663699,
+                0.00000000000009433398189512690,
+                0.00000000000041481318704258568,
+                -0.00000000000003792316480209314,
+                0.00000000000008403156304792424,
+                -0.00000000000034262934348285429,
+                0.00000000000043712191957429145,
+                -0.00000000000010475750058776541,
+                -0.00000000000011118671389559323,
+                0.00000000000037549577257259853,
+                0.00000000000013912841212197565,
+                0.00000000000010775743037572640,
+                0.00000000000029391859187648000,
+                -0.00000000000042790509060060774,
+                0.00000000000022774076114039555,
+                0.00000000000010849569622967912,
+                -0.00000000000023073801945705758,
+                0.00000000000015761203773969435,
+                0.00000000000003345710269544082,
+                -0.00000000000041525158063436123,
+                0.00000000000032655698896907146,
+                -0.00000000000044704265010452446,
+                0.00000000000034527647952039772,
+                -0.00000000000007048962392109746,
+                0.00000000000011776978751369214,
+                -0.00000000000010774341461609578,
+                0.00000000000021863343293215910,
+                0.00000000000024132639491333131,
+                0.00000000000039057462209830700,
+                -0.00000000000026570679203560751,
+                0.00000000000037135141919592021,
+                -0.00000000000017166921336082431,
+                -0.00000000000028658285157914353,
+                -0.00000000000023812542263446809,
+                0.00000000000006576659768580062,
+                -0.00000000000028210143846181267,
+                0.00000000000010701931762114254,
+                0.00000000000018119346366441110,
+                0.00000000000009840465278232627,
+                -0.00000000000033149150282752542,
+                -0.00000000000018302857356041668,
+                -0.00000000000016207400156744949,
+                0.00000000000048303314949553201,
+                -0.00000000000071560553172382115,
+                0.00000000000088821239518571855,
+                -0.00000000000030900580513238244,
+                -0.00000000000061076551972851496,
+                0.00000000000035659969663347830,
+                0.00000000000035782396591276383,
+                -0.00000000000046226087001544578,
+                0.00000000000062279762917225156,
+                0.00000000000072838947272065741,
+                0.00000000000026809646615211673,
+                -0.00000000000010960825046059278,
+                0.00000000000002311949383800537,
+                -0.00000000000058469058005299247,
+                -0.00000000000002103748251144494,
+                -0.00000000000023323182945587408,
+                -0.00000000000042333694288141916,
+                -0.00000000000043933937969737844,
+                0.00000000000041341647073835565,
+                0.00000000000006841763641591466,
+                0.00000000000047585534004430641,
+                0.00000000000083679678674757695,
+                -0.00000000000085763734646658640,
+                0.00000000000021913281229340092,
+                -0.00000000000062242842536431148,
+                -0.00000000000010983594325438430,
+                0.00000000000065310431377633651,
+                -0.00000000000047580199021710769,
+                -0.00000000000037854251265457040,
+                0.00000000000040939233218678664,
+                0.00000000000087424383914858291,
+                0.00000000000025218188456842882,
+                -0.00000000000003608131360422557,
+                -0.00000000000050518555924280902,
+                0.00000000000078699403323355317,
+                -0.00000000000067020876961949060,
+                0.00000000000016108575753932458,
+                0.00000000000058527188436251509,
+                -0.00000000000035246757297904791,
+                -0.00000000000018372084495629058,
+                0.00000000000088606689813494916,
+                0.00000000000066486268071468700,
+                0.00000000000063831615170646519,
+                0.00000000000025144230728376072,
+                -0.00000000000017239444525614834);
+
+        variable M, J:INTEGER;
+        variable F1, F2, G, Q, U, U2, V: REAL;
+        variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
+        variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
+
+        -- double logb(), ldexp();
+
+        variable U1:REAL;
+
+     begin
+
+        -- Check validity of argument
+        if ( X <= 0.0 ) then
+                assert FALSE
+                        report "X <= 0.0 in LOG(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = MATH_E ) then
+                return 1.0;
+        end if;
+
+        -- Argument reduction: 1 <= g < 2; x/2^m = g;
+        -- y = F*(1 + f/F) for |f| <= 2^-8
+
+        M := ILOGB(X);
+        G := LDEXP(X, -M);
+        J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
+        F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
+        F2 := G - F1;
+
+        -- Approximate expansion for log(1+f2/F1) ~= u + q
+        G := 1.0/(2.0*F1+F2);
+        U := 2.0*F2*G;
+        V := U*U;
+        Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
+
+        -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
+        --       u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
+        --       It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
+        --
+        if ( J /= 0 or M /= 0) then
+                U1 := U + 513.0;
+                U1 := U1 - 513.0;
+
+                -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
+                --        u1 = u to 24 bits.
+                --
+        else
+                U1 := U;
+                --TRUNC(U1); --In c this is u1 = (double) (float) (u1)
+        end if;
+
+        U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
+        -- u1 + u2 = 2f/(2F+f) to extra precision.
+
+        -- log(x) = log(2^m*F1*(1+f2/F1)) =
+        -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
+        -- (exact) + (tiny)
+
+        U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J);        -- Exact
+        U2 := (U2 + LOGF_TAIL(J)) + Q;        -- Tiny
+        U2 := U2 + LOGF_TAIL(N)*REAL(M);
+        return (U1 + U2);
+    end LOG;
+
+
+    function LOG2 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                assert FALSE
+                        report "X <= 0.0 in LOG2(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 2.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG2_OF_E*LOG(X) );
+    end LOG2;
+
+
+    function LOG10 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                   assert FALSE
+                        report "X <= 0.0 in LOG10(X)"
+                        severity ERROR;
+                   return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 10.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG10_OF_E*LOG(X) );
+    end LOG10;
+
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                 assert FALSE
+                        report "X <= 0.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        if ( BASE <= 0.0 or BASE = 1.0 )  then
+                 assert FALSE
+                        report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = BASE ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( LOG(X)/LOG(BASE));
+    end LOG;
+
+
+    function  SIN (X : in REAL ) return REAL is
+        -- Description:
+        --         See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) SIN(-X) = -SIN(X)
+        --         b) SIN(X) = X if ABS(X) < EPS
+        --         c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
+        --         d) SIN(MATH_PI_OVER_2 - X) = COS(X)
+        --         e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
+        --         f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                         EPS< ABS(X)  MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in SIN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI  then
+                return 0.0;
+        end if;
+
+        if  XLOCAL = MATH_PI_OVER_2 then
+                if NEGATIVE then
+                        return -1.0;
+                else
+                        return 1.0;
+                end if;
+        end if;
+
+        if  XLOCAL = MATH_3_PI_OVER_2 then
+                if NEGATIVE then
+                        return 1.0;
+                else
+                        return -1.0;
+                end if;
+        end if;
+
+        if XLOCAL < EPS then
+                if NEGATIVE then
+                        return -XLOCAL;
+                else
+                        return XLOCAL;
+                end if;
+        else
+                if XLOCAL < BASE_EPS then
+                        TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_2_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
+                 VALUE:=  CORDIC( KC, 0.0, x, 27, ROTATION)(1);
+        end if;
+
+        N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
+        case QUADRANT( N mod 4) is
+           when 0 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
+           when 1 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+           when 2 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
+           when 3 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+        end case;
+
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+    end SIN;
+
+
+   function COS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) COS(-X) = COS(X)
+        --        b) COS(X) = SIN(MATH_PI_OVER_2 - X)
+        --        c) COS(MATH_PI + X)  = -COS(X)
+        --        d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
+        --        e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                           EPS< ABS(X)  MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in COS(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = MATH_PI then
+                return -1.0;
+        end if;
+
+        if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
+                return 0.0;
+        end if;
+
+        TEMP := ABS(XLOCAL);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS(XLOCAL -MATH_2_PI);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS (XLOCAL - MATH_PI);
+        if TEMP < EPS then
+                return (-1.0 + 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        return SIN(MATH_PI_OVER_2 - XLOCAL);
+   end COS;
+
+   function TAN (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) TAN(0.0) = 0.0
+        --        b) TAN(-X) = -TAN(X)
+        --        c) Returns REAL'LOW on error if X < 0.0
+        --        d) Returns REAL'HIGH on error if X > 0.0
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X) ;
+        variable VALUE: REAL;
+        variable TEMP : REAL;
+
+    begin
+        -- Make 0.0 <= XLOCAL <= MATH_2_PI
+        if XLOCAL > MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in TAN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Check validity of argument
+        if XLOCAL = MATH_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'LOW);
+                else
+                        return(REAL'HIGH);
+                end if;
+        end if;
+
+        if XLOCAL = MATH_3_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'HIGH);
+                else
+                        return(REAL'LOW);
+                end if;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0 or XLOCAL = MATH_PI then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        VALUE := SIN(XLOCAL)/COS(XLOCAL);
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+   end TAN;
+
+   function ARCSIN (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCSIN(-X) = -ARCSIN(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of arguments
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCSIN(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if XLOCAL = 0.0 then
+         return 0.0;
+      elsif XLOCAL = 1.0 then
+         if NEGATIVE then
+                return -MATH_PI_OVER_2;
+         else
+                return MATH_PI_OVER_2;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL < 0.9 then
+         VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      end if;
+
+      if NEGATIVE then
+         VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCSIN;
+
+   function ARCCOS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of argument
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCCOS(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if X = 1.0 then
+         return 0.0;
+      elsif X = 0.0 then
+         return MATH_PI_OVER_2;
+      elsif X = -1.0 then
+         return MATH_PI;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL > 0.9 then
+         VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
+      end if;
+
+
+      if NEGATIVE then
+         VALUE := MATH_PI - VALUE;
+      end if;
+
+      return VALUE;
+   end ARCCOS;
+
+
+   function ARCTAN (Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCTAN(-Y) = -ARCTAN(Y)
+        --        b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
+        --        c) ARCTAN(Y) = Y for |Y| < EPS
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
+
+        variable NEGATIVE : BOOLEAN := Y < 0.0;
+        variable RECIPROCAL : BOOLEAN;
+        variable YLOCAL : REAL := ABS(Y);
+        variable VALUE : REAL;
+
+   begin
+      -- Make argument |Y| <=1.0
+      if YLOCAL > 1.0 then
+                YLOCAL := 1.0/YLOCAL;
+                RECIPROCAL := TRUE;
+      else
+                RECIPROCAL := FALSE;
+      end if;
+
+      -- Compute value for special cases
+      if YLOCAL = 0.0 then
+         if RECIPROCAL then
+                if NEGATIVE then
+                        return (-MATH_PI_OVER_2);
+                else
+                        return (MATH_PI_OVER_2);
+                end if;
+         else
+                return 0.0;
+         end if;
+      end if;
+
+      if YLOCAL < EPS then
+         if NEGATIVE then
+                if RECIPROCAL then
+                        return (-MATH_PI_OVER_2 + YLOCAL);
+                else
+                        return -YLOCAL;
+                end if;
+         else
+                if RECIPROCAL then
+                        return (MATH_PI_OVER_2 - YLOCAL);
+                else
+                        return YLOCAL;
+                end if;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      VALUE :=  CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
+
+      if RECIPROCAL then
+         VALUE := MATH_PI_OVER_2 - VALUE;
+      end if;
+
+      if NEGATIVE then
+        VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCTAN;
+
+
+   function ARCTAN (Y : in REAL; X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 on error
+
+        variable YLOCAL : REAL;
+        variable VALUE : REAL;
+   begin
+
+     -- Check validity of arguments
+     if (Y = 0.0 and X = 0.0 ) then
+           assert FALSE report
+                "ARCTAN(0.0, 0.0) is undetermined"
+                severity ERROR;
+           return 0.0;
+     end if;
+
+     -- Compute value for special cases
+     if Y = 0.0 then
+        if X > 0.0 then
+           return 0.0;
+        else
+           return MATH_PI;
+        end if;
+     end if;
+
+     if X = 0.0 then
+        if Y > 0.0 then
+           return MATH_PI_OVER_2;
+        else
+           return -MATH_PI_OVER_2;
+        end if;
+     end if;
+
+
+     -- Compute value for general cases
+     YLOCAL := ABS(Y/X);
+
+     VALUE := ARCTAN(YLOCAL);
+
+     if X < 0.0 then
+         VALUE := MATH_PI - VALUE;
+     end if;
+
+     if Y < 0.0 then
+         VALUE := -VALUE;
+     end if;
+
+     return VALUE;
+   end ARCTAN;
+
+
+    function SINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/2.0
+        --        b) SINH(-X) = SINH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)*0.5;
+
+         if NEGATIVE then
+                VALUE := -VALUE;
+        end if;
+
+        return VALUE;
+    end SINH;
+
+    function  COSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) + EXP(-X))/2.0
+        --        b) COSH(-X) = COSH(X)
+
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 1.0;
+        end if;
+
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP + 1.0/TEMP)*0.5;
+
+        return VALUE;
+    end COSH;
+
+    function  TANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
+        --        b) TANH(-X) = -TANH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
+
+        if NEGATIVE then
+            return -VALUE;
+        else
+            return VALUE;
+        end if;
+    end TANH;
+
+    function ARCSINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X + 1.0))
+
+    begin
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X + 1.0)) );
+    end ARCSINH;
+
+
+
+   function ARCCOSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X - 1.0));   X >= 1.0
+        --        b) Returns X on error
+
+    begin
+        -- Check validity of arguments
+        if X < 1.0 then
+                 assert FALSE
+                        report "X < 1.0 in ARCCOSH(X)"
+                        severity ERROR;
+                 return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 1.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X - 1.0)));
+    end ARCCOSH;
+
+    function ARCTANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
+        --        b) Returns X on error
+    begin
+        -- Check validity of arguments
+        if ABS(X) >= 1.0 then
+                assert FALSE
+                        report "ABS(X) >= 1.0 in ARCTANH(X)"
+                        severity ERROR;
+                return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
+    end ARCTANH;
+
+end  MATH_REAL;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl b/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl
new file mode 100644
index 0000000..264a94e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "EFB"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "xo2c00"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl b/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl
new file mode 100644
index 0000000..ffa641e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl
@@ -0,0 +1,124 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "EFB"
+set Para(Module) "EFB"
+set Para(libname) machxo2
+set Para(arch_name) xo2c00
+set Para(PartType) "LCMXO2-640HC"
+
+set Para(tech_syn) machxo2
+set Para(tech_cae) machxo2
+set Para(Package) "TQFP100"
+set Para(SpeedGrade) "4"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create LSE project file(*.synproj)
+proc CreateSynprojFile {} {
+	global Para
+
+	if [catch {open $Para(ModuleName).synproj w} synprojFile] {
+		puts "Cannot create LSE project file $Para(ModuleName).synproj."
+		exit -1
+	} else {
+		puts $synprojFile "-a \"$Para(tech_syn)\"
+-d $Para(PartType)
+-t $Para(Package)
+-s $Para(SpeedGrade)
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle auto
+-romstyle auto
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-use_io_insertion 0
+-resolve_mixed_drivers 0
+-use_io_reg 1
+
+-lpf 1
+-p $Para(sbp_path)
+-ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
+\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
+\"$Para(sbp_path)/$Para(ModuleName).v\"
+-top $Para(ModuleName)
+-ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
+		"
+		close $synprojFile
+	}
+}
+
+#LSE
+CreateSynprojFile
+set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
+set synthesis "$Para(FPGAPath)/synthesis"
+if {[file exists $ldcfile] == 0} {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
+} else {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
+}
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status
new file mode 100644
index 0000000..d4ddfec
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status
@@ -0,0 +1,46 @@
+
+
+    
+        
+            
+            
+            
+            
+            
+        
+        
+            
+            
+            
+            
+        
+        
+            
+            
+            
+        
+        
+            
+            
+        
+        
+            
+            
+            
+            
+            
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
new file mode 100644
index 0000000..3d236f2
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
new file mode 100644
index 0000000..4d0f7d5
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb
new file mode 100644
index 0000000..2e79d37
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
new file mode 100644
index 0000000..0a575a4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
@@ -0,0 +1 @@
+RAM2GS_rtl.vdb
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs b/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs
new file mode 100644
index 0000000..4b06874
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs
@@ -0,0 +1,2837 @@
+|************************************************************************
+| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+| Generate date: Tue Aug 17 06:21:03 2021
+|************************************************************************
+| IBIS File LibisMaker.ibs
+| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
+| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
+| North Carolina State University, ERL, 2006
+|************************************************************************
+[IBIS ver]       3.2
+[File Name]     RAM2GS_LCMXO2_640HC~.ibs
+[File Rev]       3.5
+[Date]           Thu Sep 10 07:33:23 PDT 2020
+[Source]         Lattice Semiconductor cs200fl Process
+                 LCMXO2-640HC     FINAL
+                 Lattice Semiconductor has worked hard to ensure the
+                 models below are accurate and complete.  However, the
+                 data below was generated using simulation of the
+                 input/output model files for the silicon.  Therefore,
+                 the data below is for reference and initial design
+                 purposes only.
+|
+                 Lattice Semiconductor grants permission to use this
+                 data for use in printed circuit design using this
+                 Lattice programmable logic device.  Other use of this
+                 code, including the selling or duplication of any
+                 portion is strictly prohibited.
+|
+|                NAMING CONVENTION
+|
+        The IBIS [Model] header is limited by the specification to a
+        total of characters.  With such a set of characters available
+        for naming models it becomes important to attempt to
+        meaningfully encode the IO standards so they fit within the
+        twenty character limit.  It would seem that twenty characters
+        would provide room enough for describing IO's.  However, the
+        PLD IO structure continues to grow more and more complex.  The
+        complexity is making the twenty characters insuffiently
+        descriptive.  In order to overcome this issue the naming
+        convention described below is implemented to resolve the issue.
+|
+The twenty character space is managed as follows:
+                 bbbvvvsdddprugtcoixx
+|
+                 b = standard
+                 v = voltage (x.xx V)
+                 s = slew code
+                 d = drive (xx.x ma)
+                 p = pullup code
+                 r = series resistance  or bank_vccio code
+                 u = terminate to vcc code
+                 g = terminate to gnd code
+                 t = terminate to vtt code
+                 c = common mode termination mode
+                 o = diff resistor code
+                 i = diff resistor current code
+                 x = reserved
+|
+|
+                 standard
+|
+                 lvcmos                   lvc
+                 lvcmosd                  lvd
+                 lvcmosr                  lvr             
+                 lvds25e                  lve
+                 lvttl                    lvt
+                 lvttld                   ltd
+                 pci                      pci
+                 sstl_I                   ss1
+                 sstl_II                  ss2
+                 sstld_I                  s1d
+                 sstld_II                 s2d
+                 hstl_i                   hs1
+                 hstl_ii                  hs2
+                 hstld_i                  h1d
+                 hstld_ii                 h2d
+                 lvds25                   lvs
+                 blvds25                  blv
+                 blvds25e                 blv
+                 mlvds25                  mlv
+                 mlvds25e                 mlv
+                 lvpecl33                 lvp
+                 lvpecl33e                lvp
+                 rsds25                   rsd
+                 rsds25e                  rse
+                 mipi                     mip
+                 mipi_lp                  mip
+                 vref1                    vr1
+                 vref2                    vr2
+                 ref_res                  rer
+|
+|
+                 slew
+                 na                       a
+                 fast                     f
+                 slow                     s
+|
+                 pullmode
+                 off                      a
+                 pullup                   b
+                 pulldown                 c
+                 bushold                  d
+                 clamp                    e
+                 up_clamp                 f
+                 down_clamp               g
+                 keeper_clamp             h
+|
+                 impedance or Bank_vccio
+                 off                      a
+                 25                       b
+                 33                       c
+                 50                       d
+                 100                      e
+                 3.3                      f
+                 2.5                      g
+                 1.8                      h
+                 1.5                      i
+                 1.2                      j
+|
+                 termVCC
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termGND
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termVTT
+                 off                      a
+                 60                       b
+                 75                       c
+                 120                      d
+                 150                      e
+                 210                      f
+|
+                 VCMT
+                 off                      a
+                 VCMT                     b
+                 VTT                      c
+                 DDR-2                    d
+|
+                 differential resistor
+                 off                      a
+                 100                      b
+|
+                 diff drive
+                 NA                       a
+                 2.0                      b
+                 3.5                      c
+                 1.25                     f
+                 2.5                      g
+|
+                 Reserved                 IO type
+                 in                       input only
+                 ou                       output
+                 io                       I/O
+                 od                       Open drain
+                 on                       Inverting differential I/O
+                                          (signal name only)
+                 op                       Non-Inverting differential I/O
+                                          (signal name only)
+|
+                 Lattice Semiconductor Corporation
+                 5555 NE Moore Court
+                 Hillsboro, OR 97214
+                 U.S.A
+|
+                 TEL: 1-800-Lattice (USA and Canada)
+                      408-826-6000 (other locations)
+|
+                 web: http://www.latticesemi.com/
+                 email: techsupport@latticesemi.com
+|
+|
+|
+[Disclaimer]     This IBIS source code is intended as a design reference
+   which illustrates how the Lattice Semiconductor device operates.
+   It is the user's responsibility to verify their design for
+   consistency and functionality through the use of formal
+   verification methods.  Lattice Semiconductor provides no warranty
+   regarding the use or functionality of this data.
+|
+[Copyright]      Copyright 2007 by Lattice Semiconductor Corporation
+|
+|  
+|************************************************************************
+|                       Component XO2
+|************************************************************************
+|                                                               
+[Component]       XO2                                           
+[Manufacturer]    Lattice Semiconductor Corp.                   
+[Package]
+|TQFP100
+| variable            typ              min              max     
+R_pkg                150.5m           124.0m           187.0m
+L_pkg                6.27nH           5.50nH           7.16nH
+C_pkg                0.95pF           0.87pF           1.07pF
+|
+[Pin] signal_name           model_name           R_pin     L_pin     C_pin
+10            CROW[0]              lvt330axxxefaaaaaain
+16            CROW[1]              lvt330axxxefaaaaaain
+3             Din[0]               lvt330axxxefaaaaaain
+96            Din[1]               lvt330axxxefaaaaaain
+88            Din[2]               lvt330axxxefaaaaaain
+97            Din[3]               lvt330axxxefaaaaaain
+99            Din[4]               lvt330axxxefaaaaaain
+98            Din[5]               lvt330axxxefaaaaaain
+2             Din[6]               lvt330axxxefaaaaaain
+1             Din[7]               lvt330axxxefaaaaaain
+76            Dout[0]              lvt330s040aaaaaaaaou
+86            Dout[1]              lvt330s040aaaaaaaaou
+87            Dout[2]              lvt330s040aaaaaaaaou
+85            Dout[3]              lvt330s040aaaaaaaaou
+83            Dout[4]              lvt330s040aaaaaaaaou
+84            Dout[5]              lvt330s040aaaaaaaaou
+78            Dout[6]              lvt330s040aaaaaaaaou
+82            Dout[7]              lvt330s040aaaaaaaaou
+34            LED                  lvt330s160aaaaaaaaou
+14            MAin[0]              lvt330axxxefaaaaaain
+12            MAin[1]              lvt330axxxefaaaaaain
+13            MAin[2]              lvt330axxxefaaaaaain
+21            MAin[3]              lvt330axxxefaaaaaain
+20            MAin[4]              lvt330axxxefaaaaaain
+19            MAin[5]              lvt330axxxefaaaaaain
+24            MAin[6]              lvt330axxxefaaaaaain
+18            MAin[7]              lvt330axxxefaaaaaain
+25            MAin[8]              lvt330axxxefaaaaaain
+32            MAin[9]              lvt330axxxefaaaaaain
+8             PHI2                 lvt330axxxefaaaaaain
+66            RA[0]                lvt330s040aaaaaaaaou
+64            RA[10]               lvt330s040aaaaaaaaou
+59            RA[11]               lvt330s040aaaaaaaaou
+67            RA[1]                lvt330s040aaaaaaaaou
+69            RA[2]                lvt330s040aaaaaaaaou
+71            RA[3]                lvt330s040aaaaaaaaou
+74            RA[4]                lvt330s040aaaaaaaaou
+70            RA[5]                lvt330s040aaaaaaaaou
+68            RA[6]                lvt330s040aaaaaaaaou
+75            RA[7]                lvt330s040aaaaaaaaou
+65            RA[8]                lvt330s040aaaaaaaaou
+62            RA[9]                lvt330s040aaaaaaaaou
+58            RBA[0]               lvt330s040aaaaaaaaou
+60            RBA[1]               lvt330s040aaaaaaaaou
+53            RCKE                 lvt330s040aaaaaaaaou
+63            RCLK                 lvt330axxxefaaaaaain
+51            RDQMH                lvt330s040aaaaaaaaou
+48            RDQML                lvt330s040aaaaaaaaou
+36            RD[0]                lvt330s040haaaaaaaio
+37            RD[1]                lvt330s040haaaaaaaio
+38            RD[2]                lvt330s040haaaaaaaio
+39            RD[3]                lvt330s040haaaaaaaio
+40            RD[4]                lvt330s040haaaaaaaio
+41            RD[5]                lvt330s040haaaaaaaio
+42            RD[6]                lvt330s040haaaaaaaio
+43            RD[7]                lvt330s040haaaaaaaio
+9             nCCAS                lvt330axxxefaaaaaain
+17            nCRAS                lvt330axxxefaaaaaain
+15            nFWE                 lvt330axxxefaaaaaain
+52            nRCAS                lvt330s040aaaaaaaaou
+57            nRCS                 lvt330s040aaaaaaaaou
+54            nRRAS                lvt330s040aaaaaaaaou
+49            nRWE                 lvt330s040aaaaaaaaou
+|************************************************************************
+[Model]           lvt330axxxefaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.8000V
+Vinh =            2.0000V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.1216A           0.1237A              0.1238A
+  -3.15    0.1196A           0.1223A              0.1209A
+  -3.05    0.1173A           0.1206A              0.1178A
+  -2.95    0.1149A           0.1187A              0.1145A
+  -2.85    0.1124A           0.1167A              0.1111A
+  -2.75    0.1096A           0.1144A              0.1076A
+  -2.65    0.1067A           0.1119A              0.1038A
+  -2.55    0.1036A           0.1092A              99.9050mA
+  -2.45    0.1003A           0.1063A              95.7580mA
+  -2.35    96.7690mA         0.1032A              91.3580mA
+  -2.25    92.9860mA         99.8100mA            86.6530mA
+  -2.15    88.9230mA         96.2310mA            81.5730mA
+  -2.05    84.5480mA         92.4190mA            76.0140mA
+  -1.95    79.8300mA         88.3720mA            69.8490mA
+  -1.85    74.7460mA         84.0930mA            62.9770mA
+  -1.75    69.2870mA         79.5850mA            55.3980mA
+  -1.65    63.4650mA         74.8610mA            47.2410mA
+  -1.55    57.3080mA         69.9360mA            38.7130mA
+  -1.45    50.8520mA         64.8290mA            30.0630mA
+  -1.35    44.1410mA         59.5630mA            21.7860mA
+  -1.25    37.2260mA         54.1610mA            15.4630mA
+  -1.15    30.1740mA         48.6420mA            11.3590mA
+  -1.05    23.0900mA         43.0210mA            6.9249mA
+  -0.95    16.2170mA         37.3010mA            3.1428mA
+  -0.85    10.2220mA         31.4860mA            0.8130mA
+  -0.75    6.0667mA          25.5900mA            0.1206mA
+  -0.65    3.1215mA          19.6580mA            19.6640uA
+  -0.55    1.0958mA          13.7970mA            3.9127uA
+  -0.45    0.2189mA          8.2788mA             1.9769uA
+  -0.35    37.5650uA         3.8148mA             1.5352uA
+  -0.25    5.9156uA          1.3265mA             1.2603uA
+  -0.15    0.9342uA          0.3367mA             1.0262uA
+  -0.05    0.2497uA          63.0770uA            0.8243uA
+  0.00    0.1905uA          26.3140uA            0.7347uA
+  0.05    0.1661uA          10.7330uA            0.6522uA
+  0.15    0.1377uA          1.6689uA             0.5077uA
+  0.25    0.1149uA          0.2675uA             0.3882uA
+  0.35    95.5840nA         94.4800nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2001nA          17.4270nA            -0.8025nA
+  1.55    4.6215nA          13.7460nA            -4.4469nA
+  1.65    1.0974nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8986nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2566nA            -22.2600nA
+  2.15    -16.3730nA        -7.8413nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+| End [Model] lvt330axxxefaaaaaain
+|************************************************************************
+[Model]           lvt330s040aaaaaaaaou
+Model_type        Output
+Polarity          Non-Inverting
+Enable            Active-Low
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.90    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.80    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.70    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.60    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.50    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.40    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.90    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.80    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.70    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.60    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.50    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.40    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -0.90    -11.9260mA        -8.6650mA            -14.3050mA
+  -0.80    -11.2400mA        -8.5300mA            -13.3800mA
+  -0.70    -10.7050mA        -8.3490mA            -12.9130mA
+  -0.60    -10.2262mA        -7.9463mA            -12.5750mA
+  -0.50    -9.6879mA         -7.2722mA            -12.3552mA
+  -0.40    -8.5353mA         -6.1307mA            -11.3241mA
+  -0.30    -6.5715mA         -4.6600mA            -8.7716mA
+  -0.20    -4.4298mA         -3.1245mA            -5.9312mA
+  -0.10    -2.2389mA         -1.5709mA            -3.0077mA
+  0.00    2.6070nA          1.8160nA             4.3450nA
+  0.10    2.2086mA          1.5382mA             2.9824mA
+  0.20    4.3047mA          2.9922mA             5.8245mA
+  0.30    6.2890mA          4.3627mA             8.5260mA
+  0.40    8.1616mA          5.6502mA             11.0870mA
+  0.50    9.9232mA          6.8553mA             13.5060mA
+  0.60    11.5740mA         7.9787mA             15.7840mA
+  0.70    13.1130mA         9.0208mA             17.9190mA
+  0.80    14.5410mA         9.9819mA             19.9070mA
+  0.90    15.8560mA         10.8620mA            21.7440mA
+  1.00    17.0540mA         11.6600mA            23.4200mA
+  1.10    18.1290mA         12.3750mA            24.9200mA
+  1.20    19.0710mA         13.0030mA            26.2250mA
+  1.30    19.8710mA         13.5400mA            27.3150mA
+  1.40    20.5280mA         13.9880mA            28.1920mA
+  1.50    21.0520mA         14.3520mA            28.8770mA
+  1.60    21.4690mA         14.6450mA            29.4110mA
+  1.70    21.8020mA         14.8830mA            29.8330mA
+  1.80    22.0750mA         15.0800mA            30.1740mA
+  1.90    22.3020mA         15.2450mA            30.4550mA
+  2.00    22.4950mA         15.3870mA            30.6940mA
+  2.10    22.6630mA         15.5110mA            30.8990mA
+  2.20    22.8110mA         15.6210mA            31.0780mA
+  2.30    22.9430mA         15.7190mA            31.2379mA
+  2.40    23.0630mA         15.8080mA            31.3819mA
+  2.50    23.1710mA         15.8900mA            31.5119mA
+  2.60    23.2710mA         15.9650mA            31.6318mA
+  2.70    23.3639mA         16.0350mA            31.7418mA
+  2.80    23.4499mA         16.0999mA            31.8447mA
+  2.90    23.5309mA         16.1609mA            31.9406mA
+  3.00    23.6069mA         16.2189mA            32.0305mA
+  3.10    23.6789mA         16.2739mA            32.1163mA
+  3.20    23.7478mA         16.3258mA            32.1981mA
+  3.30    23.8138mA         16.3756mA            32.2769mA
+  3.40    23.8786mA         16.4213mA            32.3557mA
+  3.50    23.9417mA         16.4526mA            32.4354mA
+  3.60    24.0002mA         16.6876mA            32.5189mA
+  3.70    24.0309mA         17.3426mA            32.6070mA
+  3.80    24.3774mA         19.1285mA            32.6921mA
+  3.90    25.3543mA         22.9154mA            32.7222mA
+  4.00    27.4942mA         28.3023mA            33.3062mA
+  4.10    30.5709mA         34.3240mA            34.9817mA
+  4.20    34.9446mA         40.5557mA            38.3579mA
+  4.30    41.2761mA         46.8344mA            42.8549mA
+  4.40    48.5706mA         53.0950mA            47.3478mA
+  4.50    56.1500mA         59.3125mA            52.6274mA
+  4.60    63.7762mA         65.4900mA            60.8279mA
+  4.70    71.3464mA         71.6374mA            70.1182mA
+  4.80    78.8056mA         77.7568mA            79.6014mA
+  4.90    86.1136mA         83.8381mA            88.9754mA
+  5.00    93.2445mA         89.8594mA            98.0452mA
+  5.10    0.1002A           95.7986mA            0.1067A
+  5.20    0.1069A           0.1016A              0.1148A
+  5.30    0.1134A           0.1074A              0.1224A
+  5.40    0.1197A           0.1130A              0.1298A
+  5.50    0.1258A           0.1184A              0.1369A
+  5.60    0.1318A           0.1237A              0.1439A
+  5.70    0.1376A           0.1289A              0.1508A
+  5.80    0.1432A           0.1340A              0.1576A
+  5.90    0.1488A           0.1390A              0.1644A
+  6.00    0.1544A           0.1438A              0.1712A
+  6.10    0.1598A           0.1485A              0.1780A
+  6.20    0.1652A           0.1530A              0.1848A
+  6.30    0.1706A           0.1575A              0.1916A
+  6.40    0.1760A           0.1620A              0.1984A
+  6.50    0.1813A           0.1663A              0.2053A
+  6.60    0.1867A           0.1705A              0.2122A
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+-3.30       0.1819A       0.1298A        0.2190A    
+-3.20       0.1819A       0.1298A        0.2177A    
+-3.10       0.1819A       0.1298A        0.2139A    
+-3.00       0.1785A       0.1298A        0.2092A    
+-2.90       0.1743A       0.1298A        0.2039A    
+-2.80       0.1697A       0.1298A        0.1982A    
+-2.70       0.1647A       0.1298A        0.1922A    
+-2.60       0.1594A       0.1298A        0.1860A    
+-2.50       0.1538A       0.1298A        0.1795A    
+-2.40       0.1479A       0.1298A        0.1728A    
+-2.30       0.1418A       0.1259A        0.1658A    
+-2.20       0.1353A       0.1198A        0.1586A    
+-2.10       0.1286A       0.1135A        0.1512A    
+-2.00       0.1216A       0.1069A        0.1435A    
+-1.90       0.1142A       0.1002A        0.1355A    
+-1.80       0.1066A       93.3488mA        0.1271A    
+-1.70       93.5831mA       86.3555mA        0.1182A    
+-1.60       85.8190mA       79.2592mA        0.1088A    
+-1.50       77.8471mA       72.0828mA        98.7659mA    
+-1.40       69.6957mA       64.8453mA        88.3330mA    
+-1.30       61.4020mA       57.5538mA        77.6100mA    
+-1.20       53.0124mA       50.2142mA        66.7828mA    
+-1.10       44.6065mA       42.8446mA        56.1774mA    
+-1.00       36.3505mA       35.4829mA        46.7939mA    
+-0.90       28.6912mA       28.2232mA        39.5361mA    
+-0.80       22.4746mA       21.3014mA        32.3042mA    
+-0.70       17.6024mA       15.3245mA        25.5251mA    
+-0.60       13.5809mA       11.1535mA        19.7918mA    
+-0.50       10.4816mA       8.4310mA        14.7443mA    
+-0.40       8.0206mA       6.4251mA        11.9096mA    
+-0.30       5.9614mA       4.6861mA        8.8891mA    
+-0.20       3.9365mA       3.0816mA        5.8934mA    
+-0.10       1.9506mA       1.5203mA        2.9319mA    
+0.00       -7.7700nA       -3.4200nA        -87.8000nA    
+0.10       -1.8904mA       -1.4640mA        -2.8585mA    
+0.20       -3.6938mA       -2.8556mA        -5.5960mA    
+0.30       -5.4106mA       -4.1752mA        -8.2131mA    
+0.40       -7.0415mA       -5.4235mA        -10.7106mA    
+0.50       -8.5871mA       -6.6009mA        -13.0875mA    
+0.60       -10.0478mA       -7.7082mA        -15.3464mA    
+0.70       -11.4233mA       -8.7458mA        -17.4873mA    
+0.80       -12.7164mA       -9.7144mA        -19.5102mA    
+0.90       -13.9250mA       -10.6140mA        -21.4151mA    
+1.00       -15.0511mA       -11.4460mA        -23.2041mA    
+1.10       -16.0947mA       -12.2110mA        -24.8771mA    
+1.20       -17.0567mA       -12.9090mA        -26.4350mA    
+1.30       -17.9380mA       -13.5400mA        -27.8770mA    
+1.40       -18.7378mA       -14.1060mA        -29.2060mA    
+1.50       -19.4578mA       -14.6060mA        -30.4200mA    
+1.60       -20.0982mA       -15.0420mA        -31.5220mA    
+1.70       -20.6608mA       -15.4150mA        -32.5110mA    
+1.80       -21.1446mA       -15.7260mA        -33.3890mA    
+1.90       -21.5526mA       -15.9770mA        -34.1570mA    
+2.00       -21.8875mA       -16.1730mA        -34.8170mA    
+2.10       -22.1540mA       -16.3230mA        -35.3710mA    
+2.20       -22.3628mA       -16.4420mA        -35.8270mA    
+2.30       -22.5316mA       -16.5430mA        -36.1970mA    
+2.40       -22.6758mA       -16.6340mA        -36.5020mA    
+2.50       -22.8058mA       -16.7200mA        -36.7650mA    
+2.60       -22.9282mA       -16.8010mA        -37.0040mA    
+2.70       -23.0458mA       -16.8800mA        -37.2270mA    
+2.80       -23.1578mA       -16.9560mA        -37.4390mA    
+2.90       -23.2659mA       -17.0290mA        -37.6420mA    
+3.00       -23.3712mA       -17.1009mA        -37.8370mA    
+3.10       -23.4737mA       -17.1709mA        -38.0259mA    
+3.20       -23.5732mA       -17.2379mA        -38.2079mA    
+3.30       -23.6690mA       -17.3046mA        -38.3849mA    
+3.40       -23.7639mA       -17.3656mA        -38.5569mA    
+3.50       -23.8544mA       -17.3881mA        -38.7229mA    
+3.60       -23.9301mA       -17.3881mA        -38.8849mA    
+3.70       -23.9301mA       -17.3881mA        -39.0415mA    
+3.80       -23.9301mA       -17.3881mA        -39.1532mA    
+3.90       -23.9301mA       -17.3881mA        -39.1532mA    
+4.00       -23.9301mA       -17.3881mA        -39.1532mA    
+4.10       -23.9301mA       -17.3881mA        -39.1532mA    
+4.20       -23.9301mA       -17.3881mA        -39.1532mA    
+4.30       -23.9301mA       -17.3881mA        -39.1532mA    
+4.40       -23.9301mA       -17.3881mA        -39.1532mA    
+4.50       -23.9301mA       -17.3881mA        -39.1532mA    
+4.60       -23.9301mA       -17.3881mA        -39.1532mA    
+4.70       -23.9301mA       -17.3881mA        -39.1532mA    
+4.80       -23.9301mA       -17.3881mA        -39.1532mA    
+4.90       -23.9301mA       -17.3881mA        -39.1532mA    
+5.00       -23.9301mA       -17.3881mA        -39.1532mA    
+5.10       -23.9301mA       -17.3881mA        -39.1532mA    
+5.20       -23.9301mA       -17.3881mA        -39.1532mA    
+5.30       -23.9301mA       -17.3881mA        -39.1532mA    
+5.40       -23.9301mA       -17.3881mA        -39.1532mA    
+5.50       -23.9301mA       -17.3881mA        -39.1532mA    
+5.60       -23.9301mA       -17.3881mA        -39.1532mA    
+5.70       -23.9301mA       -17.3881mA        -39.1532mA    
+5.80       -23.9301mA       -17.3881mA        -39.1532mA    
+5.90       -23.9301mA       -17.3881mA        -39.1532mA    
+6.00       -23.9301mA       -17.3881mA        -39.1532mA    
+6.10       -23.9301mA       -17.3881mA        -39.1532mA    
+6.20       -23.9301mA       -17.3881mA        -39.1532mA    
+6.30       -23.9301mA       -17.3881mA        -39.1532mA    
+6.40       -23.9301mA       -17.3881mA        -39.1532mA    
+6.50       -23.9301mA       -17.3881mA        -39.1532mA    
+6.55       -23.9301mA       -17.3881mA        -39.1532mA    
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.6648mA          0.7494mA             0.5971mA
+  -3.15    0.5464mA          0.6392mA             0.4620mA
+  -3.05    0.4320mA          0.5325mA             0.3346mA
+  -2.95    0.3223mA          0.4288mA             0.2203mA
+  -2.85    0.2202mA          0.3288mA             0.1294mA
+  -2.75    0.1318mA          0.2341mA             72.8310uA
+  -2.65    67.1930uA         0.1484mA             47.8290uA
+  -2.55    33.3830uA         79.2120uA            38.1420uA
+  -2.45    21.1010uA         36.2260uA            33.4220uA
+  -2.35    16.7340uA         18.9530uA            30.1320uA
+  -2.25    14.6010uA         13.5620uA            27.2560uA
+  -2.15    13.0520uA         11.4690uA            24.5640uA
+  -2.05    11.6720uA         10.2210uA            22.0120uA
+  -1.95    10.3780uA         9.1893uA             19.5960uA
+  -1.85    9.1543uA          8.2396uA             17.3210uA
+  -1.75    8.0014uA          7.3461uA             15.1920uA
+  -1.65    6.9210uA          6.5045uA             13.2170uA
+  -1.55    5.9158uA          5.7141uA             11.4020uA
+  -1.45    4.9887uA          4.9753uA             9.7529uA
+  -1.35    4.1426uA          4.2887uA             8.2767uA
+  -1.25    3.3804uA          3.6548uA             6.9786uA
+  -1.15    2.7049uA          3.0746uA             5.8648uA
+  -1.05    2.1189uA          2.5487uA             4.9428uA
+  -0.95    1.6251uA          2.0780uA             4.2177uA
+  -0.85    1.2274uA          1.6631uA             3.6560uA
+  -0.75    0.9313uA          1.3051uA             3.6560uA
+  -0.65    0.7398uA          1.0056uA             3.6560uA
+  -0.55    0.6327uA          0.7679uA             3.6560uA
+  -0.45    0.5649uA          0.5968uA             1.9769uA
+  -0.35    0.5649uA          0.4927uA             1.5352uA
+  -0.25    0.5649uA          0.4380uA             1.2603uA
+  -0.15    0.5649uA          0.4056uA             1.0262uA
+  -0.05    0.2497uA          0.3924uA             0.8243uA
+  0.00    0.1905uA          0.3924uA             0.7347uA
+  0.05    0.1661uA          0.3924uA             0.6522uA
+  0.15    0.1377uA          0.3924uA             0.5077uA
+  0.25    0.1149uA          0.2673uA             0.3882uA
+  0.35    95.5840nA         94.4790nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2001nA          17.4270nA            -0.8025nA
+  1.55    4.6216nA          13.7460nA            -4.4469nA
+  1.65    1.0975nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8985nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2565nA            -22.2600nA
+  2.15    -16.3730nA        -7.8414nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.7026/0.4330n      0.4966/0.5731n      1.0018/0.3242n
+dV/dt_f  0.6827/0.4387n      0.4730/0.5599n      0.9168/0.3576n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.1621V           2.3517V              1.9420V
+0.1010nS          2.1621V           2.3517V              1.9420V
+0.2020nS          2.1621V           2.3517V              1.9420V
+0.3030nS          2.1621V           2.3517V              1.9420V
+0.4040nS          2.1621V           2.3517V              1.9420V
+0.5051nS          2.1622V           2.3517V              2.2421V
+0.6061nS          2.1615V           2.3517V              2.8060V
+0.7071nS          2.2762V           2.3517V              3.1342V
+0.8081nS          2.7361V           2.3522V              3.3164V
+0.9091nS          2.9561V           2.3515V              3.3898V
+1.0101nS          3.0907V           2.3704V              3.4244V
+1.1111nS          3.1772V           2.6051V              3.4432V
+1.2121nS          3.2242V           2.8360V              3.4539V
+1.3131nS          3.2509V           2.9413V              3.4602V
+1.4141nS          3.2670V           3.0020V              3.4639V
+1.5152nS          3.2775V           3.0439V              3.4662V
+1.6162nS          3.2845V           3.0714V              3.4676V
+1.7172nS          3.2892V           3.0897V              3.4685V
+1.8182nS          3.2924V           3.1025V              3.4690V
+1.9192nS          3.2946V           3.1117V              3.4694V
+2.0202nS          3.2961V           3.1186V              3.4696V
+2.1212nS          3.2972V           3.1237V              3.4697V
+2.2222nS          3.2980V           3.1276V              3.4698V
+2.3232nS          3.2986V           3.1305V              3.4699V
+2.4242nS          3.2989V           3.1327V              3.4699V
+2.5253nS          3.2992V           3.1344V              3.4699V
+2.6263nS          3.2994V           3.1356V              3.4699V
+2.7273nS          3.2996V           3.1366V              3.4699V
+2.8283nS          3.2997V           3.1373V              3.4699V
+2.9293nS          3.2998V           3.1379V              3.4700V
+3.0303nS          3.2998V           3.1383V              3.4699V
+3.1313nS          3.2999V           3.1387V              3.4700V
+3.2323nS          3.2999V           3.1390V              3.4699V
+3.3333nS          3.2999V           3.1392V              3.4700V
+3.4343nS          3.2999V           3.1393V              3.4699V
+3.5354nS          3.2999V           3.1395V              3.4700V
+3.6364nS          3.3000V           3.1396V              3.4699V
+3.7374nS          3.3000V           3.1397V              3.4700V
+3.8384nS          3.3000V           3.1397V              3.4700V
+3.9394nS          3.3000V           3.1398V              3.4700V
+4.0404nS          3.3000V           3.1398V              3.4700V
+4.1414nS          3.3000V           3.1399V              3.4700V
+4.2424nS          3.3000V           3.1399V              3.4700V
+4.3434nS          3.3000V           3.1399V              3.4700V
+4.4444nS          3.3000V           3.1400V              3.4700V
+4.5455nS          3.3000V           3.1400V              3.4700V
+4.6465nS          3.3000V           3.1399V              3.4700V
+4.7475nS          3.3000V           3.1400V              3.4700V
+4.8485nS          3.3000V           3.1400V              3.4700V
+4.9495nS          3.3000V           3.1400V              3.4700V
+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4699V
+5.2525nS          3.3000V           3.1400V              3.4700V
+5.3535nS          3.3000V           3.1400V              3.4700V
+5.4545nS          3.3000V           3.1400V              3.4700V
+5.5556nS          3.3000V           3.1400V              3.4699V
+5.6566nS          3.3000V           3.1400V              3.4700V
+5.7576nS          3.3000V           3.1400V              3.4700V
+5.8586nS          3.3000V           3.1400V              3.4700V
+5.9596nS          3.3000V           3.1400V              3.4699V
+6.0606nS          3.3000V           3.1400V              3.4700V
+6.1616nS          3.3000V           3.1400V              3.4700V
+6.2626nS          3.3000V           3.1400V              3.4700V
+6.3636nS          3.3000V           3.1400V              3.4699V
+6.4646nS          3.3000V           3.1400V              3.4700V
+6.5657nS          3.3000V           3.1400V              3.4700V
+6.6667nS          3.3000V           3.1400V              3.4700V
+6.7677nS          3.3000V           3.1400V              3.4699V
+6.8687nS          3.3000V           3.1400V              3.4700V
+6.9697nS          3.3000V           3.1400V              3.4700V
+7.0707nS          3.3000V           3.1400V              3.4700V
+7.1717nS          3.3000V           3.1400V              3.4700V
+7.2727nS          3.3000V           3.1400V              3.4700V
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+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.2884uV          1.5543uV             1.3225uV
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+9.8990nS          1.1110V          0.8277V            1.6696V   
+10.0000nS          1.1109V          0.8277V            1.6696V   
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S          1.1109V          0.8277V            1.6696V   
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+10.0000nS         -1.0707uV         8.4164uV             -6.6712uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
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+5.0505nS          2.1622V           2.3519V              1.9420V
+5.1515nS          2.1622V           2.3518V              1.9420V
+5.2525nS          2.1622V           2.3518V              1.9420V
+5.3535nS          2.1622V           2.3518V              1.9420V
+5.4545nS          2.1622V           2.3518V              1.9420V
+5.5556nS          2.1622V           2.3518V              1.9420V
+5.6566nS          2.1622V           2.3517V              1.9420V
+5.7576nS          2.1621V           2.3517V              1.9420V
+5.8586nS          2.1621V           2.3517V              1.9420V
+5.9596nS          2.1621V           2.3517V              1.9420V
+6.0606nS          2.1621V           2.3517V              1.9420V
+6.1616nS          2.1621V           2.3517V              1.9420V
+6.2626nS          2.1621V           2.3517V              1.9420V
+6.3636nS          2.1621V           2.3517V              1.9420V
+6.4646nS          2.1621V           2.3517V              1.9420V
+6.5657nS          2.1621V           2.3517V              1.9420V
+6.6667nS          2.1622V           2.3517V              1.9420V
+6.7677nS          2.1621V           2.3517V              1.9420V
+6.8687nS          2.1621V           2.3517V              1.9420V
+6.9697nS          2.1621V           2.3517V              1.9420V
+7.0707nS          2.1621V           2.3517V              1.9420V
+7.1717nS          2.1621V           2.3517V              1.9420V
+7.2727nS          2.1621V           2.3517V              1.9420V
+7.3737nS          2.1621V           2.3517V              1.9420V
+7.4747nS          2.1621V           2.3517V              1.9420V
+7.5758nS          2.1621V           2.3517V              1.9420V
+7.6768nS          2.1621V           2.3517V              1.9420V
+7.7778nS          2.1621V           2.3517V              1.9420V
+7.8788nS          2.1621V           2.3517V              1.9420V
+7.9798nS          2.1621V           2.3517V              1.9420V
+8.0808nS          2.1621V           2.3517V              1.9420V
+8.1818nS          2.1621V           2.3517V              1.9420V
+8.2828nS          2.1621V           2.3517V              1.9420V
+8.3838nS          2.1621V           2.3517V              1.9420V
+8.4848nS          2.1621V           2.3517V              1.9420V
+8.5859nS          2.1621V           2.3517V              1.9420V
+8.6869nS          2.1621V           2.3517V              1.9420V
+8.7879nS          2.1621V           2.3517V              1.9420V
+8.8889nS          2.1621V           2.3517V              1.9420V
+8.9899nS          2.1621V           2.3517V              1.9420V
+9.0909nS          2.1621V           2.3517V              1.9420V
+9.1919nS          2.1621V           2.3517V              1.9420V
+9.2929nS          2.1621V           2.3517V              1.9420V
+9.3939nS          2.1621V           2.3517V              1.9420V
+9.4949nS          2.1621V           2.3517V              1.9420V
+9.5960nS          2.1621V           2.3517V              1.9420V
+9.6970nS          2.1621V           2.3517V              1.9420V
+9.7980nS          2.1621V           2.3517V              1.9420V
+9.8990nS          2.1621V           2.3517V              1.9420V
+10.0000nS         2.1621V           2.3517V              1.9420V
+|  
+| End [Model] lvt330s040aaaaaaaaou
+|************************************************************************
+[Model]           lvt330s040haaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.8000V
+Vinh =            2.0000V
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -13.0175mA        -9.4589mA            -17.0245mA
+  -3.20    -12.9707mA        -9.4248mA            -16.9624mA
+  -3.10    -12.9240mA        -9.3908mA            -16.9003mA
+  -3.00    -12.8773mA        -9.3568mA            -16.8383mA
+  -2.90    -12.8305mA        -9.3227mA            -16.7762mA
+  -2.80    -12.7838mA        -9.2887mA            -16.7142mA
+  -2.70    -12.7370mA        -9.2546mA            -16.6521mA
+  -2.60    -12.6903mA        -9.2206mA            -16.5900mA
+  -2.50    -12.6435mA        -9.1866mA            -16.5280mA
+  -2.40    -12.5968mA        -9.1525mA            -16.4659mA
+  -2.30    -12.5500mA        -9.1185mA            -16.4038mA
+  -2.20    -12.5033mA        -9.0845mA            -16.3418mA
+  -2.10    -12.4566mA        -9.0504mA            -16.2797mA
+  -2.00    -12.4098mA        -9.0164mA            -16.2176mA
+  -1.90    -12.3631mA        -8.9824mA            -16.1556mA
+  -1.80    -12.3163mA        -8.9483mA            -16.0935mA
+  -1.70    -12.2696mA        -8.9143mA            -16.0314mA
+  -1.60    -12.2228mA        -8.8803mA            -15.9694mA
+  -1.50    -12.1761mA        -8.8462mA            -15.9073mA
+  -1.40    -12.1293mA        -8.8122mA            -15.8453mA
+  -1.30    -12.0826mA        -8.7781mA            -15.7832mA
+  -1.20    -12.0359mA        -8.7441mA            -15.7211mA
+  -1.10    -11.9891mA        -8.7101mA            -15.6591mA
+  -1.00    -11.9424mA        -8.6760mA            -15.5970mA
+  -0.90    -11.8920mA        -8.6420mA            -14.2580mA
+  -0.80    -11.2030mA        -8.5040mA            -13.3310mA
+  -0.70    -10.6640mA        -8.3180mA            -12.8580mA
+  -0.60    -10.1775mA        -7.9085mA            -12.5090mA
+  -0.50    -9.6242mA         -7.2249mA            -12.2652mA
+  -0.40    -8.4558mA         -6.0810mA            -11.1990mA
+  -0.30    -6.5017mA         -4.6206mA            -8.6527mA
+  -0.20    -4.3829mA         -3.0989mA            -5.8476mA
+  -0.10    -2.2159mA         -1.5586mA            -2.9656mA
+  0.00    1.3970nA          1.1420nA             1.8430nA
+  0.10    2.1875mA          1.5273mA             2.9429mA
+  0.20    4.2657mA          2.9723mA             5.7511mA
+  0.30    6.2349mA          4.3353mA             8.4238mA
+  0.40    8.0952mA          5.6169mA             10.9612mA
+  0.50    9.8472mA          6.8175mA             13.3613mA
+  0.60    11.4909mA         7.9379mA             15.6250mA
+  0.70    13.0251mA         8.9781mA             17.7500mA
+  0.80    14.4502mA         9.9381mA             19.7321mA
+  0.90    15.7635mA         10.8176mA            21.5658mA
+  1.00    16.9605mA         11.6151mA            23.2399mA
+  1.10    18.0347mA         12.3297mA            24.7385mA
+  1.20    18.9760mA         12.9574mA            26.0423mA
+  1.30    19.7754mA         13.4941mA            27.1313mA
+  1.40    20.4319mA         13.9418mA            28.0074mA
+  1.50    21.1825mA         14.4344mA            28.6916mA
+  1.60    21.5959mA         14.7249mA            29.6115mA
+  1.70    21.9250mA         14.9601mA            30.0279mA
+  1.80    22.1935mA         15.1539mA            30.3626mA
+  1.90    22.4157mA         15.3154mA            30.6368mA
+  2.00    22.6034mA         15.4536mA            30.8683mA
+  2.10    22.7656mA         15.5735mA            31.0653mA
+  2.20    22.9074mA         15.6790mA            31.2357mA
+  2.30    23.0328mA         15.7722mA            31.3865mA
+  2.40    23.1458mA         15.8561mA            31.5207mA
+  2.50    23.2463mA         15.9326mA            31.6404mA
+  2.60    23.3383mA         16.0018mA            31.7495mA
+  2.70    23.4230mA         16.0657mA            31.8480mA
+  2.80    23.5002mA         16.1243mA            31.9389mA
+  2.90    23.5720mA         16.1785mA            32.0223mA
+  3.00    23.6383mA         16.2294mA            32.0991mA
+  3.10    23.7003mA         16.2770mA            32.1714mA
+  3.20    23.7588mA         16.3211mA            32.2390mA
+  3.30    23.8138mA         16.3630mA            32.3031mA
+  3.40    23.8674mA         16.4006mA            32.3667mA
+  3.50    23.9193mA         16.4233mA            32.4306mA
+  3.60    23.9674mA         16.4889mA            32.4982mA
+  3.70    23.9882mA         16.5546mA            32.5708mA
+  3.80    24.0840mA         16.6202mA            32.6441mA
+  3.90    24.1798mA         16.6859mA            32.7359mA
+  4.00    24.2756mA         16.7515mA            32.8665mA
+  4.10    24.3714mA         16.8172mA            32.9972mA
+  4.20    24.4672mA         16.8828mA            33.1278mA
+  4.30    24.5630mA         16.9485mA            33.2584mA
+  4.40    24.6588mA         17.0142mA            33.3891mA
+  4.50    24.7546mA         17.0798mA            33.5197mA
+  4.60    24.8504mA         17.1455mA            33.6503mA
+  4.70    24.9462mA         17.2111mA            33.7810mA
+  4.80    25.0420mA         17.2768mA            33.9116mA
+  4.90    25.1378mA         17.3424mA            34.0423mA
+  5.00    25.2336mA         17.4081mA            34.1729mA
+  5.10    25.3294mA         17.4737mA            34.3035mA
+  5.20    25.4252mA         17.5394mA            34.4342mA
+  5.30    25.5210mA         17.6051mA            34.5648mA
+  5.40    25.6168mA         17.6707mA            34.6955mA
+  5.50    25.7126mA         17.7364mA            34.8261mA
+  5.60    25.8084mA         17.8020mA            34.9567mA
+  5.70    25.9042mA         17.8677mA            35.0874mA
+  5.80    25.9999mA         17.9333mA            35.2180mA
+  5.90    26.0957mA         17.9990mA            35.3486mA
+  6.00    26.1915mA         18.0647mA            35.4793mA
+  6.10    26.2873mA         18.1303mA            35.6099mA
+  6.20    26.3831mA         18.1960mA            35.7406mA
+  6.30    26.4789mA         18.2616mA            35.8712mA
+  6.40    26.5747mA         18.3273mA            36.0018mA
+  6.50    26.6705mA         18.3929mA            36.1325mA
+  6.60    26.7663mA         18.4586mA            36.2631mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+-3.30       60.9662mA       46.6308mA        87.0217mA    
+-3.20       60.7240mA       46.4472mA        86.7600mA    
+-3.10       60.2994mA       46.2636mA        85.3500mA    
+-3.00       59.0755mA       46.0800mA        83.1700mA    
+-2.90       57.3963mA       45.5300mA        80.5900mA    
+-2.80       55.4705mA       44.3800mA        77.7700mA    
+-2.70       53.3739mA       42.9200mA        74.8000mA    
+-2.60       51.1729mA       41.2800mA        71.7300mA    
+-2.50       48.8960mA       39.5320mA        68.6000mA    
+-2.40       46.5650mA       37.7130mA        65.4100mA    
+-2.30       44.2113mA       35.8570mA        62.2000mA    
+-2.20       41.8320mA       33.9950mA        58.9610mA    
+-2.10       39.4555mA       32.1310mA        55.7110mA    
+-2.00       37.1056mA       30.2880mA        52.4470mA    
+-1.90       34.7793mA       28.4710mA        49.1720mA    
+-1.80       32.5319mA       26.6850mA        45.8900mA    
+-1.70       30.3631mA       24.9360mA        42.6060mA    
+-1.60       28.2959mA       23.2280mA        39.3910mA    
+-1.50       26.3236mA       21.5600mA        36.3540mA    
+-1.40       24.4385mA       19.9360mA        33.5720mA    
+-1.30       22.6312mA       18.3560mA        31.0630mA    
+-1.20       20.8932mA       16.8240mA        28.8020mA    
+-1.10       19.2273mA       15.3490mA        26.8550mA    
+-1.00       17.6525mA       13.9360mA        25.6750mA    
+-0.90       16.2417mA       12.5950mA        24.4660mA    
+-0.80       14.9068mA       11.3600mA        21.3180mA    
+-0.70       13.2931mA       10.2971mA        18.9703mA    
+-0.60       11.6685mA       9.2483mA        16.9105mA    
+-0.50       9.9513mA       7.8709mA        14.6683mA    
+-0.40       7.9801mA       6.2914mA        11.8564mA    
+-0.30       5.9303mA       4.6622mA        8.8439mA    
+-0.20       3.9153mA       3.0657mA        5.8617mA    
+-0.10       1.9400mA       1.5124mA        2.9160mA    
+0.00       -6.9700nA       -2.5700nA        -86.5000nA    
+0.10       -1.8799mA       -1.4564mA        -2.8429mA    
+0.20       -3.6735mA       -2.8408mA        -5.5653mA    
+0.30       -5.3808mA       -4.1535mA        -8.1679mA    
+0.40       -7.0025mA       -5.3952mA        -10.6515mA    
+0.50       -8.5393mA       -6.5665mA        -13.0149mA    
+0.60       -9.9917mA       -7.6679mA        -15.2608mA    
+0.70       -11.3594mA       -8.6999mA        -17.3894mA    
+0.80       -12.6449mA       -9.6632mA        -19.4005mA    
+0.90       -13.8465mA       -10.5579mA        -21.2942mA    
+1.00       -14.9659mA       -11.3853mA        -23.0724mA    
+1.10       -16.0032mA       -12.1460mA        -24.7353mA    
+1.20       -16.9593mA       -12.8401mA        -26.2837mA    
+1.30       -17.8352mA       -13.4675mA        -27.7167mA    
+1.40       -18.6299mA       -14.0302mA        -29.0372mA    
+1.50       -19.3454mA       -14.5272mA        -30.2434mA    
+1.60       -19.9815mA       -14.9606mA        -31.3381mA    
+1.70       -20.5404mA       -15.3313mA        -32.3204mA    
+1.80       -21.0208mA       -15.7720mA        -33.1924mA    
+1.90       -21.6437mA       -16.0228mA        -34.3429mA    
+2.00       -21.9782mA       -16.2184mA        -35.0021mA    
+2.10       -22.2442mA       -16.3681mA        -35.5553mA    
+2.20       -22.4522mA       -16.4866mA        -36.0104mA    
+2.30       -22.6203mA       -16.5871mA        -36.3794mA    
+2.40       -22.7636mA       -16.6772mA        -36.6831mA    
+2.50       -22.8919mA       -16.7617mA        -36.9446mA    
+2.60       -23.0116mA       -16.8402mA        -37.1814mA    
+2.70       -23.1247mA       -16.9153mA        -37.4005mA    
+2.80       -23.2299mA       -16.9860mA        -37.6054mA    
+2.90       -23.3289mA       -17.0521mA        -37.7972mA    
+3.00       -23.4225mA       -17.1156mA        -37.9765mA    
+3.10       -23.5107mA       -17.1755mA        -38.1452mA    
+3.20       -23.5932mA       -17.2307mA        -38.3020mA    
+3.30       -23.6690mA       -17.2845mA        -38.4487mA    
+3.40       -23.7421mA       -17.3317mA        -38.5851mA    
+3.50       -23.8099mA       -17.3821mA        -38.7103mA    
+3.60       -23.8639mA       -17.4515mA        -38.8302mA    
+3.70       -23.9593mA       -17.5209mA        -38.9459mA    
+3.80       -24.0548mA       -17.5902mA        -39.0277mA    
+3.90       -24.1501mA       -17.6596mA        -39.1834mA    
+4.00       -24.2455mA       -17.7290mA        -39.3392mA    
+4.10       -24.3409mA       -17.7983mA        -39.4949mA    
+4.20       -24.4363mA       -17.8677mA        -39.6506mA    
+4.30       -24.5317mA       -17.9371mA        -39.8063mA    
+4.40       -24.6271mA       -18.0064mA        -39.9620mA    
+4.50       -24.7225mA       -18.0758mA        -40.1178mA    
+4.60       -24.8179mA       -18.1452mA        -40.2735mA    
+4.70       -24.9133mA       -18.2145mA        -40.4292mA    
+4.80       -25.0087mA       -18.2839mA        -40.5849mA    
+4.90       -25.1041mA       -18.3532mA        -40.7406mA    
+5.00       -25.1995mA       -18.4226mA        -40.8964mA    
+5.10       -25.2949mA       -18.4920mA        -41.0521mA    
+5.20       -25.3902mA       -18.5613mA        -41.2078mA    
+5.30       -25.4857mA       -18.6307mA        -41.3635mA    
+5.40       -25.5810mA       -18.7001mA        -41.5192mA    
+5.50       -25.6765mA       -18.7694mA        -41.6750mA    
+5.60       -25.7719mA       -18.8388mA        -41.8307mA    
+5.70       -25.8673mA       -18.9082mA        -41.9864mA    
+5.80       -25.9627mA       -18.9775mA        -42.1421mA    
+5.90       -26.0580mA       -19.0469mA        -42.2978mA    
+6.00       -26.1535mA       -19.1163mA        -42.4536mA    
+6.10       -26.2488mA       -19.1856mA        -42.6093mA    
+6.20       -26.3443mA       -19.2550mA        -42.7650mA    
+6.30       -26.4396mA       -19.3244mA        -42.9207mA    
+6.40       -26.5350mA       -19.3937mA        -43.0764mA    
+6.50       -26.6305mA       -19.4631mA        -43.2322mA    
+6.55       -26.6781mA       -19.4978mA        -43.3100mA    
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9552A          -0.9302A             -0.9778A
+  -3.25    -0.9306A          -0.9058A             -0.9532A
+  -3.20    -0.9061A          -0.8814A             -0.9285A
+  -3.15    -0.8815A          -0.857A              -0.9039A
+  -3.10    -0.857A           -0.8327A             -0.8792A
+  -3.05    -0.8325A          -0.8083A             -0.8546A
+  -3.00    -0.808A           -0.784A              -0.83A
+  -2.95    -0.7836A          -0.7597A             -0.8054A
+  -2.90    -0.7591A          -0.7355A             -0.7808A
+  -2.85    -0.7347A          -0.7112A             -0.7563A
+  -2.80    -0.7103A          -0.6871A             -0.7317A
+  -2.75    -0.6859A          -0.6629A             -0.7072A
+  -2.70    -0.6616A          -0.6388A             -0.6827A
+  -2.65    -0.6373A          -0.6148A             -0.6582A
+  -2.60    -0.613A           -0.5908A             -0.6338A
+  -2.55    -0.5888A          -0.5668A             -0.6094A
+  -2.50    -0.5646A          -0.543A              -0.585A
+  -2.45    -0.5405A          -0.5192A             -0.5607A
+  -2.40    -0.5165A          -0.4955A             -0.5364A
+  -2.35    -0.4925A          -0.4719A             -0.5122A
+  -2.30    -0.4686A          -0.4484A             -0.488A
+  -2.25    -0.4448A          -0.425A              -0.4639A
+  -2.20    -0.421A           -0.4018A             -0.4398A
+  -2.15    -0.3975A          -0.3788A             -0.4159A
+  -2.10    -0.374A           -0.3561A             -0.3921A
+  -2.05    -0.3508A          -0.3336A             -0.3684A
+  -2.00    -0.3278A          -0.3115A             -0.3449A
+  -1.95    -0.3051A          -0.2898A             -0.3216A
+  -1.90    -0.2829A          -0.2688A             -0.2986A
+  -1.85    -0.2611A          -0.2485A             -0.276A
+  -1.80    -0.2402A          -0.2293A             -0.2541A
+  -1.75    -0.2203A          -0.2115A             -0.233A
+  -1.70    -0.2019A          -0.1953A             -0.2133A
+  -1.65    -0.1856A          -0.1809A             -0.1957A
+  -1.60    -0.1716A          -0.1681A             -0.1809A
+  -1.55    -0.1593A          -0.1563A             -0.1683A
+  -1.50    -0.148A           -0.1451A             -0.157A
+  -1.45    -0.1371A          -0.1342A             -0.146A
+  -1.40    -0.1266A          -0.1236A             -0.1353A
+  -1.35    -0.1161A          -0.1131A             -0.1248A
+  -1.30    -0.1059A          -0.1029A             -0.1145A
+  -1.25    -95.8525mA        -92.7685mA           -0.1044A
+  -1.20    -86.0775mA        -82.8695mA           -94.7415mA
+  -1.15    -76.6285mA        -73.2225mA           -85.5735mA
+  -1.10    -67.6045mA        -63.8875mA           -77.1175mA
+  -1.05    -59.1405mA        -54.9455mA           -69.5895mA
+  -1.00    -51.4145mA        -46.5095mA           -63.0585mA
+  -0.95    -44.6125mA        -38.7355mA           -57.1555mA
+  -0.90    -38.7695mA        -31.8215mA           -51.1065mA
+  -0.85    -33.4345mA        -25.8545mA           -44.5675mA
+  -0.80    -28.1565mA        -20.5265mA           -37.8185mA
+  -0.75    -22.9755mA        -15.7285mA           -31.1295mA
+  -0.70    -18.0095mA        -11.5805mA           -24.6635mA
+  -0.65    -13.3705mA        -8.0894mA            -18.5475mA
+  -0.60    -9.185mA          -5.219mA             -12.9245mA
+  -0.55    -5.6163mA         -2.9834mA            -7.9946mA
+  -0.50    -2.8703mA         -1.4348mA            -4.0643mA
+  -0.45    -1.1245mA         -0.5536mA            -1.5008mA
+  -0.40    -0.308mA          -0.1624mA            -0.3485mA
+  -0.35    -35.6uA           -20.3890uA           -16.0uA
+  -0.30    0.0A              0.0A                 0.0A
+  -0.25    0.0A              0.0A                 0.0A
+  -0.20    0.0A              0.0A                 0.0A
+  -0.15    0.0A              0.0A                 0.0A
+  -0.10    0.0A              0.0A                 0.0A
+  -0.05    0.0A              0.0A                 0.0A
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.1221A           0.1248A              0.1242A
+  -3.15    0.1200A           0.1232A              0.1212A
+  -3.05    0.1178A           0.1215A              0.1181A
+  -2.95    0.1153A           0.1196A              0.1148A
+  -2.85    0.1128A           0.1174A              0.1114A
+  -2.75    0.1100A           0.1151A              0.1078A
+  -2.65    0.1071A           0.1126A              0.1041A
+  -2.55    0.1039A           0.1098A              0.1001A
+  -2.45    0.1006A           0.1069A              95.9680mA
+  -2.35    97.0630mA         0.1037A              91.5590mA
+  -2.25    93.2670mA         0.1003A              86.8480mA
+  -2.15    89.1920mA         96.7010mA            81.7630mA
+  -2.05    84.8070mA         92.8600mA            76.2010mA
+  -1.95    80.0800mA         88.7860mA            70.0340mA
+  -1.85    74.9870mA         84.4790mA            63.1570mA
+  -1.75    69.5180mA         79.9450mA            55.5700mA
+  -1.65    63.6850mA         75.1950mA            47.4010mA
+  -1.55    57.5160mA         70.2440mA            38.8580mA
+  -1.45    51.0440mA         65.1120mA            30.1910mA
+  -1.35    44.3150mA         59.8210mA            21.8920mA
+  -1.25    37.3820mA         54.3940mA            15.5340mA
+  -1.15    30.3110mA         48.8520mA            11.4230mA
+  -1.05    23.2090mA         43.2090mA            6.9858mA
+  -0.95    16.3160mA         37.4680mA            3.1948mA
+  -0.85    10.2960mA         31.6320mA            0.8600mA
+  -0.75    6.1213mA          25.7150mA            0.1694mA
+  -0.65    3.1679mA          19.7630mA            65.5350uA
+  -0.55    1.1362mA          13.8830mA            37.1010uA
+  -0.45    0.2574mA          8.3464mA             19.4580uA
+  -0.35    73.3430uA         3.8624mA             3.1206uA
+  -0.25    33.6580uA         1.3608mA             -12.8040uA
+  -0.15    17.7650uA         0.3668mA             -28.1570uA
+  -0.05    5.8276uA          90.2420uA            -42.9420uA
+  0.00    0.1897uA          50.8660uA            -50.1210uA
+  0.05    -5.3380uA         31.9340uA            -57.1590uA
+  0.15    -16.0560uA        15.1110uA            -70.8070uA
+  0.25    -26.3450uA        5.7330uA             -83.8870uA
+  0.35    -36.2070uA        -2.2074uA            -96.3970uA
+  0.45    -45.6400uA        -9.6847uA            -0.1083mA
+  0.55    -54.6440uA        -16.8200uA           -0.1197mA
+  0.65    -63.2180uA        -23.6240uA           -0.1305mA
+  0.75    -71.3610uA        -30.0980uA           -0.1407mA
+  0.85    -79.0710uA        -36.2430uA           -0.1504mA
+  0.95    -86.3480uA        -42.0600uA           -0.1594mA
+  1.05    -93.1890uA        -47.5470uA           -0.1679mA
+  1.15    -99.5930uA        -52.7050uA           -0.1758mA
+  1.25    -0.1056mA         -57.5350uA           -0.1832mA
+  1.35    -0.1111mA         -62.0370uA           -0.1899mA
+  1.45    -0.1162mA         -66.2090uA           -0.1961mA
+  1.55    -0.1208mA         -70.0530uA           -0.2016mA
+  1.65    -0.1250mA         -73.5690uA           -0.2016mA
+  1.75    -0.1287mA         -76.7560uA           -0.2016mA
+  1.85    -0.1305mA         -79.6150uA           -0.2016mA
+  1.95    -0.1305mA         -82.1480uA           -0.2016mA
+  2.05    -0.1305mA         -83.2920uA           -0.2016mA
+  2.15    -0.1305mA         -83.2920uA           -0.2016mA
+  2.25    -0.1305mA         -83.2920uA           -0.2016mA
+  2.35    -0.1305mA         -83.2920uA           -0.2016mA
+  2.45    -0.1305mA         -83.2920uA           -0.2016mA
+  2.55    -0.1305mA         -83.2920uA           -0.2016mA
+  2.65    -0.1305mA         -83.2920uA           -0.2016mA
+  2.75    -0.1305mA         -83.2920uA           -0.2016mA
+  2.85    -0.1305mA         -83.2920uA           -0.2016mA
+  2.95    -0.1305mA         -83.2920uA           -0.2016mA
+  3.05    -0.1305mA         -83.2920uA           -0.2016mA
+  3.15    -0.1305mA         -83.2920uA           -0.2016mA
+  3.25    -0.1305mA         -83.2920uA           -0.2016mA
+  6.60    -0.1305mA         -83.292uA            -0.2016mA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.7026/0.4330n      0.4966/0.5731n      1.0018/0.3242n
+dV/dt_f  0.6827/0.4387n      0.4730/0.5599n      0.9168/0.3576n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.1621V           2.3517V              1.9420V
+0.1010nS          2.1621V           2.3517V              1.9420V
+0.2020nS          2.1621V           2.3517V              1.9420V
+0.3030nS          2.1621V           2.3517V              1.9420V
+0.4040nS          2.1621V           2.3517V              1.9420V
+0.5051nS          2.1622V           2.3517V              2.2421V
+0.6061nS          2.1615V           2.3517V              2.8060V
+0.7071nS          2.2762V           2.3517V              3.1342V
+0.8081nS          2.7361V           2.3522V              3.3164V
+0.9091nS          2.9561V           2.3515V              3.3898V
+1.0101nS          3.0907V           2.3704V              3.4244V
+1.1111nS          3.1772V           2.6051V              3.4432V
+1.2121nS          3.2242V           2.8360V              3.4539V
+1.3131nS          3.2509V           2.9413V              3.4602V
+1.4141nS          3.2670V           3.0020V              3.4639V
+1.5152nS          3.2775V           3.0439V              3.4662V
+1.6162nS          3.2845V           3.0714V              3.4676V
+1.7172nS          3.2892V           3.0897V              3.4685V
+1.8182nS          3.2924V           3.1025V              3.4690V
+1.9192nS          3.2946V           3.1117V              3.4694V
+2.0202nS          3.2961V           3.1186V              3.4696V
+2.1212nS          3.2972V           3.1237V              3.4697V
+2.2222nS          3.2980V           3.1276V              3.4698V
+2.3232nS          3.2986V           3.1305V              3.4699V
+2.4242nS          3.2989V           3.1327V              3.4699V
+2.5253nS          3.2992V           3.1344V              3.4699V
+2.6263nS          3.2994V           3.1356V              3.4699V
+2.7273nS          3.2996V           3.1366V              3.4699V
+2.8283nS          3.2997V           3.1373V              3.4699V
+2.9293nS          3.2998V           3.1379V              3.4700V
+3.0303nS          3.2998V           3.1383V              3.4699V
+3.1313nS          3.2999V           3.1387V              3.4700V
+3.2323nS          3.2999V           3.1390V              3.4699V
+3.3333nS          3.2999V           3.1392V              3.4700V
+3.4343nS          3.2999V           3.1393V              3.4699V
+3.5354nS          3.2999V           3.1395V              3.4700V
+3.6364nS          3.3000V           3.1396V              3.4699V
+3.7374nS          3.3000V           3.1397V              3.4700V
+3.8384nS          3.3000V           3.1397V              3.4700V
+3.9394nS          3.3000V           3.1398V              3.4700V
+4.0404nS          3.3000V           3.1398V              3.4700V
+4.1414nS          3.3000V           3.1399V              3.4700V
+4.2424nS          3.3000V           3.1399V              3.4700V
+4.3434nS          3.3000V           3.1399V              3.4700V
+4.4444nS          3.3000V           3.1400V              3.4700V
+4.5455nS          3.3000V           3.1400V              3.4700V
+4.6465nS          3.3000V           3.1399V              3.4700V
+4.7475nS          3.3000V           3.1400V              3.4700V
+4.8485nS          3.3000V           3.1400V              3.4700V
+4.9495nS          3.3000V           3.1400V              3.4700V
+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4699V
+5.2525nS          3.3000V           3.1400V              3.4700V
+5.3535nS          3.3000V           3.1400V              3.4700V
+5.4545nS          3.3000V           3.1400V              3.4700V
+5.5556nS          3.3000V           3.1400V              3.4699V
+5.6566nS          3.3000V           3.1400V              3.4700V
+5.7576nS          3.3000V           3.1400V              3.4700V
+5.8586nS          3.3000V           3.1400V              3.4700V
+5.9596nS          3.3000V           3.1400V              3.4699V
+6.0606nS          3.3000V           3.1400V              3.4700V
+6.1616nS          3.3000V           3.1400V              3.4700V
+6.2626nS          3.3000V           3.1400V              3.4700V
+6.3636nS          3.3000V           3.1400V              3.4699V
+6.4646nS          3.3000V           3.1400V              3.4700V
+6.5657nS          3.3000V           3.1400V              3.4700V
+6.6667nS          3.3000V           3.1400V              3.4700V
+6.7677nS          3.3000V           3.1400V              3.4699V
+6.8687nS          3.3000V           3.1400V              3.4700V
+6.9697nS          3.3000V           3.1400V              3.4700V
+7.0707nS          3.3000V           3.1400V              3.4700V
+7.1717nS          3.3000V           3.1400V              3.4700V
+7.2727nS          3.3000V           3.1400V              3.4700V
+7.3737nS          3.3000V           3.1400V              3.4700V
+7.4747nS          3.3000V           3.1400V              3.4700V
+7.5758nS          3.3000V           3.1400V              3.4700V
+7.6768nS          3.3000V           3.1400V              3.4700V
+7.7778nS          3.3000V           3.1400V              3.4700V
+7.8788nS          3.3000V           3.1400V              3.4700V
+7.9798nS          3.3000V           3.1400V              3.4699V
+8.0808nS          3.3000V           3.1400V              3.4700V
+8.1818nS          3.3000V           3.1400V              3.4700V
+8.2828nS          3.3000V           3.1400V              3.4700V
+8.3838nS          3.3000V           3.1400V              3.4700V
+8.4848nS          3.3000V           3.1400V              3.4700V
+8.5859nS          3.3000V           3.1400V              3.4700V
+8.6869nS          3.3000V           3.1400V              3.4700V
+8.7879nS          3.3000V           3.1400V              3.4700V
+8.8889nS          3.3000V           3.1400V              3.4700V
+8.9899nS          3.3000V           3.1400V              3.4700V
+9.0909nS          3.3000V           3.1400V              3.4700V
+9.1919nS          3.3000V           3.1400V              3.4700V
+9.2929nS          3.3000V           3.1400V              3.4700V
+9.3939nS          3.3000V           3.1400V              3.4700V
+9.4949nS          3.3000V           3.1400V              3.4700V
+9.5960nS          3.3000V           3.1400V              3.4700V
+9.6970nS          3.3000V           3.1400V              3.4700V
+9.7980nS          3.3000V           3.1400V              3.4700V
+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.2884uV          1.5543uV             1.3225uV
+0.1010nS          0.5355uV          0.8430uV             0.6254uV
+0.2020nS          -3.0614uV         0.1113uV             0.5701uV
+0.3030nS          0.6806uV          -1.9546uV            10.3860uV
+0.4040nS          3.2624uV          1.2769uV             -0.2118mV
+0.5051nS          32.7230uV         1.5286uV             -24.1640mV
+0.6061nS          -0.3955mV         2.8080uV             -9.9395mV
+0.7071nS          -15.7200mV        17.6660uV            0.1561V
+0.8081nS          -19.9850mV        99.9200uV            0.5397V
+0.9091nS          -0.4586mV         -0.2072mV            0.9226V
+1.0101nS          88.3420mV         -6.1838mV            1.2091V
+1.1111nS          0.2478V          -18.1000mV            1.3886V   
+1.2121nS          0.4471V          -16.0430mV            1.4951V   
+1.3131nS          0.6318V          -10.1180mV            1.5589V   
+1.4141nS          0.7749V          8.8815mV            1.5984V   
+1.5152nS          0.8766V          55.5920mV            1.6234V   
+1.6162nS          0.9465V          0.1340V            1.6394V   
+1.7172nS          0.9942V          0.2360V            1.6498V   
+1.8182nS          1.0272V          0.3461V            1.6566V   
+1.9192nS          1.0502V          0.4492V            1.6613V   
+2.0202nS          1.0667V          0.5367V            1.6638V   
+2.1212nS          1.0785V          0.6066V            1.6656V   
+2.2222nS          1.0871V          0.6605V            1.6667V   
+2.3232nS          1.0934V          0.7013V            1.6675V   
+2.4242nS          1.0979V          0.7318V            1.6680V   
+2.5253nS          1.1013V          0.7546V            1.6684V   
+2.6263nS          1.1038V          0.7716V            1.6687V   
+2.7273nS          1.1056V          0.7845V            1.6689V   
+2.8283nS          1.1069V          0.7942V            1.6691V   
+2.9293nS          1.1080V          0.8016V            1.6693V   
+3.0303nS          1.1087V          0.8073V            1.6693V   
+3.1313nS          1.1093V          0.8118V            1.6694V   
+3.2323nS          1.1097V          0.8152V            1.6695V   
+3.3333nS          1.1100V          0.8178V            1.6695V   
+3.4343nS          1.1103V          0.8199V            1.6695V   
+3.5354nS          1.1104V          0.8215V            1.6696V   
+3.6364nS          1.1105V          0.8228V            1.6695V   
+3.7374nS          1.1106V          0.8238V            1.6696V   
+3.8384nS          1.1107V          0.8246V            1.6696V   
+3.9394nS          1.1107V          0.8252V            1.6696V   
+4.0404nS          1.1108V          0.8257V            1.6696V   
+4.1414nS          1.1108V          0.8261V            1.6696V   
+4.2424nS          1.1108V          0.8265V            1.6696V   
+4.3434nS          1.1109V          0.8267V            1.6696V   
+4.4444nS          1.1109V          0.8269V            1.6696V   
+4.5455nS          1.1109V          0.8271V            1.6696V   
+4.6465nS          1.1109V          0.8272V            1.6696V   
+4.7475nS          1.1109V          0.8273V            1.6696V   
+4.8485nS          1.1109V          0.8274V            1.6696V   
+4.9495nS          1.1109V          0.8274V            1.6696V   
+5.0505nS          1.1109V          0.8276V            1.6696V   
+5.1515nS          1.1109V          0.8276V            1.6696V   
+5.2525nS          1.1109V          0.8276V            1.6696V   
+5.3535nS          1.1109V          0.8276V            1.6696V   
+5.4545nS          1.1109V          0.8276V            1.6696V   
+5.5556nS          1.1109V          0.8276V            1.6696V   
+5.6566nS          1.1109V          0.8276V            1.6696V   
+5.7576nS          1.1109V          0.8277V            1.6696V   
+5.8586nS          1.1109V          0.8277V            1.6696V   
+5.9596nS          1.1109V          0.8277V            1.6696V   
+6.0606nS          1.1109V          0.8277V            1.6696V   
+6.1616nS          1.1109V          0.8277V            1.6696V   
+6.2626nS          1.1109V          0.8277V            1.6696V   
+6.3636nS          1.1109V          0.8277V            1.6696V   
+6.4646nS          1.1109V          0.8277V            1.6696V   
+6.5657nS          1.1109V          0.8277V            1.6696V   
+6.6667nS          1.1110V          0.8277V            1.6696V   
+6.7677nS          1.1109V          0.8277V            1.6696V   
+6.8687nS          1.1109V          0.8277V            1.6696V   
+6.9697nS          1.1109V          0.8277V            1.6696V   
+7.0707nS          1.1110V          0.8277V            1.6696V   
+7.1717nS          1.1109V          0.8277V            1.6696V   
+7.2727nS          1.1110V          0.8277V            1.6696V   
+7.3737nS          1.1110V          0.8277V            1.6696V   
+7.4747nS          1.1110V          0.8277V            1.6696V   
+7.5758nS          1.1110V          0.8277V            1.6696V   
+7.6768nS          1.1110V          0.8277V            1.6696V   
+7.7778nS          1.1109V          0.8277V            1.6696V   
+7.8788nS          1.1110V          0.8277V            1.6696V   
+7.9798nS          1.1110V          0.8277V            1.6696V   
+8.0808nS          1.1110V          0.8277V            1.6696V   
+8.1818nS          1.1109V          0.8277V            1.6696V   
+8.2828nS          1.1110V          0.8277V            1.6696V   
+8.3838nS          1.1110V          0.8277V            1.6696V   
+8.4848nS          1.1110V          0.8277V            1.6696V   
+8.5859nS          1.1110V          0.8277V            1.6696V   
+8.6869nS          1.1110V          0.8277V            1.6696V   
+8.7879nS          1.1109V          0.8277V            1.6696V   
+8.8889nS          1.1109V          0.8277V            1.6696V   
+8.9899nS          1.1109V          0.8277V            1.6696V   
+9.0909nS          1.1109V          0.8277V            1.6696V   
+9.1919nS          1.1109V          0.8277V            1.6696V   
+9.2929nS          1.1109V          0.8277V            1.6696V   
+9.3939nS          1.1109V          0.8277V            1.6696V   
+9.4949nS          1.1109V          0.8277V            1.6696V   
+9.5960nS          1.1109V          0.8277V            1.6696V   
+9.6970nS          1.1110V          0.8277V            1.6696V   
+9.7980nS          1.1110V          0.8277V            1.6696V   
+9.8990nS          1.1110V          0.8277V            1.6696V   
+10.0000nS          1.1109V          0.8277V            1.6696V   
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S          1.1109V          0.8277V            1.6696V   
+0.1010nS          1.1109V          0.8277V            1.6696V   
+0.2020nS          1.1109V          0.8277V            1.6696V   
+0.3030nS          1.1110V          0.8277V            1.6696V   
+0.4040nS          1.1110V          0.8277V            1.6696V   
+0.5051nS          1.1109V          0.8277V            1.6644V   
+0.6061nS          1.1110V          0.8277V            1.0431V   
+0.7071nS          1.1113V          0.8277V            0.4157V   
+0.8081nS          0.9851V          0.8277V            0.1612V   
+0.9091nS          0.5727V          0.8276V            77.0900mV   
+1.0101nS          0.2814V          0.8282V            40.8740mV   
+1.1111nS          0.1329V          0.8285V            22.9430mV   
+1.2121nS          73.6840mV         0.7997V              12.4510mV
+1.3131nS          43.0370mV         0.5895V              6.8313mV
+1.4141nS          26.7550mV         0.3604V              3.7992mV
+1.5152nS          17.0970mV         0.2116V              2.1510mV
+1.6162nS          11.1140mV         0.1248V              1.2529mV
+1.7172nS          7.2776mV          75.3210mV            0.7544mV
+1.8182nS          4.8176mV          47.2290mV            0.4826mV
+1.9192nS          3.1888mV          31.3570mV            0.3253mV
+2.0202nS          2.1519mV          21.8020mV            0.2392mV
+2.1212nS          1.4430mV          15.5850mV            0.1806mV
+2.2222nS          1.0065mV          11.3310mV            0.1485mV
+2.3232nS          0.6888mV          8.3187mV             0.1251mV
+2.4242nS          0.5069mV          6.1527mV             0.1108mV
+2.5253nS          0.3566mV          4.5704mV             0.1026mV
+2.6263nS          0.2717mV          3.4134mV             96.2470uV
+2.7273nS          0.1995mV          2.5569mV             87.3860uV
+2.8283nS          0.1853mV          1.9272mV             82.9260uV
+2.9293nS          0.1277mV          1.4565mV             68.6140uV
+3.0303nS          0.1252mV          1.1098mV             60.2230uV
+3.1313nS          89.5590uV         0.8485mV             49.7170uV
+3.2323nS          94.4160uV         0.6561mV             56.7570uV
+3.3333nS          49.7470uV         0.5093mV             54.1530uV
+3.4343nS          57.0870uV         0.3863mV             49.3370uV
+3.5354nS          52.4280uV         0.3073mV             42.7020uV
+3.6364nS          77.0030uV         0.2451mV             40.7070uV
+3.7374nS          46.1550uV         0.1875mV             33.9890uV
+3.8384nS          63.3650uV         0.1621mV             34.0740uV
+3.9394nS          31.9750uV         0.1378mV             27.5110uV
+4.0404nS          46.0820uV         0.1176mV             33.5240uV
+4.1414nS          14.0450uV         0.1002mV             26.4520uV
+4.2424nS          30.8440uV         91.6770uV            22.6270uV
+4.3434nS          23.9580uV         76.4830uV            15.2880uV
+4.4444nS          37.9550uV         66.7720uV            22.2140uV
+4.5455nS          20.1420uV         54.3060uV            29.8260uV
+4.6465nS          38.7320uV         46.2710uV            31.2670uV
+4.7475nS          7.9010uV          34.7060uV            23.8310uV
+4.8485nS          28.9680uV         27.4260uV            23.1060uV
+4.9495nS          3.7079uV          16.8370uV            10.7150uV
+5.0505nS          4.6522uV          25.8205uV            14.7445uV
+5.1515nS          12.5270uV         19.1810uV            11.7510uV
+5.2525nS          10.5410uV         17.0160uV            5.4213uV
+5.3535nS          42.1190uV         11.8180uV            8.5329uV
+5.4545nS          11.4930uV         19.2340uV            13.1240uV
+5.5556nS          38.3480uV         27.0890uV            18.1120uV
+5.6566nS          1.7742uV          38.8120uV            11.7850uV
+5.7576nS          22.6050uV         31.4050uV            7.1004uV
+5.8586nS          -3.9145uV         19.9240uV            -7.3305uV
+5.9596nS          13.3160uV         7.4008uV             0.4354uV
+6.0606nS          7.3534uV          -0.9538uV            7.7540uV
+6.1616nS          33.4920uV         -8.2614uV            8.9420uV
+6.2626nS          9.8852uV          1.6769uV             5.0332uV
+6.3636nS          25.5040uV         16.3790uV            2.4944uV
+6.4646nS          -2.5946uV         32.5920uV            -5.3283uV
+6.5657nS          4.1073uV          30.8730uV            6.9637uV
+6.6667nS          2.1062uV          21.8930uV            7.5789uV
+6.7677nS          10.6270uV         5.1201uV             6.5788uV
+6.8687nS          -19.4020uV        -8.0928uV            0.9709uV
+6.9697nS          3.6023uV          5.3486uV             -0.4159uV
+7.0707nS          -20.2800uV        10.3380uV            -4.1503uV
+7.1717nS          19.4790uV         23.0950uV            -4.9697uV
+7.2727nS          -10.7860uV        7.5118uV             -8.6698uV
+7.3737nS          21.7550uV         9.0311uV             -7.4803uV
+7.4747nS          12.4390uV         -5.6908uV            -10.4050uV
+7.5758nS          18.3510uV         -4.5175uV            -8.2164uV
+7.6768nS          -7.8114uV         1.1510uV             -10.8020uV
+7.7778nS          2.0275uV          12.3600uV            -1.5528uV
+7.8788nS          -76.1190nV        12.0690uV            6.6952uV
+7.9798nS          4.0097uV          8.9861uV             10.0890uV
+8.0808nS          0.4972uV          -1.8875uV            0.6130uV
+8.1818nS          0.5840uV          -11.3150uV           -1.5820uV
+8.2828nS          -12.7280uV        -15.9390uV           -8.5048uV
+8.3838nS          3.4867uV          -5.2058uV            -1.9719uV
+8.4848nS          -4.5739uV         2.6217uV             0.5424uV
+8.5859nS          4.1249uV          2.6585uV             4.0878uV
+8.6869nS          -12.0140uV        -0.6919uV            6.4732uV
+8.7879nS          -3.8915uV         -10.4690uV           7.0541uV
+8.8889nS          -10.5260uV        -22.7580uV           2.8919uV
+8.9899nS          2.5661uV          -25.3070uV           -3.3709uV
+9.0909nS          -2.9240uV         -11.4390uV           -5.9996uV
+9.1919nS          -3.0241uV         -1.1643uV            0.8082uV
+9.2929nS          -7.9366uV         5.3328uV             0.4492uV
+9.3939nS          -2.3621uV         8.5118uV             5.8039uV
+9.4949nS          -9.1146uV         -8.6006uV            -2.4704uV
+9.5960nS          -3.7574uV         -19.3450uV           -0.8494uV
+9.6970nS          -16.6030uV        -15.4900uV           -2.2380uV
+9.7980nS          -2.4824uV         -3.6242uV            4.0030uV
+9.8990nS          -18.6820uV        15.5490uV            1.5950uV
+10.0000nS         -1.0707uV         8.4164uV             -6.6712uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
+0.1010nS          3.3000V           3.1400V              3.4700V
+0.2020nS          3.3000V           3.1400V              3.4700V
+0.3030nS          3.3000V           3.1400V              3.4700V
+0.4040nS          3.3000V           3.1400V              3.4700V
+0.5051nS          3.3000V           3.1400V              3.4758V
+0.6061nS          3.3001V           3.1400V              3.4570V
+0.7071nS          3.2983V           3.1400V              3.0951V
+0.8081nS          3.3299V           3.1400V              2.7403V
+0.9091nS          3.2987V           3.1398V              2.4747V
+1.0101nS          3.1080V           3.1409V              2.2935V
+1.1111nS          2.8866V           3.1388V              2.1742V
+1.2121nS          2.6919V           3.1507V              2.0966V
+1.3131nS          2.5414V           3.1748V              2.0453V
+1.4141nS          2.4321V           3.1565V              2.0112V
+1.5152nS          2.3547V           3.0752V              1.9884V
+1.6162nS          2.3001V           2.9642V              1.9732V
+1.7172nS          2.2616V           2.8458V              1.9629V
+1.8182nS          2.2341V           2.7389V              1.9561V
+1.9192nS          2.2145V           2.6506V              1.9515V
+2.0202nS          2.2003V           2.5809V              1.9484V
+2.1212nS          2.1900V           2.5272V              1.9463V
+2.2222nS          2.1826V           2.4862V              1.9450V
+2.3232nS          2.1771V           2.4551V              1.9440V
+2.4242nS          2.1731V           2.4314V              1.9434V
+2.5253nS          2.1702V           2.4134V              1.9430V
+2.6263nS          2.1681V           2.3996V              1.9427V
+2.7273nS          2.1665V           2.3890V              1.9425V
+2.8283nS          2.1654V           2.3808V              1.9424V
+2.9293nS          2.1646V           2.3745V              1.9423V
+3.0303nS          2.1639V           2.3696V              1.9422V
+3.1313nS          2.1635V           2.3658V              1.9422V
+3.2323nS          2.1631V           2.3628V              1.9421V
+3.3333nS          2.1629V           2.3604V              1.9421V
+3.4343nS          2.1627V           2.3586V              1.9421V
+3.5354nS          2.1626V           2.3572V              1.9420V
+3.6364nS          2.1625V           2.3560V              1.9421V
+3.7374nS          2.1624V           2.3551V              1.9421V
+3.8384nS          2.1623V           2.3544V              1.9421V
+3.9394nS          2.1623V           2.3539V              1.9420V
+4.0404nS          2.1622V           2.3534V              1.9420V
+4.1414nS          2.1622V           2.3531V              1.9420V
+4.2424nS          2.1622V           2.3528V              1.9420V
+4.3434nS          2.1622V           2.3526V              1.9420V
+4.4444nS          2.1622V           2.3524V              1.9420V
+4.5455nS          2.1622V           2.3523V              1.9420V
+4.6465nS          2.1622V           2.3522V              1.9420V
+4.7475nS          2.1622V           2.3521V              1.9420V
+4.8485nS          2.1622V           2.3520V              1.9420V
+4.9495nS          2.1622V           2.3519V              1.9420V
+5.0505nS          2.1622V           2.3519V              1.9420V
+5.1515nS          2.1622V           2.3518V              1.9420V
+5.2525nS          2.1622V           2.3518V              1.9420V
+5.3535nS          2.1622V           2.3518V              1.9420V
+5.4545nS          2.1622V           2.3518V              1.9420V
+5.5556nS          2.1622V           2.3518V              1.9420V
+5.6566nS          2.1622V           2.3517V              1.9420V
+5.7576nS          2.1621V           2.3517V              1.9420V
+5.8586nS          2.1621V           2.3517V              1.9420V
+5.9596nS          2.1621V           2.3517V              1.9420V
+6.0606nS          2.1621V           2.3517V              1.9420V
+6.1616nS          2.1621V           2.3517V              1.9420V
+6.2626nS          2.1621V           2.3517V              1.9420V
+6.3636nS          2.1621V           2.3517V              1.9420V
+6.4646nS          2.1621V           2.3517V              1.9420V
+6.5657nS          2.1621V           2.3517V              1.9420V
+6.6667nS          2.1622V           2.3517V              1.9420V
+6.7677nS          2.1621V           2.3517V              1.9420V
+6.8687nS          2.1621V           2.3517V              1.9420V
+6.9697nS          2.1621V           2.3517V              1.9420V
+7.0707nS          2.1621V           2.3517V              1.9420V
+7.1717nS          2.1621V           2.3517V              1.9420V
+7.2727nS          2.1621V           2.3517V              1.9420V
+7.3737nS          2.1621V           2.3517V              1.9420V
+7.4747nS          2.1621V           2.3517V              1.9420V
+7.5758nS          2.1621V           2.3517V              1.9420V
+7.6768nS          2.1621V           2.3517V              1.9420V
+7.7778nS          2.1621V           2.3517V              1.9420V
+7.8788nS          2.1621V           2.3517V              1.9420V
+7.9798nS          2.1621V           2.3517V              1.9420V
+8.0808nS          2.1621V           2.3517V              1.9420V
+8.1818nS          2.1621V           2.3517V              1.9420V
+8.2828nS          2.1621V           2.3517V              1.9420V
+8.3838nS          2.1621V           2.3517V              1.9420V
+8.4848nS          2.1621V           2.3517V              1.9420V
+8.5859nS          2.1621V           2.3517V              1.9420V
+8.6869nS          2.1621V           2.3517V              1.9420V
+8.7879nS          2.1621V           2.3517V              1.9420V
+8.8889nS          2.1621V           2.3517V              1.9420V
+8.9899nS          2.1621V           2.3517V              1.9420V
+9.0909nS          2.1621V           2.3517V              1.9420V
+9.1919nS          2.1621V           2.3517V              1.9420V
+9.2929nS          2.1621V           2.3517V              1.9420V
+9.3939nS          2.1621V           2.3517V              1.9420V
+9.4949nS          2.1621V           2.3517V              1.9420V
+9.5960nS          2.1621V           2.3517V              1.9420V
+9.6970nS          2.1621V           2.3517V              1.9420V
+9.7980nS          2.1621V           2.3517V              1.9420V
+9.8990nS          2.1621V           2.3517V              1.9420V
+10.0000nS         2.1621V           2.3517V              1.9420V
+|  
+| End [Model] lvt330s040haaaaaaaio
+|************************************************************************
+[Model]           lvt330s160aaaaaaaaou
+Model_type        Output
+Polarity          Non-Inverting
+Enable            Active-Low
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.00    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.90    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.80    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.70    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.60    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.50    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.40    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.00    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.90    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.80    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.70    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.60    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.50    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.40    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.00    -46.0510mA        -33.7410mA           -57.7460mA
+  -0.90    -45.1960mA        -33.7410mA           -53.3800mA
+  -0.80    -42.7900mA        -33.0880mA           -50.7690mA
+  -0.70    -40.7010mA        -32.1190mA           -48.9510mA
+  -0.60    -38.5892mA        -30.1763mA           -47.3570mA
+  -0.50    -35.7989mA        -27.1490mA           -45.2332mA
+  -0.40    -30.5530mA        -22.5448mA           -39.2561mA
+  -0.30    -23.3101mA        -17.0730mA           -30.0082mA
+  -0.20    -15.6753mA        -11.4360mA           -20.2124mA
+  -0.10    -7.9044mA         -5.7449mA            -10.2109mA
+  0.00    9.1810nA          6.6370nA             14.6880nA
+  0.10    7.8212mA          5.6449mA             10.1501mA
+  0.20    15.3310mA         11.0300mA            19.9541mA
+  0.30    22.5240mA         16.1530mA            29.4071mA
+  0.40    29.3980mA         21.0130mA            38.5000mA
+  0.50    35.9480mA         25.6080mA            47.2270mA
+  0.60    42.1700mA         29.9370mA            55.5800mA
+  0.70    48.0590mA         33.9980mA            63.5490mA
+  0.80    53.6080mA         37.7880mA            71.1220mA
+  0.90    58.8090mA         41.3050mA            78.2850mA
+  1.00    63.6510mA         44.5440mA            85.0150mA
+  1.10    68.1160mA         47.4970mA            91.2820mA
+  1.20    72.1780mA         50.1540mA            97.0390mA
+  1.30    75.8000mA         52.4980mA            0.1022A
+  1.40    78.9390mA         54.5150mA            0.1067A
+  1.50    81.5710mA         56.2010mA            0.1106A
+  1.60    83.7180mA         57.5820mA            0.1137A
+  1.70    85.4430mA         58.7040mA            0.1161A
+  1.80    86.8340mA         59.6220mA            0.1181A
+  1.90    87.9720mA         60.3850mA            0.1196A
+  2.00    88.9210mA         61.0310mA            0.1209A
+  2.10    89.7270mA         61.5880mA            0.1220A
+  2.20    90.4240mA         62.0750mA            0.1229A
+  2.30    91.0370mA         62.5080mA            0.1237A
+  2.40    91.5820mA         62.8970mA            0.1244A
+  2.50    92.0740mA         63.2500mA            0.1250A
+  2.60    92.5210mA         63.5730mA            0.1256A
+  2.70    92.9309mA         63.8720mA            0.1261A
+  2.80    93.3099mA         64.1499mA            0.1266A
+  2.90    93.6629mA         64.4089mA            0.1270A
+  3.00    93.9929mA         64.6529mA            0.1274A
+  3.10    94.3029mA         64.8829mA            0.1278A
+  3.20    94.5958mA         65.1008mA            0.1281A
+  3.30    94.8758mA         65.3076mA            0.1285A
+  3.40    95.1436mA         65.5013mA            0.1288A
+  3.50    95.4017mA         65.6576mA            0.1291A
+  3.60    95.6462mA         65.9236mA            0.1294A
+  3.70    95.8369mA         66.2546mA            0.1298A
+  3.80    96.2034mA         67.0655mA            0.1301A
+  3.90    96.5733mA         69.0584mA            0.1303A
+  4.00    97.3652mA         73.2123mA            0.1309A
+  4.10    99.2509mA         79.1820mA            0.1314A
+  4.20    0.1022A           85.9597mA            0.1322A
+  4.30    0.1063A           93.0914mA            0.1344A
+  4.40    0.1126A           0.1004A              0.1384A
+  4.50    0.1206A           0.1078A              0.1435A
+  4.60    0.1294A           0.1153A              0.1489A
+  4.70    0.1385A           0.1229A              0.1551A
+  4.80    0.1479A           0.1307A              0.1648A
+  4.90    0.1573A           0.1386A              0.1760A
+  5.00    0.1669A           0.1467A              0.1878A
+  5.10    0.1765A           0.1550A              0.1999A
+  5.20    0.1863A           0.1634A              0.2120A
+  5.30    0.1961A           0.1719A              0.2241A
+  5.40    0.2062A           0.1805A              0.2362A
+  5.50    0.2163A           0.1892A              0.2482A
+  5.60    0.2265A           0.1980A              0.2603A
+  5.70    0.2369A           0.2068A              0.2726A
+  5.80    0.2473A           0.2158A              0.2851A
+  5.90    0.2579A           0.2248A              0.2978A
+  6.00    0.2687A           0.2339A              0.3108A
+  6.10    0.2796A           0.2431A              0.3240A
+  6.20    0.2907A           0.2524A              0.3374A
+  6.30    0.3021A           0.2618A              0.3511A
+  6.40    0.3136A           0.2714A              0.3652A
+  6.50    0.3254A           0.2811A              0.3794A
+  6.60    0.3374A           0.2909A              0.3940A
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    0.3688A           0.3085A              0.4482A
+  -3.20    0.3595A           0.3039A              0.4356A
+  -3.10    0.3495A           0.2972A              0.4227A
+  -3.00    0.3390A           0.2892A              0.4094A
+  -2.90    0.3282A           0.2805A              0.3959A
+  -2.80    0.3171A           0.2712A              0.3822A
+  -2.70    0.3056A           0.2615A              0.3683A
+  -2.60    0.2939A           0.2514A              0.3543A
+  -2.50    0.2819A           0.2409A              0.3400A
+  -2.40    0.2697A           0.2303A              0.3256A
+  -2.30    0.2573A           0.2194A              0.3110A
+  -2.20    0.2447A           0.2084A              0.2962A
+  -2.10    0.2318A           0.1972A              0.2811A
+  -2.00    0.2189A           0.1859A              0.2659A
+  -1.90    0.2058A           0.1745A              0.2504A
+  -1.80    0.1927A           0.1631A              0.2346A
+  -1.70    0.1795A           0.1517A              0.2186A
+  -1.60    0.1662A           0.1402A              0.2025A
+  -1.50    0.1528A           0.1288A              0.1863A
+  -1.40    0.1394A           0.1175A              0.1702A
+  -1.30    0.1260A           0.1062A              0.1543A
+  -1.20    0.1126A           94.9202mA            0.1391A
+  -1.10    99.3436mA         83.7786mA            0.1252A
+  -1.00    86.4581mA         72.7899mA            0.1110A
+  -0.90    74.6466mA         62.0952mA            97.2911mA
+  -0.80    64.2979mA         52.0534mA            84.6162mA
+  -0.70    54.8762mA         43.3265mA            72.7261mA
+  -0.60    46.1133mA         35.9755mA            61.5078mA
+  -0.50    37.8734mA         29.3476mA            50.1553mA
+  -0.40    29.8849mA         23.1046mA            40.2866mA
+  -0.30    22.2622mA         17.0802mA            30.1199mA
+  -0.20    14.7337mA         11.2591mA            20.0045mA
+  -0.10    7.3149mA          5.5671mA             9.9673mA
+  0.00    -27.6800nA        -12.5600nA           -0.2990uA
+  0.10    -7.1350mA         -5.3932mA            -9.7862mA
+  0.20    -14.0071mA        -10.5601mA           -19.2690mA
+  0.30    -20.6131mA        -15.4991mA           -28.4448mA
+  0.40    -26.9531mA        -20.2101mA           -37.3096mA
+  0.50    -33.0231mA        -24.6920mA           -45.8605mA
+  0.60    -38.8211mA        -28.9440mA           -54.0924mA
+  0.70    -44.3460mA        -32.9660mA           -62.0013mA
+  0.80    -49.5950mA        -36.7560mA           -69.5842mA
+  0.90    -54.5660mA        -40.3130mA           -76.8361mA
+  1.00    -59.2570mA        -43.6380mA           -83.7531mA
+  1.10    -63.6650mA        -46.7280mA           -90.3311mA
+  1.20    -67.7890mA        -49.5840mA           -96.5660mA
+  1.30    -71.6270mA        -52.2040mA           -0.1025A
+  1.40    -75.1760mA        -54.5890mA           -0.1080A
+  1.50    -78.4330mA        -56.7370mA           -0.1132A
+  1.60    -81.3980mA        -58.6480mA           -0.1180A
+  1.70    -84.0680mA        -60.3220mA           -0.1224A
+  1.80    -86.4420mA        -61.7600mA           -0.1265A
+  1.90    -88.5180mA        -62.9650mA           -0.1302A
+  2.00    -90.2990mA        -63.9430mA           -0.1335A
+  2.10    -91.7860mA        -64.7110mA           -0.1365A
+  2.20    -92.9940mA        -65.3040mA           -0.1391A
+  2.30    -93.9530mA        -65.7740mA           -0.1412A
+  2.40    -94.7160mA        -66.1750mA           -0.1431A
+  2.50    -95.3540mA        -66.5370mA           -0.1446A
+  2.60    -95.9200mA        -66.8780mA           -0.1458A
+  2.70    -96.4460mA        -67.2020mA           -0.1469A
+  2.80    -96.9450mA        -67.5150mA           -0.1478A
+  2.90    -97.4230mA        -67.8180mA           -0.1487A
+  3.00    -97.8850mA        -68.1109mA           -0.1495A
+  3.10    -98.3320mA        -68.3969mA           -0.1504A
+  3.20    -98.7659mA        -68.6739mA           -0.1511A
+  3.30    -99.1879mA        -68.9436mA           -0.1519A
+  3.40    -99.5979mA        -69.2026mA           -0.1526A
+  3.50    -99.9963mA        -69.3920mA           -0.1533A
+  3.60    -0.1004A          -69.3920mA           -0.1540A
+  3.70    -0.1005A          -69.3920mA           -0.1547A
+  3.80    -0.1005A          -69.3920mA           -0.1553A
+  3.90    -0.1005A          -69.3920mA           -0.1554A
+  4.00    -0.1005A          -69.3920mA           -0.1554A
+  4.10    -0.1005A          -69.3920mA           -0.1554A
+  4.20    -0.1005A          -69.3920mA           -0.1554A
+  4.30    -0.1005A          -69.3920mA           -0.1554A
+  4.40    -0.1005A          -69.3920mA           -0.1554A
+  4.50    -0.1005A          -69.3920mA           -0.1554A
+  4.60    -0.1005A          -69.3920mA           -0.1554A
+  4.70    -0.1005A          -69.3920mA           -0.1554A
+  4.80    -0.1005A          -69.3920mA           -0.1554A
+  4.90    -0.1005A          -69.3920mA           -0.1554A
+  5.00    -0.1005A          -69.3920mA           -0.1554A
+  5.10    -0.1005A          -69.3920mA           -0.1554A
+  5.20    -0.1005A          -69.3920mA           -0.1554A
+  5.30    -0.1005A          -69.3920mA           -0.1554A
+  5.40    -0.1005A          -69.3920mA           -0.1554A
+  5.50    -0.1005A          -69.3920mA           -0.1554A
+  5.60    -0.1005A          -69.3920mA           -0.1554A
+  5.70    -0.1005A          -69.3920mA           -0.1554A
+  5.80    -0.1005A          -69.3920mA           -0.1554A
+  5.90    -0.1005A          -69.3920mA           -0.1554A
+  6.00    -0.1005A          -69.3920mA           -0.1554A
+  6.10    -0.1005A          -69.3920mA           -0.1554A
+  6.20    -0.1005A          -69.3920mA           -0.1554A
+  6.30    -0.1005A          -69.3920mA           -0.1554A
+  6.40    -0.1005A          -69.3920mA           -0.1554A
+  6.50    -0.1005A          -69.3920mA           -0.1554A
+  6.55    -0.1005A          -69.3920mA           -0.1554A
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.6648mA          0.7494mA             0.5971mA
+  -3.15    0.5464mA          0.6392mA             0.4620mA
+  -3.05    0.4320mA          0.5325mA             0.3346mA
+  -2.95    0.3223mA          0.4288mA             0.2203mA
+  -2.85    0.2202mA          0.3288mA             0.1294mA
+  -2.75    0.1318mA          0.2341mA             72.8320uA
+  -2.65    67.1940uA         0.1484mA             47.8300uA
+  -2.55    33.3840uA         79.2130uA            38.1430uA
+  -2.45    21.1020uA         36.2270uA            33.4230uA
+  -2.35    16.7350uA         18.9540uA            30.1320uA
+  -2.25    14.6020uA         13.5630uA            27.2570uA
+  -2.15    13.0530uA         11.4700uA            24.5650uA
+  -2.05    11.6730uA         10.2220uA            22.0130uA
+  -1.95    10.3790uA         9.1903uA             19.5970uA
+  -1.85    9.1554uA          8.2406uA             17.3220uA
+  -1.75    8.0024uA          7.3472uA             15.1930uA
+  -1.65    6.9220uA          6.5055uA             13.2180uA
+  -1.55    5.9168uA          5.7151uA             11.4030uA
+  -1.45    4.9897uA          4.9762uA             9.7538uA
+  -1.35    4.1435uA          4.2896uA             8.2775uA
+  -1.25    3.3813uA          3.6558uA             6.9794uA
+  -1.15    2.7058uA          3.0755uA             5.8656uA
+  -1.05    2.1197uA          2.5496uA             4.9436uA
+  -0.95    1.6260uA          2.0788uA             4.2185uA
+  -0.85    1.2282uA          1.6639uA             3.6568uA
+  -0.75    0.9321uA          1.3059uA             3.6568uA
+  -0.65    0.7406uA          1.0064uA             3.6568uA
+  -0.55    0.6334uA          0.7687uA             3.6568uA
+  -0.45    0.5657uA          0.5976uA             1.9769uA
+  -0.35    0.5657uA          0.4934uA             1.5352uA
+  -0.25    0.5657uA          0.4388uA             1.2603uA
+  -0.15    0.5657uA          0.4063uA             1.0262uA
+  -0.05    0.2497uA          0.3931uA             0.8243uA
+  0.00    0.1905uA          0.3931uA             0.7347uA
+  0.05    0.1661uA          0.3931uA             0.6522uA
+  0.15    0.1377uA          0.3931uA             0.5077uA
+  0.25    0.1149uA          0.2673uA             0.3882uA
+  0.35    95.5840nA         94.4790nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2000nA          17.4270nA            -0.8025nA
+  1.55    4.6215nA          13.7460nA            -4.4469nA
+  1.65    1.0974nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8986nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2566nA            -22.2600nA
+  2.15    -16.3730nA        -7.8413nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  1.4966/0.2592n      1.2936/0.4087n      1.7021/0.1678n
+dV/dt_f  1.5290/0.2281n      1.3043/0.3741n      1.7112/0.1501n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.7516V           0.9661V              0.6180V
+0.1010nS          0.7516V           0.9661V              0.6180V
+0.2020nS          0.7516V           0.9661V              0.6180V
+0.3030nS          0.7516V           0.9661V              0.6180V
+0.4040nS          0.7516V           0.9661V              0.6171V
+0.5051nS          0.7517V           0.9661V              0.7829V
+0.6061nS          0.7505V           0.9661V              2.0255V
+0.7071nS          0.7950V           0.9661V              2.8797V
+0.8081nS          1.7861V           0.9664V              3.3462V
+0.9091nS          2.4193V           0.9655V              3.4176V
+1.0101nS          2.8512V           0.9681V              3.4439V
+1.1111nS          3.1357V           1.3754V              3.4564V
+1.2121nS          3.2249V           2.1421V              3.4627V
+1.3131nS          3.2565V           2.5293V              3.4661V
+1.4141nS          3.2737V           2.7345V              3.4678V
+1.5152nS          3.2838V           2.8969V              3.4688V
+1.6162nS          3.2896V           3.0120V              3.4693V
+1.7172nS          3.2934V           3.0632V              3.4696V
+1.8182nS          3.2957V           3.0894V              3.4697V
+1.9192nS          3.2972V           3.1045V              3.4698V
+2.0202nS          3.2981V           3.1151V              3.4699V
+2.1212nS          3.2987V           3.1221V              3.4699V
+2.2222nS          3.2991V           3.1274V              3.4699V
+2.3232nS          3.2994V           3.1308V              3.4699V
+2.4242nS          3.2996V           3.1334V              3.4700V
+2.5253nS          3.2997V           3.1352V              3.4700V
+2.6263nS          3.2998V           3.1365V              3.4700V
+2.7273nS          3.2998V           3.1374V              3.4700V
+2.8283nS          3.2999V           3.1380V              3.4700V
+2.9293nS          3.2999V           3.1385V              3.4700V
+3.0303nS          3.2999V           3.1389V              3.4700V
+3.1313nS          3.2999V           3.1391V              3.4700V
+3.2323nS          3.3000V           3.1393V              3.4700V
+3.3333nS          3.3000V           3.1395V              3.4700V
+3.4343nS          3.3000V           3.1396V              3.4700V
+3.5354nS          3.3000V           3.1397V              3.4700V
+3.6364nS          3.3000V           3.1398V              3.4700V
+3.7374nS          3.3000V           3.1398V              3.4700V
+3.8384nS          3.3000V           3.1398V              3.4700V
+3.9394nS          3.3000V           3.1399V              3.4700V
+4.0404nS          3.3000V           3.1399V              3.4700V
+4.1414nS          3.3000V           3.1399V              3.4700V
+4.2424nS          3.3000V           3.1399V              3.4700V
+4.3434nS          3.3000V           3.1399V              3.4700V
+4.4444nS          3.3000V           3.1399V              3.4700V
+4.5455nS          3.3000V           3.1400V              3.4700V
+4.6465nS          3.3000V           3.1400V              3.4700V
+4.7475nS          3.3000V           3.1400V              3.4700V
+4.8485nS          3.3000V           3.1400V              3.4700V
+4.9495nS          3.3000V           3.1400V              3.4700V
+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4700V
+5.2525nS          3.3000V           3.1400V              3.4700V
+5.3535nS          3.3000V           3.1400V              3.4700V
+5.4545nS          3.3000V           3.1400V              3.4700V
+5.5556nS          3.3000V           3.1400V              3.4700V
+5.6566nS          3.3000V           3.1400V              3.4700V
+5.7576nS          3.3000V           3.1400V              3.4700V
+5.8586nS          3.3000V           3.1400V              3.4700V
+5.9596nS          3.3000V           3.1400V              3.4700V
+6.0606nS          3.3000V           3.1400V              3.4700V
+6.1616nS          3.3000V           3.1400V              3.4700V
+6.2626nS          3.3000V           3.1400V              3.4700V
+6.3636nS          3.3000V           3.1400V              3.4700V
+6.4646nS          3.3000V           3.1400V              3.4700V
+6.5657nS          3.3000V           3.1400V              3.4700V
+6.6667nS          3.3000V           3.1400V              3.4700V
+6.7677nS          3.3000V           3.1400V              3.4700V
+6.8687nS          3.3000V           3.1400V              3.4700V
+6.9697nS          3.3000V           3.1400V              3.4700V
+7.0707nS          3.3000V           3.1400V              3.4700V
+7.1717nS          3.3000V           3.1400V              3.4700V
+7.2727nS          3.3000V           3.1400V              3.4700V
+7.3737nS          3.3000V           3.1400V              3.4700V
+7.4747nS          3.3000V           3.1400V              3.4700V
+7.5758nS          3.3000V           3.1400V              3.4700V
+7.6768nS          3.3000V           3.1400V              3.4700V
+7.7778nS          3.3000V           3.1400V              3.4700V
+7.8788nS          3.3000V           3.1400V              3.4700V
+7.9798nS          3.3000V           3.1400V              3.4700V
+8.0808nS          3.3000V           3.1400V              3.4700V
+8.1818nS          3.3000V           3.1400V              3.4700V
+8.2828nS          3.3000V           3.1400V              3.4700V
+8.3838nS          3.3000V           3.1400V              3.4700V
+8.4848nS          3.3000V           3.1400V              3.4700V
+8.5859nS          3.3000V           3.1400V              3.4700V
+8.6869nS          3.3000V           3.1400V              3.4700V
+8.7879nS          3.3000V           3.1400V              3.4700V
+8.8889nS          3.3000V           3.1400V              3.4700V
+8.9899nS          3.3000V           3.1400V              3.4700V
+9.0909nS          3.3000V           3.1400V              3.4700V
+9.1919nS          3.3000V           3.1400V              3.4700V
+9.2929nS          3.3000V           3.1400V              3.4700V
+9.3939nS          3.3000V           3.1400V              3.4700V
+9.4949nS          3.3000V           3.1400V              3.4700V
+9.5960nS          3.3000V           3.1400V              3.4700V
+9.6970nS          3.3000V           3.1400V              3.4700V
+9.7980nS          3.3000V           3.1400V              3.4700V
+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.4849uV          0.6538uV             0.4584uV
+0.1010nS          -91.8400nV        63.2160nV            -25.7920nV
+0.2020nS          -2.6993uV         -0.4530uV            -0.2185uV
+0.3030nS          -0.1263uV         -1.9171uV            9.8177uV
+0.4040nS          2.2148uV          0.3884uV             -0.7508mV
+0.5051nS          17.9080uV         0.4320uV             -54.9180mV
+0.6061nS          -0.9283mV         2.0154uV             -38.8140mV
+0.7071nS          -36.0310mV        19.4020uV            0.5590V
+0.8081nS          -59.6090mV        49.7370uV            1.7463V
+0.9091nS          -7.5013mV         -0.5918mV            2.5098V
+1.0101nS          0.3035V           -13.7970mV           2.7118V
+1.1111nS          0.8765V           -46.7140mV           2.7764V
+1.2121nS          1.5353V           -51.2590mV           2.8047V
+1.3131nS          2.0287V           -34.8250mV           2.8192V
+1.4141nS          2.2720V           25.7290mV            2.8271V
+1.5152nS          2.3732V           0.1849V              2.8315V
+1.6162nS          2.4197V           0.4573V              2.8339V
+1.7172nS          2.4473V           0.8065V              2.8353V
+1.8182nS          2.4633V           1.1645V              2.8360V
+1.9192nS          2.4738V           1.4818V              2.8364V
+2.0202nS          2.4810V           1.7269V              2.8366V
+2.1212nS          2.4853V           1.8846V              2.8368V
+2.2222nS          2.4883V           1.9770V              2.8368V
+2.3232nS          2.4902V           2.0335V              2.8369V
+2.4242nS          2.4916V           2.0698V              2.8369V
+2.5253nS          2.4924V           2.0942V              2.8369V
+2.6263nS          2.4930V           2.1112V              2.8369V
+2.7273nS          2.4934V           2.1231V              2.8370V
+2.8283nS          2.4937V           2.1316V              2.8369V
+2.9293nS          2.4938V           2.1374V              2.8370V
+3.0303nS          2.4940V           2.1420V              2.8369V
+3.1313nS          2.4940V           2.1455V              2.8370V
+3.2323nS          2.4942V           2.1480V              2.8369V
+3.3333nS          2.4941V           2.1499V              2.8370V
+3.4343nS          2.4942V           2.1514V              2.8369V
+3.5354nS          2.4942V           2.1525V              2.8370V
+3.6364nS          2.4943V           2.1533V              2.8369V
+3.7374nS          2.4942V           2.1539V              2.8370V
+3.8384nS          2.4943V           2.1544V              2.8369V
+3.9394nS          2.4942V           2.1548V              2.8370V
+4.0404nS          2.4943V           2.1551V              2.8369V
+4.1414nS          2.4942V           2.1553V              2.8370V
+4.2424nS          2.4943V           2.1554V              2.8369V
+4.3434nS          2.4942V           2.1556V              2.8370V
+4.4444nS          2.4943V           2.1557V              2.8369V
+4.5455nS          2.4942V           2.1557V              2.8370V
+4.6465nS          2.4943V           2.1558V              2.8369V
+4.7475nS          2.4942V           2.1558V              2.8370V
+4.8485nS          2.4943V           2.1559V              2.8369V
+4.9495nS          2.4942V           2.1559V              2.8370V
+5.0505nS          2.4942V           2.1559V              2.8369V
+5.1515nS          2.4943V           2.1560V              2.8369V
+5.2525nS          2.4943V           2.1560V              2.8370V
+5.3535nS          2.4943V           2.1560V              2.8369V
+5.4545nS          2.4943V           2.1560V              2.8370V
+5.5556nS          2.4943V           2.1560V              2.8369V
+5.6566nS          2.4943V           2.1560V              2.8370V
+5.7576nS          2.4943V           2.1560V              2.8370V
+5.8586nS          2.4943V           2.1560V              2.8370V
+5.9596nS          2.4943V           2.1560V              2.8370V
+6.0606nS          2.4943V           2.1560V              2.8370V
+6.1616nS          2.4943V           2.1560V              2.8370V
+6.2626nS          2.4943V           2.1560V              2.8370V
+6.3636nS          2.4943V           2.1560V              2.8370V
+6.4646nS          2.4943V           2.1560V              2.8370V
+6.5657nS          2.4943V           2.1560V              2.8370V
+6.6667nS          2.4943V           2.1560V              2.8370V
+6.7677nS          2.4943V           2.1560V              2.8370V
+6.8687nS          2.4943V           2.1560V              2.8370V
+6.9697nS          2.4943V           2.1560V              2.8370V
+7.0707nS          2.4943V           2.1560V              2.8370V
+7.1717nS          2.4943V           2.1560V              2.8370V
+7.2727nS          2.4943V           2.1560V              2.8370V
+7.3737nS          2.4943V           2.1560V              2.8370V
+7.4747nS          2.4943V           2.1560V              2.8370V
+7.5758nS          2.4943V           2.1560V              2.8370V
+7.6768nS          2.4943V           2.1560V              2.8370V
+7.7778nS          2.4943V           2.1560V              2.8370V
+7.8788nS          2.4943V           2.1560V              2.8370V
+7.9798nS          2.4943V           2.1560V              2.8370V
+8.0808nS          2.4943V           2.1560V              2.8370V
+8.1818nS          2.4943V           2.1560V              2.8370V
+8.2828nS          2.4943V           2.1560V              2.8370V
+8.3838nS          2.4943V           2.1560V              2.8370V
+8.4848nS          2.4943V           2.1560V              2.8370V
+8.5859nS          2.4943V           2.1560V              2.8370V
+8.6869nS          2.4943V           2.1560V              2.8370V
+8.7879nS          2.4943V           2.1560V              2.8370V
+8.8889nS          2.4943V           2.1560V              2.8370V
+8.9899nS          2.4943V           2.1560V              2.8370V
+9.0909nS          2.4943V           2.1560V              2.8370V
+9.1919nS          2.4943V           2.1560V              2.8370V
+9.2929nS          2.4943V           2.1560V              2.8370V
+9.3939nS          2.4943V           2.1560V              2.8370V
+9.4949nS          2.4943V           2.1560V              2.8370V
+9.5960nS          2.4943V           2.1560V              2.8370V
+9.6970nS          2.4943V           2.1560V              2.8370V
+9.7980nS          2.4943V           2.1560V              2.8370V
+9.8990nS          2.4943V           2.1560V              2.8370V
+10.0000nS         2.4943V           2.1560V              2.8369V
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.4943V           2.1560V              2.8370V
+0.1010nS          2.4943V           2.1560V              2.8370V
+0.2020nS          2.4943V           2.1560V              2.8370V
+0.3030nS          2.4943V           2.1560V              2.8370V
+0.4040nS          2.4943V           2.1560V              2.8378V
+0.5051nS          2.4943V           2.1560V              2.8500V
+0.6061nS          2.4952V           2.1560V              1.9447V
+0.7071nS          2.4905V           2.1560V              0.3637V
+0.8081nS          2.4067V           2.1560V              67.8100mV
+0.9091nS          1.4125V           2.1561V              29.4150mV
+1.0101nS          0.4767V           2.1575V              14.9410mV
+1.1111nS          0.1262V           2.1538V              7.5466mV
+1.2121nS          43.6680mV         2.1382V              3.8422mV
+1.3131nS          26.1960mV         1.7150V              1.8945mV
+1.4141nS          16.2920mV         1.0257V              0.9804mV
+1.5152nS          10.0550mV         0.5310V              0.5148mV
+1.6162nS          6.1813mV          0.2066V              0.2988mV
+1.7172nS          3.9618mV          85.0700mV            0.1781mV
+1.8182nS          2.4789mV          45.0760mV            0.1309mV
+1.9192nS          1.5559mV          28.7760mV            93.0170uV
+2.0202nS          0.9974mV          19.8010mV            83.3720uV
+2.1212nS          0.6445mV          14.0690mV            58.3290uV
+2.2222nS          0.4351mV          10.1110mV            63.2910uV
+2.3232nS          0.2957mV          7.2280mV             53.7290uV
+2.4242nS          0.2210mV          5.1895mV             54.2190uV
+2.5253nS          0.1601mV          3.7800mV             40.3540uV
+2.6263nS          0.1279mV          2.7268mV             47.2160uV
+2.7273nS          0.1002mV          1.9853mV             36.9860uV
+2.8283nS          88.8660uV         1.4440mV             40.0480uV
+2.9293nS          72.7920uV         1.0670mV             26.3870uV
+3.0303nS          69.1040uV         0.7846mV             34.6390uV
+3.1313nS          57.4210uV         0.5846mV             26.3910uV
+3.2323nS          56.9730uV         0.4404mV             29.4630uV
+3.3333nS          47.8400uV         0.3494mV             17.8610uV
+3.4343nS          48.1880uV         0.2584mV             25.6730uV
+3.5354nS          40.2540uV         0.2118mV             18.4590uV
+3.6364nS          41.5730uV         0.1702mV             21.8800uV
+3.7374nS          34.4050uV         0.1443mV             11.4790uV
+3.8384nS          35.9660uV         0.1162mV             17.0260uV
+3.9394nS          29.3730uV         0.1105mV             5.6280uV
+4.0404nS          31.4140uV         89.4040uV            15.1470uV
+4.1414nS          25.3750uV         81.0200uV            11.2580uV
+4.2424nS          27.4070uV         65.5230uV            14.1370uV
+4.3434nS          21.6970uV         73.0300uV            6.2960uV
+4.4444nS          23.9220uV         61.3290uV            11.4660uV
+4.5455nS          18.5100uV         55.7850uV            2.5000uV
+4.6465nS          21.0070uV         43.3670uV            8.5284uV
+4.7475nS          15.9410uV         53.7310uV            -0.8463uV
+4.8485nS          18.4620uV         44.3590uV            8.1933uV
+4.9495nS          13.5820uV         42.1040uV            5.3730uV
+5.0505nS          13.8755uV         37.5100uV            5.0024uV
+5.1515nS          14.2440uV         35.8510uV            6.5401uV
+5.2525nS          9.9306uV          32.2800uV            -0.5688uV
+5.3535nS          12.5350uV         22.2570uV            4.7038uV
+5.4545nS          8.4738uV          33.7280uV            -2.8971uV
+5.5556nS          11.0900uV         26.9540uV            2.5971uV
+5.6566nS          7.1635uV          25.5280uV            -4.8609uV
+5.7576nS          9.8408uV          16.9880uV            3.2391uV
+5.8586nS          6.3372uV          28.3550uV            2.3236uV
+5.9596nS          9.0525uV          22.5320uV            4.3172uV
+6.0606nS          5.7477uV          20.9750uV            0.3230uV
+6.1616nS          8.1503uV          12.8560uV            3.9291uV
+6.2626nS          4.9071uV          23.9660uV            -1.1511uV
+6.3636nS          7.3040uV          18.3760uV            3.1809uV
+6.4646nS          4.1860uV          17.0320uV            -1.7162uV
+6.5657nS          6.6287uV          9.1986uV             2.2452uV
+6.6667nS          3.6832uV          20.0790uV            -2.7234uV
+6.7677nS          12.2830uV         15.0650uV            1.3304uV
+6.8687nS          11.0620uV         13.9980uV            -3.5352uV
+6.9697nS          6.9534uV          6.5462uV             0.3451uV
+7.0707nS          2.2290uV          17.0770uV            -4.3708uV
+7.1717nS          9.7848uV          12.3720uV            -0.5607uV
+7.2727nS          7.5664uV          11.6590uV            -5.1318uV
+7.3737nS          5.3831uV          4.8851uV             -1.5330uV
+7.4747nS          1.7643uV          15.0970uV            -5.9574uV
+7.5758nS          9.2753uV          13.3100uV            -0.1708uV
+7.6768nS          7.7000uV          23.0430uV            3.4595uV
+7.7778nS          4.9844uV          14.4320uV            7.4385uV
+7.8788nS          1.3245uV          8.9262uV             -2.6402uV
+7.9798nS          8.2644uV          4.9790uV             1.1411uV
+8.0808nS          6.6183uV          14.1310uV            1.9398uV
+8.1818nS          4.3304uV          7.8499uV             7.3706uV
+8.2828nS          0.9901uV          15.2460uV            4.3539uV
+8.3838nS          7.4534uV          11.2570uV            -1.5751uV
+8.4848nS          6.0071uV          10.9100uV            -4.0515uV
+8.5859nS          3.9708uV          6.6233uV             6.1371uV
+8.6869nS          0.8938uV          12.1060uV            5.2581uV
+8.7879nS          7.0344uV          11.9130uV            1.0700uV
+8.8889nS          5.6379uV          18.0050uV            -3.9073uV
+8.9899nS          2.9239uV          9.1095uV             0.1500uV
+9.0909nS          2.8023uV          6.8319uV             7.0838uV
+9.1919nS          8.4026uV          3.9617uV             5.4861uV
+9.2929nS          4.3812uV          7.2141uV             -1.7852uV
+9.3939nS          2.8463uV          -53.3950nV           -0.4309uV
+9.4949nS          0.5257uV          12.7920uV            -1.2755uV
+9.5960nS          6.2361uV          11.5200uV            6.5424uV
+9.6970nS          8.1020uV          10.1450uV            2.3600uV
+9.7980nS          11.5310uV         9.4795uV             0.8669uV
+9.8990nS          9.9990uV          13.4000uV            1.3956uV
+10.0000nS         9.1292uV          5.3100uV             7.4741uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
+0.1010nS          3.3000V           3.1400V              3.4700V
+0.2020nS          3.3000V           3.1400V              3.4700V
+0.3030nS          3.3000V           3.1400V              3.4700V
+0.4040nS          3.3000V           3.1400V              3.4709V
+0.5051nS          3.3000V           3.1400V              3.4873V
+0.6061nS          3.3010V           3.1400V              3.3893V
+0.7071nS          3.2951V           3.1400V              2.0959V
+0.8081nS          3.3780V           3.1400V              1.0643V
+0.9091nS          3.2704V           3.1400V              0.7316V
+1.0101nS          2.5838V           3.1420V              0.6666V
+1.1111nS          1.8182V           3.1363V              0.6418V
+1.2121nS          1.2499V           3.1699V              0.6302V
+1.3131nS          0.9556V           3.2348V              0.6244V
+1.4141nS          0.8500V           3.1829V              0.6213V
+1.5152nS          0.8083V           2.8929V              0.6196V
+1.6162nS          0.7853V           2.4877V              0.6188V
+1.7172nS          0.7729V           2.0731V              0.6184V
+1.8182nS          0.7651V           1.7150V              0.6182V
+1.9192nS          0.7601V           1.4389V              0.6181V
+2.0202nS          0.7571V           1.2526V              0.6181V
+2.1212nS          0.7551V           1.1433V              0.6181V
+2.2222nS          0.7539V           1.0821V              0.6180V
+2.3232nS          0.7531V           1.0456V              0.6180V
+2.4242nS          0.7526V           1.0220V              0.6180V
+2.5253nS          0.7523V           1.0060V              0.6180V
+2.6263nS          0.7521V           0.9948V              0.6180V
+2.7273nS          0.7519V           0.9867V              0.6180V
+2.8283nS          0.7518V           0.9812V              0.6180V
+2.9293nS          0.7518V           0.9773V              0.6180V
+3.0303nS          0.7518V           0.9745V              0.6180V
+3.1313nS          0.7517V           0.9724V              0.6180V
+3.2323nS          0.7517V           0.9708V              0.6180V
+3.3333nS          0.7517V           0.9696V              0.6180V
+3.4343nS          0.7517V           0.9687V              0.6180V
+3.5354nS          0.7517V           0.9681V              0.6180V
+3.6364nS          0.7517V           0.9676V              0.6180V
+3.7374nS          0.7517V           0.9673V              0.6180V
+3.8384nS          0.7517V           0.9670V              0.6180V
+3.9394nS          0.7517V           0.9668V              0.6180V
+4.0404nS          0.7517V           0.9666V              0.6180V
+4.1414nS          0.7517V           0.9665V              0.6180V
+4.2424nS          0.7517V           0.9664V              0.6180V
+4.3434nS          0.7517V           0.9664V              0.6180V
+4.4444nS          0.7517V           0.9663V              0.6180V
+4.5455nS          0.7517V           0.9663V              0.6180V
+4.6465nS          0.7517V           0.9662V              0.6180V
+4.7475nS          0.7517V           0.9662V              0.6180V
+4.8485nS          0.7517V           0.9662V              0.6180V
+4.9495nS          0.7516V           0.9662V              0.6180V
+5.0505nS          0.7517V           0.9662V              0.6180V
+5.1515nS          0.7517V           0.9662V              0.6180V
+5.2525nS          0.7516V           0.9661V              0.6180V
+5.3535nS          0.7517V           0.9661V              0.6180V
+5.4545nS          0.7516V           0.9661V              0.6180V
+5.5556nS          0.7517V           0.9661V              0.6180V
+5.6566nS          0.7516V           0.9661V              0.6180V
+5.7576nS          0.7516V           0.9661V              0.6180V
+5.8586nS          0.7516V           0.9661V              0.6180V
+5.9596nS          0.7517V           0.9661V              0.6180V
+6.0606nS          0.7516V           0.9661V              0.6180V
+6.1616nS          0.7517V           0.9661V              0.6180V
+6.2626nS          0.7516V           0.9661V              0.6180V
+6.3636nS          0.7517V           0.9661V              0.6180V
+6.4646nS          0.7517V           0.9661V              0.6180V
+6.5657nS          0.7516V           0.9661V              0.6180V
+6.6667nS          0.7516V           0.9661V              0.6180V
+6.7677nS          0.7516V           0.9661V              0.6180V
+6.8687nS          0.7516V           0.9661V              0.6180V
+6.9697nS          0.7517V           0.9661V              0.6180V
+7.0707nS          0.7516V           0.9661V              0.6180V
+7.1717nS          0.7516V           0.9661V              0.6180V
+7.2727nS          0.7516V           0.9661V              0.6180V
+7.3737nS          0.7516V           0.9661V              0.6180V
+7.4747nS          0.7516V           0.9661V              0.6180V
+7.5758nS          0.7516V           0.9661V              0.6180V
+7.6768nS          0.7516V           0.9661V              0.6180V
+7.7778nS          0.7516V           0.9661V              0.6180V
+7.8788nS          0.7516V           0.9661V              0.6180V
+7.9798nS          0.7516V           0.9661V              0.6180V
+8.0808nS          0.7516V           0.9661V              0.6180V
+8.1818nS          0.7516V           0.9661V              0.6180V
+8.2828nS          0.7516V           0.9661V              0.6180V
+8.3838nS          0.7516V           0.9661V              0.6180V
+8.4848nS          0.7516V           0.9661V              0.6180V
+8.5859nS          0.7516V           0.9661V              0.6180V
+8.6869nS          0.7516V           0.9661V              0.6180V
+8.7879nS          0.7516V           0.9661V              0.6180V
+8.8889nS          0.7516V           0.9661V              0.6180V
+8.9899nS          0.7517V           0.9661V              0.6180V
+9.0909nS          0.7516V           0.9661V              0.6180V
+9.1919nS          0.7517V           0.9661V              0.6180V
+9.2929nS          0.7516V           0.9661V              0.6180V
+9.3939nS          0.7517V           0.9661V              0.6180V
+9.4949nS          0.7516V           0.9661V              0.6180V
+9.5960nS          0.7516V           0.9661V              0.6180V
+9.6970nS          0.7516V           0.9661V              0.6180V
+9.7980nS          0.7516V           0.9661V              0.6180V
+9.8990nS          0.7516V           0.9661V              0.6180V
+10.0000nS         0.7517V           0.9661V              0.6180V
+|  
+| End [Model] lvt330s160aaaaaaaaou
+|************************************************************************
+| End [Component]
+[End]
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
new file mode 100644
index 0000000..46f0e3d
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
@@ -0,0 +1,71 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Tue Aug 17 06:21:09 2021 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RCLK : 63 : in *
+NOTE PINS nFWE : 15 : in *
+NOTE PINS nCRAS : 17 : in *
+NOTE PINS nCCAS : 9 : in *
+NOTE PINS Din[0] : 3 : in *
+NOTE PINS Din[1] : 96 : in *
+NOTE PINS Din[2] : 88 : in *
+NOTE PINS Din[3] : 97 : in *
+NOTE PINS Din[4] : 99 : in *
+NOTE PINS Din[5] : 98 : in *
+NOTE PINS Din[6] : 2 : in *
+NOTE PINS Din[7] : 1 : in *
+NOTE PINS CROW[0] : 10 : in *
+NOTE PINS CROW[1] : 16 : in *
+NOTE PINS MAin[0] : 14 : in *
+NOTE PINS MAin[1] : 12 : in *
+NOTE PINS MAin[2] : 13 : in *
+NOTE PINS MAin[3] : 21 : in *
+NOTE PINS MAin[4] : 20 : in *
+NOTE PINS MAin[5] : 19 : in *
+NOTE PINS MAin[6] : 24 : in *
+NOTE PINS MAin[7] : 18 : in *
+NOTE PINS MAin[8] : 25 : in *
+NOTE PINS MAin[9] : 32 : in *
+NOTE PINS PHI2 : 8 : in *
+NOTE PINS RDQML : 48 : out *
+NOTE PINS RDQMH : 51 : out *
+NOTE PINS nRCAS : 52 : out *
+NOTE PINS nRRAS : 54 : out *
+NOTE PINS nRWE : 49 : out *
+NOTE PINS RCKE : 53 : out *
+NOTE PINS nRCS : 57 : out *
+NOTE PINS RA[0] : 66 : out *
+NOTE PINS RA[1] : 67 : out *
+NOTE PINS RA[2] : 69 : out *
+NOTE PINS RA[3] : 71 : out *
+NOTE PINS RA[4] : 74 : out *
+NOTE PINS RA[5] : 70 : out *
+NOTE PINS RA[6] : 68 : out *
+NOTE PINS RA[7] : 75 : out *
+NOTE PINS RA[8] : 65 : out *
+NOTE PINS RA[9] : 62 : out *
+NOTE PINS RA[10] : 64 : out *
+NOTE PINS RA[11] : 59 : out *
+NOTE PINS RBA[0] : 58 : out *
+NOTE PINS RBA[1] : 60 : out *
+NOTE PINS LED : 34 : out *
+NOTE PINS Dout[0] : 76 : out *
+NOTE PINS Dout[1] : 86 : out *
+NOTE PINS Dout[2] : 87 : out *
+NOTE PINS Dout[3] : 85 : out *
+NOTE PINS Dout[4] : 83 : out *
+NOTE PINS Dout[5] : 84 : out *
+NOTE PINS Dout[6] : 78 : out *
+NOTE PINS Dout[7] : 82 : out *
+NOTE PINS RD[0] : 36 : inout *
+NOTE PINS RD[1] : 37 : inout *
+NOTE PINS RD[2] : 38 : inout *
+NOTE PINS RD[3] : 39 : inout *
+NOTE PINS RD[4] : 40 : inout *
+NOTE PINS RD[5] : 41 : inout *
+NOTE PINS RD[6] : 42 : inout *
+NOTE PINS RD[7] : 43 : inout *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: on *
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
new file mode 100644
index 0000000..e5894f8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
@@ -0,0 +1,22 @@
+----------------------------------------------------------------------
+Report for cell RAM2GS.TECH
+Register bits:  119 of 877 (13.569%)
+I/O cells:      63
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                                 BB         8          100.0
+                              CCU2D        10          100.0
+                                EFB         1          100.0
+                            FD1P3AX        30          100.0
+                            FD1P3AY         4          100.0
+                            FD1P3IX         3          100.0
+                            FD1S3AX        64          100.0
+                            FD1S3IX        14          100.0
+                            FD1S3JX         4          100.0
+                                GSR         1          100.0
+                                 IB        25          100.0
+                                INV         3          100.0
+                               LUT4       236          100.0
+                                 OB        30          100.0
+                              PFUMX        16          100.0
+                              TOTAL       449
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
new file mode 100644
index 0000000..86c3161
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
@@ -0,0 +1,86 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:21:07 2021
+
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit
new file mode 100644
index 0000000..cdb167c
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd
new file mode 100644
index 0000000..352b225
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
new file mode 100644
index 0000000..36624e7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
@@ -0,0 +1,273 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 17 06:20:57 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "63";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:59 2021
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
new file mode 100644
index 0000000..f2f6100
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
@@ -0,0 +1,233 @@
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
new file mode 100644
index 0000000..c0f7313
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
@@ -0,0 +1,41 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 4;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 52;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 13;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
+GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_2_LOADNUM = 7;
+; Global primary clock #3
+GLOBAL_PRIMARY_3_SIGNALNAME = nCCAS_c;
+GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_3_LOADNUM = 4;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 13;
+BANK_0_AVAIL = 19;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 20;
+BANK_1_AVAIL = 20;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 12;
+BANK_2_AVAIL = 20;
+BANK_2_VCCIO = 3.3V;
+BANK_2_VREF1 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 18;
+BANK_3_AVAIL = 20;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
new file mode 100644
index 0000000..edce2f7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:51 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.135        0            0.304        0            10           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
new file mode 100644
index 0000000..3343732
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
@@ -0,0 +1,1431 @@
+*
+NOTE Diamond (64-bit) 3.12.0.240.2 JEDEC Compatible Fuse File.*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
+NOTE All Rights Reserved.*
+NOTE DATE CREATED:	Tue Aug 17 06:21:07 2021*
+NOTE DESIGN NAME:	RAM2GS_LCMXO2_640HC_impl1.ncd*
+NOTE DEVICE NAME:	LCMXO2-640HC-4TQFP100*
+NOTE JEDEC FILE STATUS:	Final   Version 1.95*
+NOTE PIN ASSIGNMENTS*
+NOTE PINS RCLK : 63 : in*
+NOTE PINS nFWE : 15 : in*
+NOTE PINS nCRAS : 17 : in*
+NOTE PINS nCCAS : 9 : in*
+NOTE PINS Din[0] : 3 : in*
+NOTE PINS Din[1] : 96 : in*
+NOTE PINS Din[2] : 88 : in*
+NOTE PINS Din[3] : 97 : in*
+NOTE PINS Din[4] : 99 : in*
+NOTE PINS Din[5] : 98 : in*
+NOTE PINS Din[6] : 2 : in*
+NOTE PINS Din[7] : 1 : in*
+NOTE PINS CROW[0] : 10 : in*
+NOTE PINS CROW[1] : 16 : in*
+NOTE PINS MAin[0] : 14 : in*
+NOTE PINS MAin[1] : 12 : in*
+NOTE PINS MAin[2] : 13 : in*
+NOTE PINS MAin[3] : 21 : in*
+NOTE PINS MAin[4] : 20 : in*
+NOTE PINS MAin[5] : 19 : in*
+NOTE PINS MAin[6] : 24 : in*
+NOTE PINS MAin[7] : 18 : in*
+NOTE PINS MAin[8] : 25 : in*
+NOTE PINS MAin[9] : 32 : in*
+NOTE PINS PHI2 : 8 : in*
+NOTE PINS RDQML : 48 : out*
+NOTE PINS RDQMH : 51 : out*
+NOTE PINS nRCAS : 52 : out*
+NOTE PINS nRRAS : 54 : out*
+NOTE PINS nRWE : 49 : out*
+NOTE PINS RCKE : 53 : out*
+NOTE PINS nRCS : 57 : out*
+NOTE PINS RA[0] : 66 : out*
+NOTE PINS RA[1] : 67 : out*
+NOTE PINS RA[2] : 69 : out*
+NOTE PINS RA[3] : 71 : out*
+NOTE PINS RA[4] : 74 : out*
+NOTE PINS RA[5] : 70 : out*
+NOTE PINS RA[6] : 68 : out*
+NOTE PINS RA[7] : 75 : out*
+NOTE PINS RA[8] : 65 : out*
+NOTE PINS RA[9] : 62 : out*
+NOTE PINS RA[10] : 64 : out*
+NOTE PINS RA[11] : 59 : out*
+NOTE PINS RBA[0] : 58 : out*
+NOTE PINS RBA[1] : 60 : out*
+NOTE PINS LED : 34 : out*
+NOTE PINS Dout[0] : 76 : out*
+NOTE PINS Dout[1] : 86 : out*
+NOTE PINS Dout[2] : 87 : out*
+NOTE PINS Dout[3] : 85 : out*
+NOTE PINS Dout[4] : 83 : out*
+NOTE PINS Dout[5] : 84 : out*
+NOTE PINS Dout[6] : 78 : out*
+NOTE PINS Dout[7] : 82 : out*
+NOTE PINS RD[0] : 36 : inout*
+NOTE PINS RD[1] : 37 : inout*
+NOTE PINS RD[2] : 38 : inout*
+NOTE PINS RD[3] : 39 : inout*
+NOTE PINS RD[4] : 40 : inout*
+NOTE PINS RD[5] : 41 : inout*
+NOTE PINS RD[6] : 42 : inout*
+NOTE PINS RD[7] : 43 : inout*
+QP100*
+QF171904*
+G0*
+F0*
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
new file mode 100644
index 0000000..d0353b8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
new file mode 100644
index 0000000..2743d95
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 200.000000 MHz;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
new file mode 100644
index 0000000..641fd41
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
@@ -0,0 +1,9954 @@
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
new file mode 100644
index 0000000..e49c545
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
@@ -0,0 +1,402 @@
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
+     rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
+     _640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
+     O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/17/21  06:20:50
+
+Design Summary
+--------------
+
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+Design Summary (cont)
+---------------------
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nFWE                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nRWE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RD[2]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_151 was merged into signal PHI2_c
+Signal nRWE_N_209 was merged into signal nRWE_N_210
+Signal RCLK_c_enable_22 was merged into signal InitReady
+Signal n2557 was merged into signal nRowColSel_N_34
+Signal n4935 was merged into signal Ready
+Signal n4933 was merged into signal nRowColSel_N_35
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
+Block i4008 was optimized away.
+Block nRWE_I_53_1_lut was optimized away.
+Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
+Block i1683_1_lut was optimized away.
+Block i1044_1_lut_rep_86 was optimized away.
+Block i1684_1_lut_rep_84 was optimized away.
+Block i1 was optimized away.
+
+     
+
+Embedded Functional Block Connection Summary
+--------------------------------------------
+
+   Desired WISHBONE clock frequency: 50.0 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            NO_WB
+      UFM Connection:                DISABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+
+                                    Page 5
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb
+         Type: EFB
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 6
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
new file mode 100644
index 0000000..2d70ad1
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
@@ -0,0 +1,9 @@
+-v
+1
+
+
+-gt
+
+
+-mapchkpnt 0
+-sethld
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd
new file mode 100644
index 0000000..352b225
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd
new file mode 100644
index 0000000..d58e470
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t
new file mode 100644
index 0000000..16daf53
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t
@@ -0,0 +1,9 @@
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t
new file mode 100644
index 0000000..6ff5632
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "RAM2GS_LCMXO2_640HC_impl1.log"
+-o "RAM2GS_LCMXO2_640HC_impl1.csv"
+-pr "RAM2GS_LCMXO2_640HC_impl1.prf"
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad
new file mode 100644
index 0000000..36624e7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad
@@ -0,0 +1,273 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 17 06:20:57 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "63";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:59 2021
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par
new file mode 100644
index 0000000..2ecfaff
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par
@@ -0,0 +1,261 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:51 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.135        0            0.304        0            10           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
new file mode 100644
index 0000000..dbb9d92
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
@@ -0,0 +1,158 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
new file mode 100644
index 0000000..e5e32de
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 4
+-sphld m
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b
new file mode 100644
index 0000000..2579ff8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b
@@ -0,0 +1,5 @@
+
+
+-g RamCfg:Reset
+
+-path "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"  
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
new file mode 100644
index 0000000..0cce058
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
@@ -0,0 +1,2547 @@
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              13.035ns  (30.0% logic, 70.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     13.035ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_111.CLK to   SLICE_111.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_111.Q1 to   SLICE_158.B0 Bank_5
+CTOF_DEL    ---     0.495   SLICE_158.B0 to   SLICE_158.F0 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F0 to   SLICE_139.B0 n4610
+CTOF_DEL    ---     0.495   SLICE_139.B0 to   SLICE_139.F0 SLICE_139
+ROUTE         2   e 1.234   SLICE_139.F0 to   SLICE_114.B1 n4628
+CTOF_DEL    ---     0.495   SLICE_114.B1 to   SLICE_114.F1 SLICE_114
+ROUTE         4   e 1.234   SLICE_114.F1 to   SLICE_116.B1 n2384
+CTOF_DEL    ---     0.495   SLICE_116.B1 to   SLICE_116.F1 SLICE_116
+ROUTE         2   e 0.480   SLICE_116.F1 to   SLICE_116.D0 n4888
+CTOF_DEL    ---     0.495   SLICE_116.D0 to   SLICE_116.F0 SLICE_116
+ROUTE         1   e 1.234   SLICE_116.F0 to    SLICE_19.B1 n4624
+CTOF_DEL    ---     0.495    SLICE_19.B1 to    SLICE_19.F1 SLICE_19
+ROUTE         4   e 1.234    SLICE_19.F1 to   SLICE_130.C0 C1Submitted_N_232
+CTOF_DEL    ---     0.495   SLICE_130.C0 to   SLICE_130.F0 SLICE_130
+ROUTE         1   e 1.234   SLICE_130.F0 to    SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   13.035   (30.0% logic, 70.0% route), 8 logic levels.
+
+Report:   26.684ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 2.077ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              13.757ns  (33.7% logic, 66.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     13.757ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_5.CLK to     SLICE_5.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23   e 1.234     SLICE_5.Q1 to    SLICE_98.B1 FS_8
+CTOF_DEL    ---     0.495    SLICE_98.B1 to    SLICE_98.F1 SLICE_98
+ROUTE         4   e 1.234    SLICE_98.F1 to    SLICE_93.B1 n4924
+CTOF_DEL    ---     0.495    SLICE_93.B1 to    SLICE_93.F1 SLICE_93
+ROUTE         1   e 1.234    SLICE_93.F1 to   SLICE_133.D0 n98
+CTOF_DEL    ---     0.495   SLICE_133.D0 to   SLICE_133.F0 SLICE_133
+ROUTE         2   e 0.480   SLICE_133.F0 to   SLICE_133.B1 n2199
+CTOF_DEL    ---     0.495   SLICE_133.B1 to   SLICE_133.F1 SLICE_133
+ROUTE         1   e 1.234   SLICE_133.F1 to *9/SLICE_84.C1 n53
+CTOOFX_DEL  ---     0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84
+ROUTE         1   e 1.234 *SLICE_84.OFX0 to   SLICE_148.C1 n14_adj_3
+CTOF_DEL    ---     0.495   SLICE_148.C1 to   SLICE_148.F1 SLICE_148
+ROUTE         2   e 1.234   SLICE_148.F1 to   SLICE_135.C0 n12_adj_8
+CTOF_DEL    ---     0.495   SLICE_135.C0 to   SLICE_135.F0 SLICE_135
+ROUTE         2   e 1.234   SLICE_135.F0 to    SLICE_70.A1 n14_adj_7
+CTOF_DEL    ---     0.495    SLICE_70.A1 to    SLICE_70.F1 SLICE_70
+ROUTE         1   e 0.001    SLICE_70.F1 to   SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   13.757   (33.7% logic, 66.3% route), 9 logic levels.
+
+Report:   13.923ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_54 and
+      5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets
+     12.500ns offset RCLK to RA[10] by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[9] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[8] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[7] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 1.234   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[6] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[5] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 1.234   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[4] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[3] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[2] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[1] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[0] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 1.234   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_59 and
+      5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_35 and
+      5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets
+     12.500ns offset RCLK to RCKE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 1.234    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_62 and
+      5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRWE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_60 and
+      5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRRAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_57 and
+      5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQMH by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQML by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.684 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    13.923 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.D0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.D0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_118.CLK to   SLICE_118.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_118.Q0 to   SLICE_118.M1 n1197 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_54 and
+      2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 0.515   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 0.515   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 0.515   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 0.515   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_59 and
+      2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_35 and
+      2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_62 and
+      2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_60 and
+      2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_57 and
+      2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
new file mode 100644
index 0000000..56e0a5c
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
@@ -0,0 +1,4466 @@
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.357ns  (34.5% logic, 65.5% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.357ns physical path delay SLICE_151 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.357   (34.5% logic, 65.5% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.083ns  (35.3% logic, 64.7% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.083ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.083   (35.3% logic, 64.7% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   25.800ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   12.427ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.334ns  (71.9% logic, 28.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_54 and
+      6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
+     12.500ns offset RCLK to RA[10] by 3.015ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     1.777      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    6.334   (71.9% logic, 28.1% route), 2 logic levels.
+
+Report:    9.485ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.495ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.854ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
+     12.500ns offset RCLK to RA[9] by 1.495ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.016      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     1.786       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.854   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:   11.005ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.386ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.963ns  (63.4% logic, 36.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
+     12.500ns offset RCLK to RA[8] by 1.386ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     1.858      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.963   (63.4% logic, 36.6% route), 3 logic levels.
+
+Report:   11.114ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.797ns  (64.8% logic, 35.2% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
+     12.500ns offset RCLK to RA[7] by 1.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     1.728      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.797   (64.8% logic, 35.2% route), 3 logic levels.
+
+Report:   10.948ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.401ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.948ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
+     12.500ns offset RCLK to RA[6] by 1.401ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     1.843      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.948   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:   11.099ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[5] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     1.852       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[4] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     1.852       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.027ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
+     12.500ns offset RCLK to RA[3] by 1.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     1.985      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    8.027   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:   11.178ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.577ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.772ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
+     12.500ns offset RCLK to RA[2] by 1.577ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     1.924       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.772   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.923ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.770ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
+     12.500ns offset RCLK to RA[1] by 1.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     1.728      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.770   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.921ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.494ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
+     12.500ns offset RCLK to RA[0] by 1.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     1.425      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.494   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.645ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_59 and
+      6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     1.966      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.616ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.733ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_35 and
+      6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
+     12.500ns offset RCLK to RCKE by 2.616ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     2.176       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    6.733   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    9.884ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.225ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.124ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_62 and
+      6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
+     12.500ns offset RCLK to nRWE by 3.225ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     1.567      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    6.124   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    9.275ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.703ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.646ns  (68.6% logic, 31.4% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_60 and
+      6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
+     12.500ns offset RCLK to nRRAS by 2.703ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     2.089      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    6.646   (68.6% logic, 31.4% route), 2 logic levels.
+
+Report:    9.797ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_57 and
+      6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCAS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     1.966      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.790ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
+     12.500ns offset RCLK to RDQMH by 1.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.648      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     2.090       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.790   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:   10.941ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.859ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.490ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
+     12.500ns offset RCLK to RDQML by 1.859ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     1.642       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.490   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.641ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    25.800 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    12.427 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.485 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.005 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.114 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.948 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.099 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.178 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.923 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.921 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.645 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.884 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.275 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.797 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.941 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.641 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C9C.Q0 to       R3C9C.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.A0 to       R3C9C.F0 SLICE_15
+ROUTE         1     0.000       R3C9C.F0 to      R3C9C.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.474ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_549  (to PHI2_c -)
+
+   Delay:               0.461ns  (50.8% logic, 49.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.461ns physical path delay SLICE_19 to SLICE_21 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.003       R4C9B.F0 to      R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
+                  --------
+                    0.461   (50.8% logic, 49.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.538ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_543  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.510ns  (45.9% logic, 54.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.510ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.538ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9B.CLK to       R3C9B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.133       R3C9B.Q0 to       R3C9D.D0 ADSubmitted
+CTOF_DEL    ---     0.101       R3C9D.D0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.510   (45.9% logic, 54.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.860ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.832ns  (40.3% logic, 59.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.832ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.860ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.224       R3C9C.Q0 to       R3C9C.B1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.B1 to       R3C9C.F1 SLICE_15
+ROUTE         1     0.130       R3C9C.F1 to       R3C9D.A0 n7
+CTOF_DEL    ---     0.101       R3C9D.A0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.832   (40.3% logic, 59.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_544  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_145 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.141       R4C9B.F0 to       R5C9A.D1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C9A.D1 to       R5C9A.F1 SLICE_110
+ROUTE         1     0.145       R5C9A.F1 to       R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.009ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift_547  (to PHI2_c -)
+                   FF                        CmdUFMData_548
+
+   Delay:               0.981ns  (34.1% logic, 65.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.981ns physical path delay SLICE_19 to SLICE_161 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.009ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.059       R4C9B.F0 to       R4C9B.C1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R4C9B.C1 to       R4C9B.F1 SLICE_21
+ROUTE         1     0.363       R4C9B.F1 to       R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
+                  --------
+                    0.981   (34.1% logic, 65.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_544  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_521  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_145 to SLICE_32 meets
+     -0.013ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.013ns) by 175.457ns
+
+ Physical Path Details:
+
+      Data path SLICE_145 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_145 (from PHI2_c)
+ROUTE         1     0.210       R5C8A.Q0 to       R5C8C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R5C8C.A0 to       R5C8C.F0 SLICE_32
+ROUTE         1     0.000       R5C8C.F0 to      R5C8C.DI0 RA11_N_217 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i2  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_543  (to PHI2_c -)
+
+   Delay:               0.787ns  (42.6% logic, 57.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.787ns physical path delay SLICE_143 to SLICE_10 meets
+     -0.028ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.028ns) by 175.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_143 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C8D.CLK to       R2C8D.Q0 SLICE_143 (from PHI2_c)
+ROUTE         2     0.139       R2C8D.Q0 to       R2C9C.C1 Bank_2
+CTOF_DEL    ---     0.101       R2C9C.C1 to       R2C9C.F1 SLICE_132
+ROUTE         1     0.056       R2C9C.F1 to       R2C9C.C0 n4782
+CTOF_DEL    ---     0.101       R2C9C.C0 to       R2C9C.F0 SLICE_132
+ROUTE         1     0.257       R2C9C.F0 to       R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
+                  --------
+                    0.787   (42.6% logic, 57.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_143:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R2C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9C.CLK to       R4C9C.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1     0.152       R4C9C.Q0 to       R4C9C.M1 n1197 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_127 to SLICE_127 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_127 to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_127 (from RCLK_c)
+ROUTE         1     0.152      R4C10B.Q0 to      R4C10B.M1 n1195 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_518  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_519  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C10C.CLK to      R6C10C.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R6C10C.Q0 to      R6C10C.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_163 to SLICE_163 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_163 to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_163 (from RCLK_c)
+ROUTE         1     0.152      R4C10D.Q0 to      R4C10D.M1 n1189 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_91 to SLICE_91 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_91 to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_91 (from RCLK_c)
+ROUTE         1     0.152       R4C8D.Q0 to       R4C8D.M1 n1185 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_94 to SLICE_94 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_94 (from RCLK_c)
+ROUTE         1     0.152       R4C7D.Q0 to       R4C7D.M1 n1187 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_512  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_513  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_95 to SLICE_35 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.152       R4C7A.Q0 to       R4C7B.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_515  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_516  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154       R5C7A.Q0 to       R5C7A.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_162 to SLICE_162 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_162 to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_162 (from RCLK_c)
+ROUTE         4     0.155      R3C10C.Q0 to      R3C10C.M1 nRCS_N_172 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i2  (from RCLK_c +)
+   Destination:    FF         Data in        FS_972__i2  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C6B.CLK to       R6C6B.Q1 SLICE_0 (from RCLK_c)
+ROUTE         3     0.132       R6C6B.Q1 to       R6C6B.A1 FS_2
+CTOF_DEL    ---     0.101       R6C6B.A1 to       R6C6B.F1 SLICE_0
+ROUTE         1     0.000       R6C6B.F1 to      R6C6B.DI1 n93 (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.217ns  (81.5% logic, 18.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_54 and
+      2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     0.411      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.217   (81.5% logic, 18.5% route), 2 logic levels.
+
+Report:    3.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.561ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.542ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.561ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.219      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     0.416       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.542   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    3.561ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.608ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.589ns  (73.7% logic, 26.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.608ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     0.451      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.589   (73.7% logic, 26.3% route), 3 logic levels.
+
+Report:    3.608ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.533ns  (75.3% logic, 24.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     0.397      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.533   (75.3% logic, 24.7% route), 3 logic levels.
+
+Report:    3.552ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.554ns  (74.7% logic, 25.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     0.416      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.554   (74.7% logic, 25.3% route), 3 logic levels.
+
+Report:    3.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     0.421       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     0.421       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.615ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.596ns  (73.5% logic, 26.5% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.615ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     0.463      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.596   (73.5% logic, 26.5% route), 3 logic levels.
+
+Report:    3.615ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.527ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.508ns  (76.0% logic, 24.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.527ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     0.456       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.508   (76.0% logic, 24.0% route), 3 logic levels.
+
+Report:    3.527ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.549ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.530ns  (75.4% logic, 24.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.549ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     0.397      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.530   (75.4% logic, 24.6% route), 3 logic levels.
+
+Report:    3.549ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.452ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.471ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     0.316      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.452   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.471ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_59 and
+      2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     0.475      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.362ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.343ns  (77.1% logic, 22.9% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_35 and
+      2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.362ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     0.537       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.343   (77.1% logic, 22.9% route), 2 logic levels.
+
+Report:    3.362ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.194ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.175ns  (83.0% logic, 17.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_62 and
+      2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.194ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     0.369      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.175   (83.0% logic, 17.0% route), 2 logic levels.
+
+Report:    3.194ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.303ns  (78.4% logic, 21.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_60 and
+      2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.497      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.303   (78.4% logic, 21.6% route), 2 logic levels.
+
+Report:    3.322ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_57 and
+      2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     0.475      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.540ns  (75.1% logic, 24.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.139      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     0.494       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.540   (75.1% logic, 24.9% route), 3 logic levels.
+
+Report:    3.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.470ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.451ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.470ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     0.399       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.451   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.470ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.561 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.552 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.615 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.527 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.549 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.471 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.362 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.194 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.322 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.470 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
new file mode 100644
index 0000000..7a7fffc
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
@@ -0,0 +1,152 @@
+
+Bitgen Report
+
+
+
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:21:07 2021
+
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
new file mode 100644
index 0000000..eeaaea8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
@@ -0,0 +1,198 @@
+
+I/O Timing Report
+
+
+
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Tue Aug 17 06:21:03 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.195      M       1.729     4
+CROW[1] nCRAS F    -0.218      M       1.801     4
+Din[0]  PHI2  F     6.339      4       1.186     4
+Din[0]  nCCAS F     1.641      4       0.107     M
+Din[1]  PHI2  F     6.084      4       1.570     4
+Din[1]  nCCAS F     0.198      4       1.314     4
+Din[2]  PHI2  F     3.778      4       1.771     4
+Din[2]  nCCAS F     0.075      4       1.431     4
+Din[3]  PHI2  F     4.331      4       1.705     4
+Din[3]  nCCAS F    -0.116      M       1.722     4
+Din[4]  PHI2  F     6.176      4       1.711     4
+Din[4]  nCCAS F     1.065      4       0.575     4
+Din[5]  PHI2  F     4.684      4       1.261     4
+Din[5]  nCCAS F    -0.081      M       1.625     4
+Din[6]  PHI2  F     5.243      4       0.356     4
+Din[6]  nCCAS F     1.414      4       0.309     4
+Din[7]  PHI2  F     6.602      4       1.175     4
+Din[7]  nCCAS F    -0.286      M       2.137     4
+MAin[0] PHI2  F     5.034      4       0.629     4
+MAin[0] nCRAS F     1.094      4       0.380     4
+MAin[1] PHI2  F     6.081      4       1.157     4
+MAin[1] nCRAS F     0.544      4       0.877     4
+MAin[2] PHI2  F     9.979      4      -0.319     M
+MAin[2] nCRAS F    -0.050      M       1.401     4
+MAin[3] PHI2  F     9.162      4      -0.219     M
+MAin[3] nCRAS F     1.032      4       0.440     4
+MAin[4] PHI2  F    11.678      4      -0.770     M
+MAin[4] nCRAS F    -0.150      M       1.620     4
+MAin[5] PHI2  F     8.668      4      -0.081     M
+MAin[5] nCRAS F    -0.050      M       1.401     4
+MAin[6] PHI2  F     8.516      4      -0.025     M
+MAin[6] nCRAS F     1.003      4       0.478     4
+MAin[7] PHI2  F     9.320      4      -0.061     M
+MAin[7] nCRAS F     1.001      4       0.478     4
+MAin[8] nCRAS F    -0.146      M       1.657     4
+MAin[9] nCRAS F    -0.360      M       2.140     4
+PHI2    RCLK  R     3.079      4      -0.602     M
+nCCAS   RCLK  R     3.574      4      -0.705     M
+nCCAS   nCRAS F     3.232      4      -0.351     M
+nCRAS   RCLK  R     2.757      4      -0.470     M
+nFWE    PHI2  F     5.913      4       0.723     4
+nFWE    nCRAS F     0.547      4       0.890     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    10.062         4        3.164          M
+RA[0]  RCLK  R    10.645         4        3.471          M
+RA[0]  nCRAS F    11.744         4        3.770          M
+RA[10] RCLK  R     9.485         4        3.236          M
+RA[11] PHI2  R    11.513         4        3.824          M
+RA[1]  RCLK  R    10.921         4        3.549          M
+RA[1]  nCRAS F    12.664         4        4.036          M
+RA[2]  RCLK  R    10.923         4        3.527          M
+RA[2]  nCRAS F    12.463         4        3.984          M
+RA[3]  RCLK  R    11.178         4        3.615          M
+RA[3]  nCRAS F    12.304         4        3.917          M
+RA[4]  RCLK  R    11.365         4        3.630          M
+RA[4]  nCRAS F    13.243         4        4.179          M
+RA[5]  RCLK  R    11.365         4        3.630          M
+RA[5]  nCRAS F    12.940         4        4.098          M
+RA[6]  RCLK  R    11.099         4        3.573          M
+RA[6]  nCRAS F    12.162         4        3.870          M
+RA[7]  RCLK  R    10.948         4        3.552          M
+RA[7]  nCRAS F    12.282         4        3.936          M
+RA[8]  RCLK  R    11.114         4        3.608          M
+RA[8]  nCRAS F    12.909         4        4.116          M
+RA[9]  RCLK  R    11.005         4        3.561          M
+RA[9]  nCRAS F    12.959         4        4.081          M
+RBA[0] nCRAS F    11.842         4        3.911          M
+RBA[1] nCRAS F    11.343         4        3.771          M
+RCKE   RCLK  R     9.884         4        3.362          M
+RDQMH  RCLK  R    10.941         4        3.559          M
+RDQML  RCLK  R    10.641         4        3.470          M
+RD[0]  nCCAS F    12.628         4        4.413          M
+RD[1]  nCCAS F    12.231         4        4.302          M
+RD[2]  nCCAS F    12.231         4        4.302          M
+RD[3]  nCCAS F    11.928         4        4.221          M
+RD[4]  nCCAS F    12.427         4        4.361          M
+RD[5]  nCCAS F    12.697         4        4.400          M
+RD[6]  nCCAS F    12.427         4        4.361          M
+RD[7]  nCCAS F    12.427         4        4.361          M
+nRCAS  RCLK  R     9.674         4        3.300          M
+nRCS   RCLK  R     9.674         4        3.300          M
+nRRAS  RCLK  R     9.797         4        3.322          M
+nRWE   RCLK  R     9.275         4        3.194          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: M
+
+
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
new file mode 100644
index 0000000..547499e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
@@ -0,0 +1,41 @@
+-a "MachXO2"
+-d LCMXO2-640HC
+-t TQFP100
+-s 4
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
+-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+-top RAM2GS
+
+
+-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
+
+-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
new file mode 100644
index 0000000..a89e71e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
@@ -0,0 +1,24 @@
+[ActiveSupport MAP]
+Device = LCMXO2-640HC;
+Package = TQFP100;
+Performance = 4;
+LUTS_avail = 640;
+LUTS_used = 255;
+FF_avail = 719;
+FF_used = 119;
+INPUT_LVTTL33 = 25;
+OUTPUT_LVTTL33 = 30;
+BIDI_LVTTL33 = 8;
+IO_avail = 79;
+IO_used = 63;
+EBR_avail = 2;
+EBR_used = 0;
+;
+; start of EFB statistics
+I2C = 0;
+SPI = 0;
+TimerCounter = 0;
+UFM = 0;
+PLL = 0;
+; end of EFB statistics
+;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
new file mode 100644
index 0000000..7137797
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
@@ -0,0 +1,94 @@
+[ START MERGED ]
+n4935 Ready
+n4933 nRowColSel_N_35
+n2557 nRowColSel_N_34
+nRWE_N_209 nRWE_N_210
+PHI2_N_151 PHI2_c
+RCLK_c_enable_22 InitReady
+[ END MERGED ]
+[ START CLIPPED ]
+GND_net
+VCC_net
+FS_972_add_4_1/S0
+FS_972_add_4_1/CI
+FS_972_add_4_19/S1
+FS_972_add_4_19/CO
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
new file mode 100644
index 0000000..1264102
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
@@ -0,0 +1,10 @@
+---------------------------------------------------
+Report for cell RAM2GS
+   Instance path: RAM2GS
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     131.00        100.0
+                                  LUT4	     235.00        100.0
+                                 IOBUF	         63        100.0
+                                PFUREG	        119        100.0
+                                RIPPLE	         10        100.0
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
new file mode 100644
index 0000000..953ea66
Binary files /dev/null and b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd differ
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
new file mode 100644
index 0000000..f2e71ae
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
@@ -0,0 +1,428 @@
+
+Project Summary
+
+
+
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
+     rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
+     _640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
+     O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/17/21  06:20:50
+
+
+Design Summary
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| nFWE                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| nRWE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| RD[2]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_151 was merged into signal PHI2_c
+Signal nRWE_N_209 was merged into signal nRWE_N_210
+Signal RCLK_c_enable_22 was merged into signal InitReady
+Signal n2557 was merged into signal nRowColSel_N_34
+Signal n4935 was merged into signal Ready
+Signal n4933 was merged into signal nRowColSel_N_35
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
+Block i4008 was optimized away.
+Block nRWE_I_53_1_lut was optimized away.
+Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
+Block i1683_1_lut was optimized away.
+Block i1044_1_lut_rep_86 was optimized away.
+Block i1684_1_lut_rep_84 was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 50.0 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            NO_WB
+      UFM Connection:                DISABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb
+         Type: EFB
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
new file mode 100644
index 0000000..23f37c5
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
@@ -0,0 +1,338 @@
+
+PAD Specification File
+
+
+
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 17 06:20:57 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "63";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:59 2021
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
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+
    
+
    
+
    
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+
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
new file mode 100644
index 0000000..65dfab2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
@@ -0,0 +1,329 @@
+
+Place & Route Report
+
+
+
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:51 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.135        0            0.304        0            10           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 1.135ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.135
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
new file mode 100644
index 0000000..e426f18
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
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    RAM2GS_LCMXO2_640HC project summary
    Module Name:RAM2GS_LCMXO2_640HCSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO2_640HC.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prf
    Product Version:3.12.0.240.2Patch Version:
    Updated:2021/08/17 06:21:51
    Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1
    Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
new file mode 100644
index 0000000..8f5276d
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
@@ -0,0 +1,2780 @@
+
+Lattice Map TRACE Report
+
+
+
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              13.035ns  (30.0% logic, 70.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     13.035ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_111.CLK to   SLICE_111.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_111.Q1 to   SLICE_158.B0 Bank_5
+CTOF_DEL    ---     0.495   SLICE_158.B0 to   SLICE_158.F0 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F0 to   SLICE_139.B0 n4610
+CTOF_DEL    ---     0.495   SLICE_139.B0 to   SLICE_139.F0 SLICE_139
+ROUTE         2   e 1.234   SLICE_139.F0 to   SLICE_114.B1 n4628
+CTOF_DEL    ---     0.495   SLICE_114.B1 to   SLICE_114.F1 SLICE_114
+ROUTE         4   e 1.234   SLICE_114.F1 to   SLICE_116.B1 n2384
+CTOF_DEL    ---     0.495   SLICE_116.B1 to   SLICE_116.F1 SLICE_116
+ROUTE         2   e 0.480   SLICE_116.F1 to   SLICE_116.D0 n4888
+CTOF_DEL    ---     0.495   SLICE_116.D0 to   SLICE_116.F0 SLICE_116
+ROUTE         1   e 1.234   SLICE_116.F0 to    SLICE_19.B1 n4624
+CTOF_DEL    ---     0.495    SLICE_19.B1 to    SLICE_19.F1 SLICE_19
+ROUTE         4   e 1.234    SLICE_19.F1 to   SLICE_130.C0 C1Submitted_N_232
+CTOF_DEL    ---     0.495   SLICE_130.C0 to   SLICE_130.F0 SLICE_130
+ROUTE         1   e 1.234   SLICE_130.F0 to    SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   13.035   (30.0% logic, 70.0% route), 8 logic levels.
+
+Report:   26.684ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 2.077ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              13.757ns  (33.7% logic, 66.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     13.757ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_5.CLK to     SLICE_5.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23   e 1.234     SLICE_5.Q1 to    SLICE_98.B1 FS_8
+CTOF_DEL    ---     0.495    SLICE_98.B1 to    SLICE_98.F1 SLICE_98
+ROUTE         4   e 1.234    SLICE_98.F1 to    SLICE_93.B1 n4924
+CTOF_DEL    ---     0.495    SLICE_93.B1 to    SLICE_93.F1 SLICE_93
+ROUTE         1   e 1.234    SLICE_93.F1 to   SLICE_133.D0 n98
+CTOF_DEL    ---     0.495   SLICE_133.D0 to   SLICE_133.F0 SLICE_133
+ROUTE         2   e 0.480   SLICE_133.F0 to   SLICE_133.B1 n2199
+CTOF_DEL    ---     0.495   SLICE_133.B1 to   SLICE_133.F1 SLICE_133
+ROUTE         1   e 1.234   SLICE_133.F1 to *9/SLICE_84.C1 n53
+CTOOFX_DEL  ---     0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84
+ROUTE         1   e 1.234 *SLICE_84.OFX0 to   SLICE_148.C1 n14_adj_3
+CTOF_DEL    ---     0.495   SLICE_148.C1 to   SLICE_148.F1 SLICE_148
+ROUTE         2   e 1.234   SLICE_148.F1 to   SLICE_135.C0 n12_adj_8
+CTOF_DEL    ---     0.495   SLICE_135.C0 to   SLICE_135.F0 SLICE_135
+ROUTE         2   e 1.234   SLICE_135.F0 to    SLICE_70.A1 n14_adj_7
+CTOF_DEL    ---     0.495    SLICE_70.A1 to    SLICE_70.F1 SLICE_70
+ROUTE         1   e 0.001    SLICE_70.F1 to   SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   13.757   (33.7% logic, 66.3% route), 9 logic levels.
+
+Report:   13.923ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_54 and
+      5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets
+     12.500ns offset RCLK to RA[10] by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[9] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[8] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[7] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 1.234   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[6] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[5] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 1.234   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[4] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[3] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[2] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[1] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[0] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 1.234   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_59 and
+      5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_35 and
+      5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets
+     12.500ns offset RCLK to RCKE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 1.234    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_62 and
+      5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRWE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_60 and
+      5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRRAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_57 and
+      5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQMH by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQML by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.684 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    13.923 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.D0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.D0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_118.CLK to   SLICE_118.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_118.Q0 to   SLICE_118.M1 n1197 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_54 and
+      2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 0.515   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 0.515   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 0.515   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 0.515   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_59 and
+      2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_35 and
+      2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_62 and
+      2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_60 and
+      2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_57 and
+      2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
new file mode 100644
index 0000000..774a443
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
@@ -0,0 +1,4699 @@
+
+Lattice TRACE Report
+
+
+
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.357ns  (34.5% logic, 65.5% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.357ns physical path delay SLICE_151 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.357   (34.5% logic, 65.5% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.083ns  (35.3% logic, 64.7% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.083ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.083   (35.3% logic, 64.7% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   25.800ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   12.427ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.334ns  (71.9% logic, 28.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_54 and
+      6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
+     12.500ns offset RCLK to RA[10] by 3.015ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     1.777      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    6.334   (71.9% logic, 28.1% route), 2 logic levels.
+
+Report:    9.485ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.495ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.854ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
+     12.500ns offset RCLK to RA[9] by 1.495ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.016      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     1.786       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.854   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:   11.005ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.386ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.963ns  (63.4% logic, 36.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
+     12.500ns offset RCLK to RA[8] by 1.386ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     1.858      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.963   (63.4% logic, 36.6% route), 3 logic levels.
+
+Report:   11.114ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.797ns  (64.8% logic, 35.2% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
+     12.500ns offset RCLK to RA[7] by 1.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     1.728      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.797   (64.8% logic, 35.2% route), 3 logic levels.
+
+Report:   10.948ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.401ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.948ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
+     12.500ns offset RCLK to RA[6] by 1.401ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     1.843      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.948   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:   11.099ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[5] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     1.852       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[4] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     1.852       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.027ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
+     12.500ns offset RCLK to RA[3] by 1.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     1.985      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    8.027   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:   11.178ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.577ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.772ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
+     12.500ns offset RCLK to RA[2] by 1.577ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     1.924       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.772   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.923ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.770ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
+     12.500ns offset RCLK to RA[1] by 1.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     1.728      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.770   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.921ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.494ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
+     12.500ns offset RCLK to RA[0] by 1.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     1.425      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.494   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.645ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_59 and
+      6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     1.966      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.616ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.733ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_35 and
+      6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
+     12.500ns offset RCLK to RCKE by 2.616ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     2.176       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    6.733   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    9.884ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.225ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.124ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_62 and
+      6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
+     12.500ns offset RCLK to nRWE by 3.225ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     1.567      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    6.124   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    9.275ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.703ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.646ns  (68.6% logic, 31.4% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_60 and
+      6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
+     12.500ns offset RCLK to nRRAS by 2.703ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     2.089      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    6.646   (68.6% logic, 31.4% route), 2 logic levels.
+
+Report:    9.797ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_57 and
+      6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCAS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     1.966      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.790ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
+     12.500ns offset RCLK to RDQMH by 1.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.648      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     2.090       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.790   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:   10.941ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.859ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.490ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
+     12.500ns offset RCLK to RDQML by 1.859ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     1.642       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.490   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.641ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    25.800 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    12.427 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.485 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.005 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.114 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.948 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.099 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.178 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.923 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.921 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.645 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.884 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.275 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.797 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.941 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.641 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C9C.Q0 to       R3C9C.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.A0 to       R3C9C.F0 SLICE_15
+ROUTE         1     0.000       R3C9C.F0 to      R3C9C.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.474ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_549  (to PHI2_c -)
+
+   Delay:               0.461ns  (50.8% logic, 49.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.461ns physical path delay SLICE_19 to SLICE_21 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.003       R4C9B.F0 to      R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
+                  --------
+                    0.461   (50.8% logic, 49.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.538ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_543  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.510ns  (45.9% logic, 54.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.510ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.538ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9B.CLK to       R3C9B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.133       R3C9B.Q0 to       R3C9D.D0 ADSubmitted
+CTOF_DEL    ---     0.101       R3C9D.D0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.510   (45.9% logic, 54.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.860ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.832ns  (40.3% logic, 59.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.832ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.860ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.224       R3C9C.Q0 to       R3C9C.B1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.B1 to       R3C9C.F1 SLICE_15
+ROUTE         1     0.130       R3C9C.F1 to       R3C9D.A0 n7
+CTOF_DEL    ---     0.101       R3C9D.A0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.832   (40.3% logic, 59.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_544  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_145 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.141       R4C9B.F0 to       R5C9A.D1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C9A.D1 to       R5C9A.F1 SLICE_110
+ROUTE         1     0.145       R5C9A.F1 to       R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.009ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift_547  (to PHI2_c -)
+                   FF                        CmdUFMData_548
+
+   Delay:               0.981ns  (34.1% logic, 65.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.981ns physical path delay SLICE_19 to SLICE_161 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.009ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.059       R4C9B.F0 to       R4C9B.C1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R4C9B.C1 to       R4C9B.F1 SLICE_21
+ROUTE         1     0.363       R4C9B.F1 to       R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
+                  --------
+                    0.981   (34.1% logic, 65.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_544  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_521  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_145 to SLICE_32 meets
+     -0.013ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.013ns) by 175.457ns
+
+ Physical Path Details:
+
+      Data path SLICE_145 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_145 (from PHI2_c)
+ROUTE         1     0.210       R5C8A.Q0 to       R5C8C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R5C8C.A0 to       R5C8C.F0 SLICE_32
+ROUTE         1     0.000       R5C8C.F0 to      R5C8C.DI0 RA11_N_217 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i2  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_543  (to PHI2_c -)
+
+   Delay:               0.787ns  (42.6% logic, 57.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.787ns physical path delay SLICE_143 to SLICE_10 meets
+     -0.028ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.028ns) by 175.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_143 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C8D.CLK to       R2C8D.Q0 SLICE_143 (from PHI2_c)
+ROUTE         2     0.139       R2C8D.Q0 to       R2C9C.C1 Bank_2
+CTOF_DEL    ---     0.101       R2C9C.C1 to       R2C9C.F1 SLICE_132
+ROUTE         1     0.056       R2C9C.F1 to       R2C9C.C0 n4782
+CTOF_DEL    ---     0.101       R2C9C.C0 to       R2C9C.F0 SLICE_132
+ROUTE         1     0.257       R2C9C.F0 to       R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
+                  --------
+                    0.787   (42.6% logic, 57.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_143:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R2C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9C.CLK to       R4C9C.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1     0.152       R4C9C.Q0 to       R4C9C.M1 n1197 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_127 to SLICE_127 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_127 to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_127 (from RCLK_c)
+ROUTE         1     0.152      R4C10B.Q0 to      R4C10B.M1 n1195 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_518  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_519  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C10C.CLK to      R6C10C.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R6C10C.Q0 to      R6C10C.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_163 to SLICE_163 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_163 to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_163 (from RCLK_c)
+ROUTE         1     0.152      R4C10D.Q0 to      R4C10D.M1 n1189 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_91 to SLICE_91 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_91 to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_91 (from RCLK_c)
+ROUTE         1     0.152       R4C8D.Q0 to       R4C8D.M1 n1185 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_94 to SLICE_94 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_94 (from RCLK_c)
+ROUTE         1     0.152       R4C7D.Q0 to       R4C7D.M1 n1187 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_512  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_513  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_95 to SLICE_35 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.152       R4C7A.Q0 to       R4C7B.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_515  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_516  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154       R5C7A.Q0 to       R5C7A.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_162 to SLICE_162 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_162 to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_162 (from RCLK_c)
+ROUTE         4     0.155      R3C10C.Q0 to      R3C10C.M1 nRCS_N_172 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i2  (from RCLK_c +)
+   Destination:    FF         Data in        FS_972__i2  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C6B.CLK to       R6C6B.Q1 SLICE_0 (from RCLK_c)
+ROUTE         3     0.132       R6C6B.Q1 to       R6C6B.A1 FS_2
+CTOF_DEL    ---     0.101       R6C6B.A1 to       R6C6B.F1 SLICE_0
+ROUTE         1     0.000       R6C6B.F1 to      R6C6B.DI1 n93 (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.217ns  (81.5% logic, 18.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_54 and
+      2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     0.411      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.217   (81.5% logic, 18.5% route), 2 logic levels.
+
+Report:    3.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.561ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.542ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.561ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.219      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     0.416       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.542   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    3.561ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.608ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.589ns  (73.7% logic, 26.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.608ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     0.451      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.589   (73.7% logic, 26.3% route), 3 logic levels.
+
+Report:    3.608ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.533ns  (75.3% logic, 24.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     0.397      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.533   (75.3% logic, 24.7% route), 3 logic levels.
+
+Report:    3.552ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.554ns  (74.7% logic, 25.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     0.416      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.554   (74.7% logic, 25.3% route), 3 logic levels.
+
+Report:    3.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     0.421       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     0.421       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.615ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.596ns  (73.5% logic, 26.5% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.615ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     0.463      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.596   (73.5% logic, 26.5% route), 3 logic levels.
+
+Report:    3.615ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.527ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.508ns  (76.0% logic, 24.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.527ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     0.456       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.508   (76.0% logic, 24.0% route), 3 logic levels.
+
+Report:    3.527ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.549ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.530ns  (75.4% logic, 24.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.549ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     0.397      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.530   (75.4% logic, 24.6% route), 3 logic levels.
+
+Report:    3.549ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.452ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.471ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     0.316      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.452   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.471ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_59 and
+      2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     0.475      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.362ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.343ns  (77.1% logic, 22.9% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_35 and
+      2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.362ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     0.537       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.343   (77.1% logic, 22.9% route), 2 logic levels.
+
+Report:    3.362ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.194ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.175ns  (83.0% logic, 17.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_62 and
+      2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.194ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     0.369      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.175   (83.0% logic, 17.0% route), 2 logic levels.
+
+Report:    3.194ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.303ns  (78.4% logic, 21.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_60 and
+      2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.497      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.303   (78.4% logic, 21.6% route), 2 logic levels.
+
+Report:    3.322ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_57 and
+      2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     0.475      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.540ns  (75.1% logic, 24.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.139      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     0.494       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.540   (75.1% logic, 24.9% route), 3 logic levels.
+
+Report:    3.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.470ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.451ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.470ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     0.399       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.451   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.470ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.561 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.552 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.615 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.527 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.549 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.471 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.362 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.194 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.322 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.470 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log
new file mode 100644
index 0000000..0265ac7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log
@@ -0,0 +1,15 @@
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+    452 blocks expanded
+completed the first expansion
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
new file mode 100644
index 0000000..71c3f66
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
@@ -0,0 +1,335 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 17 06:19:46 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
+            130 items scored, 125 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i4 to CmdLEDEN_545
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i4 to Cmdn8MEGEN_546
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i5 to CmdLEDEN_545
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 0.941                                  Bank[5]
+LUT4        ---     0.493              B to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+Warning: 13.106 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            1392 items scored, 1147 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.222ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
+
+   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.062ns data_path FS_972__i8 to wb_adr_i4 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
+
+ Path Details: FS_972__i8 to wb_adr_i4
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
+Route        23   e 1.894                                  FS[8]
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i28_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[4]
+                  --------
+                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
+
+
+Error:  The following path violates requirements by 10.222ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i6  (to RCLK_c +)
+
+   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.062ns data_path FS_972__i8 to wb_adr_i6 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
+
+ Path Details: FS_972__i8 to wb_adr_i6
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
+Route        23   e 1.894                                  FS[8]
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i29_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[6]
+                  --------
+                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
+
+
+Error:  The following path violates requirements by 10.216ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i6  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
+
+   Delay:                  15.056ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.056ns data_path FS_972__i6 to wb_adr_i4 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
+
+ Path Details: FS_972__i6 to wb_adr_i4
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i6 (from RCLK_c)
+Route        21   e 1.888                                  FS[6]
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i28_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[4]
+                  --------
+                   15.056  (30.7% logic, 69.3% route), 10 logic levels.
+
+Warning: 15.222 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |     5.000 ns|    26.212 ns|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    15.222 ns|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n14                                     |      16|     200|     15.72%
+                                        |        |        |
+n12_adj_8                               |       2|     198|     15.57%
+                                        |        |        |
+n14_adj_3                               |       1|     183|     14.39%
+                                        |        |        |
+n14_adj_7                               |       2|     176|     13.84%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 1272  Score: 5951146
+
+Constraints cover  1577 paths, 335 nets, and 954 connections (77.9% coverage)
+
+
+Peak memory: 59748352 bytes, TRCE: 3297280 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
new file mode 100644
index 0000000..098f931
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
@@ -0,0 +1,402 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 17 05:43:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            120 items scored, 116 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.528ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.743ns  (30.6% logic, 69.4% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.743ns data_path Bank_i1 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.528ns
+
+ Path Details: Bank_i1 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         2   e 1.198                                  Bank[1]
+LUT4        ---     0.493              B to Z              i1819_2_lut
+Route         1   e 0.941                                  n2427
+LUT4        ---     0.493              C to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.743  (30.6% logic, 69.4% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.471ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.686ns  (30.7% logic, 69.3% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.686ns data_path Bank_i3 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
+
+ Path Details: Bank_i3 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1799_2_lut
+Route         2   e 1.141                                  n2407
+LUT4        ---     0.493              A to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.686  (30.7% logic, 69.3% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.471ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i6  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.686ns  (30.7% logic, 69.3% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.686ns data_path Bank_i6 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
+
+ Path Details: Bank_i6 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i6 (from PHI2_c)
+Route         1   e 0.941                                  Bank[6]
+LUT4        ---     0.493              A to Z              i1799_2_lut
+Route         2   e 1.141                                  n2407
+LUT4        ---     0.493              A to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.686  (30.7% logic, 69.3% route), 8 logic levels.
+
+Warning: 13.028 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            466 items scored, 158 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i9  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             n8MEGEN_557  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i9 to n8MEGEN_557 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i9 to n8MEGEN_557
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i9 (from RCLK_c)
+Route         3   e 1.315                                  FS[9]
+LUT4        ---     0.493              A to Z              i1847_4_lut
+Route         1   e 0.941                                  n2455
+LUT4        ---     0.493              B to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i9  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             LEDEN_556  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i9 to LEDEN_556 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i9 to LEDEN_556
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i9 (from RCLK_c)
+Route         3   e 1.315                                  FS[9]
+LUT4        ---     0.493              A to Z              i1847_4_lut
+Route         1   e 0.941                                  n2455
+LUT4        ---     0.493              B to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i8  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             n8MEGEN_557  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i8 to n8MEGEN_557 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i8 to n8MEGEN_557
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i8 (from RCLK_c)
+Route         3   e 1.315                                  FS[8]
+LUT4        ---     0.493              B to Z              i1821_2_lut
+Route         1   e 0.941                                  n2429
+LUT4        ---     0.493              C to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+Warning: 8.233 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    26.056 ns|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.233 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1712                                   |       5|     104|     37.96%
+                                        |        |        |
+n2465                                   |       1|      52|     18.98%
+                                        |        |        |
+n2251                                   |       1|      41|     14.96%
+                                        |        |        |
+n2551                                   |       2|      40|     14.60%
+                                        |        |        |
+n2250                                   |       1|      39|     14.23%
+                                        |        |        |
+n2252                                   |       1|      39|     14.23%
+                                        |        |        |
+XOR8MEG_N_117                           |       3|      34|     12.41%
+                                        |        |        |
+n2249                                   |       1|      33|     12.04%
+                                        |        |        |
+n2253                                   |       1|      33|     12.04%
+                                        |        |        |
+C1Submitted_N_200                       |       4|      32|     11.68%
+                                        |        |        |
+n2379                                   |       2|      32|     11.68%
+                                        |        |        |
+n2435                                   |       1|      32|     11.68%
+                                        |        |        |
+RCLK_c_enable_10                        |       2|      30|     10.95%
+                                        |        |        |
+n2384                                   |       1|      30|     10.95%
+                                        |        |        |
+n2385                                   |       1|      30|     10.95%
+                                        |        |        |
+n2407                                   |       2|      28|     10.22%
+                                        |        |        |
+n2453                                   |       2|      28|     10.22%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 274  Score: 1700966
+
+Constraints cover  587 paths, 177 nets, and 436 connections (66.4% coverage)
+
+
+Peak memory: 55074816 bytes, TRCE: 434176 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
new file mode 100644
index 0000000..e6fdb98
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
@@ -0,0 +1,1243 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
+// Netlist written on Tue Aug 17 06:19:46 2021
+//
+// Verilog Description of module RAM2GS
+//
+
+module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
+            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
+            nRCAS, RDQMH, RDQML) /* synthesis syn_module_defined=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1[8:14])
+    input PHI2;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    input [9:0]MAin;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    input [1:0]CROW;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    input [7:0]Din;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    output [7:0]Dout;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    input nCCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    input nCRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    input nFWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12])
+    output LED;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12])
+    output [1:0]RBA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    output [11:0]RA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    inout [7:0]RD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    output nRCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17])
+    input RCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    output RCKE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17])
+    output nRWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49])
+    output nRRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28])
+    output nRCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39])
+    output RDQMH;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21])
+    output RDQML;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14])
+    
+    wire PHI2_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    wire nCCAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    wire nCRAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    wire wb_clk /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(317[6:12])
+    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    wire PHI2_N_151 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(37[6:13])
+    
+    wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, 
+        RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, 
+        Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0;
+    wire [7:0]Bank;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(30[12:16])
+    
+    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
+        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
+        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
+        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n1975;
+    wire [9:0]RowA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(50[12:16])
+    
+    wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, 
+        RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
+    wire [7:0]WRD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(58[12:15])
+    
+    wire C1Submitted, ADSubmitted, CmdEnable, CmdSubmitted, CmdLEDEN, 
+        Cmdn8MEGEN, CmdUFMData, CmdUFMShift, n4097, InitReady, Ready, 
+        n10;
+    wire [17:0]FS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    
+    wire wb_rst, wb_cyc_stb, wb_we;
+    wire [7:0]wb_adr;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(321[12:18])
+    wire [7:0]wb_dati;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(322[12:19])
+    wire [1:0]wb_dato;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(323[13:20])
+    
+    wire LED_N_134, RA11_N_217, n1197, n3, RCKE_N_165, nRowColSel_N_35, 
+        nRWE_N_215, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, 
+        nRCS_N_179, n2557, nRCS_N_175, n2556, n4883, nRCS_N_174, 
+        nRCAS_N_199, nRWE_N_211, RCKEEN_N_153, nRCS_N_172, nRCAS_N_198, 
+        nRWE_N_210, nRWE_N_209, n1196, n1195, n1194, n1193, n3622, 
+        Ready_N_284, nRCS_N_170, Ready_N_280, nRCS_N_169, nRRAS_N_189, 
+        nRCAS_N_194, nRWE_N_204, RCKEEN_N_152, n3989, n1, CmdEnable_N_243, 
+        C1Submitted_N_232, XOR8MEG_N_149, CmdLEDEN_N_251, Cmdn8MEGEN_N_260, 
+        n4901, n2199, wb_adr_7__N_92, RCLK_c_enable_27, n4149, n17, 
+        wb_we_N_354, n2426, n5144, n4539, n93, n38, n4900, n87, 
+        wb_we_N_351, n638, n646, n4893, wb_cyc_stb_N_350, n4888, 
+        n5142, n4087, wb_cyc_stb_N_348, n89, n4880, n80, n4899, 
+        n2238, n746, n747, n748, n751, n752, n754, n755, n756, 
+        n757, n758, n759, n760, n761, n4094, n4093, n4882, n4628, 
+        n23, n4624, n4892, n4092, n4622, n3609, n4091, LEDEN_N_110, 
+        n8MEGEN_N_139, PHI2_N_151_enable_3, n4610, RCLK_c_enable_25, 
+        RCLK_c_enable_28, n4887, n4548, n84, wb_we_N_338, n2549, 
+        n83, n1969, n1971, wb_cyc_stb_N_307, n4517;
+    wire [7:0]wb_adr_7__N_60;
+    wire [7:0]wb_dati_7__N_68;
+    
+    wire n1192, n1191, n1189, n1188, n1187, n1186, n1185, n6, 
+        n3_adj_1, n4519, n2308, n14, n86, n39, PHI2_N_151_enable_1, 
+        n12, n2040, n2104, n1286, n4869, PHI2_N_151_enable_5, RCLK_c_enable_24, 
+        n4165, n1972, Dout_c, n1965, n1974, n10_adj_2, n78, n2262, 
+        n2252, n2258, n1973, n14_adj_3, n4884, n2244, n1885, n56, 
+        n4859, n4858, n1889, RCLK_c_enable_20, RCLK_c_enable_29, n4898, 
+        n45, n53, n85, n92, RCLK_c_enable_26, n4526, n4090, n1970, 
+        n4939, n4938, n95, n4937, n4089, n2384, n4850, n42, 
+        n3_adj_4, n4936, n1968, n91, n94, n90, n88, n79, n4935, 
+        n42_adj_5, n81, n82, n1_adj_6, n14_adj_7, n4574, n4504, 
+        n4088, n4086, n12_adj_8, n4934, PHI2_N_151_enable_6, n4933, 
+        n4585, n4932, n4733, n98, n4732, n3671, n4931, n4930, 
+        n4125, n4929, n4928, n4731, n4927, n4926, n4925, n4924, 
+        n4730, n4897, n4923, RCLK_c_enable_22, n4729, n53_adj_9, 
+        n175, n4921, n4920, n4919, n4164, n4918, n4917, n4916, 
+        n4915, n12_adj_10, n4914, n4913, n4896, n4807, n4806, 
+        n4582, n15, n4129, n3969, n4911, n3711, n4910, n4527, 
+        n4909, n4530, n4891, n6_adj_11, n4718, n4908, n6_adj_12, 
+        n4895, n4890, n4886, n4, n4907, n4_adj_13, PHI2_N_151_enable_7, 
+        n4782, n4889, n4894, n14_adj_14, n4885, n4777, n4776, 
+        n6_adj_15, n4906, n4905, n4941, n4632, n4513, n3_adj_16, 
+        n20, n4904, n4775, n4618, n4774, n4634, n22, n4903, 
+        n4902, n4940, n7;
+    
+    VHI i2 (.Z(VCC_net));
+    INV i4006 (.A(nCCAS_c), .Z(nCCAS_N_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    FD1P3AX IS_FSM__i15 (.D(n1185), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(Ready_N_284));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i15.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i14 (.D(n1186), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1185));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i14.GSR = "ENABLED";
+    FD1S3AX PHI2r2_513 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r2_513.GSR = "ENABLED";
+    FD1S3AX PHI2r3_514 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r3_514.GSR = "ENABLED";
+    FD1S3AX RASr_515 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr_515.GSR = "ENABLED";
+    FD1S3AX RASr2_516 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr2_516.GSR = "ENABLED";
+    FD1S3AX RASr3_517 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr3_517.GSR = "ENABLED";
+    FD1S3AX CASr_518 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr_518.GSR = "ENABLED";
+    FD1S3AX CASr2_519 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr2_519.GSR = "ENABLED";
+    FD1S3AX CASr3_520 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr3_520.GSR = "ENABLED";
+    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i0.GSR = "ENABLED";
+    FD1S3IX S_FSM_i2 (.D(n2556), .CK(RCLK_c), .CD(n4933), .Q(nRowColSel_N_34));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i0.GSR = "ENABLED";
+    FD1S3AX FWEr_525 (.D(n4932), .CK(nCRAS_N_9), .Q(FWEr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam FWEr_525.GSR = "ENABLED";
+    FD1S3AX CBR_526 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam CBR_526.GSR = "ENABLED";
+    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RBA__i1.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i13 (.D(n1187), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1186));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i13.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i12 (.D(n1188), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1187));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i12.GSR = "ENABLED";
+    EFB ufmefb (.WBCLKI(wb_clk), .WBRSTI(wb_rst), .WBCYCI(wb_cyc_stb), 
+        .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), .WBADRI0(wb_adr[0]), .WBADRI1(wb_adr[1]), 
+        .WBADRI2(wb_adr[2]), .WBADRI3(wb_adr[3]), .WBADRI4(wb_adr[4]), 
+        .WBADRI5(wb_adr[5]), .WBADRI6(wb_adr[6]), .WBADRI7(wb_adr[7]), 
+        .WBDATI0(wb_dati[0]), .WBDATI1(wb_dati[1]), .WBDATI2(wb_dati[2]), 
+        .WBDATI3(wb_dati[3]), .WBDATI4(wb_dati[4]), .WBDATI5(wb_dati[5]), 
+        .WBDATI6(wb_dati[6]), .WBDATI7(wb_dati[7]), .I2C1SCLI(GND_net), 
+        .I2C1SDAI(GND_net), .I2C2SCLI(GND_net), .I2C2SDAI(GND_net), .SPISCKI(GND_net), 
+        .SPIMISOI(GND_net), .SPIMOSII(GND_net), .SPISCSN(GND_net), .TCCLKI(GND_net), 
+        .TCRSTN(GND_net), .TCIC(GND_net), .PLL0DATI0(GND_net), .PLL0DATI1(GND_net), 
+        .PLL0DATI2(GND_net), .PLL0DATI3(GND_net), .PLL0DATI4(GND_net), 
+        .PLL0DATI5(GND_net), .PLL0DATI6(GND_net), .PLL0DATI7(GND_net), 
+        .PLL0ACKI(GND_net), .PLL1DATI0(GND_net), .PLL1DATI1(GND_net), 
+        .PLL1DATI2(GND_net), .PLL1DATI3(GND_net), .PLL1DATI4(GND_net), 
+        .PLL1DATI5(GND_net), .PLL1DATI6(GND_net), .PLL1DATI7(GND_net), 
+        .PLL1ACKI(GND_net), .WBDATO0(wb_dato[0]), .WBDATO1(wb_dato[1])) /* synthesis syn_instantiated=1 */ ;
+    defparam ufmefb.EFB_I2C1 = "DISABLED";
+    defparam ufmefb.EFB_I2C2 = "DISABLED";
+    defparam ufmefb.EFB_SPI = "DISABLED";
+    defparam ufmefb.EFB_TC = "DISABLED";
+    defparam ufmefb.EFB_TC_PORTMODE = "NO_WB";
+    defparam ufmefb.EFB_UFM = "DISABLED";
+    defparam ufmefb.EFB_WB_CLK_FREQ = "50.0";
+    defparam ufmefb.DEV_DENSITY = "1200L";
+    defparam ufmefb.UFM_INIT_PAGES = 0;
+    defparam ufmefb.UFM_INIT_START_PAGE = 0;
+    defparam ufmefb.UFM_INIT_ALL_ZEROS = "ENABLED";
+    defparam ufmefb.UFM_INIT_FILE_NAME = "NONE";
+    defparam ufmefb.UFM_INIT_FILE_FORMAT = "HEX";
+    defparam ufmefb.I2C1_ADDRESSING = "7BIT";
+    defparam ufmefb.I2C2_ADDRESSING = "7BIT";
+    defparam ufmefb.I2C1_SLAVE_ADDR = "0b1000001";
+    defparam ufmefb.I2C2_SLAVE_ADDR = "0b1000010";
+    defparam ufmefb.I2C1_BUS_PERF = "100kHz";
+    defparam ufmefb.I2C2_BUS_PERF = "100kHz";
+    defparam ufmefb.I2C1_CLK_DIVIDER = 1;
+    defparam ufmefb.I2C2_CLK_DIVIDER = 1;
+    defparam ufmefb.I2C1_GEN_CALL = "DISABLED";
+    defparam ufmefb.I2C2_GEN_CALL = "DISABLED";
+    defparam ufmefb.I2C1_WAKEUP = "DISABLED";
+    defparam ufmefb.I2C2_WAKEUP = "DISABLED";
+    defparam ufmefb.SPI_MODE = "SLAVE";
+    defparam ufmefb.SPI_CLK_DIVIDER = 1;
+    defparam ufmefb.SPI_LSB_FIRST = "DISABLED";
+    defparam ufmefb.SPI_CLK_INV = "DISABLED";
+    defparam ufmefb.SPI_PHASE_ADJ = "DISABLED";
+    defparam ufmefb.SPI_SLAVE_HANDSHAKE = "DISABLED";
+    defparam ufmefb.SPI_INTR_TXRDY = "DISABLED";
+    defparam ufmefb.SPI_INTR_RXRDY = "DISABLED";
+    defparam ufmefb.SPI_INTR_TXOVR = "DISABLED";
+    defparam ufmefb.SPI_INTR_RXOVR = "DISABLED";
+    defparam ufmefb.SPI_WAKEUP = "DISABLED";
+    defparam ufmefb.TC_MODE = "CTCM";
+    defparam ufmefb.TC_SCLK_SEL = "PCLOCK";
+    defparam ufmefb.TC_CCLK_SEL = 1;
+    defparam ufmefb.GSR = "ENABLED";
+    defparam ufmefb.TC_TOP_SET = 65535;
+    defparam ufmefb.TC_OCR_SET = 32767;
+    defparam ufmefb.TC_OC_MODE = "TOGGLE";
+    defparam ufmefb.TC_RESETN = "ENABLED";
+    defparam ufmefb.TC_TOP_SEL = "ON";
+    defparam ufmefb.TC_OV_INT = "OFF";
+    defparam ufmefb.TC_OCR_INT = "OFF";
+    defparam ufmefb.TC_ICR_INT = "OFF";
+    defparam ufmefb.TC_OVERFLOW = "ENABLED";
+    defparam ufmefb.TC_ICAPTURE = "DISABLED";
+    FD1P3AX IS_FSM__i11 (.D(n1189), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1188));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i11.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i10 (.D(nRWE_N_210), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1189));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i10.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i9 (.D(n1191), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRWE_N_210));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i9.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i8 (.D(n1192), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1191));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i8.GSR = "ENABLED";
+    FD1S3AX RCKE_531 (.D(RCKE_N_165), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(133[9] 136[5])
+    defparam RCKE_531.GSR = "ENABLED";
+    FD1P3AY nRCS_532 (.D(nRCS_N_169), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRCS_532.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i7 (.D(n1193), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1192));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i7.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i6 (.D(n1194), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1193));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i6.GSR = "ENABLED";
+    FD1S3IX S_FSM_i3 (.D(n2556), .CK(RCLK_c), .CD(n2557), .Q(nRowColSel_N_33));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i5 (.D(n1195), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1194));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i5.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i4 (.D(n1196), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1195));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i4.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i3 (.D(n1197), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1196));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_198), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1197));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i2.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i1 (.D(nRCS_N_172), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRCAS_N_198));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i1.GSR = "ENABLED";
+    FD1P3AY nRRAS_533 (.D(nRRAS_N_189), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRRAS_533.GSR = "ENABLED";
+    LUT4 m1_lut (.Z(n5144)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
+    defparam m1_lut.init = 16'hffff;
+    FD1P3AY nRCAS_534 (.D(nRCAS_N_194), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRCAS_534.GSR = "ENABLED";
+    FD1P3AY nRWE_535 (.D(nRWE_N_204), .SP(RCLK_c_enable_29), .CK(RCLK_c), 
+            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRWE_535.GSR = "ENABLED";
+    FD1S3JX RA10_536 (.D(n4129), .CK(RCLK_c), .PD(nRWE_N_209), .Q(n1975));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam RA10_536.GSR = "ENABLED";
+    FD1P3AX RCKEEN_537 (.D(RCKEEN_N_152), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(RCKEEN));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam RCKEEN_537.GSR = "ENABLED";
+    FD1S3JX C1Submitted_542 (.D(n2549), .CK(PHI2_N_151), .PD(C1Submitted_N_232), 
+            .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam C1Submitted_542.GSR = "ENABLED";
+    FD1P3IX wb_we_553 (.D(wb_we_N_338), .SP(RCLK_c_enable_25), .CD(wb_adr_7__N_92), 
+            .CK(RCLK_c), .Q(wb_we));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_we_553.GSR = "ENABLED";
+    LUT4 nRCS_I_34_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), 
+         .D(nRCS_N_175), .Z(nRCS_N_174)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ;
+    defparam nRCS_I_34_3_lut_4_lut.init = 16'h1f10;
+    FD1S3AX CmdSubmitted_549 (.D(XOR8MEG_N_149), .CK(PHI2_N_151), .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdSubmitted_549.GSR = "ENABLED";
+    FD1S3AX FS_972__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i17.GSR = "ENABLED";
+    PFUMX i12 (.BLUT(n3), .ALUT(n758), .C0(InitReady), .Z(wb_dati_7__N_68[3]));
+    FD1S3AX FS_972__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i16.GSR = "ENABLED";
+    FD1S3AX FS_972__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i15.GSR = "ENABLED";
+    FD1S3AX FS_972__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i14.GSR = "ENABLED";
+    FD1S3AX FS_972__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i13.GSR = "ENABLED";
+    FD1S3AX FS_972__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i12.GSR = "ENABLED";
+    FD1S3AX FS_972__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i11.GSR = "ENABLED";
+    FD1S3AX FS_972__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i10.GSR = "ENABLED";
+    FD1S3AX FS_972__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i9.GSR = "ENABLED";
+    FD1S3AX FS_972__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i8.GSR = "ENABLED";
+    FD1S3AX FS_972__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i7.GSR = "ENABLED";
+    FD1S3AX FS_972__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i6.GSR = "ENABLED";
+    FD1S3AX wb_adr_i0 (.D(wb_adr_7__N_60[0]), .CK(RCLK_c), .Q(wb_adr[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i0.GSR = "ENABLED";
+    FD1S3AX FS_972__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i5.GSR = "ENABLED";
+    FD1S3AX FS_972__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i4.GSR = "ENABLED";
+    FD1S3AX FS_972__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i3.GSR = "ENABLED";
+    FD1S3AX FS_972__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i2.GSR = "ENABLED";
+    FD1S3AX FS_972__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i1.GSR = "ENABLED";
+    FD1P3AX wb_rst_551 (.D(n3671), .SP(RCLK_c_enable_22), .CK(RCLK_c), 
+            .Q(wb_rst));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_rst_551.GSR = "ENABLED";
+    FD1S3AX wb_dati_i0 (.D(wb_dati_7__N_68[0]), .CK(RCLK_c), .Q(wb_dati[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i0.GSR = "ENABLED";
+    FD1S3AX S_FSM_i1 (.D(n4921), .CK(RCLK_c), .Q(nRowColSel_N_35));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i1.GSR = "ENABLED";
+    FD1P3AX LEDEN_556 (.D(LEDEN_N_110), .SP(RCLK_c_enable_24), .CK(RCLK_c), 
+            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam LEDEN_556.GSR = "ENABLED";
+    FD1P3AX n8MEGEN_557 (.D(n8MEGEN_N_139), .SP(RCLK_c_enable_24), .CK(RCLK_c), 
+            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam n8MEGEN_557.GSR = "ENABLED";
+    FD1S3AX PHI2r_512 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r_512.GSR = "ENABLED";
+    FD1S3IX S_FSM_i4 (.D(n1286), .CK(RCLK_c), .CD(n4921), .Q(nRowColSel_N_32));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i4.GSR = "ENABLED";
+    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12])
+    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14])
+    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21])
+    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39])
+    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28])
+    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49])
+    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17])
+    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17])
+    OB RA_pad_0 (.I(RA_c_0), .O(RA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_1 (.I(RA_c_1), .O(RA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_2 (.I(RA_c_2), .O(RA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_3 (.I(RA_c_3), .O(RA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_4 (.I(RA_c_4), .O(RA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_5 (.I(RA_c_5), .O(RA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_6 (.I(RA_c_6), .O(RA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_7 (.I(RA_c_7), .O(RA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_8 (.I(RA_c_8), .O(RA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_9 (.I(RA_c_9), .O(RA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_10 (.I(n1975), .O(RA[10]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    OB LED_pad (.I(LED_N_134), .O(LED));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12])
+    OB Dout_pad_0 (.I(Dout_c), .O(Dout[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_1 (.I(n1974), .O(Dout[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_2 (.I(n1973), .O(Dout[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_3 (.I(n1972), .O(Dout[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_4 (.I(n1971), .O(Dout[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_5 (.I(n1970), .O(Dout[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_6 (.I(n1969), .O(Dout[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_7 (.I(n1968), .O(Dout[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    BB Dout_pad_0__1130 (.I(WRD[0]), .T(n1965), .B(RD[0]), .O(Dout_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_1__1129 (.I(WRD[1]), .T(n1965), .B(RD[1]), .O(n1974));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_2__1128 (.I(WRD[2]), .T(n1965), .B(RD[2]), .O(n1973));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_3__1127 (.I(WRD[3]), .T(n1965), .B(RD[3]), .O(n1972));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_4__1126 (.I(WRD[4]), .T(n1965), .B(RD[4]), .O(n1971));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_5__1125 (.I(WRD[5]), .T(n1965), .B(RD[5]), .O(n1970));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_6__1124 (.I(WRD[6]), .T(n1965), .B(RD[6]), .O(n1969));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    FD1S3AX wb_dati_i7 (.D(wb_dati_7__N_68[7]), .CK(RCLK_c), .Q(wb_dati[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i7.GSR = "ENABLED";
+    FD1S3AX wb_dati_i6 (.D(wb_dati_7__N_68[6]), .CK(RCLK_c), .Q(wb_dati[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i6.GSR = "ENABLED";
+    FD1S3AX wb_dati_i5 (.D(wb_dati_7__N_68[5]), .CK(RCLK_c), .Q(wb_dati[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i5.GSR = "ENABLED";
+    FD1S3AX wb_dati_i4 (.D(wb_dati_7__N_68[4]), .CK(RCLK_c), .Q(wb_dati[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i4.GSR = "ENABLED";
+    FD1S3AX wb_dati_i3 (.D(wb_dati_7__N_68[3]), .CK(RCLK_c), .Q(wb_dati[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i3.GSR = "ENABLED";
+    FD1S3AX wb_dati_i2 (.D(wb_dati_7__N_68[2]), .CK(RCLK_c), .Q(wb_dati[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i2.GSR = "ENABLED";
+    FD1S3AX wb_dati_i1 (.D(wb_dati_7__N_68[1]), .CK(RCLK_c), .Q(wb_dati[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i1.GSR = "ENABLED";
+    CCU2D FS_972_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4086), 
+          .COUT(n4087), .S0(n94), .S1(n93));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_3.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_3.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_3.INJECT1_0 = "NO";
+    defparam FS_972_add_4_3.INJECT1_1 = "NO";
+    PFUMX i1369 (.BLUT(wb_we_N_351), .ALUT(n2104), .C0(n4886), .Z(n2238));
+    FD1P3IX wb_cyc_stb_552 (.D(wb_cyc_stb_N_307), .SP(RCLK_c_enable_25), 
+            .CD(wb_adr_7__N_92), .CK(RCLK_c), .Q(wb_cyc_stb));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_cyc_stb_552.GSR = "ENABLED";
+    FD1S3AX wb_adr_i7 (.D(wb_adr_7__N_60[7]), .CK(RCLK_c), .Q(wb_adr[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i7.GSR = "ENABLED";
+    FD1S3AX wb_adr_i6 (.D(wb_adr_7__N_60[6]), .CK(RCLK_c), .Q(wb_adr[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i6.GSR = "ENABLED";
+    FD1S3AX wb_adr_i5 (.D(wb_adr_7__N_60[5]), .CK(RCLK_c), .Q(wb_adr[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i5.GSR = "ENABLED";
+    FD1S3AX wb_adr_i4 (.D(wb_adr_7__N_60[4]), .CK(RCLK_c), .Q(wb_adr[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i4.GSR = "ENABLED";
+    FD1S3AX wb_adr_i3 (.D(wb_adr_7__N_60[3]), .CK(RCLK_c), .Q(wb_adr[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i3.GSR = "ENABLED";
+    FD1S3AX wb_adr_i2 (.D(wb_adr_7__N_60[2]), .CK(RCLK_c), .Q(wb_adr[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i2.GSR = "ENABLED";
+    FD1S3AX wb_adr_i1 (.D(wb_adr_7__N_60[1]), .CK(RCLK_c), .Q(wb_adr[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i1.GSR = "ENABLED";
+    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RBA__i2.GSR = "ENABLED";
+    CCU2D FS_972_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4093), 
+          .COUT(n4094), .S0(n80), .S1(n79));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_17.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_17.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_17.INJECT1_0 = "NO";
+    defparam FS_972_add_4_17.INJECT1_1 = "NO";
+    CCU2D FS_972_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4092), 
+          .COUT(n4093), .S0(n82), .S1(n81));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_15.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_15.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_15.INJECT1_0 = "NO";
+    defparam FS_972_add_4_15.INJECT1_1 = "NO";
+    FD1P3AX CmdEnable_541 (.D(CmdEnable_N_243), .SP(PHI2_N_151_enable_1), 
+            .CK(PHI2_N_151), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdEnable_541.GSR = "ENABLED";
+    FD1P3AX InitReady_530 (.D(n5144), .SP(RCLK_c_enable_26), .CK(RCLK_c), 
+            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(126[9] 130[5])
+    defparam InitReady_530.GSR = "ENABLED";
+    PFUMX i12_adj_1 (.BLUT(n3_adj_4), .ALUT(n755), .C0(InitReady), .Z(wb_dati_7__N_68[6]));
+    LUT4 i1_3_lut_4_lut_then_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4941)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_then_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_else_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4940)) /* synthesis lut_function=(!(A (B+(D))+!A (B+(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_else_4_lut.init = 16'h0133;
+    LUT4 i2692_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_215)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(160[14] 176[8])
+    defparam i2692_2_lut.init = 16'hdddd;
+    LUT4 i217_2_lut_rep_70 (.A(FS[9]), .B(FS[5]), .Z(n4919)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i217_2_lut_rep_70.init = 16'heeee;
+    LUT4 i1_2_lut (.A(n3989), .B(n3969), .Z(wb_dati_7__N_68[1])) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut.init = 16'heeee;
+    LUT4 n4542_bdd_4_lut (.A(FS[10]), .B(FS[11]), .C(FS[7]), .D(n4924), 
+         .Z(n4806)) /* synthesis lut_function=(!((B ((D)+!C)+!B (C+(D)))+!A)) */ ;
+    defparam n4542_bdd_4_lut.init = 16'h0082;
+    LUT4 i1_2_lut_4_lut (.A(n4929), .B(XOR8MEG_N_149), .C(Din_c_4), .D(n4931), 
+         .Z(PHI2_N_151_enable_3)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
+    defparam i1_2_lut_4_lut.init = 16'h4000;
+    PFUMX i3861 (.BLUT(n4777), .ALUT(n761), .C0(InitReady), .Z(wb_dati_7__N_68[0]));
+    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i0.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut (.A(CBR), .B(FWEr), .C(n4618), .D(nRowColSel_N_34), 
+         .Z(n20)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(206[26:30])
+    defparam i1_4_lut_4_lut.init = 16'h5540;
+    LUT4 n10_bdd_4_lut_3959 (.A(n10_adj_2), .B(FS[10]), .C(FS[11]), .D(n14), 
+         .Z(n4517)) /* synthesis lut_function=(A+(B (D)+!B ((D)+!C))) */ ;
+    defparam n10_bdd_4_lut_3959.init = 16'hffab;
+    LUT4 i3141_4_lut_4_lut (.A(n4895), .B(n3609), .C(FS[10]), .D(FS[11]), 
+         .Z(n38)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A !(B (C)+!B (C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i3141_4_lut_4_lut.init = 16'h5350;
+    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i7.GSR = "ENABLED";
+    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i6.GSR = "ENABLED";
+    LUT4 i2_3_lut_rep_77 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .Z(n4926)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i2_3_lut_rep_77.init = 16'h8080;
+    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i5.GSR = "ENABLED";
+    CCU2D FS_972_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4091), 
+          .COUT(n4092), .S0(n84), .S1(n83));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_13.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_13.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_13.INJECT1_0 = "NO";
+    defparam FS_972_add_4_13.INJECT1_1 = "NO";
+    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i4.GSR = "ENABLED";
+    LUT4 i1_2_lut_rep_57_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .D(nRCS_N_172), .Z(n4906)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i1_2_lut_rep_57_4_lut.init = 16'hff7f;
+    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i3.GSR = "ENABLED";
+    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i1.GSR = "ENABLED";
+    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i9.GSR = "ENABLED";
+    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i8.GSR = "ENABLED";
+    LUT4 n2426_bdd_4_lut (.A(n2426), .B(n4165), .C(FS[11]), .D(FS[10]), 
+         .Z(n5142)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
+    defparam n2426_bdd_4_lut.init = 16'hca00;
+    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i7.GSR = "ENABLED";
+    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i6.GSR = "ENABLED";
+    BB Dout_pad_7__1123 (.I(WRD[7]), .T(n1965), .B(RD[7]), .O(n1968));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i5.GSR = "ENABLED";
+    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i4.GSR = "ENABLED";
+    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i3.GSR = "ENABLED";
+    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i2.GSR = "ENABLED";
+    LUT4 i3798_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i3798_2_lut_4_lut.init = 16'h0080;
+    LUT4 i3_4_lut (.A(Din_c_6), .B(n4624), .C(Din_c_5), .D(n4548), .Z(C1Submitted_N_232)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
+    defparam i3_4_lut.init = 16'h0200;
+    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i1.GSR = "ENABLED";
+    GSR GSR_INST (.GSR(VCC_net));
+    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i7.GSR = "ENABLED";
+    LUT4 i1392_4_lut (.A(wb_we_N_354), .B(n2258), .C(n10_adj_2), .D(n4), 
+         .Z(n2262)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1392_4_lut.init = 16'hccca;
+    LUT4 i1388_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4891), 
+         .Z(n2258)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1388_4_lut.init = 16'hccca;
+    CCU2D FS_972_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4090), 
+          .COUT(n4091), .S0(n86), .S1(n85));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_11.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_11.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_11.INJECT1_0 = "NO";
+    defparam FS_972_add_4_11.INJECT1_1 = "NO";
+    LUT4 i1_2_lut_rep_35_3_lut_4_lut_4_lut (.A(n4920), .B(n4902), .C(n4899), 
+         .D(FS[10]), .Z(n4884)) /* synthesis lut_function=(A+(B (C)+!B !((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_35_3_lut_4_lut_4_lut.init = 16'heafa;
+    LUT4 i1_2_lut_rep_78 (.A(FS[7]), .B(FS[6]), .Z(n4927)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_2_lut_rep_78.init = 16'heeee;
+    LUT4 i2_2_lut_rep_51_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), 
+         .D(FS[9]), .Z(n4900)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i2_2_lut_rep_51_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i1_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), .D(FS[5]), 
+         .Z(n53_adj_9)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut.init = 16'hf0e0;
+    LUT4 i1_2_lut_rep_79 (.A(FS[5]), .B(FS[9]), .Z(n4928)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_79.init = 16'h2222;
+    LUT4 n34_bdd_2_lut_3877_3_lut (.A(FS[5]), .B(FS[9]), .C(n4806), .Z(n4807)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam n34_bdd_2_lut_3877_3_lut.init = 16'h2020;
+    LUT4 n61_bdd_4_lut_3912 (.A(n4923), .B(n12_adj_8), .C(n45), .D(FS[10]), 
+         .Z(n4850)) /* synthesis lut_function=(A (B+!((D)+!C))+!A (B)) */ ;
+    defparam n61_bdd_4_lut_3912.init = 16'hccec;
+    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i6.GSR = "ENABLED";
+    LUT4 i3122_3_lut_3_lut_4_lut (.A(n4927), .B(n4905), .C(n646), .D(FS[10]), 
+         .Z(n23)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i3122_3_lut_3_lut_4_lut.init = 16'h11f0;
+    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i5.GSR = "ENABLED";
+    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i4.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut_4_lut (.A(FS[10]), .B(n3_adj_16), .C(FS[11]), 
+         .D(n4895), .Z(n42_adj_5)) /* synthesis lut_function=(!(A+(B (C (D))+!B ((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_4_lut.init = 16'h0454;
+    LUT4 n1097_bdd_2_lut_3927 (.A(n4858), .B(FS[9]), .Z(n4859)) /* synthesis lut_function=(A+!(B)) */ ;
+    defparam n1097_bdd_2_lut_3927.init = 16'hbbbb;
+    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i3.GSR = "ENABLED";
+    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i2.GSR = "ENABLED";
+    FD1S3AX FS_972__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i0.GSR = "ENABLED";
+    LUT4 i7_4_lut_4_lut (.A(FS[4]), .B(n4517), .C(n10), .D(n14_adj_14), 
+         .Z(n4539)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(692[20:26])
+    defparam i7_4_lut_4_lut.init = 16'h4000;
+    LUT4 FS_5__bdd_4_lut_3949 (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4858)) /* synthesis lut_function=(A (B (C (D))+!B !(D))+!A !(B+(C (D)))) */ ;
+    defparam FS_5__bdd_4_lut_3949.init = 16'h8133;
+    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i1.GSR = "ENABLED";
+    LUT4 n9_bdd_2_lut_3908_4_lut (.A(n4910), .B(n4919), .C(FS[10]), .D(FS[12]), 
+         .Z(n4775)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam n9_bdd_2_lut_3908_4_lut.init = 16'h0200;
+    FD1P3AX CmdUFMData_548 (.D(Din_c_0), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), 
+            .Q(CmdUFMData)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdUFMData_548.GSR = "ENABLED";
+    LUT4 i3106_3_lut_3_lut (.A(FS[12]), .B(FS[11]), .C(n53), .Z(n1_adj_6)) /* synthesis lut_function=(!(A (B+!(C))+!A !(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i3106_3_lut_3_lut.init = 16'h7070;
+    LUT4 nRCAS_I_0_594_3_lut_4_lut (.A(nRCAS_N_198), .B(n4906), .C(Ready), 
+         .D(nRCAS_N_199), .Z(nRCAS_N_194)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6])
+    defparam nRCAS_I_0_594_3_lut_4_lut.init = 16'hfe0e;
+    LUT4 i5_4_lut_4_lut (.A(FS[12]), .B(n4895), .C(n4519), .D(n2308), 
+         .Z(n12_adj_10)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i5_4_lut_4_lut.init = 16'h4000;
+    LUT4 Din_7__I_0_i6_2_lut_rep_80 (.A(Din_c_6), .B(Din_c_7), .Z(n4929)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam Din_7__I_0_i6_2_lut_rep_80.init = 16'heeee;
+    LUT4 i1_4_lut_4_lut_adj_2 (.A(n4907), .B(FS[12]), .C(n42), .D(n4807), 
+         .Z(n3_adj_4)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_2.init = 16'h5140;
+    LUT4 FS_7__bdd_4_lut_3948 (.A(FS[7]), .B(FS[9]), .C(FS[8]), .D(n4939), 
+         .Z(n638)) /* synthesis lut_function=(!(A (B (C+(D)))+!A (B (C)+!B !(C+(D))))) */ ;
+    defparam FS_7__bdd_4_lut_3948.init = 16'h373e;
+    PFUMX i29 (.BLUT(n56), .ALUT(n1_adj_6), .C0(n4632), .Z(n14_adj_3));
+    LUT4 i2_3_lut_rep_33_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), 
+         .D(XOR8MEG_N_149), .Z(n4882)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i2_3_lut_rep_33_4_lut.init = 16'h1000;
+    LUT4 i1_2_lut_rep_59_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
+         .Z(n4908)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i1_2_lut_rep_59_3_lut.init = 16'hfefe;
+    LUT4 i21_3_lut_4_lut_4_lut (.A(n4907), .B(n759), .C(InitReady), .D(n4880), 
+         .Z(wb_dati_7__N_68[2])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i21_3_lut_4_lut_4_lut.init = 16'hc5c0;
+    PFUMX i13 (.BLUT(n4539), .ALUT(n4513), .C0(InitReady), .Z(RCLK_c_enable_24));
+    LUT4 i1_4_lut_4_lut_adj_3 (.A(n4907), .B(n4900), .C(n4890), .D(FS[5]), 
+         .Z(n45)) /* synthesis lut_function=(!(A+(B (C)+!B !((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_3.init = 16'h1505;
+    LUT4 FS_6__bdd_4_lut_3962 (.A(FS[6]), .B(FS[5]), .C(FS[8]), .D(FS[7]), 
+         .Z(n4869)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+(D)))+!A !(B (C+(D))+!B (C)))) */ ;
+    defparam FS_6__bdd_4_lut_3962.init = 16'h7ef0;
+    LUT4 i3707_2_lut_rep_81 (.A(MAin_c_3), .B(MAin_c_6), .Z(n4930)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3707_2_lut_rep_81.init = 16'h8888;
+    LUT4 i1_2_lut_rep_82 (.A(Din_c_3), .B(Din_c_5), .Z(n4931)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut_rep_82.init = 16'h8888;
+    PFUMX i3859 (.BLUT(n4775), .ALUT(n4774), .C0(FS[11]), .Z(n4776));
+    LUT4 i21_3_lut_4_lut_4_lut_adj_4 (.A(n4907), .B(n756), .C(InitReady), 
+         .D(n4880), .Z(wb_dati_7__N_68[5])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i21_3_lut_4_lut_4_lut_adj_4.init = 16'hc5c0;
+    LUT4 i1_4_lut_4_lut_adj_5 (.A(n4907), .B(FS[12]), .C(n42), .D(n39), 
+         .Z(n3)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_5.init = 16'h5140;
+    FD1P3AX CmdUFMShift_547 (.D(Din_c_1), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), 
+            .Q(CmdUFMShift)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdUFMShift_547.GSR = "ENABLED";
+    FD1P3AX Cmdn8MEGEN_546 (.D(Cmdn8MEGEN_N_260), .SP(PHI2_N_151_enable_5), 
+            .CK(PHI2_N_151), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam Cmdn8MEGEN_546.GSR = "ENABLED";
+    FD1P3AX CmdLEDEN_545 (.D(CmdLEDEN_N_251), .SP(PHI2_N_151_enable_5), 
+            .CK(PHI2_N_151), .Q(CmdLEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdLEDEN_545.GSR = "ENABLED";
+    LUT4 i1_2_lut_4_lut_4_lut (.A(n4907), .B(FS[12]), .C(n42_adj_5), .D(n38), 
+         .Z(n3_adj_1)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_4_lut_4_lut.init = 16'h5140;
+    FD1P3AX Ready_540 (.D(n5144), .SP(Ready_N_280), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam Ready_540.GSR = "ENABLED";
+    FD1P3AX XOR8MEG_544 (.D(Din_c_0), .SP(PHI2_N_151_enable_6), .CK(PHI2_N_151), 
+            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam XOR8MEG_544.GSR = "ENABLED";
+    LUT4 i3748_4_lut (.A(Din_c_3), .B(MAin_c_0), .C(Din_c_2), .D(n4888), 
+         .Z(n4624)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i3748_4_lut.init = 16'hfffe;
+    FD1S3IX RA11_521 (.D(RA11_N_217), .CK(PHI2_c), .CD(n4935), .Q(RA_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam RA11_521.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i0 (.D(Ready_N_284), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRCS_N_172));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i0.GSR = "ENABLED";
+    FD1P3AX wb_clk_550 (.D(n1889), .SP(RCLK_c_enable_28), .CK(RCLK_c), 
+            .Q(wb_clk));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_clk_550.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut_adj_6 (.A(n4907), .B(FS[11]), .C(n3711), .D(n175), 
+         .Z(n17)) /* synthesis lut_function=(!(A+(B (C)+!B !(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_6.init = 16'h1504;
+    FD1P3AX nRowColSel_538 (.D(n1885), .SP(RCLK_c_enable_29), .CK(RCLK_c), 
+            .Q(nRowColSel));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRowColSel_538.GSR = "ENABLED";
+    LUT4 i2_3_lut_rep_62_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_2), 
+         .D(Din_c_6), .Z(n4911)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
+    defparam i2_3_lut_rep_62_4_lut.init = 16'h0080;
+    LUT4 i2_1_lut_rep_83 (.A(nFWE_c), .Z(n4932)) /* synthesis lut_function=(!(A)) */ ;
+    defparam i2_1_lut_rep_83.init = 16'h5555;
+    LUT4 i1_2_lut_2_lut (.A(nFWE_c), .B(n4504), .Z(n4548)) /* synthesis lut_function=(!(A+!(B))) */ ;
+    defparam i1_2_lut_2_lut.init = 16'h4444;
+    LUT4 i1684_1_lut_rep_84 (.A(nRowColSel_N_35), .Z(n4933)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i1684_1_lut_rep_84.init = 16'h5555;
+    LUT4 i2736_4_lut (.A(wb_adr[7]), .B(InitReady), .C(wb_adr[6]), .D(n4901), 
+         .Z(wb_adr_7__N_60[7])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2736_4_lut.init = 16'hc088;
+    LUT4 i29_3_lut (.A(n14_adj_7), .B(n746), .C(InitReady), .Z(wb_adr_7__N_60[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i29_3_lut.init = 16'hcaca;
+    LUT4 i3_4_lut_4_lut (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), 
+         .D(nRCS_N_172), .Z(nRCS_N_170)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i3_4_lut_4_lut.init = 16'hff7f;
+    LUT4 i2787_2_lut_rep_85 (.A(FS[10]), .B(FS[11]), .Z(n4934)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i2787_2_lut_rep_85.init = 16'h8888;
+    LUT4 i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut (.A(FS[11]), .B(n14), 
+         .Z(n4891)) /* synthesis lut_function=((B)+!A) */ ;
+    defparam i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut.init = 16'hdddd;
+    LUT4 i3_4_lut_4_lut_adj_7 (.A(n4907), .B(n4904), .C(InitReady), .D(n4895), 
+         .Z(n3969)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3_4_lut_4_lut_adj_7.init = 16'h0004;
+    FD1P3IX ADSubmitted_543 (.D(n4883), .SP(PHI2_N_151_enable_7), .CD(C1Submitted_N_232), 
+            .CK(PHI2_N_151), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam ADSubmitted_543.GSR = "ENABLED";
+    LUT4 CmdLEDEN_I_69_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_1), 
+         .D(LEDEN), .Z(CmdLEDEN_N_251)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam CmdLEDEN_I_69_3_lut_4_lut.init = 16'hdf02;
+    LUT4 Cmdn8MEGEN_I_72_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_0), 
+         .D(n8MEGEN), .Z(Cmdn8MEGEN_N_260)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam Cmdn8MEGEN_I_72_3_lut_4_lut.init = 16'hdf02;
+    CCU2D FS_972_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4089), 
+          .COUT(n4090), .S0(n88), .S1(n87));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_9.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_9.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_9.INJECT1_0 = "NO";
+    defparam FS_972_add_4_9.INJECT1_1 = "NO";
+    LUT4 i3804_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), 
+         .Z(n3671)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i3804_2_lut_4_lut.init = 16'h0001;
+    LUT4 i1_2_lut_rep_53 (.A(FS[11]), .B(n14), .Z(n4902)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_53.init = 16'heeee;
+    LUT4 i3808_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(InitReady), 
+         .Z(wb_adr_7__N_92)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i3808_2_lut_4_lut.init = 16'h0001;
+    LUT4 i1_2_lut_rep_64_3_lut (.A(FS[10]), .B(FS[11]), .C(n14), .Z(n4913)) /* synthesis lut_function=(((C)+!B)+!A) */ ;
+    defparam i1_2_lut_rep_64_3_lut.init = 16'hf7f7;
+    LUT4 mux_427_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[3]), 
+         .D(wb_adr[4]), .Z(n748)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i5_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1044_1_lut_rep_86 (.A(Ready), .Z(n4935)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i1044_1_lut_rep_86.init = 16'h5555;
+    LUT4 n4729_bdd_2_lut_3976 (.A(n4729), .B(FS[11]), .Z(n4730)) /* synthesis lut_function=(!((B)+!A)) */ ;
+    defparam n4729_bdd_2_lut_3976.init = 16'h2222;
+    LUT4 i1_3_lut_rep_34_4_lut (.A(MAin_c_0), .B(n4888), .C(n4911), .D(n4548), 
+         .Z(n4883)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_3_lut_rep_34_4_lut.init = 16'h2000;
+    LUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n14), .C(FS[10]), .Z(n4)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_3_lut.init = 16'hefef;
+    LUT4 n3572_bdd_4_lut_3847 (.A(n4890), .B(wb_cyc_stb_N_350), .C(n638), 
+         .D(FS[10]), .Z(n4729)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n3572_bdd_4_lut_3847.init = 16'h88f0;
+    LUT4 n4733_bdd_2_lut (.A(n4733), .B(n3969), .Z(wb_adr_7__N_60[0])) /* synthesis lut_function=(A+(B)) */ ;
+    defparam n4733_bdd_2_lut.init = 16'heeee;
+    LUT4 i28_3_lut (.A(n14_adj_7), .B(n748), .C(InitReady), .Z(wb_adr_7__N_60[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i28_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_rep_44_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), 
+         .D(n4920), .Z(n4893)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_44_3_lut_4_lut.init = 16'hffef;
+    LUT4 i1_2_lut_2_lut_adj_8 (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i1_2_lut_2_lut_adj_8.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_37_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), 
+         .D(n4920), .Z(n4886)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_37_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n2040), .C(nRowColSel_N_32), 
+         .D(nRowColSel_N_35), .Z(RCLK_c_enable_29)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd;
+    LUT4 i2742_4_lut (.A(wb_adr[3]), .B(InitReady), .C(wb_adr[2]), .D(n4901), 
+         .Z(wb_adr_7__N_60[3])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2742_4_lut.init = 16'hc088;
+    LUT4 i2_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), 
+         .Z(n10)) /* synthesis lut_function=(!(A (D)+!A (B (D)+!B ((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i2_2_lut_4_lut.init = 16'h00fe;
+    LUT4 i2743_4_lut (.A(wb_adr[2]), .B(InitReady), .C(wb_adr[1]), .D(n4901), 
+         .Z(wb_adr_7__N_60[2])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2743_4_lut.init = 16'hc088;
+    CCU2D FS_972_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4088), 
+          .COUT(n4089), .S0(n90), .S1(n89));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_7.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_7.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_7.INJECT1_0 = "NO";
+    defparam FS_972_add_4_7.INJECT1_1 = "NO";
+    LUT4 i2_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[8]), .D(FS[6]), 
+         .Z(n3_adj_16)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i2_3_lut_4_lut.init = 16'h0100;
+    LUT4 nRCS_N_179_bdd_4_lut (.A(nRCS_N_179), .B(n2040), .C(nRWE_N_215), 
+         .D(nRowColSel_N_35), .Z(nRWE_N_211)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
+    defparam nRCS_N_179_bdd_4_lut.init = 16'hf0dd;
+    LUT4 i34_4_lut (.A(n7), .B(ADSubmitted), .C(C1Submitted_N_232), .D(n4889), 
+         .Z(PHI2_N_151_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;
+    defparam i34_4_lut.init = 16'hc0c5;
+    LUT4 FS_8__bdd_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[6]), .D(FS[8]), 
+         .Z(n4718)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam FS_8__bdd_3_lut_4_lut.init = 16'h0100;
+    LUT4 i13_4_lut (.A(MAin_c_0), .B(C1Submitted), .C(MAin_c_1), .D(n6_adj_11), 
+         .Z(n7)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (C))) */ ;
+    defparam i13_4_lut.init = 16'h2505;
+    LUT4 i2_2_lut_rep_54_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n4903)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2_2_lut_rep_54_2_lut.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_87 (.A(FS[7]), .B(FS[5]), .Z(n4936)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut_rep_87.init = 16'h8888;
+    LUT4 n34_bdd_2_lut_3867_3_lut_4_lut (.A(n4782), .B(n4930), .C(n4628), 
+         .D(n4582), .Z(PHI2_N_151_enable_7)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam n34_bdd_2_lut_3867_3_lut_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_adj_9 (.A(n4938), .B(n4914), .C(FS[9]), .D(n98), 
+         .Z(n2199)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_adj_9.init = 16'hc5cf;
+    LUT4 i3_4_lut_adj_10 (.A(FS[11]), .B(FS[12]), .C(n4907), .D(n23), 
+         .Z(n4125)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i3_4_lut_adj_10.init = 16'h0400;
+    LUT4 i1_2_lut_rep_49_3_lut_4_lut (.A(FS[7]), .B(FS[5]), .C(FS[9]), 
+         .D(n4937), .Z(n4898)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1_2_lut_rep_49_3_lut_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_adj_11 (.A(FS[10]), .B(n4923), .C(n12_adj_8), 
+         .D(n45), .Z(n14_adj_7)) /* synthesis lut_function=(A (C)+!A (B (C+(D))+!B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_3_lut_4_lut_adj_11.init = 16'hf4f0;
+    LUT4 i1_2_lut_rep_88 (.A(FS[6]), .B(FS[8]), .Z(n4937)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_88.init = 16'h8888;
+    LUT4 i1_2_lut_rep_65_3_lut_4_lut (.A(FS[6]), .B(FS[8]), .C(FS[5]), 
+         .D(FS[7]), .Z(n4914)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_65_3_lut_4_lut.init = 16'h8000;
+    LUT4 i3_4_lut_adj_12 (.A(Din_c_1), .B(Din_c_0), .C(Din_c_7), .D(Din_c_4), 
+         .Z(n4504)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_12.init = 16'h0040;
+    LUT4 i1_2_lut_rep_89 (.A(FS[7]), .B(FS[8]), .Z(n4938)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_89.init = 16'heeee;
+    LUT4 i2_3_lut (.A(InitReady), .B(FS[12]), .C(n754), .Z(n4165)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2_3_lut.init = 16'h8080;
+    LUT4 i1_2_lut_rep_45_3_lut_4_lut (.A(FS[7]), .B(FS[8]), .C(FS[9]), 
+         .D(n4939), .Z(n4894)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i1_2_lut_rep_45_3_lut_4_lut.init = 16'hfffe;
+    LUT4 n61_bdd_4_lut (.A(n4923), .B(n4895), .C(n4530), .D(FS[10]), 
+         .Z(n4880)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ;
+    defparam n61_bdd_4_lut.init = 16'h11f0;
+    LUT4 i1_2_lut_rep_90 (.A(FS[5]), .B(FS[6]), .Z(n4939)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_2_lut_rep_90.init = 16'heeee;
+    LUT4 i2_2_lut_rep_66_3_lut_4_lut (.A(FS[5]), .B(FS[6]), .C(FS[8]), 
+         .D(FS[7]), .Z(n4915)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i2_2_lut_rep_66_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i13_4_lut_adj_13 (.A(n4582), .B(n4628), .C(n15), .D(n4930), 
+         .Z(n2384)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ;
+    defparam i13_4_lut_adj_13.init = 16'hf7ff;
+    LUT4 i1_2_lut_adj_14 (.A(MAin_c_7), .B(Bank[2]), .Z(n15)) /* synthesis lut_function=((B)+!A) */ ;
+    defparam i1_2_lut_adj_14.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_38_4_lut (.A(n53_adj_9), .B(n4914), .C(FS[9]), .D(FS[11]), 
+         .Z(n4887)) /* synthesis lut_function=(A (B (C (D)))+!A (B (D)+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(464[4] 521[11])
+    defparam i1_2_lut_rep_38_4_lut.init = 16'hc500;
+    LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_172), .B(n4926), .C(Ready), .D(nRCAS_N_198), 
+         .Z(n4129)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6])
+    defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb;
+    LUT4 i1_3_lut_3_lut_4_lut (.A(FS[7]), .B(n4924), .C(n4914), .D(FS[9]), 
+         .Z(wb_cyc_stb_N_348)) /* synthesis lut_function=(A (C (D))+!A (B (C (D))+!B (C+!(D)))) */ ;
+    defparam i1_3_lut_3_lut_4_lut.init = 16'hf011;
+    LUT4 i1_2_lut_rep_58 (.A(n14), .B(FS[13]), .Z(n4907)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_rep_58.init = 16'heeee;
+    LUT4 i1_2_lut_adj_15 (.A(RASr2), .B(nRowColSel_N_32), .Z(n2556)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam i1_2_lut_adj_15.init = 16'h2222;
+    CCU2D FS_972_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4094), 
+          .S0(n78));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_19.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_19.INIT1 = 16'h0000;
+    defparam FS_972_add_4_19.INJECT1_0 = "NO";
+    defparam FS_972_add_4_19.INJECT1_1 = "NO";
+    LUT4 i3746_2_lut_3_lut (.A(n14), .B(FS[13]), .C(FS[10]), .Z(n4622)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3746_2_lut_3_lut.init = 16'hfefe;
+    LUT4 i3709_2_lut (.A(Bank[3]), .B(MAin_c_5), .Z(n4582)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3709_2_lut.init = 16'h8888;
+    LUT4 i3711_4_lut (.A(n4890), .B(n4887), .C(n2199), .D(FS[10]), .Z(n4585)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3711_4_lut.init = 16'ha088;
+    PFUMX i12_adj_16 (.BLUT(n4526), .ALUT(n751), .C0(InitReady), .Z(wb_adr_7__N_60[1]));
+    LUT4 i3751_4_lut (.A(Bank[1]), .B(n4610), .C(n4574), .D(Bank[0]), 
+         .Z(n4628)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i3751_4_lut.init = 16'h8000;
+    LUT4 i1_2_lut_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n14_adj_3), .Z(n12_adj_8)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_2_lut_3_lut.init = 16'h1010;
+    LUT4 i3734_4_lut (.A(MAin_c_4), .B(Bank[5]), .C(Bank[4]), .D(Bank[6]), 
+         .Z(n4610)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i3734_4_lut.init = 16'h8000;
+    PFUMX i1383 (.BLUT(n2244), .ALUT(n2252), .C0(n4634), .Z(wb_we_N_338));
+    LUT4 i2856_2_lut_3_lut_4_lut (.A(n14), .B(FS[13]), .C(n4915), .D(FS[9]), 
+         .Z(n2426)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i2856_2_lut_3_lut_4_lut.init = 16'h0001;
+    LUT4 i1669_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[0]), 
+         .D(Cmdn8MEGEN), .Z(n8MEGEN_N_139)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ;
+    defparam i1669_3_lut_4_lut.init = 16'hfe10;
+    LUT4 i3701_2_lut (.A(Bank[7]), .B(MAin_c_2), .Z(n4574)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3701_2_lut.init = 16'h8888;
+    LUT4 n34_bdd_2_lut_3863_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4776), 
+         .Z(n4777)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam n34_bdd_2_lut_3863_2_lut_3_lut.init = 16'h1010;
+    LUT4 i1382_3_lut (.A(wb_we_N_354), .B(wb_cyc_stb), .C(InitReady), 
+         .Z(n2252)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1382_3_lut.init = 16'hcaca;
+    PFUMX i12_adj_17 (.BLUT(n3_adj_1), .ALUT(n757), .C0(InitReady), .Z(wb_dati_7__N_68[4]));
+    LUT4 n34_bdd_2_lut_3841_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4731), 
+         .Z(n4732)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam n34_bdd_2_lut_3841_2_lut_3_lut.init = 16'h1010;
+    LUT4 i1375_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4913), 
+         .Z(n2244)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1375_4_lut.init = 16'hccca;
+    LUT4 i6_4_lut (.A(n4149), .B(n12_adj_10), .C(n4622), .D(n4164), 
+         .Z(n4526)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i6_4_lut.init = 16'h0800;
+    LUT4 mux_427_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[7]), 
+         .D(wb_adr[0]), .Z(n752)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i1_3_lut_4_lut.init = 16'hf780;
+    LUT4 i6_4_lut_adj_18 (.A(FS[13]), .B(n12), .C(FS[17]), .D(FS[14]), 
+         .Z(RCLK_c_enable_26)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i6_4_lut_adj_18.init = 16'h8000;
+    LUT4 i5_4_lut (.A(FS[12]), .B(FS[16]), .C(FS[15]), .D(n4934), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i5_4_lut.init = 16'h8000;
+    LUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_5), .B(n4929), .C(XOR8MEG_N_149), 
+         .D(Din_c_4), .Z(PHI2_N_151_enable_6)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i2_3_lut_4_lut_adj_19.init = 16'h0010;
+    LUT4 i1_2_lut_rep_39 (.A(MAin_c_1), .B(n2384), .Z(n4888)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_2_lut_rep_39.init = 16'hdddd;
+    PFUMX i3833 (.BLUT(n4732), .ALUT(n752), .C0(InitReady), .Z(n4733));
+    LUT4 i1683_1_lut (.A(nRowColSel_N_34), .Z(n2557)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i1683_1_lut.init = 16'h5555;
+    LUT4 i1_2_lut_rep_36_3_lut (.A(MAin_c_1), .B(n2384), .C(MAin_c_0), 
+         .Z(n4885)) /* synthesis lut_function=((B+!(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_2_lut_rep_36_3_lut.init = 16'hdfdf;
+    LUT4 i92_4_lut (.A(n4887), .B(n2199), .C(FS[10]), .D(n4890), .Z(n53)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i92_4_lut.init = 16'hcafa;
+    LUT4 i3812_2_lut (.A(FS[11]), .B(FS[12]), .Z(n4632)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3812_2_lut.init = 16'hbbbb;
+    LUT4 i6_4_lut_adj_20 (.A(FS[10]), .B(n4527), .C(n4924), .D(n4936), 
+         .Z(n14_adj_14)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
+    defparam i6_4_lut_adj_20.init = 16'h0400;
+    LUT4 i4_4_lut (.A(FS[1]), .B(n4902), .C(n4920), .D(n6_adj_12), .Z(n4527)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i4_4_lut.init = 16'h0100;
+    PFUMX i3123 (.BLUT(n4125), .ALUT(n760), .C0(InitReady), .Z(n3989));
+    LUT4 i1_3_lut (.A(FS[0]), .B(FS[2]), .C(FS[3]), .Z(n6_adj_12)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
+    defparam i1_3_lut.init = 16'h4040;
+    LUT4 i1_2_lut_rep_60 (.A(FS[10]), .B(n14), .Z(n4909)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_60.init = 16'heeee;
+    LUT4 nRCS_N_170_I_0_4_lut (.A(nRCS_N_170), .B(n4918), .C(Ready), .D(nRowColSel_N_35), 
+         .Z(nRRAS_N_189)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRCS_N_170_I_0_4_lut.init = 16'h3afa;
+    LUT4 i1_3_lut_adj_21 (.A(n4882), .B(Din_c_5), .C(Din_c_3), .Z(PHI2_N_151_enable_5)) /* synthesis lut_function=(A ((C)+!B)) */ ;
+    defparam i1_3_lut_adj_21.init = 16'ha2a2;
+    LUT4 FS_17__I_0_579_i10_2_lut (.A(FS[12]), .B(FS[13]), .Z(n10_adj_2)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(461[30:46])
+    defparam FS_17__I_0_579_i10_2_lut.init = 16'heeee;
+    LUT4 i3_4_lut_adj_22 (.A(FS[15]), .B(FS[17]), .C(FS[16]), .D(FS[14]), 
+         .Z(n14)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i3_4_lut_adj_22.init = 16'hfffe;
+    LUT4 i1_2_lut_rep_50_3_lut (.A(FS[10]), .B(n14), .C(FS[11]), .Z(n4899)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_50_3_lut.init = 16'hefef;
+    LUT4 i1_2_lut_rep_43_3_lut_4_lut (.A(FS[10]), .B(n14), .C(n4920), 
+         .D(FS[11]), .Z(n4892)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_43_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i3_4_lut_adj_23 (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n4889), 
+         .Z(XOR8MEG_N_149)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_23.init = 16'h0040;
+    LUT4 i3712_2_lut_rep_40 (.A(nFWE_c), .B(n2384), .Z(n4889)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i3712_2_lut_rep_40.init = 16'heeee;
+    LUT4 nRCAS_I_46_4_lut (.A(nRCS_N_175), .B(CBR), .C(nRowColSel_N_35), 
+         .D(RASr2), .Z(nRCAS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7])
+    defparam nRCAS_I_46_4_lut.init = 16'h3afa;
+    LUT4 i66_4_lut (.A(FS[10]), .B(n3609), .C(FS[11]), .D(n2308), .Z(n39)) /* synthesis lut_function=(!(A (C+(D))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i66_4_lut.init = 16'h101a;
+    LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_284), .Z(n6_adj_15)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam i2_2_lut.init = 16'h8888;
+    LUT4 i2_2_lut_4_lut_adj_24 (.A(n4931), .B(Din_c_6), .C(Din_c_2), .D(n4504), 
+         .Z(n6_adj_11)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
+    defparam i2_2_lut_4_lut_adj_24.init = 16'h2000;
+    LUT4 FS_17__I_0_572_i10_2_lut_rep_71 (.A(FS[12]), .B(FS[13]), .Z(n4920)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam FS_17__I_0_572_i10_2_lut_rep_71.init = 16'hdddd;
+    LUT4 i1676_3_lut_4_lut (.A(nFWE_c), .B(n2384), .C(MAin_c_1), .D(C1Submitted), 
+         .Z(n2549)) /* synthesis lut_function=(A (D)+!A (B (D)+!B !(C+!(D)))) */ ;
+    defparam i1676_3_lut_4_lut.init = 16'hef00;
+    LUT4 RA11_I_57_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_217)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(91[22:51])
+    defparam RA11_I_57_3_lut.init = 16'hc6c6;
+    LUT4 i2387_3_lut_4_lut (.A(FS[5]), .B(n4924), .C(FS[11]), .D(n53_adj_9), 
+         .Z(n98)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ;
+    defparam i2387_3_lut_4_lut.init = 16'hfe0e;
+    LUT4 i1_4_lut (.A(FS[2]), .B(n4884), .C(n4886), .D(n4517), .Z(n1)) /* synthesis lut_function=(!((B (C (D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_4_lut.init = 16'h2aaa;
+    LUT4 i2506_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_165)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(19[12:17])
+    defparam i2506_4_lut.init = 16'hcfc8;
+    LUT4 i2801_4_lut (.A(FWEr), .B(n4903), .C(n2040), .D(n4_adj_13), 
+         .Z(n1885)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2801_4_lut.init = 16'h3032;
+    LUT4 i1_2_lut_adj_25 (.A(CASr3), .B(CBR), .Z(n4_adj_13)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(222[16:37])
+    defparam i1_2_lut_adj_25.init = 16'heeee;
+    LUT4 i2_2_lut_3_lut_4_lut_adj_26 (.A(n4898), .B(n4894), .C(n4897), 
+         .D(FS[11]), .Z(n4519)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
+    defparam i2_2_lut_3_lut_4_lut_adj_26.init = 16'h4000;
+    LUT4 n9_bdd_4_lut_3892 (.A(n4895), .B(n4718), .C(FS[10]), .D(FS[12]), 
+         .Z(n4774)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B (C (D)+!C !(D))+!B (C+!(D))))) */ ;
+    defparam n9_bdd_4_lut_3892.init = 16'h05c0;
+    LUT4 i1_4_lut_adj_27 (.A(FS[10]), .B(n646), .C(n4895), .D(FS[11]), 
+         .Z(n42)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_adj_27.init = 16'h0544;
+    LUT4 MAin_9__I_0_565_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
+         .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i3_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
+         .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i4_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
+         .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i5_3_lut.init = 16'hcaca;
+    LUT4 i2319_3_lut_rep_47_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n4938), 
+         .Z(n4896)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2319_3_lut_rep_47_4_lut.init = 16'h808f;
+    LUT4 i24_3_lut_rep_48_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n53_adj_9), 
+         .Z(n4897)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i24_3_lut_rep_48_4_lut.init = 16'h808f;
+    LUT4 i1_3_lut_4_lut_adj_28 (.A(n4927), .B(n4925), .C(FS[10]), .D(FS[12]), 
+         .Z(n175)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i1_3_lut_4_lut_adj_28.init = 16'h0100;
+    LUT4 i1_3_lut_3_lut_4_lut_adj_29 (.A(n4937), .B(n4936), .C(n4938), 
+         .D(FS[9]), .Z(wb_cyc_stb_N_350)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_3_lut_3_lut_4_lut_adj_29.init = 16'h880f;
+    LUT4 i2708_2_lut_rep_41_3_lut_3_lut_4_lut (.A(n4937), .B(n4936), .C(n4915), 
+         .D(FS[9]), .Z(n4890)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2708_2_lut_rep_41_3_lut_3_lut_4_lut.init = 16'h77f0;
+    LUT4 MAin_9__I_0_565_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
+         .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i6_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
+         .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i7_3_lut.init = 16'hcaca;
+    PFUMX i3831 (.BLUT(n4585), .ALUT(n4730), .C0(FS[12]), .Z(n4731));
+    LUT4 MAin_9__I_0_565_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
+         .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i8_3_lut.init = 16'hcaca;
+    CCU2D FS_972_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n4086), 
+          .S1(n95));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_1.INIT0 = 16'hF000;
+    defparam FS_972_add_4_1.INIT1 = 16'h0555;
+    defparam FS_972_add_4_1.INJECT1_0 = "NO";
+    defparam FS_972_add_4_1.INJECT1_1 = "NO";
+    LUT4 MAin_9__I_0_565_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
+         .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i9_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
+         .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i10_3_lut.init = 16'hcaca;
+    LUT4 i2_4_lut_4_lut (.A(FS[6]), .B(n4097), .C(FS[11]), .D(n4905), 
+         .Z(n4530)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2_4_lut_4_lut.init = 16'h0010;
+    CCU2D FS_972_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4087), 
+          .COUT(n4088), .S0(n92), .S1(n91));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_5.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_5.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_5.INJECT1_0 = "NO";
+    defparam FS_972_add_4_5.INJECT1_1 = "NO";
+    LUT4 i1248_4_lut (.A(wb_cyc_stb_N_350), .B(wb_cyc_stb_N_348), .C(n4893), 
+         .D(n4892), .Z(n2104)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[12] 729[6])
+    defparam i1248_4_lut.init = 16'h0aca;
+    LUT4 i2812_2_lut_rep_69 (.A(RCKE_c), .B(RASr2), .Z(n4918)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2812_2_lut_rep_69.init = 16'heeee;
+    LUT4 i1_2_lut_rep_52_4_lut (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), 
+         .D(CmdUFMShift), .Z(n4901)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i1_2_lut_rep_52_4_lut.init = 16'h0800;
+    LUT4 i3810_4_lut (.A(InitReady), .B(n10_adj_2), .C(n4899), .D(n4), 
+         .Z(n4634)) /* synthesis lut_function=(A+!(B+(C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i3810_4_lut.init = 16'habbb;
+    LUT4 i3792_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_134)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(12[15:34])
+    defparam i3792_2_lut.init = 16'hbbbb;
+    LUT4 i2694_2_lut_rep_67 (.A(FWEr), .B(CBR), .Z(n4916)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2694_2_lut_rep_67.init = 16'heeee;
+    LUT4 RASr2_I_0_1_lut_rep_72 (.A(RASr2), .Z(n4921)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46])
+    defparam RASr2_I_0_1_lut_rep_72.init = 16'h5555;
+    LUT4 i2_3_lut_rep_68 (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), .Z(n4917)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i2_3_lut_rep_68.init = 16'h0808;
+    LUT4 i3742_2_lut (.A(nRowColSel_N_33), .B(CASr2), .Z(n4618)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7])
+    defparam i3742_2_lut.init = 16'hbbbb;
+    LUT4 nRWE_I_0_596_4_lut (.A(n3622), .B(nRWE_N_211), .C(Ready), .D(n4906), 
+         .Z(nRWE_N_204)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRWE_I_0_596_4_lut.init = 16'hcfc5;
+    LUT4 i1174_2_lut (.A(FS[9]), .B(n4869), .Z(wb_we_N_351)) /* synthesis lut_function=(!(A (B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1174_2_lut.init = 16'h7777;
+    LUT4 i3224_2_lut (.A(FS[12]), .B(FS[7]), .Z(n4097)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i3224_2_lut.init = 16'h8888;
+    LUT4 i1662_2_lut_4_lut (.A(n4548), .B(n4885), .C(n4911), .D(C1Submitted_N_232), 
+         .Z(CmdEnable_N_243)) /* synthesis lut_function=(A (B (D)+!B (C+(D)))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(301[7:24])
+    defparam i1662_2_lut_4_lut.init = 16'hff20;
+    LUT4 i3754_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n22)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
+    defparam i3754_2_lut_3_lut.init = 16'h1f1f;
+    LUT4 i4_4_lut_adj_30 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), 
+         .D(n6), .Z(RCLK_c_enable_20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i4_4_lut_adj_30.init = 16'hfffe;
+    LUT4 mux_427_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[4]), 
+         .D(wb_adr[5]), .Z(n747)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i6_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_4_lut_4_lut_adj_31 (.A(RASr2), .B(n6_adj_15), .C(nRowColSel_N_32), 
+         .D(Ready), .Z(Ready_N_280)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46])
+    defparam i1_4_lut_4_lut_adj_31.init = 16'hff40;
+    LUT4 InitReady_I_0_586_1_lut_rep_73 (.A(InitReady), .Z(RCLK_c_enable_22)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam InitReady_I_0_586_1_lut_rep_73.init = 16'h5555;
+    LUT4 nRCS_I_0_590_3_lut (.A(nRCS_N_170), .B(nRCS_N_174), .C(Ready), 
+         .Z(nRCS_N_169)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRCS_I_0_590_3_lut.init = 16'hcaca;
+    LUT4 i1390_4_lut_4_lut (.A(InitReady), .B(n2262), .C(FS[4]), .D(CmdUFMData), 
+         .Z(wb_cyc_stb_N_307)) /* synthesis lut_function=(A (D)+!A !((C)+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1390_4_lut_4_lut.init = 16'hae04;
+    LUT4 i2758_2_lut (.A(nRWE_N_210), .B(nRCAS_N_198), .Z(n3622)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2758_2_lut.init = 16'heeee;
+    LUT4 i1_2_lut_4_lut_4_lut_adj_32 (.A(InitReady), .B(PHI2r2), .C(PHI2r3), 
+         .D(CmdSubmitted), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(!(A (B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1_2_lut_4_lut_4_lut_adj_32.init = 16'h7555;
+    LUT4 i1_2_lut_3_lut_adj_33 (.A(n4917), .B(CmdUFMShift), .C(InitReady), 
+         .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B+!(C))+!A !(C)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i1_2_lut_3_lut_adj_33.init = 16'h8f8f;
+    LUT4 mux_427_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[5]), 
+         .D(wb_adr[6]), .Z(n746)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i7_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_4_lut_4_lut_adj_34 (.A(InitReady), .B(n1), .C(CmdUFMShift), 
+         .D(wb_adr_7__N_92), .Z(n1889)) /* synthesis lut_function=(!(A (C+(D))+!A ((D)+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1_4_lut_4_lut_adj_34.init = 16'h004e;
+    PFUMX i36 (.BLUT(n20), .ALUT(n22), .C0(nRowColSel_N_35), .Z(RCKEEN_N_153));
+    LUT4 mux_428_i8_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[6]), 
+         .D(wb_dati[7]), .Z(n754)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i8_3_lut_4_lut.init = 16'hf780;
+    LUT4 MAin_9__I_0_565_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
+         .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i2_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_rep_74 (.A(FS[11]), .B(FS[12]), .Z(n4923)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_74.init = 16'h8888;
+    LUT4 i1185_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n2040)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7])
+    defparam i1185_2_lut.init = 16'heeee;
+    PFUMX i3897 (.BLUT(n4850), .ALUT(n747), .C0(InitReady), .Z(wb_adr_7__N_60[5]));
+    LUT4 i2685_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n1965)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2685_2_lut.init = 16'heeee;
+    LUT4 i1_2_lut_rep_55_3_lut (.A(FS[11]), .B(FS[12]), .C(FS[10]), .Z(n4904)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_55_3_lut.init = 16'h0808;
+    LUT4 nRWE_I_53_1_lut (.A(nRWE_N_210), .Z(nRWE_N_209)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(247[14] 254[8])
+    defparam nRWE_I_53_1_lut.init = 16'h5555;
+    LUT4 i1_2_lut_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), 
+         .Z(n4164)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_3_lut_4_lut.init = 16'hfbff;
+    LUT4 i1_2_lut_rep_46_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(n4927), 
+         .D(FS[5]), .Z(n4895)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
+    defparam i1_2_lut_rep_46_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i3789_3_lut_4_lut_4_lut (.A(n4890), .B(n4859), .C(FS[10]), .D(n4896), 
+         .Z(n56)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (B+(C))) */ ;
+    defparam i3789_3_lut_4_lut_4_lut.init = 16'hfc5c;
+    LUT4 n4580_bdd_4_lut (.A(nFWE_c), .B(MAin_c_1), .C(MAin_c_7), .D(Bank[2]), 
+         .Z(n4782)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam n4580_bdd_4_lut.init = 16'h0040;
+    LUT4 i2832_2_lut_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(FS[6]), .D(FS[5]), 
+         .Z(n3609)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
+    defparam i2832_2_lut_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i2_3_lut_4_lut_adj_35 (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), 
+         .Z(n2308)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2_3_lut_4_lut_adj_35.init = 16'hfffb;
+    LUT4 i1_2_lut_rep_75 (.A(FS[6]), .B(FS[8]), .Z(n4924)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_75.init = 16'heeee;
+    LUT4 i3_4_lut_adj_36 (.A(CASr2), .B(FWEr), .C(CBR), .D(CASr3), .Z(nRCS_N_179)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
+    defparam i3_4_lut_adj_36.init = 16'h0008;
+    LUT4 i1_2_lut_3_lut_4_lut_adj_37 (.A(FS[6]), .B(FS[8]), .C(n4928), 
+         .D(FS[7]), .Z(n646)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
+    defparam i1_2_lut_3_lut_4_lut_adj_37.init = 16'h0010;
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    LUT4 i1_2_lut_rep_61_3_lut (.A(FS[6]), .B(FS[8]), .C(FS[7]), .Z(n4910)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
+    defparam i1_2_lut_rep_61_3_lut.init = 16'h1010;
+    LUT4 mux_428_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[4]), 
+         .D(wb_dati[5]), .Z(n756)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i6_3_lut_4_lut.init = 16'hf780;
+    TSALL TSALL_INST (.TSALL(GND_net));
+    LUT4 i1667_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[1]), 
+         .D(CmdLEDEN), .Z(LEDEN_N_110)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ;
+    defparam i1667_3_lut_4_lut.init = 16'hfe10;
+    LUT4 mux_428_i3_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[1]), 
+         .D(wb_dati[2]), .Z(n759)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i3_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_2_lut_rep_76 (.A(FS[9]), .B(FS[8]), .Z(n4925)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_76.init = 16'heeee;
+    LUT4 i1_3_lut_4_lut_adj_38 (.A(n4893), .B(n4892), .C(InitReady), .D(n4917), 
+         .Z(n4513)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
+    defparam i1_3_lut_4_lut_adj_38.init = 16'hf800;
+    LUT4 i1_2_lut_rep_56_3_lut (.A(FS[9]), .B(FS[8]), .C(FS[5]), .Z(n4905)) /* synthesis lut_function=(A+(B+!(C))) */ ;
+    defparam i1_2_lut_rep_56_3_lut.init = 16'hefef;
+    LUT4 i36_4_lut (.A(n5142), .B(n754), .C(InitReady), .D(n17), .Z(wb_dati_7__N_68[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i36_4_lut.init = 16'hcfca;
+    LUT4 mux_428_i4_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[2]), 
+         .D(wb_dati[3]), .Z(n758)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i4_3_lut_4_lut.init = 16'hf780;
+    LUT4 i2696_4_lut (.A(nRCS_N_179), .B(nRowColSel_N_34), .C(n4916), 
+         .D(nRowColSel_N_33), .Z(nRCS_N_175)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7])
+    defparam i2696_4_lut.init = 16'hfcdd;
+    LUT4 InitReady_I_0_3_lut (.A(InitReady), .B(RCKEEN_N_153), .C(Ready), 
+         .Z(RCKEEN_N_152)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam InitReady_I_0_3_lut.init = 16'hcaca;
+    LUT4 i2726_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n1286)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i2726_2_lut.init = 16'heeee;
+    LUT4 i3795_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i3795_2_lut.init = 16'h7777;
+    LUT4 i95_4_lut (.A(n4894), .B(FS[10]), .C(FS[12]), .D(n4900), .Z(n3711)) /* synthesis lut_function=(A (B (C+(D))+!B ((D)+!C))+!A (B (C+(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i95_4_lut.init = 16'hfec2;
+    LUT4 i2684_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(57[17:46])
+    defparam i2684_2_lut.init = 16'hbbbb;
+    LUT4 mux_428_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[0]), 
+         .D(wb_dati[1]), .Z(n760)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i2_3_lut_4_lut.init = 16'hf780;
+    LUT4 i2_3_lut_4_lut_adj_39 (.A(FS[9]), .B(FS[8]), .C(FS[7]), .D(n4939), 
+         .Z(n4149)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
+    defparam i2_3_lut_4_lut_adj_39.init = 16'hffef;
+    LUT4 mux_428_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[5]), 
+         .D(wb_dati[6]), .Z(n755)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i7_3_lut_4_lut.init = 16'hf780;
+    LUT4 mux_428_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[3]), 
+         .D(wb_dati[4]), .Z(n757)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i5_3_lut_4_lut.init = 16'hf780;
+    LUT4 mux_427_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[0]), 
+         .D(wb_adr[1]), .Z(n751)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i2_3_lut_4_lut.init = 16'hf780;
+    LUT4 MAin_9__I_0_565_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
+         .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i1_3_lut.init = 16'hcaca;
+    LUT4 mux_428_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_we), 
+         .D(wb_dati[0]), .Z(n761)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i1_3_lut_4_lut.init = 16'hf780;
+    INV i4008 (.A(PHI2_c), .Z(PHI2_N_151));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    INV i4007 (.A(nCRAS_c), .Z(nCRAS_N_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    PFUMX i3913 (.BLUT(n4940), .ALUT(n4941), .C0(FS[9]), .Z(wb_we_N_354));
+    VLO i1 (.Z(GND_net));
+    
+endmodule
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log
new file mode 100644
index 0000000..aef4f04
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log
@@ -0,0 +1,1344 @@
+
+map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial   "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf"  -c 0           
+map:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+   Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
+   Picdevice="LCMXO2-640HC"
+
+   Pictype="TQFP100"
+
+   Picspeed=4
+
+   Remove unused logic
+
+   Do not produce over sized NCDs.
+
+Part used: LCMXO2-640HCTQFP100, Performance used: 4.
+
+Loading device for application baspr from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+
+Running general design DRC...
+
+Removing unused logic...
+
+Optimizing...
+
+
+
+
+Design Summary:
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+ 
+
+   Number of warnings:  0
+   Number of errors:    0
+
+
+
+Total CPU Time: 0 secs  
+Total REAL Time: 0 secs  
+Peak Memory Usage: 36 MB
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+
+ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb"
+
+Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+
+trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+trce:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 40 MB
+
+
+mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
+
+---- MParTrce Tool ----
+Removing old design directory at request of -rem command line option to this program.
+Running par. Please wait . . .
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+    
+    
+    
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+    
+    
+    
+
+    
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+    
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Exiting par with exit code 0
+Exiting mpartrce with exit code 0
+
+trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+trce:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 40 MB
+
+
+iotiming  "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+I/O Timing Report:
+:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 4
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 5
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 6
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: M
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+Done.
+
+ibisgen "RAM2GS_LCMXO2_640HC_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo2.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Tue Aug 17 06:21:03 2021
+
+Comp: CROW[0]
+ Site: 10
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: CROW[1]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[0]
+ Site: 3
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[1]
+ Site: 96
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[2]
+ Site: 88
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[3]
+ Site: 97
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[4]
+ Site: 99
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[5]
+ Site: 98
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[6]
+ Site: 2
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[7]
+ Site: 1
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Dout[0]
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 86
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 84
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 34
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[1]
+ Site: 12
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[2]
+ Site: 13
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[3]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[4]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[5]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[6]
+ Site: 24
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[7]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[8]
+ Site: 25
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[9]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: PHI2
+ Site: 8
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: RA[0]
+ Site: 66
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 64
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 59
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 67
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 69
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 71
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 74
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 70
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 68
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 75
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 65
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 62
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 60
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 63
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: RDQMH
+ Site: 51
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 48
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 36
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[1]
+ Site: 37
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[2]
+ Site: 38
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[3]
+ Site: 39
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[4]
+ Site: 40
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[5]
+ Site: 41
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[6]
+ Site: 42
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[7]
+ Site: 43
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: nCCAS
+ Site: 9
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nCRAS
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nFWE
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nRCAS
+ Site: 52
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 54
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 49
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO2\LCMXO2-640HC\impl1\IBIS\RAM2GS_LCMXO2_640HC~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" 
+
+bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd"  "RAM2GS_LCMXO2_640HC_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.bit".
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" 
+
+bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd"  -jedec "RAM2GS_LCMXO2_640HC_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..ad12f66
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,12 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,1-731,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
+WARNING - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-2435) port 'PLL0DATI7' is not connected on this instance
+WARNING - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-1927) port 'WBDATO7' remains unconnected for this instance
+Done: design load finished with (0) errors, and (2) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
new file mode 100644
index 0000000..6529f93
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
@@ -0,0 +1,133 @@
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Tue Aug 17 06:21:03 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.195      M       1.729     4
+CROW[1] nCRAS F    -0.218      M       1.801     4
+Din[0]  PHI2  F     6.339      4       1.186     4
+Din[0]  nCCAS F     1.641      4       0.107     M
+Din[1]  PHI2  F     6.084      4       1.570     4
+Din[1]  nCCAS F     0.198      4       1.314     4
+Din[2]  PHI2  F     3.778      4       1.771     4
+Din[2]  nCCAS F     0.075      4       1.431     4
+Din[3]  PHI2  F     4.331      4       1.705     4
+Din[3]  nCCAS F    -0.116      M       1.722     4
+Din[4]  PHI2  F     6.176      4       1.711     4
+Din[4]  nCCAS F     1.065      4       0.575     4
+Din[5]  PHI2  F     4.684      4       1.261     4
+Din[5]  nCCAS F    -0.081      M       1.625     4
+Din[6]  PHI2  F     5.243      4       0.356     4
+Din[6]  nCCAS F     1.414      4       0.309     4
+Din[7]  PHI2  F     6.602      4       1.175     4
+Din[7]  nCCAS F    -0.286      M       2.137     4
+MAin[0] PHI2  F     5.034      4       0.629     4
+MAin[0] nCRAS F     1.094      4       0.380     4
+MAin[1] PHI2  F     6.081      4       1.157     4
+MAin[1] nCRAS F     0.544      4       0.877     4
+MAin[2] PHI2  F     9.979      4      -0.319     M
+MAin[2] nCRAS F    -0.050      M       1.401     4
+MAin[3] PHI2  F     9.162      4      -0.219     M
+MAin[3] nCRAS F     1.032      4       0.440     4
+MAin[4] PHI2  F    11.678      4      -0.770     M
+MAin[4] nCRAS F    -0.150      M       1.620     4
+MAin[5] PHI2  F     8.668      4      -0.081     M
+MAin[5] nCRAS F    -0.050      M       1.401     4
+MAin[6] PHI2  F     8.516      4      -0.025     M
+MAin[6] nCRAS F     1.003      4       0.478     4
+MAin[7] PHI2  F     9.320      4      -0.061     M
+MAin[7] nCRAS F     1.001      4       0.478     4
+MAin[8] nCRAS F    -0.146      M       1.657     4
+MAin[9] nCRAS F    -0.360      M       2.140     4
+PHI2    RCLK  R     3.079      4      -0.602     M
+nCCAS   RCLK  R     3.574      4      -0.705     M
+nCCAS   nCRAS F     3.232      4      -0.351     M
+nCRAS   RCLK  R     2.757      4      -0.470     M
+nFWE    PHI2  F     5.913      4       0.723     4
+nFWE    nCRAS F     0.547      4       0.890     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    10.062         4        3.164          M
+RA[0]  RCLK  R    10.645         4        3.471          M
+RA[0]  nCRAS F    11.744         4        3.770          M
+RA[10] RCLK  R     9.485         4        3.236          M
+RA[11] PHI2  R    11.513         4        3.824          M
+RA[1]  RCLK  R    10.921         4        3.549          M
+RA[1]  nCRAS F    12.664         4        4.036          M
+RA[2]  RCLK  R    10.923         4        3.527          M
+RA[2]  nCRAS F    12.463         4        3.984          M
+RA[3]  RCLK  R    11.178         4        3.615          M
+RA[3]  nCRAS F    12.304         4        3.917          M
+RA[4]  RCLK  R    11.365         4        3.630          M
+RA[4]  nCRAS F    13.243         4        4.179          M
+RA[5]  RCLK  R    11.365         4        3.630          M
+RA[5]  nCRAS F    12.940         4        4.098          M
+RA[6]  RCLK  R    11.099         4        3.573          M
+RA[6]  nCRAS F    12.162         4        3.870          M
+RA[7]  RCLK  R    10.948         4        3.552          M
+RA[7]  nCRAS F    12.282         4        3.936          M
+RA[8]  RCLK  R    11.114         4        3.608          M
+RA[8]  nCRAS F    12.909         4        4.116          M
+RA[9]  RCLK  R    11.005         4        3.561          M
+RA[9]  nCRAS F    12.959         4        4.081          M
+RBA[0] nCRAS F    11.842         4        3.911          M
+RBA[1] nCRAS F    11.343         4        3.771          M
+RCKE   RCLK  R     9.884         4        3.362          M
+RDQMH  RCLK  R    10.941         4        3.559          M
+RDQML  RCLK  R    10.641         4        3.470          M
+RD[0]  nCCAS F    12.628         4        4.413          M
+RD[1]  nCCAS F    12.231         4        4.302          M
+RD[2]  nCCAS F    12.231         4        4.302          M
+RD[3]  nCCAS F    11.928         4        4.221          M
+RD[4]  nCCAS F    12.427         4        4.361          M
+RD[5]  nCCAS F    12.697         4        4.400          M
+RD[6]  nCCAS F    12.427         4        4.361          M
+RD[7]  nCCAS F    12.427         4        4.361          M
+nRCAS  RCLK  R     9.674         4        3.300          M
+nRCS   RCLK  R     9.674         4        3.300          M
+nRRAS  RCLK  R     9.797         4        3.322          M
+nRWE   RCLK  R     9.275         4        3.194          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
new file mode 100644
index 0000000..0409f06
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 25.800 ns (350.000 ns);
+Period_1 = 2.500 ns (350.000 ns);
+Period_2 = 2.500 ns (350.000 ns);
+Period_3 = 12.427 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 9.485 ns (12.500 ns);
+Tco_17 = 11.005 ns (12.500 ns);
+Tco_18 = 11.114 ns (12.500 ns);
+Tco_19 = 10.948 ns (12.500 ns);
+Tco_20 = 11.099 ns (12.500 ns);
+Tco_21 = 11.365 ns (12.500 ns);
+Tco_22 = 11.365 ns (12.500 ns);
+Tco_23 = 11.178 ns (12.500 ns);
+Tco_24 = 10.923 ns (12.500 ns);
+Tco_25 = 10.921 ns (12.500 ns);
+Tco_26 = 10.645 ns (12.500 ns);
+Tco_27 = 9.674 ns (12.500 ns);
+Tco_28 = 9.884 ns (12.500 ns);
+Tco_29 = 9.275 ns (12.500 ns);
+Tco_30 = 9.797 ns (12.500 ns);
+Tco_31 = 9.674 ns (12.500 ns);
+Tco_32 = 10.941 ns (12.500 ns);
+Tco_33 = 10.641 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 5;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 3.236 ns (0.000 ns);
+Tco_17 = 3.561 ns (0.000 ns);
+Tco_18 = 3.608 ns (0.000 ns);
+Tco_19 = 3.552 ns (0.000 ns);
+Tco_20 = 3.573 ns (0.000 ns);
+Tco_21 = 3.630 ns (0.000 ns);
+Tco_22 = 3.630 ns (0.000 ns);
+Tco_23 = 3.615 ns (0.000 ns);
+Tco_24 = 3.527 ns (0.000 ns);
+Tco_25 = 3.549 ns (0.000 ns);
+Tco_26 = 3.471 ns (0.000 ns);
+Tco_27 = 3.300 ns (0.000 ns);
+Tco_28 = 3.362 ns (0.000 ns);
+Tco_29 = 3.194 ns (0.000 ns);
+Tco_30 = 3.322 ns (0.000 ns);
+Tco_31 = 3.300 ns (0.000 ns);
+Tco_32 = 3.559 ns (0.000 ns);
+Tco_33 = 3.470 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 5;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
new file mode 100644
index 0000000..7c23447
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
@@ -0,0 +1,271 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:19:45 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
+INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+######## Missing driver on net n1128. Patching with GND.
+######## Missing driver on net n1132. Patching with GND.
+######## Missing driver on net n1133. Patching with GND.
+######## Missing driver on net n1134. Patching with GND.
+######## Missing driver on net n1135. Patching with GND.
+######## Missing driver on net n1131. Patching with GND.
+######## Missing driver on net n1130. Patching with GND.
+######## Missing driver on net n1136. Patching with GND.
+######## Missing driver on net n1137. Patching with GND.
+######## Missing driver on net n1138. Patching with GND.
+######## Missing driver on net n1139. Patching with GND.
+######## Missing driver on net n1140. Patching with GND.
+######## Missing driver on net n1141. Patching with GND.
+######## Missing driver on net n1142. Patching with GND.
+######## Missing driver on net n1143. Patching with GND.
+######## Missing driver on net n1144. Patching with GND.
+######## Missing driver on net n1145. Patching with GND.
+######## Missing driver on net n1146. Patching with GND.
+######## Missing driver on net n1147. Patching with GND.
+######## Missing driver on net n1148. Patching with GND.
+######## Missing driver on net n1129. Patching with GND.
+######## Missing driver on net n1149. Patching with GND.
+######## Missing driver on net n1150. Patching with GND.
+######## Missing driver on net n1151. Patching with GND.
+######## Missing driver on net n1152. Patching with GND.
+######## Missing driver on net n1153. Patching with GND.
+######## Missing driver on net n1154. Patching with GND.
+######## Missing driver on net n1155. Patching with GND.
+######## Missing driver on net n1156. Patching with GND.
+######## Missing driver on net n1157. Patching with GND.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 119 of 877 (13 % )
+BB => 8
+CCU2D => 10
+EFB => 1
+FD1P3AX => 30
+FD1P3AY => 4
+FD1P3IX => 3
+FD1S3AX => 64
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 25
+INV => 3
+LUT4 => 236
+OB => 30
+PFUMX => 16
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 5
+  Net : RCLK_c, loads : 79
+  Net : PHI2_c, loads : 11
+  Net : nCRAS_c, loads : 2
+  Net : nCCAS_c, loads : 2
+  Net : wb_clk, loads : 1
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_20, loads : 4
+  Net : RCLK_c_enable_25, loads : 2
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_29, loads : 2
+  Net : PHI2_N_151_enable_5, loads : 2
+  Net : PHI2_N_151_enable_3, loads : 2
+  Net : PHI2_N_151_enable_1, loads : 1
+  Net : Ready_N_280, loads : 1
+  Net : PHI2_N_151_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 36
+  Net : FS_11, loads : 32
+  Net : FS_10, loads : 32
+  Net : FS_9, loads : 26
+  Net : FS_7, loads : 25
+  Net : FS_8, loads : 23
+  Net : FS_6, loads : 21
+  Net : FS_5, loads : 21
+  Net : FS_12, loads : 20
+  Net : CmdUFMShift, loads : 16
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |  200.000 MHz|   38.150 MHz|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   65.694 MHz|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 57.273  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.952  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
new file mode 100644
index 0000000..14e4497
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
@@ -0,0 +1,336 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:19:45 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
+INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+######## Missing driver on net n1128. Patching with GND.
+######## Missing driver on net n1132. Patching with GND.
+######## Missing driver on net n1133. Patching with GND.
+######## Missing driver on net n1134. Patching with GND.
+######## Missing driver on net n1135. Patching with GND.
+######## Missing driver on net n1131. Patching with GND.
+######## Missing driver on net n1130. Patching with GND.
+######## Missing driver on net n1136. Patching with GND.
+######## Missing driver on net n1137. Patching with GND.
+######## Missing driver on net n1138. Patching with GND.
+######## Missing driver on net n1139. Patching with GND.
+######## Missing driver on net n1140. Patching with GND.
+######## Missing driver on net n1141. Patching with GND.
+######## Missing driver on net n1142. Patching with GND.
+######## Missing driver on net n1143. Patching with GND.
+######## Missing driver on net n1144. Patching with GND.
+######## Missing driver on net n1145. Patching with GND.
+######## Missing driver on net n1146. Patching with GND.
+######## Missing driver on net n1147. Patching with GND.
+######## Missing driver on net n1148. Patching with GND.
+######## Missing driver on net n1129. Patching with GND.
+######## Missing driver on net n1149. Patching with GND.
+######## Missing driver on net n1150. Patching with GND.
+######## Missing driver on net n1151. Patching with GND.
+######## Missing driver on net n1152. Patching with GND.
+######## Missing driver on net n1153. Patching with GND.
+######## Missing driver on net n1154. Patching with GND.
+######## Missing driver on net n1155. Patching with GND.
+######## Missing driver on net n1156. Patching with GND.
+######## Missing driver on net n1157. Patching with GND.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 119 of 877 (13 % )
+BB => 8
+CCU2D => 10
+EFB => 1
+FD1P3AX => 30
+FD1P3AY => 4
+FD1P3IX => 3
+FD1S3AX => 64
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 25
+INV => 3
+LUT4 => 236
+OB => 30
+PFUMX => 16
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 5
+  Net : RCLK_c, loads : 79
+  Net : PHI2_c, loads : 11
+  Net : nCRAS_c, loads : 2
+  Net : nCCAS_c, loads : 2
+  Net : wb_clk, loads : 1
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_20, loads : 4
+  Net : RCLK_c_enable_25, loads : 2
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_29, loads : 2
+  Net : PHI2_N_151_enable_5, loads : 2
+  Net : PHI2_N_151_enable_3, loads : 2
+  Net : PHI2_N_151_enable_1, loads : 1
+  Net : Ready_N_280, loads : 1
+  Net : PHI2_N_151_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 36
+  Net : FS_11, loads : 32
+  Net : FS_10, loads : 32
+  Net : FS_9, loads : 26
+  Net : FS_7, loads : 25
+  Net : FS_8, loads : 23
+  Net : FS_6, loads : 21
+  Net : FS_5, loads : 21
+  Net : FS_12, loads : 20
+  Net : CmdUFMShift, loads : 16
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |  200.000 MHz|   38.150 MHz|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   65.694 MHz|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 57.273  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.952  secs
+--------------------------------------------------------------
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..b0c79e4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,350 @@
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file
new file mode 100644
index 0000000..ca7af8d
--- /dev/null
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log b/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log
new file mode 100644
index 0000000..e93ec92
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 05:48:29 2021
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : EFB
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+    Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
+    Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
+    I/O buffer       : not inserted
+    EDIF output      : EFB.edn
+    Verilog output   : EFB.v
+    Verilog template : EFB_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : EFB.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/CPLD/LCMXO2/RAM2GS-LCMXO2.v b/CPLD/LCMXO2/RAM2GS-LCMXO2.v
new file mode 100644
index 0000000..48ace8c
--- /dev/null
+++ b/CPLD/LCMXO2/RAM2GS-LCMXO2.v
@@ -0,0 +1,731 @@
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
+			  nCCAS, nCRAS, nFWE, LED,
+			  RBA, RA, RD, nRCS, RCLK, RCKE,
+			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+
+	/* 65816 Phase 2 Clock */
+	input PHI2;
+
+	/* Activity LED */
+	reg LEDEN = 0;
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
+
+	/* Async. DRAM Control Inputs */
+	input nCCAS, nCRAS;
+
+	/* Synchronized PHI2 and DRAM signals */
+	reg PHI2r, PHI2r2, PHI2r3;
+	reg RASr, RASr2, RASr3;
+	reg CASr, CASr2, CASr3;
+	reg FWEr;
+	reg CBR;
+
+	/* 65816 Data */
+	input [7:0] Din;
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
+
+	/* Latched 65816 Bank Address */
+	reg [7:0] Bank;
+
+	/* Async. DRAM Address Bus */
+	input [1:0] CROW;
+	input [9:0] MAin;
+	input nFWE;
+	reg n8MEGEN = 0;
+	reg XOR8MEG = 0;
+	
+	/* SDRAM Clock */
+	input RCLK;
+	
+	/* SDRAM */
+	reg RCKEEN;
+	output reg RCKE = 0;
+	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+	output reg [1:0] RBA;
+	reg nRowColSel;
+	reg RA11;
+	reg RA10;
+	reg [9:0] RowA;
+	output [11:0] RA;
+	assign RA[11] = RA11;
+	assign RA[10] = RA10;
+	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+	reg [7:0] WRD;
+	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+
+	/* UFM Command Interface */
+	reg C1Submitted = 0;
+	reg ADSubmitted = 0;
+	reg CmdEnable = 0;
+	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
+	reg Cmdn8MEGEN = 0;
+	reg CmdUFMData = 0;
+	reg CmdUFMShift = 0;
+	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+	
+	/* State Counters */
+	reg InitReady = 0; // 1 if ready for init sequence
+	reg Ready = 0; // 1 if done with init sequence
+	reg [1:0] S = 0; // post-RAS State counter
+	reg [17:0] FS = 0; // Fast init state counter
+	reg [3:0] IS = 0; // Init state counter
+	reg WriteDone;
+	
+	/* Synchronize PHI2, RAS, CAS */
+	always @(posedge RCLK) begin
+		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+	end
+	
+	/* Latch 65816 bank when PHI2 rises */
+	always @(posedge PHI2) begin
+		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+		else RA11 <= 1'b0; // Reserved in mode register
+		Bank[7:0] <= Din[7:0]; // Latch bank
+	end
+	
+	/* Latch bank address, row address, WE, and CAS when RAS falls */
+	always @(negedge nCRAS) begin
+		if (Ready) begin
+			RBA[1:0] <= CROW[1:0];
+			RowA[9:0] <= MAin[9:0];
+		end else begin
+			RBA[1:0] <= 2'b00;		// Reserved in mode register
+			RowA[9] <= 1'b1;		// "1" for single write mode
+			RowA[8] <= 1'b0;		// Reserved
+			RowA[7] <= 1'b0;		// "0" for not test mode
+			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
+			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
+			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
+		end
+		FWEr <= ~nFWE;
+		CBR <= ~nCCAS;
+	end
+
+	/* Latch write data when CAS falls */
+	always @(negedge nCCAS) begin
+		WRD[7:0] <= Din[7:0];
+	end
+
+	/* State counter from RAS */
+	always @(posedge RCLK) begin
+		if (~RASr2) S <= 0;
+		else if (S==2'h3) S <= 2'h3;
+		else S <= S+1;
+	end
+	/* Init state counter */
+	always @(posedge RCLK) begin
+		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+		FS <= FS+1;
+		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+	end
+
+	/* SDRAM CKE */
+	always @(posedge RCLK) begin
+		// Only 1 LUT4 allowed for this function!
+		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+	end
+
+	/* SDRAM command */
+	always @(posedge RCLK) begin
+		if (Ready) begin
+			if (S==0) begin
+				if (RASr2) begin
+					if (CBR) begin
+						// AREF
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b0;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // RA10 is don't care
+					end else begin
+						// ACT
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b1;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // Bank RA10 consistently "1"
+					end
+					// Enable clock only for reads
+					RCKEEN <= ~CBR & ~FWEr;
+				end else if (RCKE) begin
+					// PCall
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+					RCKEEN <= 1'b1;
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+					RCKEEN <= 1'b1;
+				end
+				nRowColSel <= 1'b0; // Select registered row addres
+			end else if (S==1) begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR; // Disable clock if refresh cycle
+			end else if (S==2) begin
+				if (~FWEr & ~CBR) begin
+					// RD
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+			end else if (S==3) begin
+				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+					// WR
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= ~(~FWEr | CASr3 | CBR);
+				RCKEEN <= ~(~FWEr | CASr2 | CBR);
+			end
+		end else if (InitReady) begin
+			if (S==0 & RASr2) begin
+				if (IS==0) begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end else if (IS==1) begin
+					// PC all
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+				end else if (IS==9) begin
+					// Load mode register
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b0; // Reserved in mode register
+				end else begin
+					// AREF
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				IS <= IS+1;
+			end else begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+			end
+			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b1;
+		end else begin
+			// NOP
+			nRCS <= 1'b1;
+			nRRAS <= 1'b1;
+			nRCAS <= 1'b1;
+			nRWE <= 1'b1;
+			RA10 <= 1'b1; // RA10 is don't care
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b0;
+		end
+	end
+	
+	/* Submit command when PHI2 falls */
+	always @(negedge PHI2) begin
+		// Magic number check
+		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+			if (ADSubmitted) begin
+				CmdEnable <= 1'b1;
+			end
+			C1Submitted <= 1'b1;
+			ADSubmitted <= 1'b0;
+		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+			if (C1Submitted) begin
+				CmdEnable <= 1'b1;
+			end
+			ADSubmitted <= 1'b1;
+			C1Submitted <= 1'b0;
+		end else if (C1WR | ADWR) begin // wrong magic number submitted
+			CmdEnable <= 1'b0;
+			C1Submitted <= 1'b0;
+			ADSubmitted <= 1'b0;
+		end else if (CMDWR) CmdEnable <= 1'b0;
+
+		// Submit command
+		if (CMDWR & CmdEnable) begin
+			if (Din[7:4]==4'h0) begin
+				XOR8MEG <= Din[0];
+			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
+				Cmdn8MEGEN <= ~Din[0];
+			end else if (Din[7:4]==4'h3 && Din[3]) begin
+				CmdLEDEN <= LEDEN;
+				Cmdn8MEGEN <= n8MEGEN;
+				CmdUFMShift <= Din[1];
+				CmdUFMData <= Din[0];
+			end
+			CmdSubmitted <= 1;
+		end else CmdSubmitted <= 0;
+	end
+	
+	reg wb_clk;
+	reg wb_rst;
+	reg wb_cyc_stb;
+	reg wb_we;
+	reg [7:0] wb_adr;
+	reg [7:0] wb_dati;
+	wire [1:0] wb_dato;
+	
+	EFB ufmefb (
+		.WBCLKI(wb_clk),
+		.WBRSTI(wb_rst),
+		.WBCYCI(wb_cyc_stb),
+		.WBSTBI(wb_cyc_stb), 
+		.WBWEI(wb_we),
+		.WBADRI7(wb_adr[7]),
+		.WBADRI6(wb_adr[6]),
+		.WBADRI5(wb_adr[5]),
+		.WBADRI4(wb_adr[4]),
+		.WBADRI3(wb_adr[3]),
+		.WBADRI2(wb_adr[2]),
+		.WBADRI1(wb_adr[1]),
+		.WBADRI0(wb_adr[0]),
+		.WBDATI7(wb_dati[7]),
+		.WBDATI6(wb_dati[6]),
+		.WBDATI5(wb_dati[5]),
+		.WBDATI4(wb_dati[4]),
+		.WBDATI3(wb_dati[3]),
+		.WBDATI2(wb_dati[2]),
+		.WBDATI1(wb_dati[1]),
+		.WBDATI0(wb_dati[0]),
+		.WBDATO1(wb_dato[1]),
+		.WBDATO0(wb_dato[0]));
+
+	/* UFM Control */
+	always @(posedge RCLK) begin
+		if (~InitReady && FS[17:10]==8'h00) begin
+			wb_clk <= 1'b0;
+			wb_rst <= ~FS[9];
+			wb_cyc_stb <= 1'b0;
+			wb_we <= 1'b0;
+			wb_adr[7:0] <= 8'h00;
+			wb_dati[7:0] <= 8'h00;
+		end else if (~InitReady && FS[17:10]==8'h01) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Enable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h74;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Enable configuration interface - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h08;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Enable configuration interface - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Enable configuration interface - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h02) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Poll status register - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h3C;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Poll status register - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Poll status register - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Poll status register - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Read status register 1/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h3C;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h06: begin // Read status register 2/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Read status register 3/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Read status register 4/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h03) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Set UFM address - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hB4;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Set UFM address - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Set UFM address - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Set UFM address - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Set UFM address - data 1/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h40;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h06: begin // Set UFM address - data 2/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Set UFM address - data 3/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Set UFM address - data 4/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h01;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h04) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Read UFM page - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hCA;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Read UFM page - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h10;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Read UFM page - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Read UFM page - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h01;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Read UFM page - data 1/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+					
+					if (FS[4:0]==5'h0C) begin
+						LEDEN <= wb_dato[1];
+						n8MEGEN <= wb_dato[0];
+					end
+				end 5'h06: begin // Read UFM page - data 2/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Read UFM page - data 3/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Read UFM page - data 4/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h09: begin // Read UFM page - data 5/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0A: begin // Read UFM page - data 6/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0B: begin // Read UFM page - data 7/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0C: begin // Read UFM page - data 8/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0D: begin // Read UFM page - data 9/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0E: begin // Read UFM page - data 10/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0F: begin // Read UFM page - data 11/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h10: begin // Read UFM page - data 12/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h11: begin // Read UFM page - data 13/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h12: begin // Read UFM page - data 14/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h13: begin // Read UFM page - data 15/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h14: begin // Read UFM page - data 16/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h05) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Disable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h26;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Disable configuration interface - operand 1/2
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Disable configuration interface - operand 2/2
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h06) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Disable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hFF;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady) begin
+			wb_clk <= 1'b0;
+			wb_rst <= 1'b0;
+			wb_cyc_stb <= 1'b0;
+			wb_we <= 1'b0;
+			wb_adr[7:0] <= 8'h00;
+			wb_dati[7:0] <= 8'h00;
+		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+			// Set user command signals after PHI2 falls
+			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMShift, CmdUFMData
+			LEDEN <= CmdLEDEN;
+			n8MEGEN <= Cmdn8MEGEN;
+			if (CmdUFMShift) begin
+				wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
+				wb_dati[7:0] <= { wb_dati[6:0], wb_we };
+				wb_we <= wb_cyc_stb;
+				wb_cyc_stb <= CmdUFMData;
+				wb_clk <= 1'b0;
+			end else wb_clk <= 1'b1;
+		end
+	end
+endmodule
diff --git a/CPLD/AGM-src/RAM4GS.qpf b/CPLD/MAX/MAXII/RAM2GS-MAXII.qpf
old mode 100755
new mode 100644
similarity index 84%
rename from CPLD/AGM-src/RAM4GS.qpf
rename to CPLD/MAX/MAXII/RAM2GS-MAXII.qpf
index aceec8c..74f038f
--- a/CPLD/AGM-src/RAM4GS.qpf
+++ b/CPLD/MAX/MAXII/RAM2GS-MAXII.qpf
@@ -16,15 +16,15 @@
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 21:16:34  March 08, 2020
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 18:32:31  August 16, 2021
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "13.0"
-DATE = "21:16:34  March 08, 2020"
+DATE = "18:32:31  August 16, 2021"
 
 # Revisions
 
-PROJECT_REVISION = "RAM4GS"
+PROJECT_REVISION = "RAM2GS"
diff --git a/CPLD/MAXII/RAM4GS.qsf b/CPLD/MAX/MAXII/RAM2GS.qsf
old mode 100755
new mode 100644
similarity index 97%
rename from CPLD/MAXII/RAM4GS.qsf
rename to CPLD/MAX/MAXII/RAM2GS.qsf
index ed8578e..5aa99ad
--- a/CPLD/MAXII/RAM4GS.qsf
+++ b/CPLD/MAX/MAXII/RAM2GS.qsf
@@ -38,12 +38,10 @@
 
 set_global_assignment -name FAMILY "MAX II"
 set_global_assignment -name DEVICE EPM240T100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
+set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34  MARCH 08, 2020"
 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name SDC_FILE constraints.sdc
-set_global_assignment -name VERILOG_FILE RAM4GS.v
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -174,7 +172,6 @@ set_location_assignment PIN_95 -to RD[6]
 set_location_assignment PIN_97 -to RD[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
 
-set_global_assignment -name MIF_FILE RAM4GS.mif
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
 set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
@@ -210,4 +207,6 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
 set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
+set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
+set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif"
 set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD/MAX/MAXII/RAM2GS.qws b/CPLD/MAX/MAXII/RAM2GS.qws
new file mode 100644
index 0000000..4620ebd
Binary files /dev/null and b/CPLD/MAX/MAXII/RAM2GS.qws differ
diff --git a/CPLD/AGM-src/UFM.qip b/CPLD/MAX/MAXII/UFM.qip
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/UFM.qip
rename to CPLD/MAX/MAXII/UFM.qip
diff --git a/CPLD/MAXII/UFM.v b/CPLD/MAX/MAXII/UFM.v
old mode 100755
new mode 100644
similarity index 83%
rename from CPLD/MAXII/UFM.v
rename to CPLD/MAX/MAXII/UFM.v
index c063115..f58dd72
--- a/CPLD/MAXII/UFM.v
+++ b/CPLD/MAX/MAXII/UFM.v
@@ -33,8 +33,8 @@
 //applicable agreement for further details.
 
 
-//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
-//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ  VERSION_END
+//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
+//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
@@ -43,7 +43,7 @@
 //synopsys translate_off
 `timescale 1 ps / 1 ps
 //synopsys translate_on
-module  UFM_altufm_none_1br
+module  UFM_altufm_none_imr
 	( 
 	arclk,
 	ardin,
@@ -117,23 +117,23 @@ module  UFM_altufm_none_1br
 	defparam
 		maxii_ufm_block1.address_width = 9,
 		maxii_ufm_block1.erase_time = 500000000,
-		maxii_ufm_block1.init_file = "RAM4GS.mif",
+		maxii_ufm_block1.init_file = "RAM2GS-MAX.mif",
 		maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
 		maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
 		maxii_ufm_block1.osc_sim_setting = 180000,
 		maxii_ufm_block1.program_time = 1600000,
 		maxii_ufm_block1.lpm_type = "maxii_ufm";
@@ -155,7 +155,7 @@ module  UFM_altufm_none_1br
 		ufm_osc = wire_maxii_ufm_block1_osc,
 		ufm_oscena = oscena,
 		ufm_program = program;
-endmodule //UFM_altufm_none_1br
+endmodule //UFM_altufm_none_imr
 //VALID FILE
 
 
@@ -200,7 +200,7 @@ module UFM (
 	wire  drdout = sub_wire2;
 	wire  busy = sub_wire3;
 
-	UFM_altufm_none_1br	UFM_altufm_none_1br_component (
+	UFM_altufm_none_imr	UFM_altufm_none_imr_component (
 				.arshft (arshft),
 				.drclk (drclk),
 				.erase (erase),
@@ -224,7 +224,7 @@ endmodule
 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
 // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
-// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif"
+// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif"
 // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
 // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb
new file mode 100644
index 0000000..b4b4e46
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb
new file mode 100644
index 0000000..bc59c9d
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(0).cnf.hdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb
new file mode 100644
index 0000000..f8b441f
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb
new file mode 100644
index 0000000..619591b
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(1).cnf.hdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb
new file mode 100644
index 0000000..0d88168
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb
new file mode 100644
index 0000000..832159d
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.(2).cnf.hdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg
new file mode 100644
index 0000000..5738a14
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/RAM2GS.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153617401 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing started: Mon Aug 16 18:40:17 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153617637 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153617652 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153617808 ""}
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb
new file mode 100644
index 0000000..201b4bb
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.asm.rdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb b/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb
new file mode 100644
index 0000000..3d7511a
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.asm_labs.ddb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb
new file mode 100644
index 0000000..819e5d8
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb
new file mode 100644
index 0000000..d79937a
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.hdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb
new file mode 100644
index 0000000..a767c09
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.idb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt b/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt
new file mode 100644
index 0000000..73afc77
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.kpt differ
diff --git a/CPLD/AGM-src/db/RAM4GS.cmp.logdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.logdb
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/db/RAM4GS.cmp.logdb
rename to CPLD/MAX/MAXII/db/RAM2GS.cmp.logdb
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb
new file mode 100644
index 0000000..8a93cad
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp.rdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb
new file mode 100644
index 0000000..ff3e753
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.cmp0.ddb differ
diff --git a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info b/CPLD/MAX/MAXII/db/RAM2GS.db_info
old mode 100755
new mode 100644
similarity index 72%
rename from CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info
rename to CPLD/MAX/MAXII/db/RAM2GS.db_info
index dda2847..5d4d051
--- a/CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.db_info
+++ b/CPLD/MAX/MAXII/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 Version_Index = 302049280
-Creation_Time = Mon Jun 15 13:43:18 2020
+Creation_Time = Tue Sep 28 21:30:08 2021
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg
new file mode 100644
index 0000000..74840a8
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/RAM2GS.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153614132 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153614132 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153614309 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153614325 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153614465 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 336 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153614512 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153614512 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153614621 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153614621 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153614621 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153614621 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 332 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 334 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 333 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153614653 ""}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153614668 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153614668 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153614699 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153614699 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153614715 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153614715 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 18 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  18 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153614715 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153614746 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153614887 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615071 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153615085 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153615678 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615678 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153615709 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153615943 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153615943 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616286 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153616286 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616302 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153616333 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153616395 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing ended: Mon Aug 16 18:40:16 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153616427 ""}
diff --git a/CPLD/AGM-src/db/RAM4GS.hier_info b/CPLD/MAX/MAXII/db/RAM2GS.hier_info
old mode 100755
new mode 100644
similarity index 93%
rename from CPLD/AGM-src/db/RAM4GS.hier_info
rename to CPLD/MAX/MAXII/db/RAM2GS.hier_info
index 97bc269..ca4de37
--- a/CPLD/AGM-src/db/RAM4GS.hier_info
+++ b/CPLD/MAX/MAXII/db/RAM2GS.hier_info
@@ -1,4 +1,4 @@
-|RAM4GS
+|RAM2GS
 PHI2 => Bank[0].CLK
 PHI2 => Bank[1].CLK
 PHI2 => Bank[2].CLK
@@ -152,12 +152,14 @@ nCRAS => RowA[8].CLK
 nCRAS => RowA[9].CLK
 nCRAS => RBA[0]~reg0.CLK
 nCRAS => RBA[1]~reg0.CLK
+nCRAS => comb.IN1
 nCRAS => RASr.DATAIN
 nFWE => comb.IN1
 nFWE => CMDWR.IN1
 nFWE => ADWR.IN1
 nFWE => C1WR.IN1
 nFWE => FWEr.DATAIN
+LED <= comb.DB_MAX_OUTPUT_PORT_TYPE
 RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
@@ -184,9 +186,10 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RCLK => UFMProgram.CLK
 RCLK => UFMErase.CLK
 RCLK => UFMReqErase.CLK
-RCLK => n8MEGEN.CLK
+RCLK => LEDEN.CLK
 RCLK => UFMInitDone.CLK
-RCLK => UFMD.CLK
+RCLK => n8MEGEN.CLK
+RCLK => UFMD[15].CLK
 RCLK => DRShift.CLK
 RCLK => DRDIn.CLK
 RCLK => DRCLK.CLK
@@ -243,7 +246,7 @@ RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
 RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
 
 
-|RAM4GS|UFM:UFM_inst
+|RAM2GS|UFM:UFM_inst
 arclk => arclk.IN1
 ardin => ardin.IN1
 arshft => arshft.IN1
@@ -253,13 +256,13 @@ drshft => drshft.IN1
 erase => erase.IN1
 oscena => oscena.IN1
 program => program.IN1
-busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
-drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
-osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
-rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
+busy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.busy
+drdout <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.drdout
+osc <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.osc
+rtpbusy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.rtpbusy
 
 
-|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
+|RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component
 arclk => maxii_ufm_block1.ARCLK
 ardin => maxii_ufm_block1.ARDIN
 arshft => maxii_ufm_block1.ARSHFT
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.hif b/CPLD/MAX/MAXII/db/RAM2GS.hif
new file mode 100644
index 0000000..98245db
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.hif differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.ipinfo b/CPLD/MAX/MAXII/db/RAM2GS.ipinfo
new file mode 100644
index 0000000..b9c2697
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.ipinfo differ
diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.html b/CPLD/MAX/MAXII/db/RAM2GS.lpc.html
old mode 100755
new mode 100644
similarity index 93%
rename from CPLD/AGM-src/db/RAM4GS.lpc.html
rename to CPLD/MAX/MAXII/db/RAM2GS.lpc.html
index d50a19d..76d3fb3
--- a/CPLD/AGM-src/db/RAM4GS.lpc.html
+++ b/CPLD/MAX/MAXII/db/RAM2GS.lpc.html
@@ -16,7 +16,7 @@
 Output only Bidir
 
 
-UFM_inst|UFM_altufm_none_1br_component
+UFM_inst|UFM_altufm_none_imr_component
 9
 0
 0
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb b/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb
new file mode 100644
index 0000000..b40333d
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb differ
diff --git a/CPLD/AGM-src/db/RAM4GS.lpc.txt b/CPLD/MAX/MAXII/db/RAM2GS.lpc.txt
old mode 100755
new mode 100644
similarity index 96%
rename from CPLD/AGM-src/db/RAM4GS.lpc.txt
rename to CPLD/MAX/MAXII/db/RAM2GS.lpc.txt
index d8d214c..6debc2c
--- a/CPLD/AGM-src/db/RAM4GS.lpc.txt
+++ b/CPLD/MAX/MAXII/db/RAM2GS.lpc.txt
@@ -3,6 +3,6 @@
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
 ; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_1br_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; UFM_inst|UFM_altufm_none_imr_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
 ; UFM_inst                               ; 9     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.cdb b/CPLD/MAX/MAXII/db/RAM2GS.map.cdb
new file mode 100644
index 0000000..3a1913b
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.hdb b/CPLD/MAX/MAXII/db/RAM2GS.map.hdb
new file mode 100644
index 0000000..5a4b799
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.hdb differ
diff --git a/CPLD/AGM-src/db/RAM4GS.map.logdb b/CPLD/MAX/MAXII/db/RAM2GS.map.logdb
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/db/RAM4GS.map.logdb
rename to CPLD/MAX/MAXII/db/RAM2GS.map.logdb
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg
new file mode 100644
index 0000000..c1f2c80
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/RAM2GS.map.qmsg
@@ -0,0 +1,27 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153611805 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:11 2021 " "Processing started: Mon Aug 16 18:40:11 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153612070 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153612117 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_imr " "Found entity 1: UFM_altufm_none_imr" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153612195 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_imr UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component " "Elaborating entity \"UFM_altufm_none_imr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component\"" {  } { { "UFM.v" "UFM_altufm_none_imr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""}
+{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0" {  } {  } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153612257 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153612865 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153612865 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153612943 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:12 2021 " "Processing ended: Mon Aug 16 18:40:12 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""}
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.map.rdb b/CPLD/MAX/MAXII/db/RAM2GS.map.rdb
new file mode 100644
index 0000000..e611b88
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.map.rdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb
new file mode 100644
index 0000000..b64e6b9
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.pre_map.hdb differ
diff --git a/CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb b/CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb
old mode 100755
new mode 100644
similarity index 67%
rename from CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb
rename to CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb
index 42a925d..89aa9b4
Binary files a/CPLD/AGM-src/db/RAM4GS.tis_db_list.ddb and b/CPLD/MAX/MAXII/db/RAM2GS.pti_db_list.ddb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb b/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..dce5122
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb
new file mode 100644
index 0000000..312e8ac
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.routing.rdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb
new file mode 100644
index 0000000..7950f8a
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv.hdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb
new file mode 100644
index 0000000..f549130
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..9f7460b
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.rtlv_sg_swap.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb
new file mode 100644
index 0000000..5b2fdc3
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.cdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb
new file mode 100644
index 0000000..77a25c9
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sgdiff.hdb differ
diff --git a/CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci
old mode 100755
new mode 100644
similarity index 59%
rename from CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci
rename to CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci
index 754b594..1d6d60f
Binary files a/CPLD/AGM-src/db/RAM4GS.sld_design_entry_dsc.sci and b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry.sci differ
diff --git a/CPLD/MAXII/db/RAM4GS.sld_design_entry.sci b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci
old mode 100755
new mode 100644
similarity index 59%
rename from CPLD/MAXII/db/RAM4GS.sld_design_entry.sci
rename to CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci
index 754b594..1d6d60f
Binary files a/CPLD/MAXII/db/RAM4GS.sld_design_entry.sci and b/CPLD/MAX/MAXII/db/RAM2GS.sld_design_entry_dsc.sci differ
diff --git a/CPLD/AGM-src/db/RAM4GS.smart_action.txt b/CPLD/MAX/MAXII/db/RAM2GS.smart_action.txt
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/db/RAM4GS.smart_action.txt
rename to CPLD/MAX/MAXII/db/RAM2GS.smart_action.txt
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg
new file mode 100644
index 0000000..33c9310
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/RAM2GS.sta.qmsg
@@ -0,0 +1,23 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153618889 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:18 2021 " "Processing started: Mon Aug 16 18:40:18 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153618967 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153619091 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153619201 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153619419 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153619466 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153619466 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.339      -245.761 RCLK  " "   -8.339      -245.761 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.271       -88.383 PHI2  " "   -8.271       -88.383 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.317        -2.784 nCRAS  " "   -0.317        -2.784 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.858 " "Worst-case hold slack is -16.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.858       -16.858 ARCLK  " "  -16.858       -16.858 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.363       -16.363 DRCLK  " "  -16.363       -16.363 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.103        -0.195 nCRAS  " "   -0.103        -0.195 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.060        -0.060 PHI2  " "   -0.060        -0.060 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.192         0.000 RCLK  " "    1.192         0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153619559 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:19 2021 " "Processing ended: Mon Aug 16 18:40:19 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""}
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb
new file mode 100644
index 0000000..1d00921
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sta.rdb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb
new file mode 100644
index 0000000..d59ad7a
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb differ
diff --git a/CPLD/AGM-src/db/RAM4GS.syn_hier_info b/CPLD/MAX/MAXII/db/RAM2GS.syn_hier_info
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/db/RAM4GS.syn_hier_info
rename to CPLD/MAX/MAXII/db/RAM2GS.syn_hier_info
diff --git a/CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb b/CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb
old mode 100755
new mode 100644
similarity index 67%
rename from CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb
rename to CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb
index 61ca8da..91bbe10
Binary files a/CPLD/AGM-src/db/RAM4GS.pti_db_list.ddb and b/CPLD/MAX/MAXII/db/RAM2GS.tis_db_list.ddb differ
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.tmw_info b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info
new file mode 100644
index 0000000..16f5f5b
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s
+start_analysis_synthesis:s-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s-start_full_compilation
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb b/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb
new file mode 100644
index 0000000..e64e992
Binary files /dev/null and b/CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb differ
diff --git a/CPLD/MAX/MAXII/db/logic_util_heursitic.dat b/CPLD/MAX/MAXII/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..ff5fe7f
Binary files /dev/null and b/CPLD/MAX/MAXII/db/logic_util_heursitic.dat differ
diff --git a/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg b/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg
new file mode 100644
index 0000000..54a2998
--- /dev/null
+++ b/CPLD/MAX/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg
@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153597248 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:39:57 2021 " "Processing started: Mon Aug 16 18:39:57 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153597248 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153597529 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153597576 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597592 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153597592 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153597638 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153597638 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_imr " "Found entity 1: UFM_altufm_none_imr" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153597638 ""}
+{ "Error" "EVRFX_SV_NO_SINGLE_VALUED_PACKED_DIMENSION" "RAM2GS-MAX.v(59) " "SystemVerilog error at RAM2GS-MAX.v(59): can't declare packed array dimension with a single-valued range" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 59 0 0 } }  } 0 10989 "SystemVerilog error at %1!s!: can't declare packed array dimension with a single-valued range" 0 0 "Quartus II" 0 -1 1629153597638 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Aug 16 18:39:57 2021 " "Processing ended: Mon Aug 16 18:39:57 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153597670 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153598258 ""}
diff --git a/CPLD/AGM-src/incremental_db/README b/CPLD/MAX/MAXII/incremental_db/README
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/incremental_db/README
rename to CPLD/MAX/MAXII/incremental_db/README
diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info
old mode 100755
new mode 100644
similarity index 72%
rename from CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info
rename to CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info
index dda2847..414a0d6
--- a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.db_info
+++ b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 Version_Index = 302049280
-Creation_Time = Mon Jun 15 13:43:18 2020
+Creation_Time = Mon Aug 16 18:40:12 2021
diff --git a/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
new file mode 100644
index 0000000..0c26b10
Binary files /dev/null and b/CPLD/MAX/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ
diff --git a/CPLD/AGM-src/output_files/RAM4GS.asm.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt
old mode 100755
new mode 100644
similarity index 73%
rename from CPLD/AGM-src/output_files/RAM4GS.asm.rpt
rename to CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt
index 1915f58..878a98d
--- a/CPLD/AGM-src/output_files/RAM4GS.asm.rpt
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.asm.rpt
@@ -1,6 +1,6 @@
-Assembler report for RAM4GS
-Thu Jul 23 02:20:55 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Assembler report for RAM2GS
+Mon Aug 16 18:40:17 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof
+  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof
   6. Assembler Messages
 
 
@@ -37,9 +37,9 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Jul 23 02:20:55 2020 ;
-; Revision Name         ; RAM4GS                                ;
-; Top-level Entity Name ; RAM4GS                                ;
+; Assembler Status      ; Successful - Mon Aug 16 18:40:17 2021 ;
+; Revision Name         ; RAM2GS                                ;
+; Top-level Entity Name ; RAM2GS                                ;
 ; Family                ; MAX II                                ;
 ; Device                ; EPM240T100C5                          ;
 +-----------------------+---------------------------------------+
@@ -75,40 +75,40 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+-----------+---------------+
 
 
-+--------------------------------------------+
-; Assembler Generated Files                  ;
-+--------------------------------------------+
-; File Name                                  ;
-+--------------------------------------------+
-; /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
-+--------------------------------------------+
++-----------------------------------------------------------------------------+
+; Assembler Generated Files                                                   ;
++-----------------------------------------------------------------------------+
+; File Name                                                                   ;
++-----------------------------------------------------------------------------+
+; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ;
++-----------------------------------------------------------------------------+
 
 
-+----------------------------------------------------------------------+
-; Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
-+----------------+-----------------------------------------------------+
-; Option         ; Setting                                             ;
-+----------------+-----------------------------------------------------+
-; Device         ; EPM240T100C5                                        ;
-; JTAG usercode  ; 0x00173F26                                          ;
-; Checksum       ; 0x0017428E                                          ;
-+----------------+-----------------------------------------------------+
++-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ;
++----------------+--------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                              ;
++----------------+--------------------------------------------------------------------------------------+
+; Device         ; EPM240T100C5                                                                         ;
+; JTAG usercode  ; 0x001737AB                                                                           ;
+; Checksum       ; 0x00173A1B                                                                           ;
++----------------+--------------------------------------------------------------------------------------+
 
 
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
+Info: Running Quartus II 64-Bit Assembler
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Thu Jul 23 02:20:53 2020
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
+    Info: Processing started: Mon Aug 16 18:40:17 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 296 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:55 2020
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 381 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:17 2021
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.done b/CPLD/MAX/MAXII/output_files/RAM2GS.done
new file mode 100644
index 0000000..ad0c117
--- /dev/null
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.done
@@ -0,0 +1 @@
+Mon Aug 16 18:40:20 2021
diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt
old mode 100755
new mode 100644
similarity index 86%
rename from CPLD/MAXII/output_files/RAM4GS.fit.rpt
rename to CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt
index 15a6629..29e0daf
--- a/CPLD/MAXII/output_files/RAM4GS.fit.rpt
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.rpt
@@ -1,6 +1,6 @@
-Fitter report for RAM4GS
-Thu Jul 23 02:20:50 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Fitter report for RAM2GS
+Mon Aug 16 18:40:16 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -59,15 +59,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Fitter Summary                                                              ;
 +---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Thu Jul 23 02:20:50 2020           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM4GS                                          ;
-; Top-level Entity Name     ; RAM4GS                                          ;
+; Fitter Status             ; Successful - Mon Aug 16 18:40:16 2021           ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; RAM2GS                                          ;
+; Top-level Entity Name     ; RAM2GS                                          ;
 ; Family                    ; MAX II                                          ;
 ; Device                    ; EPM240T100C5                                    ;
 ; Timing Models             ; Final                                           ;
-; Total logic elements      ; 170 / 240 ( 71 % )                              ;
-; Total pins                ; 62 / 80 ( 78 % )                                ;
+; Total logic elements      ; 168 / 240 ( 70 % )                              ;
+; Total pins                ; 63 / 80 ( 79 % )                                ;
 ; Total virtual pins        ; 0                                               ;
 ; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
 +---------------------------+-------------------------------------------------+
@@ -122,27 +122,21 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------------------+--------------------------------+
 
 
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 2           ;
-; Maximum allowed            ; 2           ;
-;                            ;             ;
-; Average used               ; 1.33        ;
-; Maximum used               ; 2           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;  33.3%      ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
 
 
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
+The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pin.
 
 
 +------------------------------------------------------------------+
@@ -150,43 +144,43 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 +---------------------------------------------+--------------------+
 ; Resource                                    ; Usage              ;
 +---------------------------------------------+--------------------+
-; Total logic elements                        ; 170 / 240 ( 71 % ) ;
-;     -- Combinational with no register       ; 74                 ;
-;     -- Register only                        ; 21                 ;
-;     -- Combinational with a register        ; 75                 ;
+; Total logic elements                        ; 168 / 240 ( 70 % ) ;
+;     -- Combinational with no register       ; 71                 ;
+;     -- Register only                        ; 20                 ;
+;     -- Combinational with a register        ; 77                 ;
 ;                                             ;                    ;
 ; Logic element usage by number of LUT inputs ;                    ;
-;     -- 4 input functions                    ; 57                 ;
-;     -- 3 input functions                    ; 41                 ;
-;     -- 2 input functions                    ; 42                 ;
+;     -- 4 input functions                    ; 58                 ;
+;     -- 3 input functions                    ; 40                 ;
+;     -- 2 input functions                    ; 41                 ;
 ;     -- 1 input functions                    ; 8                  ;
 ;     -- 0 input functions                    ; 1                  ;
 ;                                             ;                    ;
 ; Logic elements by mode                      ;                    ;
-;     -- normal mode                          ; 154                ;
+;     -- normal mode                          ; 152                ;
 ;     -- arithmetic mode                      ; 16                 ;
-;     -- qfbk mode                            ; 6                  ;
+;     -- qfbk mode                            ; 7                  ;
 ;     -- register cascade mode                ; 0                  ;
 ;     -- synchronous clear/load mode          ; 25                 ;
 ;     -- asynchronous clear/load mode         ; 0                  ;
 ;                                             ;                    ;
-; Total registers                             ; 96 / 240 ( 40 % )  ;
-; Total LABs                                  ; 22 / 24 ( 92 % )   ;
+; Total registers                             ; 97 / 240 ( 40 % )  ;
+; Total LABs                                  ; 23 / 24 ( 96 % )   ;
 ; Logic elements in carry chains              ; 17                 ;
 ; Virtual pins                                ; 0                  ;
-; I/O pins                                    ; 62 / 80 ( 78 % )   ;
+; I/O pins                                    ; 63 / 80 ( 79 % )   ;
 ;     -- Clock pins                           ; 2 / 4 ( 50 % )     ;
 ;                                             ;                    ;
 ; Global signals                              ; 4                  ;
 ; UFM blocks                                  ; 1 / 1 ( 100 % )    ;
 ; Global clocks                               ; 4 / 4 ( 100 % )    ;
 ; JTAGs                                       ; 0 / 1 ( 0 % )      ;
-; Average interconnect usage (total/H/V)      ; 25% / 27% / 23%    ;
-; Peak interconnect usage (total/H/V)         ; 25% / 27% / 23%    ;
-; Maximum fan-out                             ; 54                 ;
-; Highest non-global fan-out                  ; 38                 ;
-; Total fan-out                               ; 644                ;
-; Average fan-out                             ; 2.76               ;
+; Average interconnect usage (total/H/V)      ; 21% / 23% / 19%    ;
+; Peak interconnect usage (total/H/V)         ; 21% / 23% / 19%    ;
+; Maximum fan-out                             ; 55                 ;
+; Highest non-global fan-out                  ; 39                 ;
+; Total fan-out                               ; 643                ;
+; Average fan-out                             ; 2.77               ;
 +---------------------------------------------+--------------------+
 
 
@@ -216,9 +210,9 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 21                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 54                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
+; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 15                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
+; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
 
@@ -236,6 +230,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED     ; 66    ; 2        ; 8            ; 3            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVTTL  ; 16mA             ; yes                    ; Fitter               ; 10 pF ; -                    ; -                   ;
 ; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -249,11 +244,11 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -265,14 +260,14 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 ; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
 
@@ -282,7 +277,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
 +----------+-------------------+---------------+--------------+
 ; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 24 / 42 ( 57 % )  ; 3.3V          ; --           ;
+; 2        ; 25 / 42 ( 60 % )  ; 3.3V          ; --           ;
 +----------+-------------------+---------------+--------------+
 
 
@@ -356,7 +351,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; 63       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
 ; 64       ; 51         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
 ; 65       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
+; 66       ; 52         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;           ; Row I/O    ; N               ; yes      ; Off          ;
 ; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
 ; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
 ; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
@@ -416,9 +411,9 @@ Note: User assignments will override these defaults. The user specified values a
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 ; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM4GS                                                   ; 170 (170)   ; 96           ; 1          ; 62   ; 0            ; 74 (74)      ; 21 (21)           ; 75 (75)          ; 17 (17)         ; 6 (6)      ; |RAM4GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work         ;
+; |RAM2GS                                                   ; 168 (168)   ; 97           ; 1          ; 63   ; 0            ; 71 (71)      ; 20 (20)           ; 77 (77)          ; 17 (17)         ; 7 (7)      ; |RAM2GS                                                                ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
+;       |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work         ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
@@ -428,6 +423,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------+----------+---------------+
 ; Name    ; Pin Type ; Pad to Core 0 ;
 +---------+----------+---------------+
+; nCRAS   ; Input    ; (0)           ;
 ; MAin[0] ; Input    ; (0)           ;
 ; MAin[1] ; Input    ; (0)           ;
 ; MAin[2] ; Input    ; (0)           ;
@@ -438,10 +434,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; MAin[7] ; Input    ; (0)           ;
 ; MAin[8] ; Input    ; (0)           ;
 ; MAin[9] ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; nCRAS   ; Input    ; (0)           ;
-; CROW[1] ; Input    ; (1)           ;
 ; RCLK    ; Input    ; (0)           ;
+; CROW[0] ; Input    ; (1)           ;
+; CROW[1] ; Input    ; (1)           ;
 ; PHI2    ; Input    ; (0)           ;
 ; Din[6]  ; Input    ; (1)           ;
 ; nFWE    ; Input    ; (1)           ;
@@ -461,6 +456,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Dout[5] ; Output   ; --            ;
 ; Dout[6] ; Output   ; --            ;
 ; Dout[7] ; Output   ; --            ;
+; LED     ; Output   ; --            ;
 ; RBA[0]  ; Output   ; --            ;
 ; RBA[1]  ; Output   ; --            ;
 ; RA[0]   ; Output   ; --            ;
@@ -498,16 +494,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
 ; Name           ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1     ; LC_X6_Y3_N3 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdSubmitted~0 ; LC_X6_Y3_N9 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1        ; LC_X2_Y1_N3 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; CmdDRDIn~1     ; LC_X6_Y2_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
+; CmdSubmitted~0 ; LC_X5_Y2_N5 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; DRDIn~1        ; LC_X4_Y1_N2 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
 ; PHI2           ; PIN_52      ; 21      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-; RCLK           ; PIN_12      ; 54      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; Ready          ; LC_X3_Y2_N1 ; 38      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~5      ; LC_X5_Y3_N0 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; comb~2         ; LC_X4_Y4_N6 ; 8       ; Output enable           ; no     ; --                   ; --               ;
+; RCLK           ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
+; Ready          ; LC_X3_Y4_N6 ; 39      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; always8~5      ; LC_X6_Y2_N2 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; comb~3         ; LC_X4_Y4_N9 ; 8       ; Output enable           ; no     ; --                   ; --               ;
 ; nCCAS          ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-; nCRAS          ; PIN_67      ; 15      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
+; nCRAS          ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
 
 
@@ -517,9 +513,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +-------+----------+---------+----------------------+------------------+
 ; PHI2  ; PIN_52   ; 21      ; Global Clock         ; GCLK3            ;
-; RCLK  ; PIN_12   ; 54      ; Global Clock         ; GCLK0            ;
+; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
 ; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
-; nCRAS ; PIN_67   ; 15      ; Global Clock         ; GCLK1            ;
+; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK1            ;
 +-------+----------+---------+----------------------+------------------+
 
 
@@ -528,99 +524,99 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------------------------------------------------------------------------+---------+
 ; Name                                                                                        ; Fan-Out ;
 +---------------------------------------------------------------------------------------------+---------+
-; Ready                                                                                       ; 38      ;
+; Ready                                                                                       ; 39      ;
 ; nRowColSel                                                                                  ; 13      ;
 ; S[1]                                                                                        ; 12      ;
 ; S[0]                                                                                        ; 12      ;
 ; RASr2                                                                                       ; 9       ;
 ; Din[6]                                                                                      ; 8       ;
-; comb~2                                                                                      ; 8       ;
-; FS[4]                                                                                       ; 8       ;
+; comb~3                                                                                      ; 8       ;
 ; Din[5]                                                                                      ; 7       ;
 ; Din[4]                                                                                      ; 7       ;
-; FS[5]                                                                                       ; 7       ;
 ; IS[0]~0                                                                                     ; 7       ;
 ; Din[7]                                                                                      ; 6       ;
 ; Din[0]                                                                                      ; 6       ;
 ; MAin[1]                                                                                     ; 6       ;
-; FS[6]                                                                                       ; 6       ;
-; always9~1                                                                                   ; 6       ;
 ; IS[0]                                                                                       ; 6       ;
+; FS[4]                                                                                       ; 6       ;
 ; Din[3]                                                                                      ; 5       ;
 ; Din[2]                                                                                      ; 5       ;
 ; MAin[0]                                                                                     ; 5       ;
-; FS[8]~27                                                                                    ; 5       ;
+; FS[8]~31                                                                                    ; 5       ;
 ; FS[3]~13                                                                                    ; 5       ;
 ; FS[3]                                                                                       ; 5       ;
-; always9~2                                                                                   ; 5       ;
-; FS[17]                                                                                      ; 5       ;
-; FS[16]                                                                                      ; 5       ;
 ; IS[1]                                                                                       ; 5       ;
 ; CBR                                                                                         ; 5       ;
 ; FWEr                                                                                        ; 5       ;
+; FS[6]                                                                                       ; 5       ;
+; FS[5]                                                                                       ; 5       ;
+; FS[17]                                                                                      ; 5       ;
+; FS[16]                                                                                      ; 5       ;
+; UFMD[15]                                                                                    ; 5       ;
 ; Din[1]                                                                                      ; 4       ;
 ; MAin[9]                                                                                     ; 4       ;
 ; MAin[7]                                                                                     ; 4       ;
 ; MAin[6]                                                                                     ; 4       ;
 ; CmdDRDIn~1                                                                                  ; 4       ;
-; UFMD                                                                                        ; 4       ;
-; FS[13]~21                                                                                   ; 4       ;
+; FS[13]~27                                                                                   ; 4       ;
 ; CMDWR~2                                                                                     ; 4       ;
 ; UFMReqErase                                                                                 ; 4       ;
+; always9~3                                                                                   ; 4       ;
+; DRCLK~0                                                                                     ; 4       ;
+; always9~2                                                                                   ; 4       ;
 ; Equal9~0                                                                                    ; 4       ;
-; n8MEGEN                                                                                     ; 4       ;
 ; IS[3]                                                                                       ; 4       ;
 ; IS[2]                                                                                       ; 4       ;
 ; InitReady                                                                                   ; 4       ;
+; always9~0                                                                                   ; 4       ;
 ; nFWE                                                                                        ; 3       ;
 ; MAin[5]                                                                                     ; 3       ;
 ; MAin[4]                                                                                     ; 3       ;
 ; MAin[3]                                                                                     ; 3       ;
 ; MAin[2]                                                                                     ; 3       ;
-; FS[0]                                                                                       ; 3       ;
 ; always8~5                                                                                   ; 3       ;
 ; CMDWR                                                                                       ; 3       ;
 ; CmdEnable                                                                                   ; 3       ;
+; FS[0]                                                                                       ; 3       ;
 ; always8~4                                                                                   ; 3       ;
 ; always8~2                                                                                   ; 3       ;
 ; Equal0~0                                                                                    ; 3       ;
-; always9~3                                                                                   ; 3       ;
-; UFMInitDone                                                                                 ; 3       ;
 ; nRCS~3                                                                                      ; 3       ;
+; n8MEGEN                                                                                     ; 3       ;
+; UFMInitDone~0                                                                               ; 3       ;
+; UFMInitDone                                                                                 ; 3       ;
 ; RCKE~reg0                                                                                   ; 3       ;
+; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; 3       ;
 ; MAin[8]                                                                                     ; 2       ;
-; FS[1]                                                                                       ; 2       ;
-; FS[2]                                                                                       ; 2       ;
-; Equal25~0                                                                                   ; 2       ;
-; FS[9]                                                                                       ; 2       ;
-; FS[8]                                                                                       ; 2       ;
 ; CmdSubmitted~0                                                                              ; 2       ;
 ; Equal17~0                                                                                   ; 2       ;
 ; CmdDRDIn~0                                                                                  ; 2       ;
 ; XOR8MEG~0                                                                                   ; 2       ;
 ; Equal0~3                                                                                    ; 2       ;
+; Ready~0                                                                                     ; 2       ;
+; Equal26~0                                                                                   ; 2       ;
+; FS[9]                                                                                       ; 2       ;
+; FS[8]                                                                                       ; 2       ;
 ; Equal5~1                                                                                    ; 2       ;
-; FS[15]                                                                                      ; 2       ;
 ; FS[14]                                                                                      ; 2       ;
 ; FS[13]                                                                                      ; 2       ;
 ; FS[12]                                                                                      ; 2       ;
 ; FS[11]                                                                                      ; 2       ;
 ; FS[10]                                                                                      ; 2       ;
-; Ready~0                                                                                     ; 2       ;
+; FS[15]                                                                                      ; 2       ;
+; Equal24~0                                                                                   ; 2       ;
+; FS[2]                                                                                       ; 2       ;
+; FS[1]                                                                                       ; 2       ;
 ; UFMOscEN~0                                                                                  ; 2       ;
 ; C1Submitted                                                                                 ; 2       ;
 ; Equal0~1                                                                                    ; 2       ;
 ; always8~0                                                                                   ; 2       ;
 ; CmdUFMErase                                                                                 ; 2       ;
 ; CmdUFMPrgm                                                                                  ; 2       ;
-; always9~6                                                                                   ; 2       ;
-; always9~5                                                                                   ; 2       ;
-; ARCLK~1                                                                                     ; 2       ;
 ; always9~4                                                                                   ; 2       ;
-; DRDIn~1                                                                                     ; 2       ;
-; FS[7]                                                                                       ; 2       ;
-; always9~0                                                                                   ; 2       ;
 ; PHI2r2                                                                                      ; 2       ;
+; DRDIn~1                                                                                     ; 2       ;
+; CmdSubmitted                                                                                ; 2       ;
 ; RASr                                                                                        ; 2       ;
 ; RCKEEN                                                                                      ; 2       ;
 ; CASr2                                                                                       ; 2       ;
@@ -630,13 +626,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; XOR8MEG                                                                                     ; 2       ;
 ; RA10~0                                                                                      ; 2       ;
 ; nRowColSel~0                                                                                ; 2       ;
+; always9~1                                                                                   ; 2       ;
+; FS[7]                                                                                       ; 2       ;
 ; UFMOscEN                                                                                    ; 2       ;
 ; UFMErase                                                                                    ; 2       ;
 ; UFMProgram                                                                                  ; 2       ;
-; ARShift                                                                                     ; 2       ;
-; ARCLK                                                                                       ; 2       ;
-; DRShift                                                                                     ; 2       ;
-; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; 2       ;
+; LEDEN                                                                                       ; 2       ;
 ; UFMProgram~_wirecell                                                                        ; 1       ;
 ; UFMOscEN~_wirecell                                                                          ; 1       ;
 ; UFMErase~_wirecell                                                                          ; 1       ;
@@ -652,37 +647,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; CROW[0]                                                                                     ; 1       ;
 ; CmdEnable~1                                                                                 ; 1       ;
 ; CmdEnable~0                                                                                 ; 1       ;
-; UFMD~1                                                                                      ; 1       ;
-; FS[1]~33COUT1_50                                                                            ; 1       ;
-; FS[1]~33                                                                                    ; 1       ;
-; UFMD~0                                                                                      ; 1       ;
-; UFMReqErase~0                                                                               ; 1       ;
-; FS[2]~31COUT1_52                                                                            ; 1       ;
-; FS[2]~31                                                                                    ; 1       ;
-; FS[9]~29COUT1_62                                                                            ; 1       ;
-; FS[9]~29                                                                                    ; 1       ;
-; UFMInitDone~0                                                                               ; 1       ;
 ; PHI2r                                                                                       ; 1       ;
 ; RCKEEN~2                                                                                    ; 1       ;
 ; RCKEEN~1                                                                                    ; 1       ;
 ; RCKEEN~0                                                                                    ; 1       ;
 ; CASr                                                                                        ; 1       ;
 ; Equal16~0                                                                                   ; 1       ;
+; n8MEGEN~3                                                                                   ; 1       ;
+; PHI2r3                                                                                      ; 1       ;
+; n8MEGEN~2                                                                                   ; 1       ;
+; n8MEGEN~1                                                                                   ; 1       ;
 ; n8MEGEN~0                                                                                   ; 1       ;
 ; Cmdn8MEGEN                                                                                  ; 1       ;
 ; IS[0]~3                                                                                     ; 1       ;
-; FS[15]~25COUT1_72                                                                           ; 1       ;
-; FS[15]~25                                                                                   ; 1       ;
-; FS[14]~23COUT1_70                                                                           ; 1       ;
-; FS[14]~23                                                                                   ; 1       ;
-; Equal5~0                                                                                    ; 1       ;
-; FS[12]~19COUT1_68                                                                           ; 1       ;
-; FS[12]~19                                                                                   ; 1       ;
-; FS[11]~17COUT1_66                                                                           ; 1       ;
-; FS[11]~17                                                                                   ; 1       ;
-; FS[10]~15COUT1_64                                                                           ; 1       ;
-; FS[10]~15                                                                                   ; 1       ;
 ; Ready~1                                                                                     ; 1       ;
+; FS[9]~33COUT1_62                                                                            ; 1       ;
+; FS[9]~33                                                                                    ; 1       ;
+; FS[14]~29COUT1_70                                                                           ; 1       ;
+; FS[14]~29                                                                                   ; 1       ;
+; Equal5~0                                                                                    ; 1       ;
+; FS[12]~25COUT1_68                                                                           ; 1       ;
+; FS[12]~25                                                                                   ; 1       ;
+; FS[11]~23COUT1_66                                                                           ; 1       ;
+; FS[11]~23                                                                                   ; 1       ;
+; FS[10]~21COUT1_64                                                                           ; 1       ;
+; FS[10]~21                                                                                   ; 1       ;
+; FS[15]~19COUT1_72                                                                           ; 1       ;
+; FS[15]~19                                                                                   ; 1       ;
+; UFMD[15]~0                                                                                  ; 1       ;
+; FS[2]~17COUT1_52                                                                            ; 1       ;
+; FS[2]~17                                                                                    ; 1       ;
+; FS[1]~15COUT1_50                                                                            ; 1       ;
+; FS[1]~15                                                                                    ; 1       ;
 ; WRD[7]                                                                                      ; 1       ;
 ; WRD[6]                                                                                      ; 1       ;
 ; WRD[5]                                                                                      ; 1       ;
@@ -704,23 +700,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Bank[2]                                                                                     ; 1       ;
 ; Bank[3]                                                                                     ; 1       ;
 ; Bank[1]                                                                                     ; 1       ;
-; ARShift~0                                                                                   ; 1       ;
-; ARCLK~3                                                                                     ; 1       ;
-; ARCLK~2                                                                                     ; 1       ;
+; always9~5                                                                                   ; 1       ;
 ; ARCLK~0                                                                                     ; 1       ;
 ; CmdDRCLK                                                                                    ; 1       ;
-; DRCLK~0                                                                                     ; 1       ;
-; FS[6]~11COUT1_58                                                                            ; 1       ;
-; FS[6]~11                                                                                    ; 1       ;
-; FS[7]~9COUT1_60                                                                             ; 1       ;
-; FS[7]~9                                                                                     ; 1       ;
-; FS[16]~5COUT1_74                                                                            ; 1       ;
-; FS[16]~5                                                                                    ; 1       ;
-; FS[4]~3COUT1_54                                                                             ; 1       ;
-; FS[4]~3                                                                                     ; 1       ;
-; FS[5]~1COUT1_56                                                                             ; 1       ;
-; FS[5]~1                                                                                     ; 1       ;
-; CmdSubmitted                                                                                ; 1       ;
 ; CmdDRDIn                                                                                    ; 1       ;
 ; nRCAS~1                                                                                     ; 1       ;
 ; nRCAS~0                                                                                     ; 1       ;
@@ -729,10 +711,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; nRCS~4                                                                                      ; 1       ;
 ; nRCS~2                                                                                      ; 1       ;
 ; nRowColSel~1                                                                                ; 1       ;
+; FS[4]~11COUT1_54                                                                            ; 1       ;
+; FS[4]~11                                                                                    ; 1       ;
+; FS[6]~9COUT1_58                                                                             ; 1       ;
+; FS[6]~9                                                                                     ; 1       ;
+; FS[5]~7COUT1_56                                                                             ; 1       ;
+; FS[5]~7                                                                                     ; 1       ;
+; FS[7]~5COUT1_60                                                                             ; 1       ;
+; FS[7]~5                                                                                     ; 1       ;
+; FS[16]~1COUT1_74                                                                            ; 1       ;
+; FS[16]~1                                                                                    ; 1       ;
+; ARShift                                                                                     ; 1       ;
+; ARCLK                                                                                       ; 1       ;
+; DRShift                                                                                     ; 1       ;
 ; DRCLK                                                                                       ; 1       ;
 ; DRDIn                                                                                       ; 1       ;
+; comb~2                                                                                      ; 1       ;
 ; comb~1                                                                                      ; 1       ;
-; comb~0                                                                                      ; 1       ;
 ; nRCAS~reg0                                                                                  ; 1       ;
 ; nRRAS~reg0                                                                                  ; 1       ;
 ; nRWE~reg0                                                                                   ; 1       ;
@@ -761,6 +756,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; RowA[0]                                                                                     ; 1       ;
 ; RBA[1]~reg0                                                                                 ; 1       ;
 ; RBA[0]~reg0                                                                                 ; 1       ;
+; comb~0                                                                                      ; 1       ;
 +---------------------------------------------------------------------------------------------+---------+
 
 
@@ -769,64 +765,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------------+--------------------+
 ; Other Routing Resource Type ; Usage              ;
 +-----------------------------+--------------------+
-; C4s                         ; 152 / 784 ( 19 % ) ;
-; Direct links                ; 45 / 888 ( 5 % )   ;
+; C4s                         ; 126 / 784 ( 16 % ) ;
+; Direct links                ; 41 / 888 ( 5 % )   ;
 ; Global clocks               ; 4 / 4 ( 100 % )    ;
-; LAB clocks                  ; 15 / 32 ( 47 % )   ;
-; LUT chains                  ; 22 / 216 ( 10 % )  ;
-; Local interconnects         ; 270 / 888 ( 30 % ) ;
-; R4s                         ; 155 / 704 ( 22 % ) ;
+; LAB clocks                  ; 16 / 32 ( 50 % )   ;
+; LUT chains                  ; 17 / 216 ( 8 % )   ;
+; Local interconnects         ; 252 / 888 ( 28 % ) ;
+; R4s                         ; 134 / 704 ( 19 % ) ;
 +-----------------------------+--------------------+
 
 
 +---------------------------------------------------------------------------+
 ; LAB Logic Elements                                                        ;
 +--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 7.73) ; Number of LABs  (Total = 22) ;
+; Number of Logic Elements  (Average = 7.30) ; Number of LABs  (Total = 23) ;
 +--------------------------------------------+------------------------------+
-; 1                                          ; 0                            ;
-; 2                                          ; 2                            ;
-; 3                                          ; 2                            ;
-; 4                                          ; 2                            ;
-; 5                                          ; 0                            ;
-; 6                                          ; 1                            ;
-; 7                                          ; 0                            ;
-; 8                                          ; 2                            ;
+; 1                                          ; 2                            ;
+; 2                                          ; 3                            ;
+; 3                                          ; 0                            ;
+; 4                                          ; 1                            ;
+; 5                                          ; 1                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 1                            ;
+; 8                                          ; 3                            ;
 ; 9                                          ; 0                            ;
-; 10                                         ; 13                           ;
+; 10                                         ; 12                           ;
 +--------------------------------------------+------------------------------+
 
 
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.18) ; Number of LABs  (Total = 22) ;
+; LAB-wide Signals  (Average = 1.26) ; Number of LABs  (Total = 23) ;
 +------------------------------------+------------------------------+
-; 1 Clock                            ; 14                           ;
+; 1 Clock                            ; 17                           ;
 ; 1 Clock enable                     ; 2                            ;
-; 1 Sync. clear                      ; 3                            ;
+; 1 Sync. clear                      ; 4                            ;
 ; 1 Sync. load                       ; 1                            ;
-; 2 Clocks                           ; 6                            ;
+; 2 Clocks                           ; 5                            ;
 +------------------------------------+------------------------------+
 
 
 +----------------------------------------------------------------------------+
 ; LAB Signals Sourced                                                        ;
 +---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 7.91) ; Number of LABs  (Total = 22) ;
+; Number of Signals Sourced  (Average = 7.57) ; Number of LABs  (Total = 23) ;
 +---------------------------------------------+------------------------------+
 ; 0                                           ; 0                            ;
-; 1                                           ; 0                            ;
-; 2                                           ; 2                            ;
-; 3                                           ; 2                            ;
-; 4                                           ; 2                            ;
+; 1                                           ; 2                            ;
+; 2                                           ; 3                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 1                            ;
 ; 5                                           ; 0                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 0                            ;
-; 8                                           ; 1                            ;
-; 9                                           ; 1                            ;
-; 10                                          ; 11                           ;
-; 11                                          ; 1                            ;
+; 6                                           ; 0                            ;
+; 7                                           ; 2                            ;
+; 8                                           ; 3                            ;
+; 9                                           ; 0                            ;
+; 10                                          ; 9                            ;
+; 11                                          ; 2                            ;
 ; 12                                          ; 1                            ;
 +---------------------------------------------+------------------------------+
 
@@ -834,48 +830,47 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.73) ; Number of LABs  (Total = 22) ;
+; Number of Signals Sourced Out  (Average = 5.17) ; Number of LABs  (Total = 23) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 0                            ;
-; 1                                               ; 2                            ;
+; 1                                               ; 3                            ;
 ; 2                                               ; 2                            ;
-; 3                                               ; 3                            ;
-; 4                                               ; 2                            ;
-; 5                                               ; 0                            ;
-; 6                                               ; 4                            ;
-; 7                                               ; 2                            ;
-; 8                                               ; 1                            ;
-; 9                                               ; 3                            ;
-; 10                                              ; 3                            ;
+; 3                                               ; 0                            ;
+; 4                                               ; 4                            ;
+; 5                                               ; 3                            ;
+; 6                                               ; 3                            ;
+; 7                                               ; 4                            ;
+; 8                                               ; 2                            ;
+; 9                                               ; 1                            ;
+; 10                                              ; 1                            ;
 +-------------------------------------------------+------------------------------+
 
 
-+-----------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                         ;
-+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 10.18) ; Number of LABs  (Total = 22) ;
-+----------------------------------------------+------------------------------+
-; 0                                            ; 0                            ;
-; 1                                            ; 0                            ;
-; 2                                            ; 0                            ;
-; 3                                            ; 2                            ;
-; 4                                            ; 1                            ;
-; 5                                            ; 1                            ;
-; 6                                            ; 0                            ;
-; 7                                            ; 1                            ;
-; 8                                            ; 2                            ;
-; 9                                            ; 4                            ;
-; 10                                           ; 1                            ;
-; 11                                           ; 1                            ;
-; 12                                           ; 2                            ;
-; 13                                           ; 3                            ;
-; 14                                           ; 1                            ;
-; 15                                           ; 0                            ;
-; 16                                           ; 1                            ;
-; 17                                           ; 1                            ;
-; 18                                           ; 0                            ;
-; 19                                           ; 1                            ;
-+----------------------------------------------+------------------------------+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 9.04) ; Number of LABs  (Total = 23) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 2                            ;
+; 2                                           ; 1                            ;
+; 3                                           ; 3                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 0                            ;
+; 6                                           ; 1                            ;
+; 7                                           ; 3                            ;
+; 8                                           ; 1                            ;
+; 9                                           ; 2                            ;
+; 10                                          ; 1                            ;
+; 11                                          ; 0                            ;
+; 12                                          ; 1                            ;
+; 13                                          ; 2                            ;
+; 14                                          ; 2                            ;
+; 15                                          ; 1                            ;
+; 16                                          ; 1                            ;
+; 17                                          ; 1                            ;
+; 18                                          ; 1                            ;
++---------------------------------------------+------------------------------+
 
 
 +-------------------------------------------------------------------------+
@@ -920,8 +915,8 @@ Note: This table only shows the top 3 path(s) that have the largest delay added
 +-----------------+
 ; Fitter Messages ;
 +-----------------+
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (119006): Selected device EPM240T100C5 for design "RAM4GS"
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EPM240T100C5 for design "RAM2GS"
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
 Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
@@ -932,7 +927,9 @@ Info (176444): Device migration not selected. If you intend to use device migrat
     Info (176445): Device EPM570T100C5 is compatible
     Info (176445): Device EPM570T100I5 is compatible
     Info (176445): Device EPM570T100A5 is compatible
-Info (332104): Reading SDC File: 'constraints.sdc'
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins
+    Info (169086): Pin LED not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332144): No user constrained base clocks found in the design
 Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
     Info (332127): Assuming a default timing requirement
@@ -951,11 +948,12 @@ Info (186216): Automatically promoted some destinations of signal "PHI2" to use
     Info (186217): Destination "PHI2r" may be non-global or may not use global clock
 Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position
 Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock
+    Info (186217): Destination "comb~0" may be non-global or may not use global clock
     Info (186217): Destination "RASr" may be non-global or may not use global clock
 Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position
 Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock
     Info (186217): Destination "CBR" may be non-global or may not use global clock
-    Info (186217): Destination "comb~2" may be non-global or may not use global clock
+    Info (186217): Destination "comb~3" may be non-global or may not use global clock
     Info (186217): Destination "CASr" may be non-global or may not use global clock
 Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position
 Info (186079): Completed Auto Global Promotion Operation
@@ -964,6 +962,13 @@ Info (186391): Fitter is using Normal packing mode for logic elements with Auto
 Info (186468): Started processing fast register assignments
 Info (186469): Finished processing fast register assignments
 Info (176235): Finished register packing
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  18 pins available
 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -971,23 +976,23 @@ Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
 Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 20% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170195): Router estimated average interconnect usage is 18% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings
-    Info: Peak virtual memory: 376 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:50 2020
-    Info: Elapsed time: 00:00:08
-    Info: Total CPU time (on all processors): 00:00:08
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 548 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:16 2021
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:03
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg.
 
 
diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.smsg b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/output_files/RAM4GS.fit.smsg
rename to CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary
new file mode 100644
index 0000000..6659118
--- /dev/null
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.fit.summary
@@ -0,0 +1,11 @@
+Fitter Status : Successful - Mon Aug 16 18:40:16 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX II
+Device : EPM240T100C5
+Timing Models : Final
+Total logic elements : 168 / 240 ( 70 % )
+Total pins : 63 / 80 ( 79 % )
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM4GS.flow.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt
old mode 100755
new mode 100644
similarity index 57%
rename from CPLD/MAXII/output_files/RAM4GS.flow.rpt
rename to CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt
index cab50ca..cd5d6a1
--- a/CPLD/MAXII/output_files/RAM4GS.flow.rpt
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.flow.rpt
@@ -1,6 +1,6 @@
-Flow report for RAM4GS
-Thu Jul 23 02:21:02 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Flow report for RAM2GS
+Mon Aug 16 18:40:19 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -40,15 +40,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Flow Summary                                                                ;
 +---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Thu Jul 23 02:20:55 2020           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM4GS                                          ;
-; Top-level Entity Name     ; RAM4GS                                          ;
+; Flow Status               ; Successful - Mon Aug 16 18:40:17 2021           ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; RAM2GS                                          ;
+; Top-level Entity Name     ; RAM2GS                                          ;
 ; Family                    ; MAX II                                          ;
 ; Device                    ; EPM240T100C5                                    ;
 ; Timing Models             ; Final                                           ;
-; Total logic elements      ; 170 / 240 ( 71 % )                              ;
-; Total pins                ; 62 / 80 ( 78 % )                                ;
+; Total logic elements      ; 168 / 240 ( 70 % )                              ;
+; Total pins                ; 63 / 80 ( 79 % )                                ;
 ; Total virtual pins        ; 0                                               ;
 ; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
 +---------------------------+-------------------------------------------------+
@@ -59,34 +59,34 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 07/23/2020 02:20:37 ;
+; Start date & time ; 08/16/2021 18:40:12 ;
 ; Main task         ; Compilation         ;
-; Revision Name     ; RAM4GS              ;
+; Revision Name     ; RAM2GS              ;
 +-------------------+---------------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                       ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
-; Assignment Name                            ; Value                          ; Default Value ; Entity Name ; Section Id ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
-; ALLOW_POWER_UP_DONT_CARE                   ; Off                            ; On            ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                      ; 44085571633675.159548523602288 ; --            ; --          ; --         ;
-; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                             ; Off           ; --          ; --         ;
-; FITTER_EFFORT                              ; Standard Fit                   ; Auto Fit      ; --          ; --         ;
-; IP_TOOL_NAME                               ; ALTUFM_NONE                    ; --            ; --          ; --         ;
-; IP_TOOL_VERSION                            ; 13.0                           ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                     ; 85                             ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                     ; 0                              ; --            ; --          ; --         ;
-; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers          ; Normal        ; --          ; --         ;
-; OPTIMIZE_MULTI_CORNER_TIMING               ; On                             ; Off           ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                ; 10                             ; 1.0           ; --          ; --         ;
-; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                         ; 12.5%         ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                   ; output_files                   ; --            ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                   ; 10                             ; 1.0           ; --          ; --         ;
-; SAFE_STATE_MACHINE                         ; On                             ; Off           ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                            ; --            ; --          ; --         ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                            ; Value                        ; Default Value ; Entity Name ; Section Id ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
+; ALLOW_POWER_UP_DONT_CARE                   ; Off                          ; On            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                      ; 962837114763.162915361100164 ; --            ; --          ; --         ;
+; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                           ; Off           ; --          ; --         ;
+; FITTER_EFFORT                              ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
+; IP_TOOL_NAME                               ; ALTUFM_NONE                  ; --            ; --          ; --         ;
+; IP_TOOL_VERSION                            ; 13.0                         ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                     ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                     ; 0                            ; --            ; --          ; --         ;
+; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers        ; Normal        ; --          ; --         ;
+; OPTIMIZE_MULTI_CORNER_TIMING               ; On                           ; Off           ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                ; 10                           ; 1.0           ; --          ; --         ;
+; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                       ; 12.5%         ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                   ; output_files                 ; --            ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                   ; 10                           ; 1.0           ; --          ; --         ;
+; SAFE_STATE_MACHINE                         ; On                           ; Off           ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                          ; --            ; --          ; --         ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
 
 
 +-------------------------------------------------------------------------------------------------------------------------------+
@@ -94,33 +94,33 @@ applicable agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:05     ; 1.0                     ; 303 MB              ; 00:00:05                           ;
-; Fitter                    ; 00:00:08     ; 1.3                     ; 376 MB              ; 00:00:07                           ;
-; Assembler                 ; 00:00:02     ; 1.0                     ; 295 MB              ; 00:00:02                           ;
-; TimeQuest Timing Analyzer ; 00:00:05     ; 1.0                     ; 288 MB              ; 00:00:04                           ;
-; Total                     ; 00:00:20     ; --                      ; --                  ; 00:00:18                           ;
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 421 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:03     ; 1.0                     ; 548 MB              ; 00:00:03                           ;
+; Assembler                 ; 00:00:00     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 374 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:05     ; --                      ; --                  ; 00:00:06                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis      ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; Fitter                    ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; Assembler                 ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; TimeQuest Timing Analyzer ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-+---------------------------+------------------+------------+------------+----------------+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
 
 
 ------------
 ; Flow Log ;
 ------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
-quartus_sta RAM4GS -c RAM4GS
+quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+quartus_sta RAM2GS-MAXII -c RAM2GS
 
 
 
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.jdi b/CPLD/MAX/MAXII/output_files/RAM2GS.jdi
new file mode 100644
index 0000000..8f5f174
--- /dev/null
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.jdi
@@ -0,0 +1,8 @@
+
+  
+    
+  
+  
+    
+  
+
diff --git a/CPLD/MAXII/output_files/RAM4GS.map.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt
old mode 100755
new mode 100644
similarity index 80%
rename from CPLD/MAXII/output_files/RAM4GS.map.rpt
rename to CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt
index 9d88205..d013013
--- a/CPLD/MAXII/output_files/RAM4GS.map.rpt
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.rpt
@@ -1,6 +1,6 @@
-Analysis & Synthesis report for RAM4GS
-Thu Jul 23 02:20:40 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Analysis & Synthesis report for RAM2GS
+Mon Aug 16 18:40:12 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -45,13 +45,13 @@ applicable agreement for further details.
 +-------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                  ;
 +-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020           ;
-; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name               ; RAM4GS                                          ;
-; Top-level Entity Name       ; RAM4GS                                          ;
+; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:12 2021           ;
+; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name               ; RAM2GS                                          ;
+; Top-level Entity Name       ; RAM2GS                                          ;
 ; Family                      ; MAX II                                          ;
-; Total logic elements        ; 178                                             ;
-; Total pins                  ; 62                                              ;
+; Total logic elements        ; 177                                             ;
+; Total pins                  ; 63                                              ;
 ; Total virtual pins          ; 0                                               ;
 ; UFM blocks                  ; 1 / 1 ( 100 % )                                 ;
 +-----------------------------+-------------------------------------------------+
@@ -63,7 +63,7 @@ applicable agreement for further details.
 ; Option                                                                     ; Setting            ; Default Value      ;
 +----------------------------------------------------------------------------+--------------------+--------------------+
 ; Device                                                                     ; EPM240T100C5       ;                    ;
-; Top-level entity name                                                      ; RAM4GS             ; RAM4GS             ;
+; Top-level entity name                                                      ; RAM2GS             ; RAM2GS             ;
 ; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
 ; Safe State Machine                                                         ; On                 ; Off                ;
 ; Power-Up Don't Care                                                        ; Off                ; On                 ;
@@ -130,32 +130,25 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------+--------------------+
 
 
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 2           ;
-; Maximum allowed            ; 2           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                      ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                              ; Library ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; RAM4GS.v                         ; yes             ; User Verilog HDL File            ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v   ;         ;
-; RAM4GS.mif                       ; yes             ; User Memory Initialization File  ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v      ;         ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                  ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                   ; File Name with Absolute Path                               ; Library ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
+; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File       ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ;         ;
+; UFM.v                            ; yes             ; User Wizard-Generated File  ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v  ;         ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -163,32 +156,32 @@ applicable agreement for further details.
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 178   ;
-;     -- Combinational with no register       ; 82    ;
+; Total logic elements                        ; 177   ;
+;     -- Combinational with no register       ; 80    ;
 ;     -- Register only                        ; 29    ;
-;     -- Combinational with a register        ; 67    ;
+;     -- Combinational with a register        ; 68    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 57    ;
-;     -- 3 input functions                    ; 41    ;
-;     -- 2 input functions                    ; 42    ;
+;     -- 4 input functions                    ; 58    ;
+;     -- 3 input functions                    ; 40    ;
+;     -- 2 input functions                    ; 41    ;
 ;     -- 1 input functions                    ; 8     ;
 ;     -- 0 input functions                    ; 1     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 162   ;
+;     -- normal mode                          ; 161   ;
 ;     -- arithmetic mode                      ; 16    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
 ;     -- synchronous clear/load mode          ; 9     ;
 ;     -- asynchronous clear/load mode         ; 0     ;
 ;                                             ;       ;
-; Total registers                             ; 96    ;
+; Total registers                             ; 97    ;
 ; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 62    ;
+; I/O pins                                    ; 63    ;
 ; UFM blocks                                  ; 1     ;
 ; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 54    ;
+; Maximum fan-out                             ; 55    ;
 ; Total fan-out                               ; 643   ;
 ; Average fan-out                             ; 2.67  ;
 +---------------------------------------------+-------+
@@ -199,20 +192,20 @@ applicable agreement for further details.
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 ; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM4GS                                                   ; 178 (178)   ; 96           ; 1          ; 62   ; 0            ; 82 (82)      ; 29 (29)           ; 67 (67)          ; 17 (17)         ; 0 (0)      ; |RAM4GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work         ;
+; |RAM2GS                                                   ; 177 (177)   ; 97           ; 1          ; 63   ; 0            ; 80 (80)      ; 29 (29)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
+;       |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work         ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                                                       ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                      ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
-; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                            ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                           ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
+; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
 
 
 +------------------------------------------------------+
@@ -220,7 +213,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 96    ;
+; Total registers                              ; 97    ;
 ; Number of registers using Synchronous Clear  ; 6     ;
 ; Number of registers using Synchronous Load   ; 3     ;
 ; Number of registers using Asynchronous Clear ; 0     ;
@@ -248,8 +241,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|S[0]               ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|C1Submitted        ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[0]               ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|ADSubmitted        ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 
 
@@ -269,22 +262,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Analysis & Synthesis Messages ;
 +-------------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
+Info: Running Quartus II 64-Bit Analysis & Synthesis
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Thu Jul 23 02:20:35 2020
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v
-    Info (12023): Found entity 1: RAM4GS
+    Info: Processing started: Mon Aug 16 18:40:11 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v
+    Info (12023): Found entity 1: RAM2GS
 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_1br
+    Info (12023): Found entity 1: UFM_altufm_none_imr
     Info (12023): Found entity 2: UFM
-Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)
+Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)
 Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
-Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component"
+Info (12128): Elaborating entity "UFM_altufm_none_imr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component"
+Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0
 Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
 Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
 Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
@@ -295,21 +289,21 @@ Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot
 Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
 Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 29 output pins
+    Info (21059): Implemented 30 output pins
     Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 178 logic cells
+    Info (21061): Implemented 177 logic cells
     Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 303 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:41 2020
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:05
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings
+    Info: Peak virtual memory: 421 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:12 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg.
 
 
diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.smsg b/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg
old mode 100755
new mode 100644
similarity index 71%
rename from CPLD/AGM-src/output_files/RAM4GS.map.smsg
rename to CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg
index 4c14264..a8e8eb9
--- a/CPLD/AGM-src/output_files/RAM4GS.map.smsg
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM4GS.v(52): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z"
 Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
 Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary
new file mode 100644
index 0000000..4c4a5bb
--- /dev/null
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.map.summary
@@ -0,0 +1,9 @@
+Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:12 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX II
+Total logic elements : 177
+Total pins : 63
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/AGM-src/output_files/RAM4GS.pin b/CPLD/MAX/MAXII/output_files/RAM2GS.pin
old mode 100755
new mode 100644
similarity index 98%
rename from CPLD/AGM-src/output_files/RAM4GS.pin
rename to CPLD/MAX/MAXII/output_files/RAM2GS.pin
index 86ba0f4..4acd586
--- a/CPLD/AGM-src/output_files/RAM4GS.pin
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.pin
@@ -57,8 +57,8 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP  "RAM4GS"  ASSIGNED TO AN: EPM240T100C5
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "RAM2GS"  ASSIGNED TO AN: EPM240T100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
@@ -127,7 +127,7 @@ GND*                         : 62        :        :                   :
 VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
 GND*                         : 64        :        :                   :         : 2         :                
 GNDINT                       : 65        : gnd    :                   :         :           :                
-GND*                         : 66        :        :                   :         : 2         :                
+LED                          : 66        : output : 3.3-V LVTTL       :         : 2         : N              
 nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
 MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
 MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.pof b/CPLD/MAX/MAXII/output_files/RAM2GS.pof
new file mode 100644
index 0000000..f288ab0
Binary files /dev/null and b/CPLD/MAX/MAXII/output_files/RAM2GS.pof differ
diff --git a/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt
new file mode 100644
index 0000000..b9aa2bf
--- /dev/null
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.rpt
@@ -0,0 +1,1576 @@
+TimeQuest Timing Analyzer report for RAM2GS
+Mon Aug 16 18:40:19 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Fmax Summary
+  6. Setup Summary
+  7. Hold Summary
+  8. Recovery Summary
+  9. Removal Summary
+ 10. Minimum Pulse Width Summary
+ 11. Setup: 'ARCLK'
+ 12. Setup: 'DRCLK'
+ 13. Setup: 'RCLK'
+ 14. Setup: 'PHI2'
+ 15. Setup: 'nCRAS'
+ 16. Hold: 'ARCLK'
+ 17. Hold: 'DRCLK'
+ 18. Hold: 'nCRAS'
+ 19. Hold: 'PHI2'
+ 20. Hold: 'RCLK'
+ 21. Minimum Pulse Width: 'ARCLK'
+ 22. Minimum Pulse Width: 'DRCLK'
+ 23. Minimum Pulse Width: 'PHI2'
+ 24. Minimum Pulse Width: 'RCLK'
+ 25. Minimum Pulse Width: 'nCCAS'
+ 26. Minimum Pulse Width: 'nCRAS'
+ 27. Setup Times
+ 28. Hold Times
+ 29. Clock to Output Times
+ 30. Minimum Clock to Output Times
+ 31. Propagation Delay
+ 32. Minimum Propagation Delay
+ 33. Output Enable Times
+ 34. Minimum Output Enable Times
+ 35. Output Disable Times
+ 36. Minimum Output Disable Times
+ 37. Setup Transfers
+ 38. Hold Transfers
+ 39. Report TCCS
+ 40. Report RSKM
+ 41. Unconstrained Paths
+ 42. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                      ;
++--------------------+-------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
+; Revision Name      ; RAM2GS                                                            ;
+; Device Family      ; MAX II                                                            ;
+; Device Name        ; EPM240T100C5                                                      ;
+; Timing Models      ; Final                                                             ;
+; Delay Model        ; Slow Model                                                        ;
+; Rise/Fall Delays   ; Unavailable                                                       ;
++--------------------+-------------------------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                            ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; ARCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
+; DRCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
+; nCCAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
+; nCRAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
+; PHI2       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
+; RCLK       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+
+
++--------------------------------------------------+
+; Fmax Summary                                     ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 10.0 MHz   ; 10.0 MHz        ; ARCLK      ;      ;
+; 10.0 MHz   ; 10.0 MHz        ; DRCLK      ;      ;
+; 57.01 MHz  ; 57.01 MHz       ; PHI2       ;      ;
+; 121.57 MHz ; 121.57 MHz      ; RCLK       ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++---------------------------------+
+; Setup Summary                   ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -99.000 ; -99.000       ;
+; DRCLK ; -99.000 ; -99.000       ;
+; RCLK  ; -8.339  ; -245.761      ;
+; PHI2  ; -8.271  ; -88.383       ;
+; nCRAS ; -0.317  ; -2.784        ;
++-------+---------+---------------+
+
+
++---------------------------------+
+; Hold Summary                    ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -16.858 ; -16.858       ;
+; DRCLK ; -16.363 ; -16.363       ;
+; nCRAS ; -0.103  ; -0.195        ;
+; PHI2  ; -0.060  ; -0.060        ;
+; RCLK  ; 1.192   ; 0.000         ;
++-------+---------+---------------+
+
+
+--------------------
+; Recovery Summary ;
+--------------------
+No paths to report.
+
+
+-------------------
+; Removal Summary ;
+-------------------
+No paths to report.
+
+
++---------------------------------+
+; Minimum Pulse Width Summary     ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -29.500 ; -59.000       ;
+; DRCLK ; -29.500 ; -59.000       ;
+; PHI2  ; -2.289  ; -2.289        ;
+; RCLK  ; -2.289  ; -2.289        ;
+; nCCAS ; -2.289  ; -2.289        ;
+; nCRAS ; -2.289  ; -2.289        ;
++-------+---------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 1.000        ; 0.000      ; 80.000     ;
+; -22.142 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 1.000        ; -1.613     ; 1.529      ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 1.000        ; 0.000      ; 80.000     ;
+; -22.699 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -1.595     ; 2.104      ;
+; -22.637 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -1.595     ; 2.042      ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'RCLK'                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; -8.339 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 5.262      ;
+; -7.863 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.786      ;
+; -7.540 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 5.138      ;
+; -7.536 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 5.134      ;
+; -7.431 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.354      ;
+; -7.397 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.320      ;
+; -7.226 ; FS[12]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.893      ;
+; -7.147 ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.814      ;
+; -7.078 ; FS[11]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.745      ;
+; -7.033 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.631      ;
+; -7.000 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.598      ;
+; -6.983 ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.650      ;
+; -6.966 ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.633      ;
+; -6.929 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.527      ;
+; -6.898 ; FS[13]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.565      ;
+; -6.794 ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.461      ;
+; -6.759 ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.426      ;
+; -6.748 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.346      ;
+; -6.664 ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.331      ;
+; -6.657 ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.324      ;
+; -6.657 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.255      ;
+; -6.654 ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.321      ;
+; -6.621 ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.288      ;
+; -6.620 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 3.543      ;
+; -6.611 ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.278      ;
+; -6.559 ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.226      ;
+; -6.552 ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.219      ;
+; -6.549 ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.216      ;
+; -6.541 ; FS[10]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.208      ;
+; -6.499 ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.166      ;
+; -6.451 ; FS[7]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.118      ;
+; -6.444 ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.111      ;
+; -6.441 ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.108      ;
+; -6.431 ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.098      ;
+; -6.416 ; IS[0]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.083      ;
+; -6.389 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.987      ;
+; -6.373 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 8.635      ;
+; -6.359 ; FS[16]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.026      ;
+; -6.351 ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.018      ;
+; -6.312 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 3.235      ;
+; -6.282 ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.949      ;
+; -6.257 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.855      ;
+; -6.254 ; FS[17]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.921      ;
+; -6.250 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.848      ;
+; -6.203 ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.870      ;
+; -6.195 ; FS[16]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.862      ;
+; -6.159 ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.826      ;
+; -6.146 ; FS[7]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.813      ;
+; -6.099 ; RCKE~reg0                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.766      ;
+; -6.090 ; FS[17]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.757      ;
+; -6.074 ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.741      ;
+; -6.054 ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.721      ;
+; -6.023 ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.690      ;
+; -5.982 ; FS[7]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.649      ;
+; -5.946 ; FS[7]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.613      ;
+; -5.885 ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.552      ;
+; -5.827 ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.494      ;
+; -5.783 ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.450      ;
+; -5.753 ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.420      ;
+; -5.751 ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.418      ;
+; -5.703 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 7.965      ;
+; -5.684 ; FS[2]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.351      ;
+; -5.666 ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.333      ;
+; -5.664 ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.331      ;
+; -5.663 ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.330      ;
+; -5.657 ; FS[6]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.324      ;
+; -5.655 ; FS[4]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.322      ;
+; -5.650 ; FS[6]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.317      ;
+; -5.648 ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.315      ;
+; -5.647 ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.314      ;
+; -5.645 ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.312      ;
+; -5.626 ; FS[6]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.293      ;
+; -5.604 ; FS[14]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.271      ;
+; -5.594 ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.261      ;
+; -5.578 ; Ready                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.245      ;
+; -5.571 ; Ready                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.238      ;
+; -5.568 ; Ready                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.235      ;
+; -5.558 ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.225      ;
+; -5.555 ; UFMInitDone                                                                                 ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.222      ;
+; -5.552 ; FS[0]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.219      ;
+; -5.548 ; UFMInitDone                                                                                 ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.215      ;
+; -5.545 ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.212      ;
+; -5.544 ; S[0]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.211      ;
+; -5.535 ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.202      ;
+; -5.451 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFMD[15]    ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 7.713      ;
+; -5.438 ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.105      ;
+; -5.430 ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.097      ;
+; -5.398 ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.065      ;
+; -5.395 ; Ready                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.062      ;
+; -5.386 ; RASr2                                                                                       ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.053      ;
+; -5.363 ; FS[5]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.030      ;
+; -5.357 ; FS[3]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.024      ;
+; -5.356 ; FS[5]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.023      ;
+; -5.353 ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.020      ;
+; -5.345 ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.012      ;
+; -5.333 ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.000      ;
+; -5.332 ; FS[5]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.999      ;
+; -5.329 ; FS[4]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.996      ;
+; -5.329 ; FS[6]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.996      ;
+; -5.325 ; FS[15]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.992      ;
++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2'                                                                                             ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -8.271 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
+; -8.271 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
+; -8.271 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
+; -8.271 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
+; -8.251 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
+; -8.115 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
+; -8.115 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
+; -8.115 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
+; -8.115 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
+; -8.095 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.262      ;
+; -7.799 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.966      ;
+; -7.799 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.966      ;
+; -7.643 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.810      ;
+; -7.643 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.810      ;
+; -7.577 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
+; -7.577 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
+; -7.577 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
+; -7.577 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
+; -7.557 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.724      ;
+; -7.105 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.272      ;
+; -7.105 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.272      ;
+; -7.088 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.255      ;
+; -7.088 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.255      ;
+; -7.075 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
+; -7.075 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
+; -7.075 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
+; -7.075 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
+; -7.055 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.222      ;
+; -7.054 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
+; -7.054 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
+; -7.054 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
+; -7.054 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
+; -7.034 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.201      ;
+; -6.998 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.165      ;
+; -6.932 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.099      ;
+; -6.932 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.099      ;
+; -6.900 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
+; -6.900 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
+; -6.900 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
+; -6.900 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
+; -6.880 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.047      ;
+; -6.872 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.039      ;
+; -6.842 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.009      ;
+; -6.716 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.883      ;
+; -6.603 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.770      ;
+; -6.603 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.770      ;
+; -6.582 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.749      ;
+; -6.582 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.749      ;
+; -6.428 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.595      ;
+; -6.428 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.595      ;
+; -6.394 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.561      ;
+; -6.394 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.561      ;
+; -6.362 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
+; -6.362 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
+; -6.362 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
+; -6.362 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
+; -6.342 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.509      ;
+; -6.304 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.471      ;
+; -6.178 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.345      ;
+; -5.892 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.059      ;
+; -5.892 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.059      ;
+; -5.890 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.057      ;
+; -5.890 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.057      ;
+; -5.871 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.038      ;
+; -5.871 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.038      ;
+; -5.847 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
+; -5.847 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
+; -5.847 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
+; -5.847 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
+; -5.827 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.994      ;
+; -5.802 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.969      ;
+; -5.781 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.948      ;
+; -5.717 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.884      ;
+; -5.717 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.884      ;
+; -5.676 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.843      ;
+; -5.655 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.822      ;
+; -5.627 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.794      ;
+; -5.501 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.668      ;
+; -5.375 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.542      ;
+; -5.375 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.542      ;
+; -5.179 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.346      ;
+; -5.179 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.346      ;
+; -5.089 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.256      ;
+; -4.963 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.130      ;
+; -4.664 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.831      ;
+; -4.664 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.831      ;
+; -4.574 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.741      ;
+; -4.448 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.615      ;
+; -4.234 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.901      ;
+; -4.234 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.901      ;
+; -3.754 ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.421      ;
+; -3.695 ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.362      ;
+; -3.674 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
+; -3.674 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
+; -3.674 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
+; -3.674 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
+; -3.404 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 3.571      ;
+; -3.307 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.974      ;
+; -3.297 ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.964      ;
+; -2.824 ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.491      ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Setup: 'nCRAS'                                                                                         ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -0.317 ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.053      ;
+; -0.311 ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.047      ;
+; -0.310 ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.046      ;
+; -0.277 ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.013      ;
+; -0.276 ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.012      ;
+; -0.275 ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.011      ;
+; -0.267 ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.003      ;
+; -0.253 ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.989      ;
+; -0.252 ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.988      ;
+; -0.246 ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.982      ;
+; 0.038  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.500        ; 5.917      ; 6.046      ;
+; 0.079  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.657      ;
+; 0.538  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 1.000        ; 5.917      ; 6.046      ;
+; 0.549  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.187      ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.858 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -1.613     ; 1.529      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.363 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -1.595     ; 2.042      ;
+; -16.301 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -1.595     ; 2.104      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS'                                                                                          ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -0.103 ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.187      ;
+; -0.092 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 5.917      ; 6.046      ;
+; 0.367  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.657      ;
+; 0.408  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -0.500       ; 5.917      ; 6.046      ;
+; 0.692  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.982      ;
+; 0.698  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.988      ;
+; 0.699  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.989      ;
+; 0.713  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.003      ;
+; 0.721  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.011      ;
+; 0.722  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.012      ;
+; 0.723  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.013      ;
+; 0.756  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.046      ;
+; 0.757  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.047      ;
+; 0.763  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.053      ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Hold: 'PHI2'                                                                                              ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -0.060 ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.244      ; 3.405      ;
+; 0.172  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -0.500       ; 3.244      ; 3.137      ;
+; 0.206  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.244      ; 3.671      ;
+; 2.578  ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.799      ;
+; 2.676  ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.897      ;
+; 3.054  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.275      ;
+; 3.270  ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.491      ;
+; 3.565  ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.286      ;
+; 3.566  ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.287      ;
+; 3.743  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.964      ;
+; 3.753  ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.974      ;
+; 3.850  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.571      ;
+; 4.080  ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.801      ;
+; 4.081  ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.802      ;
+; 4.120  ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
+; 4.120  ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
+; 4.120  ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
+; 4.120  ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
+; 4.141  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.362      ;
+; 4.200  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.421      ;
+; 4.618  ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.339      ;
+; 4.619  ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.340      ;
+; 4.680  ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.901      ;
+; 4.680  ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.901      ;
+; 4.772  ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.493      ;
+; 4.773  ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.494      ;
+; 4.774  ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.495      ;
+; 4.793  ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.514      ;
+; 4.794  ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.515      ;
+; 4.894  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.615      ;
+; 5.025  ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.746      ;
+; 5.289  ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.010      ;
+; 5.295  ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.016      ;
+; 5.296  ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.017      ;
+; 5.409  ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.130      ;
+; 5.540  ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.261      ;
+; 5.821  ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.542      ;
+; 5.821  ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.542      ;
+; 5.827  ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.548      ;
+; 5.833  ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.554      ;
+; 5.834  ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.555      ;
+; 5.947  ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.668      ;
+; 5.981  ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.702      ;
+; 5.989  ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.710      ;
+; 5.990  ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.711      ;
+; 6.002  ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.723      ;
+; 6.078  ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.799      ;
+; 6.101  ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.822      ;
+; 6.122  ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.843      ;
+; 6.232  ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.953      ;
+; 6.253  ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.974      ;
+; 6.293  ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
+; 6.293  ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
+; 6.293  ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
+; 6.293  ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
+; 6.336  ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.057      ;
+; 6.336  ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.057      ;
+; 6.504  ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.225      ;
+; 6.624  ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.345      ;
+; 6.755  ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.476      ;
+; 6.808  ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
+; 6.808  ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
+; 6.808  ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
+; 6.808  ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
+; 6.874  ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.595      ;
+; 6.874  ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.595      ;
+; 7.028  ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.749      ;
+; 7.028  ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.749      ;
+; 7.042  ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.763      ;
+; 7.049  ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.770      ;
+; 7.049  ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.770      ;
+; 7.162  ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.883      ;
+; 7.198  ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.919      ;
+; 7.293  ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.014      ;
+; 7.318  ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.039      ;
+; 7.346  ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
+; 7.346  ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
+; 7.346  ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
+; 7.346  ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
+; 7.449  ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.170      ;
+; 7.500  ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
+; 7.500  ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
+; 7.500  ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
+; 7.500  ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
+; 7.521  ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
+; 7.521  ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
+; 7.521  ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
+; 7.521  ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
+; 7.551  ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.272      ;
+; 7.551  ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.272      ;
+; 8.023  ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
+; 8.023  ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
+; 8.023  ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
+; 8.023  ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
+; 8.089  ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.810      ;
+; 8.089  ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.810      ;
+; 8.245  ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.966      ;
+; 8.245  ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.966      ;
+; 8.561  ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.282      ;
+; 8.561  ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.282      ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK'                                                                                            ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 1.192 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 3.348      ; 4.761      ;
+; 1.245 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 3.348      ; 4.814      ;
+; 1.338 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 3.348      ; 4.907      ;
+; 1.659 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.880      ;
+; 1.692 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -0.500       ; 3.348      ; 4.761      ;
+; 1.693 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.914      ;
+; 1.703 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.924      ;
+; 1.704 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.925      ;
+; 1.706 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.927      ;
+; 1.745 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -0.500       ; 3.348      ; 4.814      ;
+; 1.809 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.030      ;
+; 1.829 ; CASr2       ; CASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.050      ;
+; 1.838 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -0.500       ; 3.348      ; 4.907      ;
+; 1.952 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.173      ;
+; 1.961 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.182      ;
+; 1.966 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.187      ;
+; 2.108 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.329      ;
+; 2.116 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.117 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.124 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.345      ;
+; 2.126 ; UFMD[15]    ; UFMD[15]    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.143 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.364      ;
+; 2.144 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.144 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.145 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.366      ;
+; 2.148 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.369      ;
+; 2.151 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.372      ;
+; 2.160 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.381      ;
+; 2.164 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.385      ;
+; 2.215 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.436      ;
+; 2.230 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.230 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.239 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.239 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.239 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.239 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.241 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.242 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
+; 2.250 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
+; 2.250 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
+; 2.267 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.488      ;
+; 2.270 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.491      ;
+; 2.271 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.492      ;
+; 2.282 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.503      ;
+; 2.332 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.553      ;
+; 2.385 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.606      ;
+; 2.395 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.616      ;
+; 2.414 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.635      ;
+; 2.596 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.817      ;
+; 2.605 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.826      ;
+; 2.647 ; RASr        ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.868      ;
+; 2.674 ; PHI2r2      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.895      ;
+; 2.689 ; S[0]        ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.910      ;
+; 2.704 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.925      ;
+; 2.741 ; Ready       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.962      ;
+; 2.744 ; Ready       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.965      ;
+; 2.748 ; Ready       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.969      ;
+; 2.797 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.018      ;
+; 2.799 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.020      ;
+; 2.825 ; RASr2       ; RASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.046      ;
+; 2.939 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.160      ;
+; 2.940 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
+; 2.948 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.169      ;
+; 2.949 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.974 ; Ready       ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.195      ;
+; 2.976 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
+; 2.976 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
+; 2.996 ; FS[0]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.217      ;
+; 3.051 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.272      ;
+; 3.059 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.280      ;
+; 3.060 ; CASr        ; CASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.076 ; CASr3       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.297      ;
+; 3.087 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
+; 3.087 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
+; 3.089 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.310      ;
+; 3.106 ; PHI2r2      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.327      ;
+; 3.107 ; FS[0]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.328      ;
+; 3.112 ; FS[17]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.333      ;
+; 3.117 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.338      ;
+; 3.161 ; S[0]        ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.382      ;
+; 3.170 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
+; 3.170 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
+; 3.174 ; RASr2       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.395      ;
+; 3.179 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.179 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.179 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.179 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
+; 3.181 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.402      ;
+; 3.182 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.403      ;
+; 3.184 ; Ready       ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.405      ;
+; 3.198 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.419      ;
+; 3.199 ; IS[0]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.420      ;
+; 3.201 ; InitReady   ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.422      ;
+; 3.226 ; Ready       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.447      ;
+; 3.257 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.478      ;
+; 3.281 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
+; 3.285 ; RASr2       ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.506      ;
+; 3.289 ; RASr2       ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.510      ;
+; 3.290 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'ARCLK'                                                                                                                                                              ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                                  ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
+; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk                                           ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk                                           ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'DRCLK'                                                                                                                                                  ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                      ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ;
+; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk                               ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk                               ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'PHI2'                                                                       ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target           ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; PHI2  ; Rise       ; PHI2             ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; ADSubmitted      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; ADSubmitted      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]          ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; C1Submitted      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; C1Submitted      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRCLK         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRCLK         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRDIn         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRDIn         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdEnable        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdEnable        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdSubmitted     ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdSubmitted     ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMErase      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMErase      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMPrgm       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMPrgm       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; RA11             ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11             ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; UFMOscEN         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; UFMOscEN         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; XOR8MEG          ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; XOR8MEG          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; ADSubmitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; ADSubmitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; C1Submitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; C1Submitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdEnable|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdEnable|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdSubmitted|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdSubmitted|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; PHI2|combout     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; PHI2|combout     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; RA11|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; UFMOscEN|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; UFMOscEN|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; XOR8MEG|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; XOR8MEG|clk      ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'RCLK'                                                                  ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; RCLK  ; Rise       ; RCLK        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARCLK       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARCLK       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARShift     ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARShift     ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr2       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr2       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr3       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr3       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRCLK       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRCLK       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRDIn       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRDIn       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRShift     ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRShift     ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[0]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[0]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[10]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[10]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[11]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[11]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[12]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[12]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[13]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[13]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[14]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[14]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[15]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[15]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[16]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[16]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[17]      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[17]      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[1]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[1]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[2]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[2]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[3]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[3]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[4]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[4]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[5]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[5]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[6]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[6]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[7]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[7]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[8]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[8]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[9]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[9]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[0]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[0]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[1]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[1]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[2]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[2]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[3]       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[3]       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; InitReady   ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; InitReady   ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; LEDEN       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; LEDEN       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r2      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r2      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r3      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r3      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RA10        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RA10        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr2       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr2       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr3       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr3       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKEEN      ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKEEN      ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKE~reg0   ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKE~reg0   ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; Ready       ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; Ready       ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[0]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[0]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[1]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[1]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMD[15]    ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMD[15]    ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMErase    ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMErase    ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMInitDone ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMInitDone ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMProgram  ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMProgram  ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMReqErase ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMReqErase ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; n8MEGEN     ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'nCCAS'                                                                   ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCCAS ; Rise       ; nCCAS         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[0]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[0]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[1]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[1]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[2]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[2]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[3]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[3]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[4]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[4]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[5]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[5]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[6]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[6]        ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[7]        ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[7]        ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[0]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[0]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[1]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[1]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[2]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[2]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[3]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[3]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[4]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[4]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[5]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[5]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[6]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[6]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[7]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[7]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; nCCAS|combout ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; nCCAS|combout ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'nCRAS'                                                                     ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target          ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCRAS ; Rise       ; nCRAS           ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; CBR             ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; CBR             ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; FWEr            ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; FWEr            ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[0]~reg0     ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[0]~reg0     ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[1]~reg0     ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[1]~reg0     ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[0]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[0]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[1]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[1]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[2]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[2]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[3]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[3]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[4]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[4]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[5]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[5]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[6]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[6]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[7]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[7]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[8]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[8]         ;
+; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[9]         ;
+; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[9]         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; CBR|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; CBR|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; FWEr|clk        ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; FWEr|clk        ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[0]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[0]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[1]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[1]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[2]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[2]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[3]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[3]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[4]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[4]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[5]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[5]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[6]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[6]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[7]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[7]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[8]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[8]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[9]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[9]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; nCRAS|combout   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; nCRAS|combout   ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Setup Times                                                             ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Din[*]    ; PHI2       ; 1.258  ; 1.258  ; Rise       ; PHI2            ;
+;  Din[0]   ; PHI2       ; -0.399 ; -0.399 ; Rise       ; PHI2            ;
+;  Din[1]   ; PHI2       ; -0.465 ; -0.465 ; Rise       ; PHI2            ;
+;  Din[2]   ; PHI2       ; -0.419 ; -0.419 ; Rise       ; PHI2            ;
+;  Din[3]   ; PHI2       ; -0.432 ; -0.432 ; Rise       ; PHI2            ;
+;  Din[4]   ; PHI2       ; -0.403 ; -0.403 ; Rise       ; PHI2            ;
+;  Din[5]   ; PHI2       ; -0.284 ; -0.284 ; Rise       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 1.258  ; 1.258  ; Rise       ; PHI2            ;
+;  Din[7]   ; PHI2       ; -0.455 ; -0.455 ; Rise       ; PHI2            ;
+; Din[*]    ; PHI2       ; 6.350  ; 6.350  ; Fall       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 6.350  ; 6.350  ; Fall       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 5.955  ; 5.955  ; Fall       ; PHI2            ;
+;  Din[2]   ; PHI2       ; 5.770  ; 5.770  ; Fall       ; PHI2            ;
+;  Din[3]   ; PHI2       ; 6.091  ; 6.091  ; Fall       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 6.121  ; 6.121  ; Fall       ; PHI2            ;
+;  Din[5]   ; PHI2       ; 5.943  ; 5.943  ; Fall       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 5.355  ; 5.355  ; Fall       ; PHI2            ;
+;  Din[7]   ; PHI2       ; 5.526  ; 5.526  ; Fall       ; PHI2            ;
+; MAin[*]   ; PHI2       ; 6.395  ; 6.395  ; Fall       ; PHI2            ;
+;  MAin[0]  ; PHI2       ; 3.121  ; 3.121  ; Fall       ; PHI2            ;
+;  MAin[1]  ; PHI2       ; 3.011  ; 3.011  ; Fall       ; PHI2            ;
+;  MAin[2]  ; PHI2       ; 6.395  ; 6.395  ; Fall       ; PHI2            ;
+;  MAin[3]  ; PHI2       ; 5.274  ; 5.274  ; Fall       ; PHI2            ;
+;  MAin[4]  ; PHI2       ; 5.540  ; 5.540  ; Fall       ; PHI2            ;
+;  MAin[5]  ; PHI2       ; 6.213  ; 6.213  ; Fall       ; PHI2            ;
+;  MAin[6]  ; PHI2       ; 4.745  ; 4.745  ; Fall       ; PHI2            ;
+;  MAin[7]  ; PHI2       ; 5.629  ; 5.629  ; Fall       ; PHI2            ;
+; nFWE      ; PHI2       ; 4.554  ; 4.554  ; Fall       ; PHI2            ;
+; PHI2      ; RCLK       ; 1.892  ; 1.892  ; Rise       ; RCLK            ;
+; nCCAS     ; RCLK       ; 1.746  ; 1.746  ; Rise       ; RCLK            ;
+; nCRAS     ; RCLK       ; 1.799  ; 1.799  ; Rise       ; RCLK            ;
+; Din[*]    ; nCCAS      ; -0.186 ; -0.186 ; Fall       ; nCCAS           ;
+;  Din[0]   ; nCCAS      ; -0.211 ; -0.211 ; Fall       ; nCCAS           ;
+;  Din[1]   ; nCCAS      ; -0.524 ; -0.524 ; Fall       ; nCCAS           ;
+;  Din[2]   ; nCCAS      ; -0.467 ; -0.467 ; Fall       ; nCCAS           ;
+;  Din[3]   ; nCCAS      ; -0.495 ; -0.495 ; Fall       ; nCCAS           ;
+;  Din[4]   ; nCCAS      ; -0.201 ; -0.201 ; Fall       ; nCCAS           ;
+;  Din[5]   ; nCCAS      ; -0.387 ; -0.387 ; Fall       ; nCCAS           ;
+;  Din[6]   ; nCCAS      ; -0.186 ; -0.186 ; Fall       ; nCCAS           ;
+;  Din[7]   ; nCCAS      ; -0.459 ; -0.459 ; Fall       ; nCCAS           ;
+; CROW[*]   ; nCRAS      ; 1.569  ; 1.569  ; Fall       ; nCRAS           ;
+;  CROW[0]  ; nCRAS      ; 1.396  ; 1.396  ; Fall       ; nCRAS           ;
+;  CROW[1]  ; nCRAS      ; 1.569  ; 1.569  ; Fall       ; nCRAS           ;
+; MAin[*]   ; nCRAS      ; -0.660 ; -0.660 ; Fall       ; nCRAS           ;
+;  MAin[0]  ; nCRAS      ; -0.660 ; -0.660 ; Fall       ; nCRAS           ;
+;  MAin[1]  ; nCRAS      ; -0.783 ; -0.783 ; Fall       ; nCRAS           ;
+;  MAin[2]  ; nCRAS      ; -1.185 ; -1.185 ; Fall       ; nCRAS           ;
+;  MAin[3]  ; nCRAS      ; -1.355 ; -1.355 ; Fall       ; nCRAS           ;
+;  MAin[4]  ; nCRAS      ; -1.507 ; -1.507 ; Fall       ; nCRAS           ;
+;  MAin[5]  ; nCRAS      ; -1.728 ; -1.728 ; Fall       ; nCRAS           ;
+;  MAin[6]  ; nCRAS      ; -1.433 ; -1.433 ; Fall       ; nCRAS           ;
+;  MAin[7]  ; nCRAS      ; -1.123 ; -1.123 ; Fall       ; nCRAS           ;
+;  MAin[8]  ; nCRAS      ; -1.416 ; -1.416 ; Fall       ; nCRAS           ;
+;  MAin[9]  ; nCRAS      ; -1.500 ; -1.500 ; Fall       ; nCRAS           ;
+; nCCAS     ; nCRAS      ; 0.462  ; 0.462  ; Fall       ; nCRAS           ;
+; nFWE      ; nCRAS      ; 1.077  ; 1.077  ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Din[*]    ; PHI2       ; 1.019  ; 1.019  ; Rise       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 0.953  ; 0.953  ; Rise       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 1.019  ; 1.019  ; Rise       ; PHI2            ;
+;  Din[2]   ; PHI2       ; 0.973  ; 0.973  ; Rise       ; PHI2            ;
+;  Din[3]   ; PHI2       ; 0.986  ; 0.986  ; Rise       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 0.957  ; 0.957  ; Rise       ; PHI2            ;
+;  Din[5]   ; PHI2       ; 0.838  ; 0.838  ; Rise       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 0.033  ; 0.033  ; Rise       ; PHI2            ;
+;  Din[7]   ; PHI2       ; 1.009  ; 1.009  ; Rise       ; PHI2            ;
+; Din[*]    ; PHI2       ; 0.456  ; 0.456  ; Fall       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 0.456  ; 0.456  ; Fall       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 0.037  ; 0.037  ; Fall       ; PHI2            ;
+;  Din[2]   ; PHI2       ; -0.029 ; -0.029 ; Fall       ; PHI2            ;
+;  Din[3]   ; PHI2       ; -0.577 ; -0.577 ; Fall       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 0.113  ; 0.113  ; Fall       ; PHI2            ;
+;  Din[5]   ; PHI2       ; -1.945 ; -1.945 ; Fall       ; PHI2            ;
+;  Din[6]   ; PHI2       ; -1.358 ; -1.358 ; Fall       ; PHI2            ;
+;  Din[7]   ; PHI2       ; -1.521 ; -1.521 ; Fall       ; PHI2            ;
+; MAin[*]   ; PHI2       ; 0.373  ; 0.373  ; Fall       ; PHI2            ;
+;  MAin[0]  ; PHI2       ; 0.263  ; 0.263  ; Fall       ; PHI2            ;
+;  MAin[1]  ; PHI2       ; 0.373  ; 0.373  ; Fall       ; PHI2            ;
+;  MAin[2]  ; PHI2       ; -1.645 ; -1.645 ; Fall       ; PHI2            ;
+;  MAin[3]  ; PHI2       ; -0.524 ; -0.524 ; Fall       ; PHI2            ;
+;  MAin[4]  ; PHI2       ; -0.790 ; -0.790 ; Fall       ; PHI2            ;
+;  MAin[5]  ; PHI2       ; -1.463 ; -1.463 ; Fall       ; PHI2            ;
+;  MAin[6]  ; PHI2       ; -1.361 ; -1.361 ; Fall       ; PHI2            ;
+;  MAin[7]  ; PHI2       ; -2.245 ; -2.245 ; Fall       ; PHI2            ;
+; nFWE      ; PHI2       ; -1.272 ; -1.272 ; Fall       ; PHI2            ;
+; PHI2      ; RCLK       ; -1.338 ; -1.338 ; Rise       ; RCLK            ;
+; nCCAS     ; RCLK       ; -1.192 ; -1.192 ; Rise       ; RCLK            ;
+; nCRAS     ; RCLK       ; -1.245 ; -1.245 ; Rise       ; RCLK            ;
+; Din[*]    ; nCCAS      ; 1.078  ; 1.078  ; Fall       ; nCCAS           ;
+;  Din[0]   ; nCCAS      ; 0.765  ; 0.765  ; Fall       ; nCCAS           ;
+;  Din[1]   ; nCCAS      ; 1.078  ; 1.078  ; Fall       ; nCCAS           ;
+;  Din[2]   ; nCCAS      ; 1.021  ; 1.021  ; Fall       ; nCCAS           ;
+;  Din[3]   ; nCCAS      ; 1.049  ; 1.049  ; Fall       ; nCCAS           ;
+;  Din[4]   ; nCCAS      ; 0.755  ; 0.755  ; Fall       ; nCCAS           ;
+;  Din[5]   ; nCCAS      ; 0.941  ; 0.941  ; Fall       ; nCCAS           ;
+;  Din[6]   ; nCCAS      ; 0.740  ; 0.740  ; Fall       ; nCCAS           ;
+;  Din[7]   ; nCCAS      ; 1.013  ; 1.013  ; Fall       ; nCCAS           ;
+; CROW[*]   ; nCRAS      ; -0.842 ; -0.842 ; Fall       ; nCRAS           ;
+;  CROW[0]  ; nCRAS      ; -0.842 ; -0.842 ; Fall       ; nCRAS           ;
+;  CROW[1]  ; nCRAS      ; -1.015 ; -1.015 ; Fall       ; nCRAS           ;
+; MAin[*]   ; nCRAS      ; 2.282  ; 2.282  ; Fall       ; nCRAS           ;
+;  MAin[0]  ; nCRAS      ; 1.214  ; 1.214  ; Fall       ; nCRAS           ;
+;  MAin[1]  ; nCRAS      ; 1.337  ; 1.337  ; Fall       ; nCRAS           ;
+;  MAin[2]  ; nCRAS      ; 1.739  ; 1.739  ; Fall       ; nCRAS           ;
+;  MAin[3]  ; nCRAS      ; 1.909  ; 1.909  ; Fall       ; nCRAS           ;
+;  MAin[4]  ; nCRAS      ; 2.061  ; 2.061  ; Fall       ; nCRAS           ;
+;  MAin[5]  ; nCRAS      ; 2.282  ; 2.282  ; Fall       ; nCRAS           ;
+;  MAin[6]  ; nCRAS      ; 1.987  ; 1.987  ; Fall       ; nCRAS           ;
+;  MAin[7]  ; nCRAS      ; 1.677  ; 1.677  ; Fall       ; nCRAS           ;
+;  MAin[8]  ; nCRAS      ; 1.970  ; 1.970  ; Fall       ; nCRAS           ;
+;  MAin[9]  ; nCRAS      ; 2.054  ; 2.054  ; Fall       ; nCRAS           ;
+; nCCAS     ; nCRAS      ; 0.092  ; 0.092  ; Fall       ; nCRAS           ;
+; nFWE      ; nCRAS      ; -0.523 ; -0.523 ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Clock to Output Times                                                   ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; RA[*]     ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
+;  RA[11]   ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
+; LED       ; RCLK       ; 9.813  ; 9.813  ; Rise       ; RCLK            ;
+; RA[*]     ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
+;  RA[0]    ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
+;  RA[1]    ; RCLK       ; 11.412 ; 11.412 ; Rise       ; RCLK            ;
+;  RA[2]    ; RCLK       ; 11.273 ; 11.273 ; Rise       ; RCLK            ;
+;  RA[3]    ; RCLK       ; 10.539 ; 10.539 ; Rise       ; RCLK            ;
+;  RA[4]    ; RCLK       ; 11.236 ; 11.236 ; Rise       ; RCLK            ;
+;  RA[5]    ; RCLK       ; 11.157 ; 11.157 ; Rise       ; RCLK            ;
+;  RA[6]    ; RCLK       ; 11.290 ; 11.290 ; Rise       ; RCLK            ;
+;  RA[7]    ; RCLK       ; 11.217 ; 11.217 ; Rise       ; RCLK            ;
+;  RA[8]    ; RCLK       ; 11.381 ; 11.381 ; Rise       ; RCLK            ;
+;  RA[9]    ; RCLK       ; 11.302 ; 11.302 ; Rise       ; RCLK            ;
+;  RA[10]   ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
+; RCKE      ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
+; RDQMH     ; RCLK       ; 10.547 ; 10.547 ; Rise       ; RCLK            ;
+; RDQML     ; RCLK       ; 11.010 ; 11.010 ; Rise       ; RCLK            ;
+; nRCAS     ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
+; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
+; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
+; nRWE      ; RCLK       ; 8.637  ; 8.637  ; Rise       ; RCLK            ;
+; RD[*]     ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 18.824 ; 18.824 ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 18.920 ; 18.920 ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 18.917 ; 18.917 ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 19.501 ; 19.501 ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 18.946 ; 18.946 ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 18.951 ; 18.951 ; Fall       ; nCCAS           ;
+; LED       ; nCRAS      ; 6.153  ; 6.153  ; Rise       ; nCRAS           ;
+; LED       ; nCRAS      ; 6.153  ; 6.153  ; Fall       ; nCRAS           ;
+; RA[*]     ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
+;  RA[0]    ; nCRAS      ; 12.954 ; 12.954 ; Fall       ; nCRAS           ;
+;  RA[1]    ; nCRAS      ; 12.928 ; 12.928 ; Fall       ; nCRAS           ;
+;  RA[2]    ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
+;  RA[3]    ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
+;  RA[4]    ; nCRAS      ; 12.862 ; 12.862 ; Fall       ; nCRAS           ;
+;  RA[5]    ; nCRAS      ; 12.781 ; 12.781 ; Fall       ; nCRAS           ;
+;  RA[6]    ; nCRAS      ; 13.093 ; 13.093 ; Fall       ; nCRAS           ;
+;  RA[7]    ; nCRAS      ; 13.020 ; 13.020 ; Fall       ; nCRAS           ;
+;  RA[8]    ; nCRAS      ; 13.070 ; 13.070 ; Fall       ; nCRAS           ;
+;  RA[9]    ; nCRAS      ; 13.106 ; 13.106 ; Fall       ; nCRAS           ;
+; RBA[*]    ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
+;  RBA[0]   ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
+;  RBA[1]   ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                           ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; RA[*]     ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
+;  RA[11]   ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
+; LED       ; RCLK       ; 9.813  ; 9.813  ; Rise       ; RCLK            ;
+; RA[*]     ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
+;  RA[0]    ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
+;  RA[1]    ; RCLK       ; 11.412 ; 11.412 ; Rise       ; RCLK            ;
+;  RA[2]    ; RCLK       ; 11.273 ; 11.273 ; Rise       ; RCLK            ;
+;  RA[3]    ; RCLK       ; 10.539 ; 10.539 ; Rise       ; RCLK            ;
+;  RA[4]    ; RCLK       ; 11.236 ; 11.236 ; Rise       ; RCLK            ;
+;  RA[5]    ; RCLK       ; 11.157 ; 11.157 ; Rise       ; RCLK            ;
+;  RA[6]    ; RCLK       ; 11.290 ; 11.290 ; Rise       ; RCLK            ;
+;  RA[7]    ; RCLK       ; 11.217 ; 11.217 ; Rise       ; RCLK            ;
+;  RA[8]    ; RCLK       ; 11.381 ; 11.381 ; Rise       ; RCLK            ;
+;  RA[9]    ; RCLK       ; 11.302 ; 11.302 ; Rise       ; RCLK            ;
+;  RA[10]   ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
+; RCKE      ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
+; RDQMH     ; RCLK       ; 10.547 ; 10.547 ; Rise       ; RCLK            ;
+; RDQML     ; RCLK       ; 11.010 ; 11.010 ; Rise       ; RCLK            ;
+; nRCAS     ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
+; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
+; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
+; nRWE      ; RCLK       ; 8.637  ; 8.637  ; Rise       ; RCLK            ;
+; RD[*]     ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 18.824 ; 18.824 ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 18.920 ; 18.920 ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 18.917 ; 18.917 ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 19.501 ; 19.501 ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 18.946 ; 18.946 ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 18.951 ; 18.951 ; Fall       ; nCCAS           ;
+; LED       ; nCRAS      ; 6.153  ; 6.153  ; Rise       ; nCRAS           ;
+; LED       ; nCRAS      ; 6.153  ; 6.153  ; Fall       ; nCRAS           ;
+; RA[*]     ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
+;  RA[0]    ; nCRAS      ; 12.954 ; 12.954 ; Fall       ; nCRAS           ;
+;  RA[1]    ; nCRAS      ; 12.928 ; 12.928 ; Fall       ; nCRAS           ;
+;  RA[2]    ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
+;  RA[3]    ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
+;  RA[4]    ; nCRAS      ; 12.862 ; 12.862 ; Fall       ; nCRAS           ;
+;  RA[5]    ; nCRAS      ; 12.781 ; 12.781 ; Fall       ; nCRAS           ;
+;  RA[6]    ; nCRAS      ; 13.093 ; 13.093 ; Fall       ; nCRAS           ;
+;  RA[7]    ; nCRAS      ; 13.020 ; 13.020 ; Fall       ; nCRAS           ;
+;  RA[8]    ; nCRAS      ; 13.070 ; 13.070 ; Fall       ; nCRAS           ;
+;  RA[9]    ; nCRAS      ; 13.106 ; 13.106 ; Fall       ; nCRAS           ;
+; RBA[*]    ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
+;  RBA[0]   ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
+;  RBA[1]   ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------+
+; Propagation Delay                                    ;
++------------+-------------+--------+----+----+--------+
+; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
++------------+-------------+--------+----+----+--------+
+; MAin[0]    ; RA[0]       ; 10.197 ;    ;    ; 10.197 ;
+; MAin[1]    ; RA[1]       ; 9.846  ;    ;    ; 9.846  ;
+; MAin[2]    ; RA[2]       ; 9.051  ;    ;    ; 9.051  ;
+; MAin[3]    ; RA[3]       ; 8.214  ;    ;    ; 8.214  ;
+; MAin[4]    ; RA[4]       ; 8.144  ;    ;    ; 8.144  ;
+; MAin[5]    ; RA[5]       ; 8.753  ;    ;    ; 8.753  ;
+; MAin[6]    ; RA[6]       ; 8.281  ;    ;    ; 8.281  ;
+; MAin[7]    ; RA[7]       ; 9.251  ;    ;    ; 9.251  ;
+; MAin[8]    ; RA[8]       ; 8.196  ;    ;    ; 8.196  ;
+; MAin[9]    ; RA[9]       ; 8.221  ;    ;    ; 8.221  ;
+; MAin[9]    ; RDQMH       ; 7.373  ;    ;    ; 7.373  ;
+; MAin[9]    ; RDQML       ; 7.833  ;    ;    ; 7.833  ;
+; RD[0]      ; Dout[0]     ; 6.115  ;    ;    ; 6.115  ;
+; RD[1]      ; Dout[1]     ; 6.297  ;    ;    ; 6.297  ;
+; RD[2]      ; Dout[2]     ; 6.244  ;    ;    ; 6.244  ;
+; RD[3]      ; Dout[3]     ; 6.825  ;    ;    ; 6.825  ;
+; RD[4]      ; Dout[4]     ; 6.717  ;    ;    ; 6.717  ;
+; RD[5]      ; Dout[5]     ; 6.723  ;    ;    ; 6.723  ;
+; RD[6]      ; Dout[6]     ; 6.184  ;    ;    ; 6.184  ;
+; RD[7]      ; Dout[7]     ; 6.756  ;    ;    ; 6.756  ;
+; nFWE       ; RD[0]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[1]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[2]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[3]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[4]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[5]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[6]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[7]       ; 16.365 ;    ;    ; 16.365 ;
++------------+-------------+--------+----+----+--------+
+
+
++------------------------------------------------------+
+; Minimum Propagation Delay                            ;
++------------+-------------+--------+----+----+--------+
+; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
++------------+-------------+--------+----+----+--------+
+; MAin[0]    ; RA[0]       ; 10.197 ;    ;    ; 10.197 ;
+; MAin[1]    ; RA[1]       ; 9.846  ;    ;    ; 9.846  ;
+; MAin[2]    ; RA[2]       ; 9.051  ;    ;    ; 9.051  ;
+; MAin[3]    ; RA[3]       ; 8.214  ;    ;    ; 8.214  ;
+; MAin[4]    ; RA[4]       ; 8.144  ;    ;    ; 8.144  ;
+; MAin[5]    ; RA[5]       ; 8.753  ;    ;    ; 8.753  ;
+; MAin[6]    ; RA[6]       ; 8.281  ;    ;    ; 8.281  ;
+; MAin[7]    ; RA[7]       ; 9.251  ;    ;    ; 9.251  ;
+; MAin[8]    ; RA[8]       ; 8.196  ;    ;    ; 8.196  ;
+; MAin[9]    ; RA[9]       ; 8.221  ;    ;    ; 8.221  ;
+; MAin[9]    ; RDQMH       ; 7.373  ;    ;    ; 7.373  ;
+; MAin[9]    ; RDQML       ; 7.833  ;    ;    ; 7.833  ;
+; RD[0]      ; Dout[0]     ; 6.115  ;    ;    ; 6.115  ;
+; RD[1]      ; Dout[1]     ; 6.297  ;    ;    ; 6.297  ;
+; RD[2]      ; Dout[2]     ; 6.244  ;    ;    ; 6.244  ;
+; RD[3]      ; Dout[3]     ; 6.825  ;    ;    ; 6.825  ;
+; RD[4]      ; Dout[4]     ; 6.717  ;    ;    ; 6.717  ;
+; RD[5]      ; Dout[5]     ; 6.723  ;    ;    ; 6.723  ;
+; RD[6]      ; Dout[6]     ; 6.184  ;    ;    ; 6.184  ;
+; RD[7]      ; Dout[7]     ; 6.756  ;    ;    ; 6.756  ;
+; nFWE       ; RD[0]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[1]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[2]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[3]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[4]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[5]       ; 16.324 ;    ;    ; 16.324 ;
+; nFWE       ; RD[6]       ; 16.365 ;    ;    ; 16.365 ;
+; nFWE       ; RD[7]       ; 16.365 ;    ;    ; 16.365 ;
++------------+-------------+--------+----+----+--------+
+
+
++-----------------------------------------------------------------------+
+; Output Enable Times                                                   ;
++-----------+------------+--------+------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
++-----------+------------+--------+------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Output Enable Times                                           ;
++-----------+------------+--------+------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
++-----------+------------+--------+------+------------+-----------------+
+
+
++-------------------------------------------------------------------------------+
+; Output Disable Times                                                          ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
++-----------+------------+-----------+-----------+------------+-----------------+
+
+
++-------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                  ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
++-----------+------------+-----------+-----------+------------+-----------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 31    ; 31   ;
+; Unconstrained Input Port Paths  ; 232   ; 232  ;
+; Unconstrained Output Ports      ; 38    ; 38   ;
+; Unconstrained Output Port Paths ; 77    ; 77   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Mon Aug 16 18:40:18 2021
+Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (306004): Started post-fitting delay annotation
+Info (306005): Delay annotation completed successfully
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
+    Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
+    Info (332105): create_clock -period 1.000 -name RCLK RCLK
+    Info (332105): create_clock -period 1.000 -name nCRAS nCRAS
+    Info (332105): create_clock -period 1.000 -name PHI2 PHI2
+    Info (332105): create_clock -period 1.000 -name nCCAS nCCAS
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Critical Warning (332148): Timing requirements not met
+Info (332146): Worst-case setup slack is -99.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -99.000       -99.000 ARCLK 
+    Info (332119):   -99.000       -99.000 DRCLK 
+    Info (332119):    -8.339      -245.761 RCLK 
+    Info (332119):    -8.271       -88.383 PHI2 
+    Info (332119):    -0.317        -2.784 nCRAS 
+Info (332146): Worst-case hold slack is -16.858
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -16.858       -16.858 ARCLK 
+    Info (332119):   -16.363       -16.363 DRCLK 
+    Info (332119):    -0.103        -0.195 nCRAS 
+    Info (332119):    -0.060        -0.060 PHI2 
+    Info (332119):     1.192         0.000 RCLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -29.500
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -29.500       -59.000 ARCLK 
+    Info (332119):   -29.500       -59.000 DRCLK 
+    Info (332119):    -2.289        -2.289 PHI2 
+    Info (332119):    -2.289        -2.289 RCLK 
+    Info (332119):    -2.289        -2.289 nCCAS 
+    Info (332119):    -2.289        -2.289 nCRAS 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 374 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:19 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/CPLD/MAXII/output_files/RAM4GS.sta.summary b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary
old mode 100755
new mode 100644
similarity index 78%
rename from CPLD/MAXII/output_files/RAM4GS.sta.summary
rename to CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary
index a4c9ebf..adebd09
--- a/CPLD/MAXII/output_files/RAM4GS.sta.summary
+++ b/CPLD/MAX/MAXII/output_files/RAM2GS.sta.summary
@@ -10,37 +10,37 @@ Type  : Setup 'DRCLK'
 Slack : -99.000
 TNS   : -99.000
 
-Type  : Setup 'PHI2'
-Slack : -9.292
-TNS   : -92.804
-
 Type  : Setup 'RCLK'
-Slack : -8.365
-TNS   : -253.063
+Slack : -8.339
+TNS   : -245.761
+
+Type  : Setup 'PHI2'
+Slack : -8.271
+TNS   : -88.383
 
 Type  : Setup 'nCRAS'
-Slack : -0.490
-TNS   : -0.577
-
-Type  : Hold 'DRCLK'
-Slack : -16.306
-TNS   : -16.306
+Slack : -0.317
+TNS   : -2.784
 
 Type  : Hold 'ARCLK'
-Slack : -16.272
-TNS   : -16.272
+Slack : -16.858
+TNS   : -16.858
 
-Type  : Hold 'RCLK'
-Slack : -0.874
-TNS   : -0.874
-
-Type  : Hold 'PHI2'
-Slack : -0.396
-TNS   : -0.396
+Type  : Hold 'DRCLK'
+Slack : -16.363
+TNS   : -16.363
 
 Type  : Hold 'nCRAS'
-Slack : -0.125
-TNS   : -0.125
+Slack : -0.103
+TNS   : -0.195
+
+Type  : Hold 'PHI2'
+Slack : -0.060
+TNS   : -0.060
+
+Type  : Hold 'RCLK'
+Slack : 1.192
+TNS   : 0.000
 
 Type  : Minimum Pulse Width 'ARCLK'
 Slack : -29.500
diff --git a/CPLD/MAXII/RAM4GS.qpf b/CPLD/MAX/MAXV/RAM2GS-MAXV.qpf
old mode 100755
new mode 100644
similarity index 84%
rename from CPLD/MAXII/RAM4GS.qpf
rename to CPLD/MAX/MAXV/RAM2GS-MAXV.qpf
index aceec8c..8fb201a
--- a/CPLD/MAXII/RAM4GS.qpf
+++ b/CPLD/MAX/MAXV/RAM2GS-MAXV.qpf
@@ -16,15 +16,15 @@
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 21:16:34  March 08, 2020
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 18:33:17  August 16, 2021
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "13.0"
-DATE = "21:16:34  March 08, 2020"
+DATE = "18:33:17  August 16, 2021"
 
 # Revisions
 
-PROJECT_REVISION = "RAM4GS"
+PROJECT_REVISION = "RAM2GS"
diff --git a/CPLD/AGM-src/RAM4GS.qsf b/CPLD/MAX/MAXV/RAM2GS.qsf
old mode 100755
new mode 100644
similarity index 96%
rename from CPLD/AGM-src/RAM4GS.qsf
rename to CPLD/MAX/MAXV/RAM2GS.qsf
index ed8578e..ecad28a
--- a/CPLD/AGM-src/RAM4GS.qsf
+++ b/CPLD/MAX/MAXV/RAM2GS.qsf
@@ -36,14 +36,12 @@
 # -------------------------------------------------------------------------- #
 
 
-set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE EPM240T100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
+set_global_assignment -name FAMILY "MAX V"
+set_global_assignment -name DEVICE 5M240ZT100C5
+set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34  MARCH 08, 2020"
 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name SDC_FILE constraints.sdc
-set_global_assignment -name VERILOG_FILE RAM4GS.v
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -174,7 +172,6 @@ set_location_assignment PIN_95 -to RD[6]
 set_location_assignment PIN_97 -to RD[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
 
-set_global_assignment -name MIF_FILE RAM4GS.mif
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
 set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
@@ -210,4 +207,6 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
 set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
 set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
+set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
+set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif"
 set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD/MAX/MAXV/RAM2GS.qws b/CPLD/MAX/MAXV/RAM2GS.qws
new file mode 100644
index 0000000..9b19765
Binary files /dev/null and b/CPLD/MAX/MAXV/RAM2GS.qws differ
diff --git a/CPLD/MAXII/UFM.qip b/CPLD/MAX/MAXV/UFM.qip
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/UFM.qip
rename to CPLD/MAX/MAXV/UFM.qip
diff --git a/CPLD/AGM-src/UFM.v b/CPLD/MAX/MAXV/UFM.v
old mode 100755
new mode 100644
similarity index 80%
rename from CPLD/AGM-src/UFM.v
rename to CPLD/MAX/MAXV/UFM.v
index c063115..16db83a
--- a/CPLD/AGM-src/UFM.v
+++ b/CPLD/MAX/MAXV/UFM.v
@@ -9,7 +9,7 @@
 // 			ALTUFM_NONE
 //
 // Simulation Library Files(s):
-// 			maxii
+// 			maxv
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@@ -33,17 +33,17 @@
 //applicable agreement for further details.
 
 
-//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
-//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ  VERSION_END
+//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
+//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
 
-//synthesis_resources = maxii_ufm 1 
+//synthesis_resources = maxv_ufm 1 
 //synopsys translate_off
 `timescale 1 ps / 1 ps
 //synopsys translate_on
-module  UFM_altufm_none_1br
+module  UFM_altufm_none_mjr
 	( 
 	arclk,
 	ardin,
@@ -90,7 +90,7 @@ module  UFM_altufm_none_1br
 	wire  ufm_oscena;
 	wire  ufm_program;
 
-	maxii_ufm   maxii_ufm_block1
+	maxv_ufm   maxii_ufm_block1
 	( 
 	.arclk(ufm_arclk),
 	.ardin(ufm_ardin),
@@ -117,26 +117,26 @@ module  UFM_altufm_none_1br
 	defparam
 		maxii_ufm_block1.address_width = 9,
 		maxii_ufm_block1.erase_time = 500000000,
-		maxii_ufm_block1.init_file = "RAM4GS.mif",
+		maxii_ufm_block1.init_file = "RAM2GS-MAX.mif",
 		maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
+		maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
 		maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
 		maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
+		maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
 		maxii_ufm_block1.osc_sim_setting = 180000,
 		maxii_ufm_block1.program_time = 1600000,
-		maxii_ufm_block1.lpm_type = "maxii_ufm";
+		maxii_ufm_block1.lpm_type = "maxv_ufm";
 	assign
 		busy = ufm_busy,
 		drdout = ufm_drdout,
@@ -155,7 +155,7 @@ module  UFM_altufm_none_1br
 		ufm_osc = wire_maxii_ufm_block1_osc,
 		ufm_oscena = oscena,
 		ufm_program = program;
-endmodule //UFM_altufm_none_1br
+endmodule //UFM_altufm_none_mjr
 //VALID FILE
 
 
@@ -200,7 +200,7 @@ module UFM (
 	wire  drdout = sub_wire2;
 	wire  busy = sub_wire3;
 
-	UFM_altufm_none_1br	UFM_altufm_none_1br_component (
+	UFM_altufm_none_mjr	UFM_altufm_none_mjr_component (
 				.arshft (arshft),
 				.drclk (drclk),
 				.erase (erase),
@@ -221,10 +221,10 @@ endmodule
 // CNX file retrieval info
 // ============================================================
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V"
 // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
-// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V"
+// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif"
 // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
 // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
@@ -265,4 +265,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
-// Retrieval info: LIB_FILE: maxii
+// Retrieval info: LIB_FILE: maxv
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb
new file mode 100644
index 0000000..b4b4e46
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb
new file mode 100644
index 0000000..54a1d9d
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(0).cnf.hdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb
new file mode 100644
index 0000000..8cd9b78
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb
new file mode 100644
index 0000000..eb76e4a
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(1).cnf.hdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb
new file mode 100644
index 0000000..0d88168
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb
new file mode 100644
index 0000000..0a94ff8
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.(2).cnf.hdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg
new file mode 100644
index 0000000..1db2993
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153622162 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing started: Mon Aug 16 18:40:21 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153622381 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153622381 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:22 2021 " "Processing ended: Mon Aug 16 18:40:22 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153622537 ""}
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb
new file mode 100644
index 0000000..d5c4ae9
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.asm.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb
new file mode 100644
index 0000000..f0193ba
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.asm_labs.ddb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb
new file mode 100644
index 0000000..7958469
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb
new file mode 100644
index 0000000..32f50d6
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.hdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb
new file mode 100644
index 0000000..8b3dcdc
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.idb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt b/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt
new file mode 100644
index 0000000..73afc77
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.kpt differ
diff --git a/CPLD/MAXII/db/RAM4GS.cmp.logdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.logdb
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/db/RAM4GS.cmp.logdb
rename to CPLD/MAX/MAXV/db/RAM2GS.cmp.logdb
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb
new file mode 100644
index 0000000..4c11aeb
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb b/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb
new file mode 100644
index 0000000..62186e1
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.cmp0.ddb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.db_info b/CPLD/MAX/MAXV/db/RAM2GS.db_info
new file mode 100644
index 0000000..816de1e
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Mon Aug 16 18:36:34 2021
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg
new file mode 100644
index 0000000..5f9e7a9
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153618530 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153618530 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153618639 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153618639 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153618748 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 336 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153618764 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153618764 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153618842 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153618842 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 332 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 334 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 333 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153618873 ""}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153618889 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153618889 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153618904 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153618904 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153618920 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 17 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  17 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153618920 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153618951 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153619045 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619232 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153619247 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153619871 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619871 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153619903 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153620137 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153620137 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621129 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153621129 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621139 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153621169 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153621219 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing ended: Mon Aug 16 18:40:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153621239 ""}
diff --git a/CPLD/MAXII/db/RAM4GS.hier_info b/CPLD/MAX/MAXV/db/RAM2GS.hier_info
old mode 100755
new mode 100644
similarity index 93%
rename from CPLD/MAXII/db/RAM4GS.hier_info
rename to CPLD/MAX/MAXV/db/RAM2GS.hier_info
index 97bc269..d04c06b
--- a/CPLD/MAXII/db/RAM4GS.hier_info
+++ b/CPLD/MAX/MAXV/db/RAM2GS.hier_info
@@ -1,4 +1,4 @@
-|RAM4GS
+|RAM2GS
 PHI2 => Bank[0].CLK
 PHI2 => Bank[1].CLK
 PHI2 => Bank[2].CLK
@@ -152,12 +152,14 @@ nCRAS => RowA[8].CLK
 nCRAS => RowA[9].CLK
 nCRAS => RBA[0]~reg0.CLK
 nCRAS => RBA[1]~reg0.CLK
+nCRAS => comb.IN1
 nCRAS => RASr.DATAIN
 nFWE => comb.IN1
 nFWE => CMDWR.IN1
 nFWE => ADWR.IN1
 nFWE => C1WR.IN1
 nFWE => FWEr.DATAIN
+LED <= comb.DB_MAX_OUTPUT_PORT_TYPE
 RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
@@ -184,9 +186,10 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
 RCLK => UFMProgram.CLK
 RCLK => UFMErase.CLK
 RCLK => UFMReqErase.CLK
-RCLK => n8MEGEN.CLK
+RCLK => LEDEN.CLK
 RCLK => UFMInitDone.CLK
-RCLK => UFMD.CLK
+RCLK => n8MEGEN.CLK
+RCLK => UFMD[15].CLK
 RCLK => DRShift.CLK
 RCLK => DRDIn.CLK
 RCLK => DRCLK.CLK
@@ -243,7 +246,7 @@ RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
 RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
 
 
-|RAM4GS|UFM:UFM_inst
+|RAM2GS|UFM:UFM_inst
 arclk => arclk.IN1
 ardin => ardin.IN1
 arshft => arshft.IN1
@@ -253,13 +256,13 @@ drshft => drshft.IN1
 erase => erase.IN1
 oscena => oscena.IN1
 program => program.IN1
-busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
-drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
-osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
-rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
+busy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.busy
+drdout <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.drdout
+osc <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.osc
+rtpbusy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.rtpbusy
 
 
-|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
+|RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component
 arclk => maxii_ufm_block1.ARCLK
 ardin => maxii_ufm_block1.ARDIN
 arshft => maxii_ufm_block1.ARSHFT
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.hif b/CPLD/MAX/MAXV/db/RAM2GS.hif
new file mode 100644
index 0000000..6fb7059
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.hif differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.ipinfo b/CPLD/MAX/MAXV/db/RAM2GS.ipinfo
new file mode 100644
index 0000000..fa2304d
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.ipinfo differ
diff --git a/CPLD/MAXII/db/RAM4GS.lpc.html b/CPLD/MAX/MAXV/db/RAM2GS.lpc.html
old mode 100755
new mode 100644
similarity index 93%
rename from CPLD/MAXII/db/RAM4GS.lpc.html
rename to CPLD/MAX/MAXV/db/RAM2GS.lpc.html
index d50a19d..707f37e
--- a/CPLD/MAXII/db/RAM4GS.lpc.html
+++ b/CPLD/MAX/MAXV/db/RAM2GS.lpc.html
@@ -16,7 +16,7 @@
 Output only Bidir
 
 
-UFM_inst|UFM_altufm_none_1br_component
+UFM_inst|UFM_altufm_none_mjr_component
 9
 0
 0
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb b/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb
new file mode 100644
index 0000000..8216994
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.lpc.rdb differ
diff --git a/CPLD/MAXII/db/RAM4GS.lpc.txt b/CPLD/MAX/MAXV/db/RAM2GS.lpc.txt
old mode 100755
new mode 100644
similarity index 96%
rename from CPLD/MAXII/db/RAM4GS.lpc.txt
rename to CPLD/MAX/MAXV/db/RAM2GS.lpc.txt
index d8d214c..17b369e
--- a/CPLD/MAXII/db/RAM4GS.lpc.txt
+++ b/CPLD/MAX/MAXV/db/RAM2GS.lpc.txt
@@ -3,6 +3,6 @@
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
 ; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_1br_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; UFM_inst|UFM_altufm_none_mjr_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
 ; UFM_inst                               ; 9     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
 +----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.cdb b/CPLD/MAX/MAXV/db/RAM2GS.map.cdb
new file mode 100644
index 0000000..e4871a7
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.hdb b/CPLD/MAX/MAXV/db/RAM2GS.map.hdb
new file mode 100644
index 0000000..c9ffc10
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.hdb differ
diff --git a/CPLD/MAXII/db/RAM4GS.map.logdb b/CPLD/MAX/MAXV/db/RAM2GS.map.logdb
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/db/RAM4GS.map.logdb
rename to CPLD/MAX/MAXV/db/RAM2GS.map.logdb
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg
new file mode 100644
index 0000000..92e65f5
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.map.qmsg
@@ -0,0 +1,27 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153616333 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing started: Mon Aug 16 18:40:16 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153616598 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153616661 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_mjr " "Found entity 1: UFM_altufm_none_mjr" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153616739 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_mjr UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component " "Elaborating entity \"UFM_altufm_none_mjr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component\"" {  } { { "UFM.v" "UFM_altufm_none_mjr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""}
+{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0" {  } {  } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153616785 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153617319 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153617319 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153617350 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""}
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.map.rdb b/CPLD/MAX/MAXV/db/RAM2GS.map.rdb
new file mode 100644
index 0000000..c7c7800
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.map.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb b/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb
new file mode 100644
index 0000000..723fcab
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.pplq.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb
new file mode 100644
index 0000000..36b866e
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.pre_map.hdb differ
diff --git a/CPLD/MAXII/db/RAM4GS.tis_db_list.ddb b/CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb
old mode 100755
new mode 100644
similarity index 67%
rename from CPLD/MAXII/db/RAM4GS.tis_db_list.ddb
rename to CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb
index 42a925d..89aa9b4
Binary files a/CPLD/MAXII/db/RAM4GS.tis_db_list.ddb and b/CPLD/MAX/MAXV/db/RAM2GS.pti_db_list.ddb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb b/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..dce5122
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb
new file mode 100644
index 0000000..98f9da2
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.routing.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb
new file mode 100644
index 0000000..e1281ba
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv.hdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb
new file mode 100644
index 0000000..3d52775
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..d1b2728
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.rtlv_sg_swap.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb
new file mode 100644
index 0000000..b5e30c4
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.cdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb
new file mode 100644
index 0000000..ea82e76
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sgdiff.hdb differ
diff --git a/CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci
old mode 100755
new mode 100644
similarity index 59%
rename from CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci
rename to CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci
index 754b594..1d6d60f
Binary files a/CPLD/MAXII/db/RAM4GS.sld_design_entry_dsc.sci and b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry.sci differ
diff --git a/CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci
old mode 100755
new mode 100644
similarity index 59%
rename from CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci
rename to CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci
index 754b594..1d6d60f
Binary files a/CPLD/AGM-src/db/RAM4GS.sld_design_entry.sci and b/CPLD/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci differ
diff --git a/CPLD/MAXII/db/RAM4GS.smart_action.txt b/CPLD/MAX/MAXV/db/RAM2GS.smart_action.txt
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/db/RAM4GS.smart_action.txt
rename to CPLD/MAX/MAXV/db/RAM2GS.smart_action.txt
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg
new file mode 100644
index 0000000..734cddd
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.sta.qmsg
@@ -0,0 +1,23 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153623584 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:23 2021 " "Processing started: Mon Aug 16 18:40:23 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153623662 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153623787 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153623896 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153624208 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153624255 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153624255 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -23.638      -216.621 PHI2  " "  -23.638      -216.621 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -19.942      -610.547 RCLK  " "  -19.942      -610.547 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.072        -6.479 nCRAS  " "   -3.072        -6.479 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.153 " "Worst-case hold slack is -16.153" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.153       -16.153 ARCLK  " "  -16.153       -16.153 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.623       -14.623 DRCLK  " "  -14.623       -14.623 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.569        -3.433 PHI2  " "   -2.569        -3.433 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.713        -2.822 nCRAS  " "   -0.713        -2.822 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.127         0.000 RCLK  " "    2.127         0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153624348 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:24 2021 " "Processing ended: Mon Aug 16 18:40:24 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""}
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb
new file mode 100644
index 0000000..e9c2f8b
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sta.rdb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb
new file mode 100644
index 0000000..c40c26a
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb differ
diff --git a/CPLD/AGM-src/output_files/UFM.qip b/CPLD/MAX/MAXV/db/RAM2GS.syn_hier_info
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/output_files/UFM.qip
rename to CPLD/MAX/MAXV/db/RAM2GS.syn_hier_info
diff --git a/CPLD/MAXII/db/RAM4GS.pti_db_list.ddb b/CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb
old mode 100755
new mode 100644
similarity index 67%
rename from CPLD/MAXII/db/RAM4GS.pti_db_list.ddb
rename to CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb
index 61ca8da..91bbe10
Binary files a/CPLD/MAXII/db/RAM4GS.pti_db_list.ddb and b/CPLD/MAX/MAXV/db/RAM2GS.tis_db_list.ddb differ
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.tmw_info b/CPLD/MAX/MAXV/db/RAM2GS.tmw_info
new file mode 100644
index 0000000..69e9cce
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/RAM2GS.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:10
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:04-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb b/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb
new file mode 100644
index 0000000..e64e992
Binary files /dev/null and b/CPLD/MAX/MAXV/db/RAM2GS.vpr.ammdb differ
diff --git a/CPLD/MAX/MAXV/db/logic_util_heursitic.dat b/CPLD/MAX/MAXV/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..ff5fe7f
Binary files /dev/null and b/CPLD/MAX/MAXV/db/logic_util_heursitic.dat differ
diff --git a/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg b/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg
new file mode 100644
index 0000000..7bedb77
--- /dev/null
+++ b/CPLD/MAX/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153397464 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:36:37 2021 " "Processing started: Mon Aug 16 18:36:37 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153397464 ""}
+{ "Warning" "WACF_MISSING_TCL_FILE" "UFM.qip " "Tcl Script File UFM.qip not found" { { "Info" "IACF_ACF_ASSIGNMENT_INFO" "set_global_assignment -name QIP_FILE UFM.qip " "set_global_assignment -name QIP_FILE UFM.qip" {  } {  } 0 125063 "%1!s!" 0 0 "Quartus II" 0 -1 1629153397588 ""}  } {  } 0 125092 "Tcl Script File %1!s! not found" 0 0 "Quartus II" 0 -1 1629153397588 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153397744 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "RAM4GS.v " "Can't analyze file -- file RAM4GS.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1629153397807 ""}
+{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "RAM2GS " "Top-level design entity \"RAM2GS\" is undefined" {  } {  } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Quartus II" 0 -1 1629153397854 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  3 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Aug 16 18:36:37 2021 " "Processing ended: Mon Aug 16 18:36:37 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153397885 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 3 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153398462 ""}
diff --git a/CPLD/MAXII/incremental_db/README b/CPLD/MAX/MAXV/incremental_db/README
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/incremental_db/README
rename to CPLD/MAX/MAXV/incremental_db/README
diff --git a/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info
new file mode 100644
index 0000000..4382c8d
--- /dev/null
+++ b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Mon Aug 16 18:40:16 2021
diff --git a/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
new file mode 100644
index 0000000..2a67174
Binary files /dev/null and b/CPLD/MAX/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ
diff --git a/CPLD/MAXII/output_files/RAM4GS.asm.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt
old mode 100755
new mode 100644
similarity index 70%
rename from CPLD/MAXII/output_files/RAM4GS.asm.rpt
rename to CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt
index 1915f58..f918f0d
--- a/CPLD/MAXII/output_files/RAM4GS.asm.rpt
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.asm.rpt
@@ -1,6 +1,6 @@
-Assembler report for RAM4GS
-Thu Jul 23 02:20:55 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Assembler report for RAM2GS
+Mon Aug 16 18:40:22 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof
+  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof
   6. Assembler Messages
 
 
@@ -37,11 +37,11 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Jul 23 02:20:55 2020 ;
-; Revision Name         ; RAM4GS                                ;
-; Top-level Entity Name ; RAM4GS                                ;
-; Family                ; MAX II                                ;
-; Device                ; EPM240T100C5                          ;
+; Assembler Status      ; Successful - Mon Aug 16 18:40:22 2021 ;
+; Revision Name         ; RAM2GS                                ;
+; Top-level Entity Name ; RAM2GS                                ;
+; Family                ; MAX V                                 ;
+; Device                ; 5M240ZT100C5                          ;
 +-----------------------+---------------------------------------+
 
 
@@ -75,40 +75,40 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+-----------+---------------+
 
 
-+--------------------------------------------+
-; Assembler Generated Files                  ;
-+--------------------------------------------+
-; File Name                                  ;
-+--------------------------------------------+
-; /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
-+--------------------------------------------+
++----------------------------------------------------------------------------+
+; Assembler Generated Files                                                  ;
++----------------------------------------------------------------------------+
+; File Name                                                                  ;
++----------------------------------------------------------------------------+
+; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ;
++----------------------------------------------------------------------------+
 
 
-+----------------------------------------------------------------------+
-; Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
-+----------------+-----------------------------------------------------+
-; Option         ; Setting                                             ;
-+----------------+-----------------------------------------------------+
-; Device         ; EPM240T100C5                                        ;
-; JTAG usercode  ; 0x00173F26                                          ;
-; Checksum       ; 0x0017428E                                          ;
-+----------------+-----------------------------------------------------+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ;
++----------------+-------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                             ;
++----------------+-------------------------------------------------------------------------------------+
+; Device         ; 5M240ZT100C5                                                                        ;
+; JTAG usercode  ; 0x00172F05                                                                          ;
+; Checksum       ; 0x001732F5                                                                          ;
++----------------+-------------------------------------------------------------------------------------+
 
 
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
+Info: Running Quartus II 64-Bit Assembler
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Thu Jul 23 02:20:53 2020
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
+    Info: Processing started: Mon Aug 16 18:40:21 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 296 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:55 2020
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 381 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:22 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.done b/CPLD/MAX/MAXV/output_files/RAM2GS.done
new file mode 100644
index 0000000..576e1e8
--- /dev/null
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.done
@@ -0,0 +1 @@
+Mon Aug 16 18:40:25 2021
diff --git a/CPLD/AGM-src/output_files/RAM4GS.fit.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt
old mode 100755
new mode 100644
similarity index 77%
rename from CPLD/AGM-src/output_files/RAM4GS.fit.rpt
rename to CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt
index 15a6629..1cd6280
--- a/CPLD/AGM-src/output_files/RAM4GS.fit.rpt
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.rpt
@@ -1,6 +1,6 @@
-Fitter report for RAM4GS
-Thu Jul 23 02:20:50 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Fitter report for RAM2GS
+Mon Aug 16 18:40:21 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -59,15 +59,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Fitter Summary                                                              ;
 +---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Thu Jul 23 02:20:50 2020           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM4GS                                          ;
-; Top-level Entity Name     ; RAM4GS                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
+; Fitter Status             ; Successful - Mon Aug 16 18:40:21 2021           ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; RAM2GS                                          ;
+; Top-level Entity Name     ; RAM2GS                                          ;
+; Family                    ; MAX V                                           ;
+; Device                    ; 5M240ZT100C5                                    ;
 ; Timing Models             ; Final                                           ;
-; Total logic elements      ; 170 / 240 ( 71 % )                              ;
-; Total pins                ; 62 / 80 ( 78 % )                                ;
+; Total logic elements      ; 168 / 240 ( 70 % )                              ;
+; Total pins                ; 63 / 79 ( 80 % )                                ;
 ; Total virtual pins        ; 0                                               ;
 ; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
 +---------------------------+-------------------------------------------------+
@@ -78,7 +78,7 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------------------+--------------------------------+
 ; Option                                                                     ; Setting                        ; Default Value                  ;
 +----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                                     ; EPM240T100C5                   ;                                ;
+; Device                                                                     ; 5M240ZT100C5                   ;                                ;
 ; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
 ; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
 ; Placement Effort Multiplier                                                ; 10                             ; 1.0                            ;
@@ -122,27 +122,21 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------------------+--------------------------------+
 
 
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 2           ;
-; Maximum allowed            ; 2           ;
-;                            ;             ;
-; Average used               ; 1.33        ;
-; Maximum used               ; 2           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;  33.3%      ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
 
 
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
+The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pin.
 
 
 +------------------------------------------------------------------+
@@ -150,43 +144,43 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 +---------------------------------------------+--------------------+
 ; Resource                                    ; Usage              ;
 +---------------------------------------------+--------------------+
-; Total logic elements                        ; 170 / 240 ( 71 % ) ;
-;     -- Combinational with no register       ; 74                 ;
-;     -- Register only                        ; 21                 ;
-;     -- Combinational with a register        ; 75                 ;
+; Total logic elements                        ; 168 / 240 ( 70 % ) ;
+;     -- Combinational with no register       ; 71                 ;
+;     -- Register only                        ; 20                 ;
+;     -- Combinational with a register        ; 77                 ;
 ;                                             ;                    ;
 ; Logic element usage by number of LUT inputs ;                    ;
-;     -- 4 input functions                    ; 57                 ;
-;     -- 3 input functions                    ; 41                 ;
-;     -- 2 input functions                    ; 42                 ;
+;     -- 4 input functions                    ; 58                 ;
+;     -- 3 input functions                    ; 40                 ;
+;     -- 2 input functions                    ; 41                 ;
 ;     -- 1 input functions                    ; 8                  ;
 ;     -- 0 input functions                    ; 1                  ;
 ;                                             ;                    ;
 ; Logic elements by mode                      ;                    ;
-;     -- normal mode                          ; 154                ;
+;     -- normal mode                          ; 152                ;
 ;     -- arithmetic mode                      ; 16                 ;
-;     -- qfbk mode                            ; 6                  ;
+;     -- qfbk mode                            ; 7                  ;
 ;     -- register cascade mode                ; 0                  ;
-;     -- synchronous clear/load mode          ; 25                 ;
+;     -- synchronous clear/load mode          ; 24                 ;
 ;     -- asynchronous clear/load mode         ; 0                  ;
 ;                                             ;                    ;
-; Total registers                             ; 96 / 240 ( 40 % )  ;
-; Total LABs                                  ; 22 / 24 ( 92 % )   ;
+; Total registers                             ; 97 / 240 ( 40 % )  ;
+; Total LABs                                  ; 21 / 24 ( 88 % )   ;
 ; Logic elements in carry chains              ; 17                 ;
 ; Virtual pins                                ; 0                  ;
-; I/O pins                                    ; 62 / 80 ( 78 % )   ;
-;     -- Clock pins                           ; 2 / 4 ( 50 % )     ;
+; I/O pins                                    ; 63 / 79 ( 80 % )   ;
+;     -- Clock pins                           ; 3 / 4 ( 75 % )     ;
 ;                                             ;                    ;
 ; Global signals                              ; 4                  ;
 ; UFM blocks                                  ; 1 / 1 ( 100 % )    ;
 ; Global clocks                               ; 4 / 4 ( 100 % )    ;
 ; JTAGs                                       ; 0 / 1 ( 0 % )      ;
-; Average interconnect usage (total/H/V)      ; 25% / 27% / 23%    ;
-; Peak interconnect usage (total/H/V)         ; 25% / 27% / 23%    ;
-; Maximum fan-out                             ; 54                 ;
-; Highest non-global fan-out                  ; 38                 ;
-; Total fan-out                               ; 644                ;
-; Average fan-out                             ; 2.76               ;
+; Average interconnect usage (total/H/V)      ; 27% / 29% / 25%    ;
+; Peak interconnect usage (total/H/V)         ; 27% / 29% / 25%    ;
+; Maximum fan-out                             ; 55                 ;
+; Highest non-global fan-out                  ; 39                 ;
+; Total fan-out                               ; 643                ;
+; Average fan-out                             ; 2.77               ;
 +---------------------------------------------+--------------------+
 
 
@@ -216,9 +210,9 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 21                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 54                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
+; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 15                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
+; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 ; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
 +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
 
@@ -236,6 +230,7 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED     ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVTTL  ; 16mA             ; yes                    ; Fitter               ; 10 pF ; -                    ; -                   ;
 ; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -243,17 +238,17 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -265,14 +260,14 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 ; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
+; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
 
@@ -282,116 +277,116 @@ The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
 ; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
 +----------+-------------------+---------------+--------------+
 ; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 24 / 42 ( 57 % )  ; 3.3V          ; --           ;
+; 2        ; 25 / 41 ( 61 % )  ; 3.3V          ; --           ;
 +----------+-------------------+---------------+--------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                               ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; 1        ; 83         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 10       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 11       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 13       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 25       ; 19         ; 1        ; #TDO           ; output ;              ;           ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 32       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 46       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 58       ; 48         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 60       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 61       ; 49         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 62       ; 50         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 63       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 64       ; 51         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 65       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 75       ; 61         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 76       ; 62         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 77       ; 63         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 78       ; 64         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 79       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 81       ; 65         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 82       ; 66         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 83       ; 67         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 84       ; 68         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 85       ; 69         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 86       ; 70         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 87       ; 71         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 88       ; 72         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 93       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                             ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1        ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 10       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 11       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 13       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
+; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 25       ; 19         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 32       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 46       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 58       ; 48         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 60       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 61       ; 49         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 62       ; 50         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; yes      ; Off          ;
+; 63       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
+; 64       ; 51         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 65       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 66       ; 52         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
+; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
+; 75       ; 61         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 76       ; 62         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 77       ; 63         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 78       ; 64         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 79       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 81       ; 65         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 82       ; 66         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 83       ; 67         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 84       ; 68         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 85       ; 69         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 86       ; 70         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 87       ; 71         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 88       ; 72         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
+; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 93       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
+; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
 Note: Pin directions (input, output or bidir) are based on device operating in user mode.
 
 
@@ -407,6 +402,9 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 ; 1.5 V                      ; 10 pF ; Not Available          ;
 ; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
 ; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+; 1.2 V                      ; 10 pF ; Not Available          ;
+; LVDS_E_3R                  ; 10 pF ; Not Available          ;
+; RSDS_E_3R                  ; 10 pF ; Not Available          ;
 +----------------------------+-------+------------------------+
 Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
 
@@ -416,9 +414,9 @@ Note: User assignments will override these defaults. The user specified values a
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 ; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM4GS                                                   ; 170 (170)   ; 96           ; 1          ; 62   ; 0            ; 74 (74)      ; 21 (21)           ; 75 (75)          ; 17 (17)         ; 6 (6)      ; |RAM4GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work         ;
+; |RAM2GS                                                   ; 168 (168)   ; 97           ; 1          ; 63   ; 0            ; 71 (71)      ; 20 (20)           ; 77 (77)          ; 17 (17)         ; 7 (7)      ; |RAM2GS                                                                ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
+;       |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work         ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
@@ -428,6 +426,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------+----------+---------------+
 ; Name    ; Pin Type ; Pad to Core 0 ;
 +---------+----------+---------------+
+; nCRAS   ; Input    ; (0)           ;
 ; MAin[0] ; Input    ; (0)           ;
 ; MAin[1] ; Input    ; (0)           ;
 ; MAin[2] ; Input    ; (0)           ;
@@ -438,10 +437,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; MAin[7] ; Input    ; (0)           ;
 ; MAin[8] ; Input    ; (0)           ;
 ; MAin[9] ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; nCRAS   ; Input    ; (0)           ;
-; CROW[1] ; Input    ; (1)           ;
 ; RCLK    ; Input    ; (0)           ;
+; CROW[0] ; Input    ; (1)           ;
+; CROW[1] ; Input    ; (1)           ;
 ; PHI2    ; Input    ; (0)           ;
 ; Din[6]  ; Input    ; (1)           ;
 ; nFWE    ; Input    ; (1)           ;
@@ -461,6 +459,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Dout[5] ; Output   ; --            ;
 ; Dout[6] ; Output   ; --            ;
 ; Dout[7] ; Output   ; --            ;
+; LED     ; Output   ; --            ;
 ; RBA[0]  ; Output   ; --            ;
 ; RBA[1]  ; Output   ; --            ;
 ; RA[0]   ; Output   ; --            ;
@@ -498,16 +497,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
 ; Name           ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1     ; LC_X6_Y3_N3 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdSubmitted~0 ; LC_X6_Y3_N9 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1        ; LC_X2_Y1_N3 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; PHI2           ; PIN_52      ; 21      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-; RCLK           ; PIN_12      ; 54      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; Ready          ; LC_X3_Y2_N1 ; 38      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~5      ; LC_X5_Y3_N0 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; comb~2         ; LC_X4_Y4_N6 ; 8       ; Output enable           ; no     ; --                   ; --               ;
+; CmdDRDIn~1     ; LC_X5_Y4_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
+; CmdSubmitted~0 ; LC_X6_Y2_N4 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; DRDIn~1        ; LC_X4_Y1_N2 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
+; PHI2           ; PIN_52      ; 21      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
+; RCLK           ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
+; Ready          ; LC_X3_Y2_N8 ; 39      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; always8~5      ; LC_X7_Y3_N1 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
+; comb~3         ; LC_X4_Y4_N6 ; 8       ; Output enable           ; no     ; --                   ; --               ;
 ; nCCAS          ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-; nCRAS          ; PIN_67      ; 15      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
+; nCRAS          ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
 +----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
 
 
@@ -516,10 +515,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------+----------+---------+----------------------+------------------+
 ; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +-------+----------+---------+----------------------+------------------+
-; PHI2  ; PIN_52   ; 21      ; Global Clock         ; GCLK3            ;
-; RCLK  ; PIN_12   ; 54      ; Global Clock         ; GCLK0            ;
+; PHI2  ; PIN_52   ; 21      ; Global Clock         ; GCLK1            ;
+; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
 ; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
-; nCRAS ; PIN_67   ; 15      ; Global Clock         ; GCLK1            ;
+; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK3            ;
 +-------+----------+---------+----------------------+------------------+
 
 
@@ -528,99 +527,99 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------------------------------------------------------------------------+---------+
 ; Name                                                                                        ; Fan-Out ;
 +---------------------------------------------------------------------------------------------+---------+
-; Ready                                                                                       ; 38      ;
+; Ready                                                                                       ; 39      ;
 ; nRowColSel                                                                                  ; 13      ;
 ; S[1]                                                                                        ; 12      ;
 ; S[0]                                                                                        ; 12      ;
 ; RASr2                                                                                       ; 9       ;
 ; Din[6]                                                                                      ; 8       ;
-; comb~2                                                                                      ; 8       ;
-; FS[4]                                                                                       ; 8       ;
+; comb~3                                                                                      ; 8       ;
 ; Din[5]                                                                                      ; 7       ;
 ; Din[4]                                                                                      ; 7       ;
-; FS[5]                                                                                       ; 7       ;
 ; IS[0]~0                                                                                     ; 7       ;
 ; Din[7]                                                                                      ; 6       ;
 ; Din[0]                                                                                      ; 6       ;
 ; MAin[1]                                                                                     ; 6       ;
-; FS[6]                                                                                       ; 6       ;
-; always9~1                                                                                   ; 6       ;
 ; IS[0]                                                                                       ; 6       ;
+; FS[4]                                                                                       ; 6       ;
 ; Din[3]                                                                                      ; 5       ;
 ; Din[2]                                                                                      ; 5       ;
 ; MAin[0]                                                                                     ; 5       ;
-; FS[8]~27                                                                                    ; 5       ;
+; FS[8]~31                                                                                    ; 5       ;
 ; FS[3]~13                                                                                    ; 5       ;
 ; FS[3]                                                                                       ; 5       ;
-; always9~2                                                                                   ; 5       ;
-; FS[17]                                                                                      ; 5       ;
-; FS[16]                                                                                      ; 5       ;
 ; IS[1]                                                                                       ; 5       ;
 ; CBR                                                                                         ; 5       ;
 ; FWEr                                                                                        ; 5       ;
+; FS[6]                                                                                       ; 5       ;
+; FS[5]                                                                                       ; 5       ;
+; FS[17]                                                                                      ; 5       ;
+; FS[16]                                                                                      ; 5       ;
+; UFMD[15]                                                                                    ; 5       ;
 ; Din[1]                                                                                      ; 4       ;
 ; MAin[9]                                                                                     ; 4       ;
 ; MAin[7]                                                                                     ; 4       ;
 ; MAin[6]                                                                                     ; 4       ;
 ; CmdDRDIn~1                                                                                  ; 4       ;
-; UFMD                                                                                        ; 4       ;
-; FS[13]~21                                                                                   ; 4       ;
+; FS[13]~27                                                                                   ; 4       ;
 ; CMDWR~2                                                                                     ; 4       ;
 ; UFMReqErase                                                                                 ; 4       ;
+; always9~3                                                                                   ; 4       ;
+; DRCLK~0                                                                                     ; 4       ;
+; always9~2                                                                                   ; 4       ;
 ; Equal9~0                                                                                    ; 4       ;
-; n8MEGEN                                                                                     ; 4       ;
 ; IS[3]                                                                                       ; 4       ;
 ; IS[2]                                                                                       ; 4       ;
 ; InitReady                                                                                   ; 4       ;
+; always9~0                                                                                   ; 4       ;
 ; nFWE                                                                                        ; 3       ;
 ; MAin[5]                                                                                     ; 3       ;
 ; MAin[4]                                                                                     ; 3       ;
 ; MAin[3]                                                                                     ; 3       ;
 ; MAin[2]                                                                                     ; 3       ;
-; FS[0]                                                                                       ; 3       ;
 ; always8~5                                                                                   ; 3       ;
 ; CMDWR                                                                                       ; 3       ;
 ; CmdEnable                                                                                   ; 3       ;
+; FS[0]                                                                                       ; 3       ;
 ; always8~4                                                                                   ; 3       ;
 ; always8~2                                                                                   ; 3       ;
 ; Equal0~0                                                                                    ; 3       ;
-; always9~3                                                                                   ; 3       ;
-; UFMInitDone                                                                                 ; 3       ;
 ; nRCS~3                                                                                      ; 3       ;
+; n8MEGEN                                                                                     ; 3       ;
+; UFMInitDone~0                                                                               ; 3       ;
+; UFMInitDone                                                                                 ; 3       ;
 ; RCKE~reg0                                                                                   ; 3       ;
+; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; 3       ;
 ; MAin[8]                                                                                     ; 2       ;
-; FS[1]                                                                                       ; 2       ;
-; FS[2]                                                                                       ; 2       ;
-; Equal25~0                                                                                   ; 2       ;
-; FS[9]                                                                                       ; 2       ;
-; FS[8]                                                                                       ; 2       ;
 ; CmdSubmitted~0                                                                              ; 2       ;
 ; Equal17~0                                                                                   ; 2       ;
 ; CmdDRDIn~0                                                                                  ; 2       ;
 ; XOR8MEG~0                                                                                   ; 2       ;
 ; Equal0~3                                                                                    ; 2       ;
+; Ready~0                                                                                     ; 2       ;
+; Equal26~0                                                                                   ; 2       ;
+; FS[9]                                                                                       ; 2       ;
+; FS[8]                                                                                       ; 2       ;
 ; Equal5~1                                                                                    ; 2       ;
-; FS[15]                                                                                      ; 2       ;
 ; FS[14]                                                                                      ; 2       ;
 ; FS[13]                                                                                      ; 2       ;
 ; FS[12]                                                                                      ; 2       ;
 ; FS[11]                                                                                      ; 2       ;
 ; FS[10]                                                                                      ; 2       ;
-; Ready~0                                                                                     ; 2       ;
+; FS[15]                                                                                      ; 2       ;
+; Equal24~0                                                                                   ; 2       ;
+; FS[2]                                                                                       ; 2       ;
+; FS[1]                                                                                       ; 2       ;
 ; UFMOscEN~0                                                                                  ; 2       ;
 ; C1Submitted                                                                                 ; 2       ;
 ; Equal0~1                                                                                    ; 2       ;
 ; always8~0                                                                                   ; 2       ;
 ; CmdUFMErase                                                                                 ; 2       ;
 ; CmdUFMPrgm                                                                                  ; 2       ;
-; always9~6                                                                                   ; 2       ;
-; always9~5                                                                                   ; 2       ;
-; ARCLK~1                                                                                     ; 2       ;
 ; always9~4                                                                                   ; 2       ;
-; DRDIn~1                                                                                     ; 2       ;
-; FS[7]                                                                                       ; 2       ;
-; always9~0                                                                                   ; 2       ;
 ; PHI2r2                                                                                      ; 2       ;
+; DRDIn~1                                                                                     ; 2       ;
+; CmdSubmitted                                                                                ; 2       ;
 ; RASr                                                                                        ; 2       ;
 ; RCKEEN                                                                                      ; 2       ;
 ; CASr2                                                                                       ; 2       ;
@@ -630,13 +629,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; XOR8MEG                                                                                     ; 2       ;
 ; RA10~0                                                                                      ; 2       ;
 ; nRowColSel~0                                                                                ; 2       ;
+; always9~1                                                                                   ; 2       ;
+; FS[7]                                                                                       ; 2       ;
 ; UFMOscEN                                                                                    ; 2       ;
 ; UFMErase                                                                                    ; 2       ;
 ; UFMProgram                                                                                  ; 2       ;
-; ARShift                                                                                     ; 2       ;
-; ARCLK                                                                                       ; 2       ;
-; DRShift                                                                                     ; 2       ;
-; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; 2       ;
+; LEDEN                                                                                       ; 2       ;
 ; UFMProgram~_wirecell                                                                        ; 1       ;
 ; UFMOscEN~_wirecell                                                                          ; 1       ;
 ; UFMErase~_wirecell                                                                          ; 1       ;
@@ -652,37 +650,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; CROW[0]                                                                                     ; 1       ;
 ; CmdEnable~1                                                                                 ; 1       ;
 ; CmdEnable~0                                                                                 ; 1       ;
-; UFMD~1                                                                                      ; 1       ;
-; FS[1]~33COUT1_50                                                                            ; 1       ;
-; FS[1]~33                                                                                    ; 1       ;
-; UFMD~0                                                                                      ; 1       ;
-; UFMReqErase~0                                                                               ; 1       ;
-; FS[2]~31COUT1_52                                                                            ; 1       ;
-; FS[2]~31                                                                                    ; 1       ;
-; FS[9]~29COUT1_62                                                                            ; 1       ;
-; FS[9]~29                                                                                    ; 1       ;
-; UFMInitDone~0                                                                               ; 1       ;
 ; PHI2r                                                                                       ; 1       ;
 ; RCKEEN~2                                                                                    ; 1       ;
 ; RCKEEN~1                                                                                    ; 1       ;
 ; RCKEEN~0                                                                                    ; 1       ;
 ; CASr                                                                                        ; 1       ;
 ; Equal16~0                                                                                   ; 1       ;
+; n8MEGEN~3                                                                                   ; 1       ;
+; PHI2r3                                                                                      ; 1       ;
+; n8MEGEN~2                                                                                   ; 1       ;
+; n8MEGEN~1                                                                                   ; 1       ;
 ; n8MEGEN~0                                                                                   ; 1       ;
 ; Cmdn8MEGEN                                                                                  ; 1       ;
 ; IS[0]~3                                                                                     ; 1       ;
-; FS[15]~25COUT1_72                                                                           ; 1       ;
-; FS[15]~25                                                                                   ; 1       ;
-; FS[14]~23COUT1_70                                                                           ; 1       ;
-; FS[14]~23                                                                                   ; 1       ;
-; Equal5~0                                                                                    ; 1       ;
-; FS[12]~19COUT1_68                                                                           ; 1       ;
-; FS[12]~19                                                                                   ; 1       ;
-; FS[11]~17COUT1_66                                                                           ; 1       ;
-; FS[11]~17                                                                                   ; 1       ;
-; FS[10]~15COUT1_64                                                                           ; 1       ;
-; FS[10]~15                                                                                   ; 1       ;
 ; Ready~1                                                                                     ; 1       ;
+; FS[9]~33COUT1_62                                                                            ; 1       ;
+; FS[9]~33                                                                                    ; 1       ;
+; FS[14]~29COUT1_70                                                                           ; 1       ;
+; FS[14]~29                                                                                   ; 1       ;
+; Equal5~0                                                                                    ; 1       ;
+; FS[12]~25COUT1_68                                                                           ; 1       ;
+; FS[12]~25                                                                                   ; 1       ;
+; FS[11]~23COUT1_66                                                                           ; 1       ;
+; FS[11]~23                                                                                   ; 1       ;
+; FS[10]~21COUT1_64                                                                           ; 1       ;
+; FS[10]~21                                                                                   ; 1       ;
+; FS[15]~19COUT1_72                                                                           ; 1       ;
+; FS[15]~19                                                                                   ; 1       ;
+; UFMD[15]~0                                                                                  ; 1       ;
+; FS[2]~17COUT1_52                                                                            ; 1       ;
+; FS[2]~17                                                                                    ; 1       ;
+; FS[1]~15COUT1_50                                                                            ; 1       ;
+; FS[1]~15                                                                                    ; 1       ;
 ; WRD[7]                                                                                      ; 1       ;
 ; WRD[6]                                                                                      ; 1       ;
 ; WRD[5]                                                                                      ; 1       ;
@@ -704,23 +703,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Bank[2]                                                                                     ; 1       ;
 ; Bank[3]                                                                                     ; 1       ;
 ; Bank[1]                                                                                     ; 1       ;
-; ARShift~0                                                                                   ; 1       ;
-; ARCLK~3                                                                                     ; 1       ;
-; ARCLK~2                                                                                     ; 1       ;
+; always9~5                                                                                   ; 1       ;
 ; ARCLK~0                                                                                     ; 1       ;
 ; CmdDRCLK                                                                                    ; 1       ;
-; DRCLK~0                                                                                     ; 1       ;
-; FS[6]~11COUT1_58                                                                            ; 1       ;
-; FS[6]~11                                                                                    ; 1       ;
-; FS[7]~9COUT1_60                                                                             ; 1       ;
-; FS[7]~9                                                                                     ; 1       ;
-; FS[16]~5COUT1_74                                                                            ; 1       ;
-; FS[16]~5                                                                                    ; 1       ;
-; FS[4]~3COUT1_54                                                                             ; 1       ;
-; FS[4]~3                                                                                     ; 1       ;
-; FS[5]~1COUT1_56                                                                             ; 1       ;
-; FS[5]~1                                                                                     ; 1       ;
-; CmdSubmitted                                                                                ; 1       ;
 ; CmdDRDIn                                                                                    ; 1       ;
 ; nRCAS~1                                                                                     ; 1       ;
 ; nRCAS~0                                                                                     ; 1       ;
@@ -729,10 +714,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; nRCS~4                                                                                      ; 1       ;
 ; nRCS~2                                                                                      ; 1       ;
 ; nRowColSel~1                                                                                ; 1       ;
+; FS[4]~11COUT1_54                                                                            ; 1       ;
+; FS[4]~11                                                                                    ; 1       ;
+; FS[6]~9COUT1_58                                                                             ; 1       ;
+; FS[6]~9                                                                                     ; 1       ;
+; FS[5]~7COUT1_56                                                                             ; 1       ;
+; FS[5]~7                                                                                     ; 1       ;
+; FS[7]~5COUT1_60                                                                             ; 1       ;
+; FS[7]~5                                                                                     ; 1       ;
+; FS[16]~1COUT1_74                                                                            ; 1       ;
+; FS[16]~1                                                                                    ; 1       ;
+; ARShift                                                                                     ; 1       ;
+; ARCLK                                                                                       ; 1       ;
+; DRShift                                                                                     ; 1       ;
 ; DRCLK                                                                                       ; 1       ;
 ; DRDIn                                                                                       ; 1       ;
+; comb~2                                                                                      ; 1       ;
 ; comb~1                                                                                      ; 1       ;
-; comb~0                                                                                      ; 1       ;
 ; nRCAS~reg0                                                                                  ; 1       ;
 ; nRRAS~reg0                                                                                  ; 1       ;
 ; nRWE~reg0                                                                                   ; 1       ;
@@ -761,6 +759,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; RowA[0]                                                                                     ; 1       ;
 ; RBA[1]~reg0                                                                                 ; 1       ;
 ; RBA[0]~reg0                                                                                 ; 1       ;
+; comb~0                                                                                      ; 1       ;
 +---------------------------------------------------------------------------------------------+---------+
 
 
@@ -769,112 +768,112 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------------+--------------------+
 ; Other Routing Resource Type ; Usage              ;
 +-----------------------------+--------------------+
-; C4s                         ; 152 / 784 ( 19 % ) ;
-; Direct links                ; 45 / 888 ( 5 % )   ;
+; C4s                         ; 162 / 784 ( 21 % ) ;
+; Direct links                ; 39 / 888 ( 4 % )   ;
 ; Global clocks               ; 4 / 4 ( 100 % )    ;
 ; LAB clocks                  ; 15 / 32 ( 47 % )   ;
-; LUT chains                  ; 22 / 216 ( 10 % )  ;
-; Local interconnects         ; 270 / 888 ( 30 % ) ;
-; R4s                         ; 155 / 704 ( 22 % ) ;
+; LUT chains                  ; 20 / 216 ( 9 % )   ;
+; Local interconnects         ; 275 / 888 ( 31 % ) ;
+; R4s                         ; 173 / 704 ( 25 % ) ;
 +-----------------------------+--------------------+
 
 
 +---------------------------------------------------------------------------+
 ; LAB Logic Elements                                                        ;
 +--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 7.73) ; Number of LABs  (Total = 22) ;
+; Number of Logic Elements  (Average = 8.00) ; Number of LABs  (Total = 21) ;
 +--------------------------------------------+------------------------------+
 ; 1                                          ; 0                            ;
-; 2                                          ; 2                            ;
+; 2                                          ; 1                            ;
 ; 3                                          ; 2                            ;
-; 4                                          ; 2                            ;
-; 5                                          ; 0                            ;
-; 6                                          ; 1                            ;
-; 7                                          ; 0                            ;
-; 8                                          ; 2                            ;
-; 9                                          ; 0                            ;
-; 10                                         ; 13                           ;
+; 4                                          ; 0                            ;
+; 5                                          ; 3                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 1                            ;
+; 8                                          ; 0                            ;
+; 9                                          ; 2                            ;
+; 10                                         ; 12                           ;
 +--------------------------------------------+------------------------------+
 
 
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.18) ; Number of LABs  (Total = 22) ;
+; LAB-wide Signals  (Average = 1.33) ; Number of LABs  (Total = 21) ;
 +------------------------------------+------------------------------+
-; 1 Clock                            ; 14                           ;
+; 1 Clock                            ; 12                           ;
 ; 1 Clock enable                     ; 2                            ;
-; 1 Sync. clear                      ; 3                            ;
+; 1 Sync. clear                      ; 4                            ;
 ; 1 Sync. load                       ; 1                            ;
-; 2 Clocks                           ; 6                            ;
+; 2 Clocks                           ; 9                            ;
 +------------------------------------+------------------------------+
 
 
 +----------------------------------------------------------------------------+
 ; LAB Signals Sourced                                                        ;
 +---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 7.91) ; Number of LABs  (Total = 22) ;
+; Number of Signals Sourced  (Average = 8.29) ; Number of LABs  (Total = 21) ;
 +---------------------------------------------+------------------------------+
 ; 0                                           ; 0                            ;
 ; 1                                           ; 0                            ;
-; 2                                           ; 2                            ;
-; 3                                           ; 2                            ;
-; 4                                           ; 2                            ;
-; 5                                           ; 0                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 0                            ;
-; 8                                           ; 1                            ;
+; 2                                           ; 1                            ;
+; 3                                           ; 1                            ;
+; 4                                           ; 1                            ;
+; 5                                           ; 3                            ;
+; 6                                           ; 0                            ;
+; 7                                           ; 1                            ;
+; 8                                           ; 0                            ;
 ; 9                                           ; 1                            ;
-; 10                                          ; 11                           ;
-; 11                                          ; 1                            ;
-; 12                                          ; 1                            ;
+; 10                                          ; 9                            ;
+; 11                                          ; 4                            ;
 +---------------------------------------------+------------------------------+
 
 
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.73) ; Number of LABs  (Total = 22) ;
+; Number of Signals Sourced Out  (Average = 5.76) ; Number of LABs  (Total = 21) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 0                            ;
-; 1                                               ; 2                            ;
+; 1                                               ; 0                            ;
 ; 2                                               ; 2                            ;
-; 3                                               ; 3                            ;
-; 4                                               ; 2                            ;
-; 5                                               ; 0                            ;
-; 6                                               ; 4                            ;
+; 3                                               ; 2                            ;
+; 4                                               ; 4                            ;
+; 5                                               ; 2                            ;
+; 6                                               ; 3                            ;
 ; 7                                               ; 2                            ;
-; 8                                               ; 1                            ;
-; 9                                               ; 3                            ;
-; 10                                              ; 3                            ;
+; 8                                               ; 3                            ;
+; 9                                               ; 1                            ;
+; 10                                              ; 2                            ;
 +-------------------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Distinct Inputs                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 10.18) ; Number of LABs  (Total = 22) ;
+; Number of Distinct Inputs  (Average = 11.29) ; Number of LABs  (Total = 21) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
 ; 1                                            ; 0                            ;
 ; 2                                            ; 0                            ;
 ; 3                                            ; 2                            ;
-; 4                                            ; 1                            ;
-; 5                                            ; 1                            ;
-; 6                                            ; 0                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 2                            ;
 ; 7                                            ; 1                            ;
-; 8                                            ; 2                            ;
-; 9                                            ; 4                            ;
-; 10                                           ; 1                            ;
-; 11                                           ; 1                            ;
-; 12                                           ; 2                            ;
-; 13                                           ; 3                            ;
+; 8                                            ; 0                            ;
+; 9                                            ; 1                            ;
+; 10                                           ; 2                            ;
+; 11                                           ; 2                            ;
+; 12                                           ; 4                            ;
+; 13                                           ; 1                            ;
 ; 14                                           ; 1                            ;
-; 15                                           ; 0                            ;
-; 16                                           ; 1                            ;
-; 17                                           ; 1                            ;
+; 15                                           ; 1                            ;
+; 16                                           ; 2                            ;
+; 17                                           ; 0                            ;
 ; 18                                           ; 0                            ;
 ; 19                                           ; 1                            ;
+; 20                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
 
@@ -898,8 +897,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------+----------------------+-------------------+
 ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
 +-----------------+----------------------+-------------------+
-; I/O             ; nCRAS                ; 1.3               ;
-; I/O             ; RCLK                 ; 1.2               ;
+; I/O             ; nCRAS                ; 1.4               ;
 +-----------------+----------------------+-------------------+
 Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
 This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
@@ -910,29 +908,32 @@ This will disable optimization of problematic paths and expose them for further
 +-----------------+----------------------+-------------------+
 ; Source Register ; Destination Register ; Delay Added in ns ;
 +-----------------+----------------------+-------------------+
-; nCCAS           ; CBR                  ; 1.303             ;
-; PHI2            ; PHI2r                ; 0.610             ;
-; nCRAS           ; RASr                 ; 0.301             ;
+; nCCAS           ; CBR                  ; 1.374             ;
+; PHI2            ; PHI2r                ; 0.176             ;
 +-----------------+----------------------+-------------------+
-Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
+Note: This table only shows the top 2 path(s) that have the largest delay added for hold.
 
 
 +-----------------+
 ; Fitter Messages ;
 +-----------------+
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (119006): Selected device EPM240T100C5 for design "RAM4GS"
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS"
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
 Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
 Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
 Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EPM240T100I5 is compatible
-    Info (176445): Device EPM240T100A5 is compatible
-    Info (176445): Device EPM570T100C5 is compatible
-    Info (176445): Device EPM570T100I5 is compatible
-    Info (176445): Device EPM570T100A5 is compatible
-Info (332104): Reading SDC File: 'constraints.sdc'
+    Info (176445): Device 5M80ZT100C5 is compatible
+    Info (176445): Device 5M80ZT100I5 is compatible
+    Info (176445): Device 5M160ZT100C5 is compatible
+    Info (176445): Device 5M160ZT100I5 is compatible
+    Info (176445): Device 5M240ZT100I5 is compatible
+    Info (176445): Device 5M570ZT100C5 is compatible
+    Info (176445): Device 5M570ZT100I5 is compatible
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins
+    Info (169086): Pin LED not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332144): No user constrained base clocks found in the design
 Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
     Info (332127): Assuming a default timing requirement
@@ -951,11 +952,12 @@ Info (186216): Automatically promoted some destinations of signal "PHI2" to use
     Info (186217): Destination "PHI2r" may be non-global or may not use global clock
 Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position
 Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock
+    Info (186217): Destination "comb~0" may be non-global or may not use global clock
     Info (186217): Destination "RASr" may be non-global or may not use global clock
 Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position
 Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock
     Info (186217): Destination "CBR" may be non-global or may not use global clock
-    Info (186217): Destination "comb~2" may be non-global or may not use global clock
+    Info (186217): Destination "comb~3" may be non-global or may not use global clock
     Info (186217): Destination "CASr" may be non-global or may not use global clock
 Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position
 Info (186079): Completed Auto Global Promotion Operation
@@ -964,6 +966,13 @@ Info (186391): Fitter is using Normal packing mode for logic elements with Auto
 Info (186468): Started processing fast register assignments
 Info (186469): Finished processing fast register assignments
 Info (176235): Finished register packing
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  17 pins available
 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -974,20 +983,20 @@ Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 20% of the available device resources
     Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings
-    Info: Peak virtual memory: 376 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:50 2020
-    Info: Elapsed time: 00:00:08
-    Info: Total CPU time (on all processors): 00:00:08
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 548 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:21 2021
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:03
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg.
 
 
diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.smsg b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/MAXII/output_files/RAM4GS.fit.smsg
rename to CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary
new file mode 100644
index 0000000..9f20503
--- /dev/null
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.fit.summary
@@ -0,0 +1,11 @@
+Fitter Status : Successful - Mon Aug 16 18:40:21 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX V
+Device : 5M240ZT100C5
+Timing Models : Final
+Total logic elements : 168 / 240 ( 70 % )
+Total pins : 63 / 79 ( 80 % )
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/AGM-src/output_files/RAM4GS.flow.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt
old mode 100755
new mode 100644
similarity index 55%
rename from CPLD/AGM-src/output_files/RAM4GS.flow.rpt
rename to CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt
index cab50ca..3bd2467
--- a/CPLD/AGM-src/output_files/RAM4GS.flow.rpt
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.flow.rpt
@@ -1,6 +1,6 @@
-Flow report for RAM4GS
-Thu Jul 23 02:21:02 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Flow report for RAM2GS
+Mon Aug 16 18:40:24 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -40,15 +40,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Flow Summary                                                                ;
 +---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Thu Jul 23 02:20:55 2020           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM4GS                                          ;
-; Top-level Entity Name     ; RAM4GS                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
+; Flow Status               ; Successful - Mon Aug 16 18:40:22 2021           ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; RAM2GS                                          ;
+; Top-level Entity Name     ; RAM2GS                                          ;
+; Family                    ; MAX V                                           ;
+; Device                    ; 5M240ZT100C5                                    ;
 ; Timing Models             ; Final                                           ;
-; Total logic elements      ; 170 / 240 ( 71 % )                              ;
-; Total pins                ; 62 / 80 ( 78 % )                                ;
+; Total logic elements      ; 168 / 240 ( 70 % )                              ;
+; Total pins                ; 63 / 79 ( 80 % )                                ;
 ; Total virtual pins        ; 0                                               ;
 ; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
 +---------------------------+-------------------------------------------------+
@@ -59,34 +59,34 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 07/23/2020 02:20:37 ;
+; Start date & time ; 08/16/2021 18:40:16 ;
 ; Main task         ; Compilation         ;
-; Revision Name     ; RAM4GS              ;
+; Revision Name     ; RAM2GS              ;
 +-------------------+---------------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                       ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
-; Assignment Name                            ; Value                          ; Default Value ; Entity Name ; Section Id ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
-; ALLOW_POWER_UP_DONT_CARE                   ; Off                            ; On            ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                      ; 44085571633675.159548523602288 ; --            ; --          ; --         ;
-; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                             ; Off           ; --          ; --         ;
-; FITTER_EFFORT                              ; Standard Fit                   ; Auto Fit      ; --          ; --         ;
-; IP_TOOL_NAME                               ; ALTUFM_NONE                    ; --            ; --          ; --         ;
-; IP_TOOL_VERSION                            ; 13.0                           ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                     ; 85                             ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                     ; 0                              ; --            ; --          ; --         ;
-; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers          ; Normal        ; --          ; --         ;
-; OPTIMIZE_MULTI_CORNER_TIMING               ; On                             ; Off           ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                ; 10                             ; 1.0           ; --          ; --         ;
-; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                         ; 12.5%         ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                   ; output_files                   ; --            ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                   ; 10                             ; 1.0           ; --          ; --         ;
-; SAFE_STATE_MACHINE                         ; On                             ; Off           ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                            ; --            ; --          ; --         ;
-+--------------------------------------------+--------------------------------+---------------+-------------+------------+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                            ; Value                        ; Default Value ; Entity Name ; Section Id ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
+; ALLOW_POWER_UP_DONT_CARE                   ; Off                          ; On            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                      ; 962837114763.162915361605944 ; --            ; --          ; --         ;
+; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                           ; Off           ; --          ; --         ;
+; FITTER_EFFORT                              ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
+; IP_TOOL_NAME                               ; ALTUFM_NONE                  ; --            ; --          ; --         ;
+; IP_TOOL_VERSION                            ; 13.0                         ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                     ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                     ; 0                            ; --            ; --          ; --         ;
+; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers        ; Normal        ; --          ; --         ;
+; OPTIMIZE_MULTI_CORNER_TIMING               ; On                           ; Off           ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                ; 10                           ; 1.0           ; --          ; --         ;
+; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                       ; 12.5%         ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                   ; output_files                 ; --            ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                   ; 10                           ; 1.0           ; --          ; --         ;
+; SAFE_STATE_MACHINE                         ; On                           ; Off           ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                          ; --            ; --          ; --         ;
++--------------------------------------------+------------------------------+---------------+-------------+------------+
 
 
 +-------------------------------------------------------------------------------------------------------------------------------+
@@ -94,33 +94,33 @@ applicable agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:05     ; 1.0                     ; 303 MB              ; 00:00:05                           ;
-; Fitter                    ; 00:00:08     ; 1.3                     ; 376 MB              ; 00:00:07                           ;
-; Assembler                 ; 00:00:02     ; 1.0                     ; 295 MB              ; 00:00:02                           ;
-; TimeQuest Timing Analyzer ; 00:00:05     ; 1.0                     ; 288 MB              ; 00:00:04                           ;
-; Total                     ; 00:00:20     ; --                      ; --                  ; 00:00:18                           ;
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 421 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:03     ; 1.0                     ; 548 MB              ; 00:00:03                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 368 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:06     ; --                      ; --                  ; 00:00:06                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis      ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; Fitter                    ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; Assembler                 ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-; TimeQuest Timing Analyzer ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
-+---------------------------+------------------+------------+------------+----------------+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
 
 
 ------------
 ; Flow Log ;
 ------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
-quartus_sta RAM4GS -c RAM4GS
+quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+quartus_sta RAM2GS-MAXV -c RAM2GS
 
 
 
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.jdi b/CPLD/MAX/MAXV/output_files/RAM2GS.jdi
new file mode 100644
index 0000000..448e697
--- /dev/null
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.jdi
@@ -0,0 +1,8 @@
+
+  
+    
+  
+  
+    
+  
+
diff --git a/CPLD/AGM-src/output_files/RAM4GS.map.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt
old mode 100755
new mode 100644
similarity index 80%
rename from CPLD/AGM-src/output_files/RAM4GS.map.rpt
rename to CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt
index 9d88205..ac1eb15
--- a/CPLD/AGM-src/output_files/RAM4GS.map.rpt
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.rpt
@@ -1,6 +1,6 @@
-Analysis & Synthesis report for RAM4GS
-Thu Jul 23 02:20:40 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Analysis & Synthesis report for RAM2GS
+Mon Aug 16 18:40:17 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -45,13 +45,13 @@ applicable agreement for further details.
 +-------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                  ;
 +-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020           ;
-; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name               ; RAM4GS                                          ;
-; Top-level Entity Name       ; RAM4GS                                          ;
-; Family                      ; MAX II                                          ;
-; Total logic elements        ; 178                                             ;
-; Total pins                  ; 62                                              ;
+; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:17 2021           ;
+; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name               ; RAM2GS                                          ;
+; Top-level Entity Name       ; RAM2GS                                          ;
+; Family                      ; MAX V                                           ;
+; Total logic elements        ; 177                                             ;
+; Total pins                  ; 63                                              ;
 ; Total virtual pins          ; 0                                               ;
 ; UFM blocks                  ; 1 / 1 ( 100 % )                                 ;
 +-----------------------------+-------------------------------------------------+
@@ -62,9 +62,9 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------+--------------------+
 ; Option                                                                     ; Setting            ; Default Value      ;
 +----------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                     ; EPM240T100C5       ;                    ;
-; Top-level entity name                                                      ; RAM4GS             ; RAM4GS             ;
-; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
+; Device                                                                     ; 5M240ZT100C5       ;                    ;
+; Top-level entity name                                                      ; RAM2GS             ; RAM2GS             ;
+; Family name                                                                ; MAX V              ; Cyclone IV GX      ;
 ; Safe State Machine                                                         ; On                 ; Off                ;
 ; Power-Up Don't Care                                                        ; Off                ; On                 ;
 ; Use smart compilation                                                      ; Off                ; Off                ;
@@ -130,32 +130,25 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------+--------------------+
 
 
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 2           ;
-; Maximum allowed            ; 2           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                      ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                              ; Library ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
-; RAM4GS.v                         ; yes             ; User Verilog HDL File            ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v   ;         ;
-; RAM4GS.mif                       ; yes             ; User Memory Initialization File  ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v      ;         ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                  ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                   ; File Name with Absolute Path                               ; Library ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
+; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File       ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ;         ;
+; UFM.v                            ; yes             ; User Wizard-Generated File  ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v   ;         ;
++----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -163,32 +156,32 @@ applicable agreement for further details.
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 178   ;
-;     -- Combinational with no register       ; 82    ;
+; Total logic elements                        ; 177   ;
+;     -- Combinational with no register       ; 80    ;
 ;     -- Register only                        ; 29    ;
-;     -- Combinational with a register        ; 67    ;
+;     -- Combinational with a register        ; 68    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 57    ;
-;     -- 3 input functions                    ; 41    ;
-;     -- 2 input functions                    ; 42    ;
+;     -- 4 input functions                    ; 58    ;
+;     -- 3 input functions                    ; 40    ;
+;     -- 2 input functions                    ; 41    ;
 ;     -- 1 input functions                    ; 8     ;
 ;     -- 0 input functions                    ; 1     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 162   ;
+;     -- normal mode                          ; 161   ;
 ;     -- arithmetic mode                      ; 16    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
 ;     -- synchronous clear/load mode          ; 9     ;
 ;     -- asynchronous clear/load mode         ; 0     ;
 ;                                             ;       ;
-; Total registers                             ; 96    ;
+; Total registers                             ; 97    ;
 ; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 62    ;
+; I/O pins                                    ; 63    ;
 ; UFM blocks                                  ; 1     ;
 ; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 54    ;
+; Maximum fan-out                             ; 55    ;
 ; Total fan-out                               ; 643   ;
 ; Average fan-out                             ; 2.67  ;
 +---------------------------------------------+-------+
@@ -199,20 +192,20 @@ applicable agreement for further details.
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 ; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM4GS                                                   ; 178 (178)   ; 96           ; 1          ; 62   ; 0            ; 82 (82)      ; 29 (29)           ; 67 (67)          ; 17 (17)         ; 0 (0)      ; |RAM4GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work         ;
+; |RAM2GS                                                   ; 177 (177)   ; 97           ; 1          ; 63   ; 0            ; 80 (80)      ; 29 (29)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; work         ;
+;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
+;       |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work         ;
 +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                                                       ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                      ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
-; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ;
-+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                           ;
++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                          ;
++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
+; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v ;
++--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
 
 
 +------------------------------------------------------+
@@ -220,7 +213,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 96    ;
+; Total registers                              ; 97    ;
 ; Number of registers using Synchronous Clear  ; 6     ;
 ; Number of registers using Synchronous Load   ; 3     ;
 ; Number of registers using Asynchronous Clear ; 0     ;
@@ -248,8 +241,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|S[0]               ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|C1Submitted        ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[0]               ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|ADSubmitted        ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 
 
@@ -269,22 +262,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Analysis & Synthesis Messages ;
 +-------------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
+Info: Running Quartus II 64-Bit Analysis & Synthesis
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Thu Jul 23 02:20:35 2020
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v
-    Info (12023): Found entity 1: RAM4GS
+    Info: Processing started: Mon Aug 16 18:40:16 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v
+    Info (12023): Found entity 1: RAM2GS
 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_1br
+    Info (12023): Found entity 1: UFM_altufm_none_mjr
     Info (12023): Found entity 2: UFM
-Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)
-Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)
+Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)
 Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
-Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component"
+Info (12128): Elaborating entity "UFM_altufm_none_mjr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component"
+Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0
 Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
 Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
 Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
@@ -295,21 +289,21 @@ Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot
 Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
 Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 29 output pins
+    Info (21059): Implemented 30 output pins
     Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 178 logic cells
+    Info (21061): Implemented 177 logic cells
     Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 303 megabytes
-    Info: Processing ended: Thu Jul 23 02:20:41 2020
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:05
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings
+    Info: Peak virtual memory: 421 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:17 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg.
 
 
diff --git a/CPLD/MAXII/output_files/RAM4GS.map.smsg b/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg
old mode 100755
new mode 100644
similarity index 71%
rename from CPLD/MAXII/output_files/RAM4GS.map.smsg
rename to CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg
index 4c14264..a8e8eb9
--- a/CPLD/MAXII/output_files/RAM4GS.map.smsg
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM4GS.v(52): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z"
 Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
 Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary
new file mode 100644
index 0000000..68f556c
--- /dev/null
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.map.summary
@@ -0,0 +1,9 @@
+Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:17 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : RAM2GS
+Top-level Entity Name : RAM2GS
+Family : MAX V
+Total logic elements : 177
+Total pins : 63
+Total virtual pins : 0
+UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM4GS.pin b/CPLD/MAX/MAXV/output_files/RAM2GS.pin
old mode 100755
new mode 100644
similarity index 93%
rename from CPLD/MAXII/output_files/RAM4GS.pin
rename to CPLD/MAX/MAXV/output_files/RAM2GS.pin
index 86ba0f4..299181b
--- a/CPLD/MAXII/output_files/RAM4GS.pin
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.pin
@@ -23,7 +23,7 @@
  ---------------------------------------------------------------------------------
  -- NC            : No Connect. This pin has no internal connection to the device.
  -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.8V).
  -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
  --                 of its bank.
  --					Bank 1:		3.3V
@@ -57,12 +57,12 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP  "RAM4GS"  ASSIGNED TO AN: EPM240T100C5
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "RAM2GS"  ASSIGNED TO AN: 5M240ZT100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
-GND*                         : 1         :        :                   :         : 2         :                
+GND                          : 1         : gnd    :                   :         :           :                
 RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
 nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
 nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
@@ -71,10 +71,10 @@ nRRAS                        : 6         : output : 3.3-V LVCMOS      :
 RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
 RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 10        : gnd    :                   :         :           :                
-GNDINT                       : 11        : gnd    :                   :         :           :                
+GND                          : 10        : gnd    :                   :         :           :                
+GND                          : 11        : gnd    :                   :         :           :                
 RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
+VCCINT                       : 13        : power  :                   : 1.8V    :           :                
 RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
 RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
 RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
@@ -93,7 +93,7 @@ Dout[5]                      : 28        : output : 3.3-V LVCMOS      :
 RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
 RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 32        : gnd    :                   :         :           :                
+GND                          : 32        : gnd    :                   :         :           :                
 Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
 Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
 Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
@@ -107,7 +107,7 @@ Din[0]                       : 42        : input  : 3.3-V LVCMOS      :
 Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
 Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 46        : gnd    :                   :         :           :                
+GND                          : 46        : gnd    :                   :         :           :                
 Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
 nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
 MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
@@ -121,12 +121,12 @@ Dout[2]                      : 56        : output : 3.3-V LVCMOS      :
 Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
 GND*                         : 58        :        :                   :         : 2         :                
 VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
-GNDIO                        : 60        : gnd    :                   :         :           :                
+GND                          : 60        : gnd    :                   :         :           :                
 GND*                         : 61        :        :                   :         : 2         :                
-GND*                         : 62        :        :                   :         : 2         :                
-VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
+LED                          : 62        : output : 3.3-V LVTTL       :         : 2         : N              
+VCCINT                       : 63        : power  :                   : 1.8V    :           :                
 GND*                         : 64        :        :                   :         : 2         :                
-GNDINT                       : 65        : gnd    :                   :         :           :                
+GND                          : 65        : gnd    :                   :         :           :                
 GND*                         : 66        :        :                   :         : 2         :                
 nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
 MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
@@ -140,7 +140,7 @@ GND*                         : 75        :        :                   :
 GND*                         : 76        :        :                   :         : 2         :                
 GND*                         : 77        :        :                   :         : 2         :                
 GND*                         : 78        :        :                   :         : 2         :                
-GNDIO                        : 79        : gnd    :                   :         :           :                
+GND                          : 79        : gnd    :                   :         :           :                
 VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
 GND*                         : 81        :        :                   :         : 2         :                
 GND*                         : 82        :        :                   :         : 2         :                
@@ -154,7 +154,7 @@ RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :
 RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
 RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
 RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-GNDIO                        : 93        : gnd    :                   :         :           :                
+GND                          : 93        : gnd    :                   :         :           :                
 VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
 RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
 RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.pof b/CPLD/MAX/MAXV/output_files/RAM2GS.pof
new file mode 100644
index 0000000..b9b6f58
Binary files /dev/null and b/CPLD/MAX/MAXV/output_files/RAM2GS.pof differ
diff --git a/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt
new file mode 100644
index 0000000..34ffbe8
--- /dev/null
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.rpt
@@ -0,0 +1,1576 @@
+TimeQuest Timing Analyzer report for RAM2GS
+Mon Aug 16 18:40:24 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Fmax Summary
+  6. Setup Summary
+  7. Hold Summary
+  8. Recovery Summary
+  9. Removal Summary
+ 10. Minimum Pulse Width Summary
+ 11. Setup: 'ARCLK'
+ 12. Setup: 'DRCLK'
+ 13. Setup: 'PHI2'
+ 14. Setup: 'RCLK'
+ 15. Setup: 'nCRAS'
+ 16. Hold: 'ARCLK'
+ 17. Hold: 'DRCLK'
+ 18. Hold: 'PHI2'
+ 19. Hold: 'nCRAS'
+ 20. Hold: 'RCLK'
+ 21. Minimum Pulse Width: 'ARCLK'
+ 22. Minimum Pulse Width: 'DRCLK'
+ 23. Minimum Pulse Width: 'PHI2'
+ 24. Minimum Pulse Width: 'RCLK'
+ 25. Minimum Pulse Width: 'nCCAS'
+ 26. Minimum Pulse Width: 'nCRAS'
+ 27. Setup Times
+ 28. Hold Times
+ 29. Clock to Output Times
+ 30. Minimum Clock to Output Times
+ 31. Propagation Delay
+ 32. Minimum Propagation Delay
+ 33. Output Enable Times
+ 34. Minimum Output Enable Times
+ 35. Output Disable Times
+ 36. Minimum Output Disable Times
+ 37. Setup Transfers
+ 38. Hold Transfers
+ 39. Report TCCS
+ 40. Report RSKM
+ 41. Unconstrained Paths
+ 42. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                      ;
++--------------------+-------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
+; Revision Name      ; RAM2GS                                                            ;
+; Device Family      ; MAX V                                                             ;
+; Device Name        ; 5M240ZT100C5                                                      ;
+; Timing Models      ; Final                                                             ;
+; Delay Model        ; Slow Model                                                        ;
+; Rise/Fall Delays   ; Unavailable                                                       ;
++--------------------+-------------------------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                            ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+; ARCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
+; DRCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
+; nCCAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
+; nCRAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
+; PHI2       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
+; RCLK       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
+
+
++-------------------------------------------------+
+; Fmax Summary                                    ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
+; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
+; 20.71 MHz ; 20.71 MHz       ; PHI2       ;      ;
+; 47.75 MHz ; 47.75 MHz       ; RCLK       ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++---------------------------------+
+; Setup Summary                   ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -99.000 ; -99.000       ;
+; DRCLK ; -99.000 ; -99.000       ;
+; PHI2  ; -23.638 ; -216.621      ;
+; RCLK  ; -19.942 ; -610.547      ;
+; nCRAS ; -3.072  ; -6.479        ;
++-------+---------+---------------+
+
+
++---------------------------------+
+; Hold Summary                    ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -16.153 ; -16.153       ;
+; DRCLK ; -14.623 ; -14.623       ;
+; PHI2  ; -2.569  ; -3.433        ;
+; nCRAS ; -0.713  ; -2.822        ;
+; RCLK  ; 2.127   ; 0.000         ;
++-------+---------+---------------+
+
+
+--------------------
+; Recovery Summary ;
+--------------------
+No paths to report.
+
+
+-------------------
+; Removal Summary ;
+-------------------
+No paths to report.
+
+
++---------------------------------+
+; Minimum Pulse Width Summary     ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; ARCLK ; -29.500 ; -59.000       ;
+; DRCLK ; -29.500 ; -59.000       ;
+; PHI2  ; -2.289  ; -2.289        ;
+; RCLK  ; -2.289  ; -2.289        ;
+; nCCAS ; -2.289  ; -2.289        ;
+; nCRAS ; -2.289  ; -2.289        ;
++-------+---------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 1.000        ; 0.000      ; 80.000     ;
+; -22.847 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 1.000        ; -0.884     ; 2.963      ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 1.000        ; 0.000      ; 80.000     ;
+; -24.468 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -0.994     ; 4.474      ;
+; -24.377 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -0.994     ; 4.383      ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2'                                                                                              ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -23.638 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 23.817     ;
+; -23.413 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 23.592     ;
+; -22.503 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 22.682     ;
+; -21.937 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 22.116     ;
+; -21.404 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.583     ;
+; -21.232 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.411     ;
+; -21.179 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.358     ;
+; -20.812 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.991     ;
+; -20.269 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.448     ;
+; -20.229 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
+; -20.229 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
+; -20.229 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
+; -20.229 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
+; -20.189 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.368     ;
+; -20.004 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
+; -20.004 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
+; -20.004 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
+; -20.004 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
+; -19.703 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.882     ;
+; -19.309 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.488     ;
+; -19.309 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.488     ;
+; -19.094 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
+; -19.094 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
+; -19.094 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
+; -19.094 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
+; -19.084 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.263     ;
+; -19.084 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.263     ;
+; -18.998 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.177     ;
+; -18.578 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.757     ;
+; -18.528 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
+; -18.528 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
+; -18.528 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
+; -18.528 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
+; -18.174 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.353     ;
+; -18.174 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.353     ;
+; -17.993 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.172     ;
+; -17.955 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.134     ;
+; -17.823 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
+; -17.823 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
+; -17.823 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
+; -17.823 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
+; -17.608 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.787     ;
+; -17.608 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.787     ;
+; -17.403 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
+; -17.403 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
+; -17.403 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
+; -17.403 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
+; -16.903 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.082     ;
+; -16.903 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.082     ;
+; -16.780 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
+; -16.780 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
+; -16.780 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
+; -16.780 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
+; -16.483 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.662     ;
+; -16.483 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.662     ;
+; -15.860 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.039     ;
+; -15.860 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.039     ;
+; -15.759 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.938     ;
+; -15.305 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.484     ;
+; -15.305 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.484     ;
+; -15.080 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.259     ;
+; -15.080 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.259     ;
+; -14.777 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.956     ;
+; -14.584 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
+; -14.584 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
+; -14.584 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
+; -14.584 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
+; -14.552 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.731     ;
+; -14.170 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.349     ;
+; -14.170 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.349     ;
+; -13.664 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.843     ;
+; -13.664 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.843     ;
+; -13.642 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.821     ;
+; -13.604 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.783     ;
+; -13.604 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.783     ;
+; -13.076 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.255     ;
+; -12.899 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.078     ;
+; -12.899 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.078     ;
+; -12.479 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.658     ;
+; -12.479 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.658     ;
+; -12.415 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
+; -12.415 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
+; -12.415 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
+; -12.415 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
+; -12.371 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.550     ;
+; -11.951 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.130     ;
+; -11.942 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.621     ;
+; -11.942 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.621     ;
+; -11.856 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.035     ;
+; -11.856 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.035     ;
+; -11.414 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.093     ;
+; -11.328 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 11.507     ;
+; -9.660  ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.839      ;
+; -9.660  ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.839      ;
+; -9.132  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.311      ;
+; -8.463  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 9.142      ;
+; -8.261  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 8.940      ;
+; -7.499  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 8.178      ;
+; -6.906  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 7.585      ;
+; -6.658  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.837      ;
++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'RCLK'                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; -19.942 ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.621     ;
+; -19.941 ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.620     ;
+; -19.634 ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.313     ;
+; -19.633 ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.312     ;
+; -18.886 ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.565     ;
+; -18.787 ; FS[17]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.466     ;
+; -18.771 ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.450     ;
+; -18.770 ; FS[7]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.449     ;
+; -18.479 ; FS[16]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.158     ;
+; -18.118 ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.797     ;
+; -17.725 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 11.067     ;
+; -17.709 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 13.152     ;
+; -17.616 ; FS[7]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.295     ;
+; -17.380 ; FS[6]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.059     ;
+; -17.379 ; FS[6]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.058     ;
+; -17.204 ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.883     ;
+; -17.204 ; UFMInitDone                                                                                 ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.883     ;
+; -17.203 ; UFMInitDone                                                                                 ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.882     ;
+; -16.737 ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.416     ;
+; -16.735 ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.414     ;
+; -16.583 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 9.925      ;
+; -16.436 ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.115     ;
+; -16.429 ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.108     ;
+; -16.427 ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.106     ;
+; -16.336 ; FS[17]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.015     ;
+; -16.318 ; FS[6]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.997     ;
+; -16.095 ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.774     ;
+; -16.049 ; UFMInitDone                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.728     ;
+; -16.028 ; FS[16]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.707     ;
+; -15.980 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.423     ;
+; -15.962 ; FS[5]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.641     ;
+; -15.961 ; FS[5]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.640     ;
+; -15.903 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 9.245      ;
+; -15.834 ; FS[7]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.513     ;
+; -15.712 ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.391     ;
+; -15.711 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.154     ;
+; -15.707 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.150     ;
+; -15.566 ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.245     ;
+; -15.564 ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.243     ;
+; -15.554 ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.233     ;
+; -15.538 ; Ready                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.217     ;
+; -15.499 ; Ready                                                                                       ; IS[2]       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.178     ;
+; -15.419 ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.098     ;
+; -15.371 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.814     ;
+; -15.367 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.810     ;
+; -15.320 ; RASr2                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.999     ;
+; -15.308 ; FS[4]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.987     ;
+; -15.304 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 8.646      ;
+; -15.236 ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.915     ;
+; -15.235 ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.914     ;
+; -15.165 ; FS[7]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.844     ;
+; -15.036 ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.715     ;
+; -14.996 ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.675     ;
+; -14.925 ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.604     ;
+; -14.894 ; UFMReqErase                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.573     ;
+; -14.868 ; FS[5]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.547     ;
+; -14.852 ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.531     ;
+; -14.765 ; FS[4]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.444     ;
+; -14.728 ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.407     ;
+; -14.670 ; S[0]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.349     ;
+; -14.620 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.063     ;
+; -14.568 ; S[0]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.247     ;
+; -14.564 ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.243     ;
+; -14.562 ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.241     ;
+; -14.536 ; FS[6]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.215     ;
+; -14.469 ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.148     ;
+; -14.469 ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.148     ;
+; -14.420 ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.099     ;
+; -14.370 ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.049     ;
+; -14.285 ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.964     ;
+; -14.280 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 9.723      ;
+; -14.270 ; InitReady                                                                                   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.949     ;
+; -14.267 ; UFMInitDone                                                                                 ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.946     ;
+; -14.182 ; Ready                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.861     ;
+; -14.180 ; Ready                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.859     ;
+; -14.177 ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.856     ;
+; -14.175 ; FS[6]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.854     ;
+; -14.142 ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.821     ;
+; -14.059 ; S[1]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.738     ;
+; -14.045 ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.724     ;
+; -14.017 ; FS[5]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.696     ;
+; -13.999 ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.678     ;
+; -13.997 ; UFMInitDone                                                                                 ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.676     ;
+; -13.987 ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.666     ;
+; -13.985 ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.664     ;
+; -13.979 ; IS[2]                                                                                       ; Ready       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.658     ;
+; -13.957 ; S[1]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.636     ;
+; -13.920 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 1.000        ; 0.994      ; 15.593     ;
+; -13.911 ; RASr2                                                                                       ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.590     ;
+; -13.902 ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.581     ;
+; -13.816 ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.495     ;
+; -13.814 ; FS[5]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.493     ;
+; -13.804 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 9.247      ;
+; -13.774 ; FS[6]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.453     ;
+; -13.771 ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.450     ;
+; -13.744 ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.423     ;
+; -13.663 ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.342     ;
+; -13.640 ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.319     ;
+; -13.640 ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.319     ;
+; -13.631 ; FS[15]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.310     ;
++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Setup: 'nCRAS'                                                                                         ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -3.072 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.500        ; 9.682      ; 12.933     ;
+; -2.572 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 1.000        ; 9.682      ; 12.933     ;
+; -1.936 ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 6.851      ;
+; -1.471 ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 6.386      ;
+; 0.029  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.886      ;
+; 0.030  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.885      ;
+; 0.031  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.884      ;
+; 0.033  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.882      ;
+; 0.042  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.873      ;
+; 0.042  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.873      ;
+; 1.342  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.573      ;
+; 1.343  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.572      ;
+; 1.344  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.571      ;
+; 1.353  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.562      ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.153 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -0.884     ; 2.963      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -14.623 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.994     ; 4.383      ;
+; -14.532 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.994     ; 4.474      ;
+; 60.000  ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Hold: 'PHI2'                                                                                              ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+; -2.569 ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -0.500       ; 6.837      ; 3.807      ;
+; -0.864 ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.837      ; 6.012      ;
+; -0.191 ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.837      ; 6.685      ;
+; 5.284  ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.323      ;
+; 5.457  ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.496      ;
+; 6.515  ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.554      ;
+; 7.298  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.837      ;
+; 7.546  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.585      ;
+; 8.139  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 8.178      ;
+; 8.901  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 8.940      ;
+; 9.103  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 9.142      ;
+; 9.772  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.311      ;
+; 10.300 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.839      ;
+; 10.300 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.839      ;
+; 10.451 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.990      ;
+; 10.454 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.993      ;
+; 11.968 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 11.507     ;
+; 12.054 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.093     ;
+; 12.106 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 11.645     ;
+; 12.496 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.035     ;
+; 12.496 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.035     ;
+; 12.582 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.621     ;
+; 12.582 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.621     ;
+; 12.591 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.130     ;
+; 12.647 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.186     ;
+; 12.650 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.189     ;
+; 13.011 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.550     ;
+; 13.055 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
+; 13.055 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
+; 13.055 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
+; 13.055 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
+; 13.119 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.658     ;
+; 13.119 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.658     ;
+; 13.270 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.809     ;
+; 13.273 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.812     ;
+; 13.539 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.078     ;
+; 13.539 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.078     ;
+; 13.663 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.202     ;
+; 13.690 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.229     ;
+; 13.693 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.232     ;
+; 13.716 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.255     ;
+; 14.244 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.783     ;
+; 14.244 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.783     ;
+; 14.282 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.821     ;
+; 14.302 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.841     ;
+; 14.395 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.934     ;
+; 14.398 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.937     ;
+; 14.810 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.349     ;
+; 14.810 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.349     ;
+; 14.925 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.464     ;
+; 14.961 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.500     ;
+; 14.964 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.503     ;
+; 15.192 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.731     ;
+; 15.224 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
+; 15.224 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
+; 15.224 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
+; 15.224 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
+; 15.345 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.884     ;
+; 15.417 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.956     ;
+; 15.720 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.259     ;
+; 15.720 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.259     ;
+; 15.859 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.398     ;
+; 15.871 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.410     ;
+; 15.874 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.413     ;
+; 15.945 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.484     ;
+; 15.945 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.484     ;
+; 16.050 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.589     ;
+; 16.096 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.635     ;
+; 16.099 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.638     ;
+; 16.482 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.021     ;
+; 16.616 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.155     ;
+; 16.902 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.441     ;
+; 17.420 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
+; 17.420 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
+; 17.420 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
+; 17.420 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
+; 17.526 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.065     ;
+; 17.607 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.146     ;
+; 17.751 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.290     ;
+; 18.043 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
+; 18.043 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
+; 18.043 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
+; 18.043 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
+; 18.173 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.712     ;
+; 18.463 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
+; 18.463 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
+; 18.463 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
+; 18.463 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
+; 19.083 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.622     ;
+; 19.168 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
+; 19.168 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
+; 19.168 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
+; 19.168 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
+; 19.308 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.847     ;
+; 19.734 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
+; 19.734 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
+; 19.734 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
+; 19.734 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
+; 20.644 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 20.183     ;
+; 20.644 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 20.183     ;
++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS'                                                                                          ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; -0.713 ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.562      ;
+; -0.704 ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.571      ;
+; -0.703 ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.572      ;
+; -0.702 ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.573      ;
+; 0.598  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.873      ;
+; 0.598  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.873      ;
+; 0.607  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.882      ;
+; 0.609  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.884      ;
+; 0.610  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.885      ;
+; 0.611  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.886      ;
+; 2.111  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 6.386      ;
+; 2.576  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 6.851      ;
+; 3.212  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 9.682      ; 12.933     ;
+; 3.712  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -0.500       ; 9.682      ; 12.933     ;
++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK'                                                                                            ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 2.127 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 4.946      ; 7.112      ;
+; 2.325 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 4.946      ; 7.310      ;
+; 2.627 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -0.500       ; 4.946      ; 7.112      ;
+; 2.825 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -0.500       ; 4.946      ; 7.310      ;
+; 3.362 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.401      ;
+; 3.382 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.421      ;
+; 3.813 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.852      ;
+; 3.827 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.866      ;
+; 3.902 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.941      ;
+; 3.997 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 4.946      ; 8.982      ;
+; 4.411 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.450      ;
+; 4.478 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.517      ;
+; 4.497 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -0.500       ; 4.946      ; 8.982      ;
+; 4.580 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.619      ;
+; 4.581 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.620      ;
+; 5.217 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.256      ;
+; 5.228 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
+; 5.228 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
+; 5.229 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
+; 5.229 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
+; 5.229 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
+; 5.241 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.280      ;
+; 5.244 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.283      ;
+; 5.254 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.293      ;
+; 5.269 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.308      ;
+; 5.275 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.314      ;
+; 5.335 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.374      ;
+; 5.337 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.376      ;
+; 5.392 ; PHI2r2      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.431      ;
+; 5.431 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.470      ;
+; 5.440 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
+; 5.440 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
+; 5.441 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
+; 5.441 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
+; 5.444 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.483      ;
+; 5.444 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.483      ;
+; 5.452 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.452 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.454 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.493      ;
+; 5.466 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.505      ;
+; 5.498 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.537      ;
+; 5.502 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.541      ;
+; 5.521 ; UFMD[15]    ; UFMD[15]    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.560      ;
+; 5.523 ; UFMD[15]    ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.562      ;
+; 5.524 ; UFMD[15]    ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.563      ;
+; 5.525 ; UFMD[15]    ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.564      ;
+; 5.551 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.590      ;
+; 5.564 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.603      ;
+; 5.595 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.634      ;
+; 5.690 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.729      ;
+; 5.715 ; nRowColSel  ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.754      ;
+; 5.717 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.756      ;
+; 5.730 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.769      ;
+; 5.730 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.769      ;
+; 5.952 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.991      ;
+; 5.963 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
+; 5.963 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
+; 5.964 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
+; 5.964 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
+; 5.969 ; CASr3       ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.008      ;
+; 5.989 ; FS[1]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.028      ;
+; 6.025 ; Ready       ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.064      ;
+; 6.096 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.135      ;
+; 6.107 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
+; 6.107 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
+; 6.108 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.147      ;
+; 6.113 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.152      ;
+; 6.133 ; FS[1]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.172      ;
+; 6.173 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.212      ;
+; 6.251 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
+; 6.251 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
+; 6.334 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.373      ;
+; 6.395 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.434      ;
+; 6.433 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.472      ;
+; 6.442 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
+; 6.442 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
+; 6.443 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.482      ;
+; 6.454 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
+; 6.454 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
+; 6.456 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.495      ;
+; 6.534 ; PHI2r2      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.573      ;
+; 6.560 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.599      ;
+; 6.586 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.625      ;
+; 6.587 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.626      ;
+; 6.595 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.634      ;
+; 6.598 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
+; 6.598 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
+; 6.730 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.769      ;
+; 6.742 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
+; 6.742 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
+; 6.744 ; FS[11]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
+; 6.744 ; FS[11]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
+; 6.744 ; FS[11]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
+; 6.744 ; FS[11]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
+; 6.769 ; FS[1]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
+; 6.769 ; FS[1]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
+; 6.769 ; FS[1]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
+; 6.769 ; FS[1]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
+; 6.769 ; FS[1]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
+; 6.785 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.824      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'ARCLK'                                                                                                                                                              ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                                  ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
+; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk                                           ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk                                           ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'DRCLK'                                                                                                                                                  ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                      ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ;
+; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
+; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk                               ;
+; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk                               ;
++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'PHI2'                                                                       ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target           ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; PHI2  ; Rise       ; PHI2             ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; ADSubmitted      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; ADSubmitted      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]          ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; C1Submitted      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; C1Submitted      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRCLK         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRCLK         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRDIn         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRDIn         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdEnable        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdEnable        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdSubmitted     ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdSubmitted     ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMErase      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMErase      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMPrgm       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMPrgm       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; RA11             ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11             ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; UFMOscEN         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; UFMOscEN         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; XOR8MEG          ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; XOR8MEG          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; ADSubmitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; ADSubmitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; C1Submitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; C1Submitted|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdEnable|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdEnable|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdSubmitted|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdSubmitted|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; PHI2|combout     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; PHI2|combout     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; RA11|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; UFMOscEN|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; UFMOscEN|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; XOR8MEG|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; XOR8MEG|clk      ;
++--------+--------------+----------------+------------------+-------+------------+------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'RCLK'                                                                  ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; RCLK  ; Rise       ; RCLK        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; ARCLK       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; ARCLK       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; ARShift     ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; ARShift     ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr2       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr2       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr3       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr3       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRCLK       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRCLK       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRDIn       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRDIn       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRShift     ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRShift     ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[0]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[0]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[10]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[10]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[11]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[11]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[12]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[12]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[13]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[13]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[14]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[14]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[15]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[15]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[16]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[16]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[17]      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[17]      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[1]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[1]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[2]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[2]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[3]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[3]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[4]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[4]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[5]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[5]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[6]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[6]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[7]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[7]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[8]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[8]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[9]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[9]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[0]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[0]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[1]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[1]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[2]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[2]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[3]       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[3]       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; InitReady   ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; InitReady   ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; LEDEN       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; LEDEN       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r2      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r2      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r3      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r3      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RA10        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RA10        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr2       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr2       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr3       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr3       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RCKEEN      ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKEEN      ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RCKE~reg0   ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKE~reg0   ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; Ready       ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; Ready       ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; S[0]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; S[0]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; S[1]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; S[1]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMD[15]    ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMD[15]    ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMErase    ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMErase    ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMInitDone ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMInitDone ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMProgram  ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMProgram  ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMReqErase ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMReqErase ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; n8MEGEN     ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'nCCAS'                                                                   ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCCAS ; Rise       ; nCCAS         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[0]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[0]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[1]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[1]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[2]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[2]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[3]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[3]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[4]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[4]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[5]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[5]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[6]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[6]        ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[7]        ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[7]        ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[0]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[0]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[1]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[1]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[2]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[2]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[3]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[3]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[4]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[4]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[5]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[5]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[6]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[6]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[7]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[7]|clk    ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; nCCAS|combout ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; nCCAS|combout ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'nCRAS'                                                                     ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target          ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCRAS ; Rise       ; nCRAS           ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; CBR             ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; CBR             ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; FWEr            ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; FWEr            ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RBA[0]~reg0     ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[0]~reg0     ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RBA[1]~reg0     ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[1]~reg0     ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[0]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[0]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[1]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[1]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[2]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[2]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[3]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[3]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[4]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[4]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[5]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[5]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[6]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[6]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[7]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[7]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[8]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[8]         ;
+; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[9]         ;
+; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[9]         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; CBR|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; CBR|clk         ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; FWEr|clk        ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; FWEr|clk        ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[0]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[0]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[1]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[1]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[2]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[2]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[3]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[3]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[4]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[4]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[5]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[5]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[6]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[6]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[7]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[7]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[8]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[8]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[9]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[9]|clk     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; nCRAS|combout   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; nCRAS|combout   ;
++--------+--------------+----------------+------------------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Setup Times                                                             ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Din[*]    ; PHI2       ; 5.619  ; 5.619  ; Rise       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 1.618  ; 1.618  ; Rise       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 1.922  ; 1.922  ; Rise       ; PHI2            ;
+;  Din[2]   ; PHI2       ; 3.930  ; 3.930  ; Rise       ; PHI2            ;
+;  Din[3]   ; PHI2       ; 1.790  ; 1.790  ; Rise       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 5.619  ; 5.619  ; Rise       ; PHI2            ;
+;  Din[5]   ; PHI2       ; 1.892  ; 1.892  ; Rise       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 0.488  ; 0.488  ; Rise       ; PHI2            ;
+;  Din[7]   ; PHI2       ; -1.895 ; -1.895 ; Rise       ; PHI2            ;
+; Din[*]    ; PHI2       ; 18.851 ; 18.851 ; Fall       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 15.527 ; 15.527 ; Fall       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 18.391 ; 18.391 ; Fall       ; PHI2            ;
+;  Din[2]   ; PHI2       ; 18.150 ; 18.150 ; Fall       ; PHI2            ;
+;  Din[3]   ; PHI2       ; 18.836 ; 18.836 ; Fall       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 18.731 ; 18.731 ; Fall       ; PHI2            ;
+;  Din[5]   ; PHI2       ; 18.851 ; 18.851 ; Fall       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 16.140 ; 16.140 ; Fall       ; PHI2            ;
+;  Din[7]   ; PHI2       ; 17.790 ; 17.790 ; Fall       ; PHI2            ;
+; MAin[*]   ; PHI2       ; 27.296 ; 27.296 ; Fall       ; PHI2            ;
+;  MAin[0]  ; PHI2       ; 18.855 ; 18.855 ; Fall       ; PHI2            ;
+;  MAin[1]  ; PHI2       ; 17.223 ; 17.223 ; Fall       ; PHI2            ;
+;  MAin[2]  ; PHI2       ; 22.057 ; 22.057 ; Fall       ; PHI2            ;
+;  MAin[3]  ; PHI2       ; 26.915 ; 26.915 ; Fall       ; PHI2            ;
+;  MAin[4]  ; PHI2       ; 22.048 ; 22.048 ; Fall       ; PHI2            ;
+;  MAin[5]  ; PHI2       ; 27.296 ; 27.296 ; Fall       ; PHI2            ;
+;  MAin[6]  ; PHI2       ; 23.411 ; 23.411 ; Fall       ; PHI2            ;
+;  MAin[7]  ; PHI2       ; 26.379 ; 26.379 ; Fall       ; PHI2            ;
+; nFWE      ; PHI2       ; 15.594 ; 15.594 ; Fall       ; PHI2            ;
+; PHI2      ; RCLK       ; 2.487  ; 2.487  ; Rise       ; RCLK            ;
+; nCCAS     ; RCLK       ; 2.685  ; 2.685  ; Rise       ; RCLK            ;
+; nCRAS     ; RCLK       ; 4.357  ; 4.357  ; Rise       ; RCLK            ;
+; Din[*]    ; nCCAS      ; 0.702  ; 0.702  ; Fall       ; nCCAS           ;
+;  Din[0]   ; nCCAS      ; -0.028 ; -0.028 ; Fall       ; nCCAS           ;
+;  Din[1]   ; nCCAS      ; -1.852 ; -1.852 ; Fall       ; nCCAS           ;
+;  Din[2]   ; nCCAS      ; -1.623 ; -1.623 ; Fall       ; nCCAS           ;
+;  Din[3]   ; nCCAS      ; -1.611 ; -1.611 ; Fall       ; nCCAS           ;
+;  Din[4]   ; nCCAS      ; -1.202 ; -1.202 ; Fall       ; nCCAS           ;
+;  Din[5]   ; nCCAS      ; -1.860 ; -1.860 ; Fall       ; nCCAS           ;
+;  Din[6]   ; nCCAS      ; 0.702  ; 0.702  ; Fall       ; nCCAS           ;
+;  Din[7]   ; nCCAS      ; -1.657 ; -1.657 ; Fall       ; nCCAS           ;
+; CROW[*]   ; nCRAS      ; 5.538  ; 5.538  ; Fall       ; nCRAS           ;
+;  CROW[0]  ; nCRAS      ; 5.538  ; 5.538  ; Fall       ; nCRAS           ;
+;  CROW[1]  ; nCRAS      ; 3.990  ; 3.990  ; Fall       ; nCRAS           ;
+; MAin[*]   ; nCRAS      ; 5.521  ; 5.521  ; Fall       ; nCRAS           ;
+;  MAin[0]  ; nCRAS      ; 2.776  ; 2.776  ; Fall       ; nCRAS           ;
+;  MAin[1]  ; nCRAS      ; 2.635  ; 2.635  ; Fall       ; nCRAS           ;
+;  MAin[2]  ; nCRAS      ; 2.575  ; 2.575  ; Fall       ; nCRAS           ;
+;  MAin[3]  ; nCRAS      ; 1.972  ; 1.972  ; Fall       ; nCRAS           ;
+;  MAin[4]  ; nCRAS      ; 3.637  ; 3.637  ; Fall       ; nCRAS           ;
+;  MAin[5]  ; nCRAS      ; 4.180  ; 4.180  ; Fall       ; nCRAS           ;
+;  MAin[6]  ; nCRAS      ; 2.129  ; 2.129  ; Fall       ; nCRAS           ;
+;  MAin[7]  ; nCRAS      ; 5.521  ; 5.521  ; Fall       ; nCRAS           ;
+;  MAin[8]  ; nCRAS      ; 3.654  ; 3.654  ; Fall       ; nCRAS           ;
+;  MAin[9]  ; nCRAS      ; 2.363  ; 2.363  ; Fall       ; nCRAS           ;
+; nCCAS     ; nCRAS      ; 3.572  ; 3.572  ; Fall       ; nCRAS           ;
+; nFWE      ; nCRAS      ; 2.828  ; 2.828  ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++---------------------------------------------------------------------------+
+; Hold Times                                                                ;
++-----------+------------+---------+---------+------------+-----------------+
+; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference ;
++-----------+------------+---------+---------+------------+-----------------+
+; Din[*]    ; PHI2       ; 2.255   ; 2.255   ; Rise       ; PHI2            ;
+;  Din[0]   ; PHI2       ; -1.258  ; -1.258  ; Rise       ; PHI2            ;
+;  Din[1]   ; PHI2       ; -1.562  ; -1.562  ; Rise       ; PHI2            ;
+;  Din[2]   ; PHI2       ; -3.570  ; -3.570  ; Rise       ; PHI2            ;
+;  Din[3]   ; PHI2       ; -1.430  ; -1.430  ; Rise       ; PHI2            ;
+;  Din[4]   ; PHI2       ; -5.259  ; -5.259  ; Rise       ; PHI2            ;
+;  Din[5]   ; PHI2       ; -1.532  ; -1.532  ; Rise       ; PHI2            ;
+;  Din[6]   ; PHI2       ; 0.023   ; 0.023   ; Rise       ; PHI2            ;
+;  Din[7]   ; PHI2       ; 2.255   ; 2.255   ; Rise       ; PHI2            ;
+; Din[*]    ; PHI2       ; 1.977   ; 1.977   ; Fall       ; PHI2            ;
+;  Din[0]   ; PHI2       ; 1.489   ; 1.489   ; Fall       ; PHI2            ;
+;  Din[1]   ; PHI2       ; 1.963   ; 1.963   ; Fall       ; PHI2            ;
+;  Din[2]   ; PHI2       ; 0.106   ; 0.106   ; Fall       ; PHI2            ;
+;  Din[3]   ; PHI2       ; -0.228  ; -0.228  ; Fall       ; PHI2            ;
+;  Din[4]   ; PHI2       ; 1.977   ; 1.977   ; Fall       ; PHI2            ;
+;  Din[5]   ; PHI2       ; -5.179  ; -5.179  ; Fall       ; PHI2            ;
+;  Din[6]   ; PHI2       ; -4.432  ; -4.432  ; Fall       ; PHI2            ;
+;  Din[7]   ; PHI2       ; -6.067  ; -6.067  ; Fall       ; PHI2            ;
+; MAin[*]   ; PHI2       ; -1.458  ; -1.458  ; Fall       ; PHI2            ;
+;  MAin[0]  ; PHI2       ; -3.579  ; -3.579  ; Fall       ; PHI2            ;
+;  MAin[1]  ; PHI2       ; -1.458  ; -1.458  ; Fall       ; PHI2            ;
+;  MAin[2]  ; PHI2       ; -10.193 ; -10.193 ; Fall       ; PHI2            ;
+;  MAin[3]  ; PHI2       ; -15.051 ; -15.051 ; Fall       ; PHI2            ;
+;  MAin[4]  ; PHI2       ; -10.184 ; -10.184 ; Fall       ; PHI2            ;
+;  MAin[5]  ; PHI2       ; -15.432 ; -15.432 ; Fall       ; PHI2            ;
+;  MAin[6]  ; PHI2       ; -10.945 ; -10.945 ; Fall       ; PHI2            ;
+;  MAin[7]  ; PHI2       ; -11.673 ; -11.673 ; Fall       ; PHI2            ;
+; nFWE      ; PHI2       ; -6.373  ; -6.373  ; Fall       ; PHI2            ;
+; PHI2      ; RCLK       ; -2.127  ; -2.127  ; Rise       ; RCLK            ;
+; nCCAS     ; RCLK       ; -2.325  ; -2.325  ; Rise       ; RCLK            ;
+; nCRAS     ; RCLK       ; -3.997  ; -3.997  ; Rise       ; RCLK            ;
+; Din[*]    ; nCCAS      ; 2.220   ; 2.220   ; Fall       ; nCCAS           ;
+;  Din[0]   ; nCCAS      ; 0.388   ; 0.388   ; Fall       ; nCCAS           ;
+;  Din[1]   ; nCCAS      ; 2.212   ; 2.212   ; Fall       ; nCCAS           ;
+;  Din[2]   ; nCCAS      ; 1.983   ; 1.983   ; Fall       ; nCCAS           ;
+;  Din[3]   ; nCCAS      ; 1.971   ; 1.971   ; Fall       ; nCCAS           ;
+;  Din[4]   ; nCCAS      ; 1.562   ; 1.562   ; Fall       ; nCCAS           ;
+;  Din[5]   ; nCCAS      ; 2.220   ; 2.220   ; Fall       ; nCCAS           ;
+;  Din[6]   ; nCCAS      ; -0.342  ; -0.342  ; Fall       ; nCCAS           ;
+;  Din[7]   ; nCCAS      ; 2.017   ; 2.017   ; Fall       ; nCCAS           ;
+; CROW[*]   ; nCRAS      ; -3.630  ; -3.630  ; Fall       ; nCRAS           ;
+;  CROW[0]  ; nCRAS      ; -5.178  ; -5.178  ; Fall       ; nCRAS           ;
+;  CROW[1]  ; nCRAS      ; -3.630  ; -3.630  ; Fall       ; nCRAS           ;
+; MAin[*]   ; nCRAS      ; -1.612  ; -1.612  ; Fall       ; nCRAS           ;
+;  MAin[0]  ; nCRAS      ; -2.416  ; -2.416  ; Fall       ; nCRAS           ;
+;  MAin[1]  ; nCRAS      ; -2.275  ; -2.275  ; Fall       ; nCRAS           ;
+;  MAin[2]  ; nCRAS      ; -2.215  ; -2.215  ; Fall       ; nCRAS           ;
+;  MAin[3]  ; nCRAS      ; -1.612  ; -1.612  ; Fall       ; nCRAS           ;
+;  MAin[4]  ; nCRAS      ; -3.277  ; -3.277  ; Fall       ; nCRAS           ;
+;  MAin[5]  ; nCRAS      ; -3.820  ; -3.820  ; Fall       ; nCRAS           ;
+;  MAin[6]  ; nCRAS      ; -1.769  ; -1.769  ; Fall       ; nCRAS           ;
+;  MAin[7]  ; nCRAS      ; -5.161  ; -5.161  ; Fall       ; nCRAS           ;
+;  MAin[8]  ; nCRAS      ; -3.294  ; -3.294  ; Fall       ; nCRAS           ;
+;  MAin[9]  ; nCRAS      ; -2.003  ; -2.003  ; Fall       ; nCRAS           ;
+; nCCAS     ; nCRAS      ; -3.212  ; -3.212  ; Fall       ; nCRAS           ;
+; nFWE      ; nCRAS      ; -2.468  ; -2.468  ; Fall       ; nCRAS           ;
++-----------+------------+---------+---------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Clock to Output Times                                                   ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; RA[*]     ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
+;  RA[11]   ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
+; LED       ; RCLK       ; 15.471 ; 15.471 ; Rise       ; RCLK            ;
+; RA[*]     ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
+;  RA[0]    ; RCLK       ; 25.623 ; 25.623 ; Rise       ; RCLK            ;
+;  RA[1]    ; RCLK       ; 21.305 ; 21.305 ; Rise       ; RCLK            ;
+;  RA[2]    ; RCLK       ; 21.360 ; 21.360 ; Rise       ; RCLK            ;
+;  RA[3]    ; RCLK       ; 18.901 ; 18.901 ; Rise       ; RCLK            ;
+;  RA[4]    ; RCLK       ; 21.634 ; 21.634 ; Rise       ; RCLK            ;
+;  RA[5]    ; RCLK       ; 15.577 ; 15.577 ; Rise       ; RCLK            ;
+;  RA[6]    ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
+;  RA[7]    ; RCLK       ; 20.958 ; 20.958 ; Rise       ; RCLK            ;
+;  RA[8]    ; RCLK       ; 15.905 ; 15.905 ; Rise       ; RCLK            ;
+;  RA[9]    ; RCLK       ; 24.925 ; 24.925 ; Rise       ; RCLK            ;
+;  RA[10]   ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
+; RCKE      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
+; RDQMH     ; RCLK       ; 15.935 ; 15.935 ; Rise       ; RCLK            ;
+; RDQML     ; RCLK       ; 15.786 ; 15.786 ; Rise       ; RCLK            ;
+; nRCAS     ; RCLK       ; 8.987  ; 8.987  ; Rise       ; RCLK            ;
+; nRCS      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
+; nRRAS     ; RCLK       ; 8.992  ; 8.992  ; Rise       ; RCLK            ;
+; nRWE      ; RCLK       ; 12.898 ; 12.898 ; Rise       ; RCLK            ;
+; RD[*]     ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 26.092 ; 26.092 ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 22.744 ; 22.744 ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 28.317 ; 28.317 ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 26.726 ; 26.726 ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 28.330 ; 28.330 ; Fall       ; nCCAS           ;
+; LED       ; nCRAS      ; 19.187 ; 19.187 ; Rise       ; nCRAS           ;
+; LED       ; nCRAS      ; 19.187 ; 19.187 ; Fall       ; nCRAS           ;
+; RA[*]     ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
+;  RA[0]    ; nCRAS      ; 22.368 ; 22.368 ; Fall       ; nCRAS           ;
+;  RA[1]    ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
+;  RA[2]    ; nCRAS      ; 21.361 ; 21.361 ; Fall       ; nCRAS           ;
+;  RA[3]    ; nCRAS      ; 22.589 ; 22.589 ; Fall       ; nCRAS           ;
+;  RA[4]    ; nCRAS      ; 20.580 ; 20.580 ; Fall       ; nCRAS           ;
+;  RA[5]    ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
+;  RA[6]    ; nCRAS      ; 20.958 ; 20.958 ; Fall       ; nCRAS           ;
+;  RA[7]    ; nCRAS      ; 19.907 ; 19.907 ; Fall       ; nCRAS           ;
+;  RA[8]    ; nCRAS      ; 17.186 ; 17.186 ; Fall       ; nCRAS           ;
+;  RA[9]    ; nCRAS      ; 20.624 ; 20.624 ; Fall       ; nCRAS           ;
+; RBA[*]    ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
+;  RBA[0]   ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
+;  RBA[1]   ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                           ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; RA[*]     ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
+;  RA[11]   ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
+; LED       ; RCLK       ; 15.471 ; 15.471 ; Rise       ; RCLK            ;
+; RA[*]     ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
+;  RA[0]    ; RCLK       ; 25.623 ; 25.623 ; Rise       ; RCLK            ;
+;  RA[1]    ; RCLK       ; 21.305 ; 21.305 ; Rise       ; RCLK            ;
+;  RA[2]    ; RCLK       ; 21.360 ; 21.360 ; Rise       ; RCLK            ;
+;  RA[3]    ; RCLK       ; 18.901 ; 18.901 ; Rise       ; RCLK            ;
+;  RA[4]    ; RCLK       ; 21.634 ; 21.634 ; Rise       ; RCLK            ;
+;  RA[5]    ; RCLK       ; 15.577 ; 15.577 ; Rise       ; RCLK            ;
+;  RA[6]    ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
+;  RA[7]    ; RCLK       ; 20.958 ; 20.958 ; Rise       ; RCLK            ;
+;  RA[8]    ; RCLK       ; 15.905 ; 15.905 ; Rise       ; RCLK            ;
+;  RA[9]    ; RCLK       ; 24.925 ; 24.925 ; Rise       ; RCLK            ;
+;  RA[10]   ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
+; RCKE      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
+; RDQMH     ; RCLK       ; 15.935 ; 15.935 ; Rise       ; RCLK            ;
+; RDQML     ; RCLK       ; 15.786 ; 15.786 ; Rise       ; RCLK            ;
+; nRCAS     ; RCLK       ; 8.987  ; 8.987  ; Rise       ; RCLK            ;
+; nRCS      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
+; nRRAS     ; RCLK       ; 8.992  ; 8.992  ; Rise       ; RCLK            ;
+; nRWE      ; RCLK       ; 12.898 ; 12.898 ; Rise       ; RCLK            ;
+; RD[*]     ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 26.092 ; 26.092 ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 22.744 ; 22.744 ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 28.317 ; 28.317 ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 26.726 ; 26.726 ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 28.330 ; 28.330 ; Fall       ; nCCAS           ;
+; LED       ; nCRAS      ; 19.187 ; 19.187 ; Rise       ; nCRAS           ;
+; LED       ; nCRAS      ; 19.187 ; 19.187 ; Fall       ; nCRAS           ;
+; RA[*]     ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
+;  RA[0]    ; nCRAS      ; 22.368 ; 22.368 ; Fall       ; nCRAS           ;
+;  RA[1]    ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
+;  RA[2]    ; nCRAS      ; 21.361 ; 21.361 ; Fall       ; nCRAS           ;
+;  RA[3]    ; nCRAS      ; 22.589 ; 22.589 ; Fall       ; nCRAS           ;
+;  RA[4]    ; nCRAS      ; 20.580 ; 20.580 ; Fall       ; nCRAS           ;
+;  RA[5]    ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
+;  RA[6]    ; nCRAS      ; 20.958 ; 20.958 ; Fall       ; nCRAS           ;
+;  RA[7]    ; nCRAS      ; 19.907 ; 19.907 ; Fall       ; nCRAS           ;
+;  RA[8]    ; nCRAS      ; 17.186 ; 17.186 ; Fall       ; nCRAS           ;
+;  RA[9]    ; nCRAS      ; 20.624 ; 20.624 ; Fall       ; nCRAS           ;
+; RBA[*]    ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
+;  RBA[0]   ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
+;  RBA[1]   ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------+
+; Propagation Delay                                    ;
++------------+-------------+--------+----+----+--------+
+; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
++------------+-------------+--------+----+----+--------+
+; MAin[0]    ; RA[0]       ; 17.864 ;    ;    ; 17.864 ;
+; MAin[1]    ; RA[1]       ; 16.466 ;    ;    ; 16.466 ;
+; MAin[2]    ; RA[2]       ; 16.451 ;    ;    ; 16.451 ;
+; MAin[3]    ; RA[3]       ; 16.947 ;    ;    ; 16.947 ;
+; MAin[4]    ; RA[4]       ; 17.984 ;    ;    ; 17.984 ;
+; MAin[5]    ; RA[5]       ; 14.301 ;    ;    ; 14.301 ;
+; MAin[6]    ; RA[6]       ; 18.987 ;    ;    ; 18.987 ;
+; MAin[7]    ; RA[7]       ; 19.195 ;    ;    ; 19.195 ;
+; MAin[8]    ; RA[8]       ; 14.224 ;    ;    ; 14.224 ;
+; MAin[9]    ; RA[9]       ; 15.902 ;    ;    ; 15.902 ;
+; MAin[9]    ; RDQMH       ; 17.747 ;    ;    ; 17.747 ;
+; MAin[9]    ; RDQML       ; 17.598 ;    ;    ; 17.598 ;
+; RD[0]      ; Dout[0]     ; 10.392 ;    ;    ; 10.392 ;
+; RD[1]      ; Dout[1]     ; 12.469 ;    ;    ; 12.469 ;
+; RD[2]      ; Dout[2]     ; 10.547 ;    ;    ; 10.547 ;
+; RD[3]      ; Dout[3]     ; 12.366 ;    ;    ; 12.366 ;
+; RD[4]      ; Dout[4]     ; 12.337 ;    ;    ; 12.337 ;
+; RD[5]      ; Dout[5]     ; 12.176 ;    ;    ; 12.176 ;
+; RD[6]      ; Dout[6]     ; 10.385 ;    ;    ; 10.385 ;
+; RD[7]      ; Dout[7]     ; 12.251 ;    ;    ; 12.251 ;
+; nFWE       ; RD[0]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[1]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[2]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[3]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[4]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[5]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[6]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[7]       ; 24.642 ;    ;    ; 24.642 ;
++------------+-------------+--------+----+----+--------+
+
+
++------------------------------------------------------+
+; Minimum Propagation Delay                            ;
++------------+-------------+--------+----+----+--------+
+; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
++------------+-------------+--------+----+----+--------+
+; MAin[0]    ; RA[0]       ; 17.864 ;    ;    ; 17.864 ;
+; MAin[1]    ; RA[1]       ; 16.466 ;    ;    ; 16.466 ;
+; MAin[2]    ; RA[2]       ; 16.451 ;    ;    ; 16.451 ;
+; MAin[3]    ; RA[3]       ; 16.947 ;    ;    ; 16.947 ;
+; MAin[4]    ; RA[4]       ; 17.984 ;    ;    ; 17.984 ;
+; MAin[5]    ; RA[5]       ; 14.301 ;    ;    ; 14.301 ;
+; MAin[6]    ; RA[6]       ; 18.987 ;    ;    ; 18.987 ;
+; MAin[7]    ; RA[7]       ; 19.195 ;    ;    ; 19.195 ;
+; MAin[8]    ; RA[8]       ; 14.224 ;    ;    ; 14.224 ;
+; MAin[9]    ; RA[9]       ; 15.902 ;    ;    ; 15.902 ;
+; MAin[9]    ; RDQMH       ; 17.747 ;    ;    ; 17.747 ;
+; MAin[9]    ; RDQML       ; 17.598 ;    ;    ; 17.598 ;
+; RD[0]      ; Dout[0]     ; 10.392 ;    ;    ; 10.392 ;
+; RD[1]      ; Dout[1]     ; 12.469 ;    ;    ; 12.469 ;
+; RD[2]      ; Dout[2]     ; 10.547 ;    ;    ; 10.547 ;
+; RD[3]      ; Dout[3]     ; 12.366 ;    ;    ; 12.366 ;
+; RD[4]      ; Dout[4]     ; 12.337 ;    ;    ; 12.337 ;
+; RD[5]      ; Dout[5]     ; 12.176 ;    ;    ; 12.176 ;
+; RD[6]      ; Dout[6]     ; 10.385 ;    ;    ; 10.385 ;
+; RD[7]      ; Dout[7]     ; 12.251 ;    ;    ; 12.251 ;
+; nFWE       ; RD[0]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[1]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[2]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[3]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[4]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[5]       ; 22.824 ;    ;    ; 22.824 ;
+; nFWE       ; RD[6]       ; 24.642 ;    ;    ; 24.642 ;
+; nFWE       ; RD[7]       ; 24.642 ;    ;    ; 24.642 ;
++------------+-------------+--------+----+----+--------+
+
+
++-----------------------------------------------------------------------+
+; Output Enable Times                                                   ;
++-----------+------------+--------+------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
++-----------+------------+--------+------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Output Enable Times                                           ;
++-----------+------------+--------+------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
++-----------+------------+--------+------+------------+-----------------+
+
+
++-------------------------------------------------------------------------------+
+; Output Disable Times                                                          ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
++-----------+------------+-----------+-----------+------------+-----------------+
+
+
++-------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                  ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
++-----------+------------+-----------+-----------+------------+-----------------+
+; RD[*]     ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
+; RD[*]     ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[0]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[1]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[2]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[3]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[4]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[5]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
+;  RD[6]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
+;  RD[7]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
++-----------+------------+-----------+-----------+------------+-----------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
+; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
+; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
+; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
+; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
+; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
+; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
+; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
+; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
+; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
+; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
+; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 31    ; 31   ;
+; Unconstrained Input Port Paths  ; 232   ; 232  ;
+; Unconstrained Output Ports      ; 38    ; 38   ;
+; Unconstrained Output Port Paths ; 77    ; 77   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Mon Aug 16 18:40:23 2021
+Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (306004): Started post-fitting delay annotation
+Info (306005): Delay annotation completed successfully
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
+    Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
+    Info (332105): create_clock -period 1.000 -name RCLK RCLK
+    Info (332105): create_clock -period 1.000 -name nCRAS nCRAS
+    Info (332105): create_clock -period 1.000 -name PHI2 PHI2
+    Info (332105): create_clock -period 1.000 -name nCCAS nCCAS
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Critical Warning (332148): Timing requirements not met
+Info (332146): Worst-case setup slack is -99.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -99.000       -99.000 ARCLK 
+    Info (332119):   -99.000       -99.000 DRCLK 
+    Info (332119):   -23.638      -216.621 PHI2 
+    Info (332119):   -19.942      -610.547 RCLK 
+    Info (332119):    -3.072        -6.479 nCRAS 
+Info (332146): Worst-case hold slack is -16.153
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -16.153       -16.153 ARCLK 
+    Info (332119):   -14.623       -14.623 DRCLK 
+    Info (332119):    -2.569        -3.433 PHI2 
+    Info (332119):    -0.713        -2.822 nCRAS 
+    Info (332119):     2.127         0.000 RCLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -29.500
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -29.500       -59.000 ARCLK 
+    Info (332119):   -29.500       -59.000 DRCLK 
+    Info (332119):    -2.289        -2.289 PHI2 
+    Info (332119):    -2.289        -2.289 RCLK 
+    Info (332119):    -2.289        -2.289 nCCAS 
+    Info (332119):    -2.289        -2.289 nCRAS 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 368 megabytes
+    Info: Processing ended: Mon Aug 16 18:40:24 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/CPLD/AGM-src/output_files/RAM4GS.sta.summary b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary
old mode 100755
new mode 100644
similarity index 78%
rename from CPLD/AGM-src/output_files/RAM4GS.sta.summary
rename to CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary
index a4c9ebf..44e8308
--- a/CPLD/AGM-src/output_files/RAM4GS.sta.summary
+++ b/CPLD/MAX/MAXV/output_files/RAM2GS.sta.summary
@@ -11,36 +11,36 @@ Slack : -99.000
 TNS   : -99.000
 
 Type  : Setup 'PHI2'
-Slack : -9.292
-TNS   : -92.804
+Slack : -23.638
+TNS   : -216.621
 
 Type  : Setup 'RCLK'
-Slack : -8.365
-TNS   : -253.063
+Slack : -19.942
+TNS   : -610.547
 
 Type  : Setup 'nCRAS'
-Slack : -0.490
-TNS   : -0.577
-
-Type  : Hold 'DRCLK'
-Slack : -16.306
-TNS   : -16.306
+Slack : -3.072
+TNS   : -6.479
 
 Type  : Hold 'ARCLK'
-Slack : -16.272
-TNS   : -16.272
+Slack : -16.153
+TNS   : -16.153
 
-Type  : Hold 'RCLK'
-Slack : -0.874
-TNS   : -0.874
+Type  : Hold 'DRCLK'
+Slack : -14.623
+TNS   : -14.623
 
 Type  : Hold 'PHI2'
-Slack : -0.396
-TNS   : -0.396
+Slack : -2.569
+TNS   : -3.433
 
 Type  : Hold 'nCRAS'
-Slack : -0.125
-TNS   : -0.125
+Slack : -0.713
+TNS   : -2.822
+
+Type  : Hold 'RCLK'
+Slack : 2.127
+TNS   : 0.000
 
 Type  : Minimum Pulse Width 'ARCLK'
 Slack : -29.500
diff --git a/CPLD/AGM-src/RAM4GS.mif b/CPLD/MAX/RAM2GS-MAX.mif
old mode 100755
new mode 100644
similarity index 100%
rename from CPLD/AGM-src/RAM4GS.mif
rename to CPLD/MAX/RAM2GS-MAX.mif
diff --git a/CPLD/RAM4GS-MAX.v b/CPLD/MAX/RAM2GS-MAX.v
old mode 100755
new mode 100644
similarity index 97%
rename from CPLD/RAM4GS-MAX.v
rename to CPLD/MAX/RAM2GS-MAX.v
index 3969024..b18d542
--- a/CPLD/RAM4GS-MAX.v
+++ b/CPLD/MAX/RAM2GS-MAX.v
@@ -8,7 +8,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* Activity LED */
 	reg LEDEN = 0;
-	output LED = ~(~nCRAS &&  LEDEN);
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
 
 	/* Async. DRAM Control Inputs */
 	input nCCAS, nCRAS;
@@ -22,7 +23,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* 65816 Data */
 	input [7:0] Din;
-	output [7:0] Dout = RD[7:0];
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
 
 	/* Latched 65816 Bank Address */
 	reg [7:0] Bank;
@@ -50,13 +52,14 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 	assign RA[11] = RA11;
 	assign RA[10] = RA10;
 	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
 	reg [7:0] WRD;
 	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
 	/* UFM Interface */
-	reg [15] UFMD = 0; // UFM data register bit 15
+	reg [15:15] UFMD = 0; // UFM data register bit 15
 	reg ARCLK = 0; // UFM address register clock
 	// UFM address register data input tied to 0
 	reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
@@ -97,6 +100,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 	reg ADSubmitted = 0;
 	reg CmdEnable = 0;
 	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
 	reg Cmdn8MEGEN = 0;
 	reg CmdDRCLK = 0;
 	reg CmdDRDIn = 0;
@@ -339,9 +343,11 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 			if (Din[7:4]==4'h0) begin
 				XOR8MEG <= Din[0];
 			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
 				Cmdn8MEGEN <= ~Din[0];
 				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
+			end else if (Din[7:4]==4'h2 && Din[3]==1'b0) begin
+				CmdLEDEN <= LEDEN;
 				Cmdn8MEGEN <= n8MEGEN;
 				CmdUFMErase <= Din[3];
 				CmdUFMPrgm <= Din[2];
diff --git a/CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt b/CPLD/MAX/greybox_tmp/cbx_args.txt
old mode 100755
new mode 100644
similarity index 78%
rename from CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt
rename to CPLD/MAX/greybox_tmp/cbx_args.txt
index e714d49..941c71c
--- a/CPLD/AGM-src/output_files/greybox_tmp/cbx_args.txt
+++ b/CPLD/MAX/greybox_tmp/cbx_args.txt
@@ -1,6 +1,6 @@
 ERASE_TIME=500000000
-INTENDED_DEVICE_FAMILY="MAX II"
-LPM_FILE=RAM4GS.mif
+INTENDED_DEVICE_FAMILY="MAX V"
+LPM_FILE=RAM2GS-MAX.mif
 LPM_HINT=UNUSED
 LPM_TYPE=altufm_none
 OSC_FREQUENCY=180000
@@ -8,7 +8,7 @@ PORT_ARCLKENA=PORT_UNUSED
 PORT_DRCLKENA=PORT_UNUSED
 PROGRAM_TIME=1600000
 WIDTH_UFM_ADDRESS=9
-DEVICE_FAMILY="MAX II"
+DEVICE_FAMILY="MAX V"
 CBX_AUTO_BLACKBOX=ALL
 arclk
 ardin
diff --git a/CPLD/MAXII/RAM4GS.mif b/CPLD/MAXII/RAM4GS.mif
deleted file mode 100755
index 65c8441..0000000
--- a/CPLD/MAXII/RAM4GS.mif
+++ /dev/null
@@ -1,27 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=16;
-DEPTH=512;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	[000..0FD]  :   0000;
-	0FE  :   7FFF;
-	[0FF..1FF]  :   FFFF;
-END;
diff --git a/CPLD/MAXII/constraints.sdc b/CPLD/MAXII/constraints.sdc
deleted file mode 100755
index e69de29..0000000
diff --git a/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb
deleted file mode 100755
index a80855d..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(0).cnf.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb
deleted file mode 100755
index 1a1481b..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(0).cnf.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb
deleted file mode 100755
index 84cfd7b..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(1).cnf.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb
deleted file mode 100755
index 10dc2d1..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(1).cnf.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb b/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb
deleted file mode 100755
index bf025da..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(2).cnf.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb b/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb
deleted file mode 100755
index 7121330..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.(2).cnf.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.asm.qmsg b/CPLD/MAXII/db/RAM4GS.asm.qmsg
deleted file mode 100755
index 4989b11..0000000
--- a/CPLD/MAXII/db/RAM4GS.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}
diff --git a/CPLD/MAXII/db/RAM4GS.asm.rdb b/CPLD/MAXII/db/RAM4GS.asm.rdb
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index 57f2d3d..0000000
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diff --git a/CPLD/MAXII/db/RAM4GS.asm_labs.ddb b/CPLD/MAXII/db/RAM4GS.asm_labs.ddb
deleted file mode 100755
index c9b3243..0000000
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diff --git a/CPLD/MAXII/db/RAM4GS.cmp.cdb b/CPLD/MAXII/db/RAM4GS.cmp.cdb
deleted file mode 100755
index 660f5e1..0000000
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diff --git a/CPLD/MAXII/db/RAM4GS.cmp.hdb b/CPLD/MAXII/db/RAM4GS.cmp.hdb
deleted file mode 100755
index 27f7c43..0000000
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diff --git a/CPLD/MAXII/db/RAM4GS.cmp.idb b/CPLD/MAXII/db/RAM4GS.cmp.idb
deleted file mode 100755
index e91cbcb..0000000
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diff --git a/CPLD/MAXII/db/RAM4GS.cmp.kpt b/CPLD/MAXII/db/RAM4GS.cmp.kpt
deleted file mode 100755
index 29f003a..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.cmp.kpt and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.cmp.rdb b/CPLD/MAXII/db/RAM4GS.cmp.rdb
deleted file mode 100755
index 8974ee5..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.cmp.rdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.cmp0.ddb b/CPLD/MAXII/db/RAM4GS.cmp0.ddb
deleted file mode 100755
index db1bbdb..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.cmp0.ddb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.fit.qmsg b/CPLD/MAXII/db/RAM4GS.fit.qmsg
deleted file mode 100755
index f7f2a6b..0000000
--- a/CPLD/MAXII/db/RAM4GS.fit.qmsg
+++ /dev/null
@@ -1,43 +0,0 @@
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
-{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}
diff --git a/CPLD/MAXII/db/RAM4GS.hif b/CPLD/MAXII/db/RAM4GS.hif
deleted file mode 100755
index 662d74f..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.hif and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.ipinfo b/CPLD/MAXII/db/RAM4GS.ipinfo
deleted file mode 100755
index 482f1be..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.ipinfo and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.lpc.rdb b/CPLD/MAXII/db/RAM4GS.lpc.rdb
deleted file mode 100755
index 2c939fb..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.lpc.rdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.map.cdb b/CPLD/MAXII/db/RAM4GS.map.cdb
deleted file mode 100755
index ca0a971..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.map.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.map.hdb b/CPLD/MAXII/db/RAM4GS.map.hdb
deleted file mode 100755
index 8ae41d2..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.map.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.map.qmsg b/CPLD/MAXII/db/RAM4GS.map.qmsg
deleted file mode 100755
index 543433e..0000000
--- a/CPLD/MAXII/db/RAM4GS.map.qmsg
+++ /dev/null
@@ -1,26 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" {  } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""}
diff --git a/CPLD/MAXII/db/RAM4GS.map.rdb b/CPLD/MAXII/db/RAM4GS.map.rdb
deleted file mode 100755
index d27105c..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.map.rdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.pre_map.hdb b/CPLD/MAXII/db/RAM4GS.pre_map.hdb
deleted file mode 100755
index 6f71689..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.pre_map.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.qns b/CPLD/MAXII/db/RAM4GS.qns
deleted file mode 100755
index ef67c3e..0000000
--- a/CPLD/MAXII/db/RAM4GS.qns
+++ /dev/null
@@ -1 +0,0 @@
-RAM4GS/done
diff --git a/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb b/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb
deleted file mode 100755
index a7aa640..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.root_partition.map.reg_db.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.routing.rdb b/CPLD/MAXII/db/RAM4GS.routing.rdb
deleted file mode 100755
index a1beb78..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.routing.rdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.rtlv.hdb b/CPLD/MAXII/db/RAM4GS.rtlv.hdb
deleted file mode 100755
index 802d93c..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.rtlv.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb
deleted file mode 100755
index 30b67ca..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.rtlv_sg.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb
deleted file mode 100755
index e318de4..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.rtlv_sg_swap.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.sgdiff.cdb b/CPLD/MAXII/db/RAM4GS.sgdiff.cdb
deleted file mode 100755
index 2d31b44..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.sgdiff.cdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.sgdiff.hdb b/CPLD/MAXII/db/RAM4GS.sgdiff.hdb
deleted file mode 100755
index 18597e6..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.sgdiff.hdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.sta.qmsg b/CPLD/MAXII/db/RAM4GS.sta.qmsg
deleted file mode 100755
index e020392..0000000
--- a/CPLD/MAXII/db/RAM4GS.sta.qmsg
+++ /dev/null
@@ -1,23 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.292       -92.804 PHI2  " "   -9.292       -92.804 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.365      -253.063 RCLK  " "   -8.365      -253.063 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.490        -0.577 nCRAS  " "   -0.490        -0.577 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.306       -16.306 DRCLK  " "  -16.306       -16.306 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.272       -16.272 ARCLK  " "  -16.272       -16.272 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.874        -0.874 RCLK  " "   -0.874        -0.874 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396        -0.396 PHI2  " "   -0.396        -0.396 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.125        -0.125 nCRAS  " "   -0.125        -0.125 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""}
diff --git a/CPLD/MAXII/db/RAM4GS.sta.rdb b/CPLD/MAXII/db/RAM4GS.sta.rdb
deleted file mode 100755
index 25f87ad..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.sta.rdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb
deleted file mode 100755
index 8b39503..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.sta_cmp.5_slow.tdb and /dev/null differ
diff --git a/CPLD/MAXII/db/RAM4GS.syn_hier_info b/CPLD/MAXII/db/RAM4GS.syn_hier_info
deleted file mode 100755
index e69de29..0000000
diff --git a/CPLD/MAXII/db/RAM4GS.vpr.ammdb b/CPLD/MAXII/db/RAM4GS.vpr.ammdb
deleted file mode 100755
index 2acc82b..0000000
Binary files a/CPLD/MAXII/db/RAM4GS.vpr.ammdb and /dev/null differ
diff --git a/CPLD/MAXII/db/logic_util_heursitic.dat b/CPLD/MAXII/db/logic_util_heursitic.dat
deleted file mode 100755
index c3752a7..0000000
Binary files a/CPLD/MAXII/db/logic_util_heursitic.dat and /dev/null differ
diff --git a/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg b/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg
deleted file mode 100755
index 715eafe..0000000
--- a/CPLD/MAXII/db/prev_cmp_RAM4GS.qmsg
+++ /dev/null
@@ -1,106 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" {  } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""}
-{ "Info" "0" "" "Project  = RAM4GS" {  } {  } 0 0 "Project  = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
-{ "Info" "0" "" "Revision = RAM4GS" {  } {  } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""}
-{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.292       -92.804 PHI2  " "   -9.292       -92.804 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.365      -253.063 RCLK  " "   -8.365      -253.063 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.490        -0.577 nCRAS  " "   -0.490        -0.577 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.306       -16.306 DRCLK  " "  -16.306       -16.306 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.272       -16.272 ARCLK  " "  -16.272       -16.272 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.874        -0.874 RCLK  " "   -0.874        -0.874 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396        -0.396 PHI2  " "   -0.396        -0.396 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.125        -0.125 nCRAS  " "   -0.125        -0.125 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""}
diff --git a/CPLD/MAXII/greybox_tmp/cbx_args.txt b/CPLD/MAXII/greybox_tmp/cbx_args.txt
deleted file mode 100755
index b32fb07..0000000
--- a/CPLD/MAXII/greybox_tmp/cbx_args.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-ERASE_TIME=500000000
-INTENDED_DEVICE_FAMILY="MAX II"
-LPM_FILE=RAM4GS.mif
-LPM_HINT=UNUSED
-LPM_TYPE=altufm_none
-OSC_FREQUENCY=180000
-PORT_ARCLKENA=PORT_UNUSED
-PORT_DRCLKENA=PORT_UNUSED
-PROGRAM_TIME=1600000
-WIDTH_UFM_ADDRESS=9
-DEVICE_FAMILY="MAX II"
-CBX_AUTO_BLACKBOX=ALL
-CBX_AUTO_BLACKBOX=ALL
-arclk
-ardin
-arshft
-busy
-drclk
-drdin
-drdout
-drshft
-erase
-osc
-oscena
-program
-rtpbusy
diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt
deleted file mode 100755
index 4a04335..0000000
Binary files a/CPLD/MAXII/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt and /dev/null differ
diff --git a/CPLD/MAXII/output_files/RAM4GS.cdf b/CPLD/MAXII/output_files/RAM4GS.cdf
deleted file mode 100755
index 43f46dc..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
-JedecChain;
-	FileRevision(JESD32A);
-	DefaultMfr(6E);
-
-	P ActionCode(Cfg)
-		Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
-
-ChainEnd;
-
-AlteraBegin;
-	ChainType(JTAG);
-AlteraEnd;
diff --git a/CPLD/MAXII/output_files/RAM4GS.done b/CPLD/MAXII/output_files/RAM4GS.done
deleted file mode 100755
index d7b20f4..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Jul 23 02:21:03 2020
diff --git a/CPLD/MAXII/output_files/RAM4GS.fit.summary b/CPLD/MAXII/output_files/RAM4GS.fit.summary
deleted file mode 100755
index 530787c..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.fit.summary
+++ /dev/null
@@ -1,11 +0,0 @@
-Fitter Status : Successful - Thu Jul 23 02:20:50 2020
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM4GS
-Top-level Entity Name : RAM4GS
-Family : MAX II
-Device : EPM240T100C5
-Timing Models : Final
-Total logic elements : 170 / 240 ( 71 % )
-Total pins : 62 / 80 ( 78 % )
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM4GS.jdi b/CPLD/MAXII/output_files/RAM4GS.jdi
deleted file mode 100755
index 85a8d49..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-  
-    
-  
-  
-    
-  
-
diff --git a/CPLD/MAXII/output_files/RAM4GS.map.summary b/CPLD/MAXII/output_files/RAM4GS.map.summary
deleted file mode 100755
index 56e671c..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.map.summary
+++ /dev/null
@@ -1,9 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM4GS
-Top-level Entity Name : RAM4GS
-Family : MAX II
-Total logic elements : 178
-Total pins : 62
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM4GS.pof b/CPLD/MAXII/output_files/RAM4GS.pof
deleted file mode 100755
index a168b2e..0000000
Binary files a/CPLD/MAXII/output_files/RAM4GS.pof and /dev/null differ
diff --git a/CPLD/MAXII/output_files/RAM4GS.sta.rpt b/CPLD/MAXII/output_files/RAM4GS.sta.rpt
deleted file mode 100755
index 6462353..0000000
--- a/CPLD/MAXII/output_files/RAM4GS.sta.rpt
+++ /dev/null
@@ -1,1588 +0,0 @@
-TimeQuest Timing Analyzer report for RAM4GS
-Thu Jul 23 02:21:02 2020
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. SDC File List
-  5. Clocks
-  6. Fmax Summary
-  7. Setup Summary
-  8. Hold Summary
-  9. Recovery Summary
- 10. Removal Summary
- 11. Minimum Pulse Width Summary
- 12. Setup: 'ARCLK'
- 13. Setup: 'DRCLK'
- 14. Setup: 'PHI2'
- 15. Setup: 'RCLK'
- 16. Setup: 'nCRAS'
- 17. Hold: 'DRCLK'
- 18. Hold: 'ARCLK'
- 19. Hold: 'RCLK'
- 20. Hold: 'PHI2'
- 21. Hold: 'nCRAS'
- 22. Minimum Pulse Width: 'ARCLK'
- 23. Minimum Pulse Width: 'DRCLK'
- 24. Minimum Pulse Width: 'PHI2'
- 25. Minimum Pulse Width: 'RCLK'
- 26. Minimum Pulse Width: 'nCCAS'
- 27. Minimum Pulse Width: 'nCRAS'
- 28. Setup Times
- 29. Hold Times
- 30. Clock to Output Times
- 31. Minimum Clock to Output Times
- 32. Propagation Delay
- 33. Minimum Propagation Delay
- 34. Output Enable Times
- 35. Minimum Output Enable Times
- 36. Output Disable Times
- 37. Minimum Output Disable Times
- 38. Setup Transfers
- 39. Hold Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths
- 43. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                                      ;
-+--------------------+-------------------------------------------------------------------+
-; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
-; Revision Name      ; RAM4GS                                                            ;
-; Device Family      ; MAX II                                                            ;
-; Device Name        ; EPM240T100C5                                                      ;
-; Timing Models      ; Final                                                             ;
-; Delay Model        ; Slow Model                                                        ;
-; Rise/Fall Delays   ; Unavailable                                                       ;
-+--------------------+-------------------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 2           ;
-; Maximum allowed            ; 2           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 2           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ; < 0.1%      ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------+
-; SDC File List                                       ;
-+-----------------+--------+--------------------------+
-; SDC File Path   ; Status ; Read at                  ;
-+-----------------+--------+--------------------------+
-; constraints.sdc ; OK     ; Thu Jul 23 02:21:01 2020 ;
-+-----------------+--------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                            ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; DRCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-; nCCAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
-; nCRAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
-; PHI2       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
-; RCLK       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-
-
-+--------------------------------------------------+
-; Fmax Summary                                     ;
-+------------+-----------------+------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 10.0 MHz   ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz   ; 10.0 MHz        ; DRCLK      ;      ;
-; 51.06 MHz  ; 51.06 MHz       ; PHI2       ;      ;
-; 128.87 MHz ; 128.87 MHz      ; RCLK       ;      ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -99.000 ; -99.000       ;
-; DRCLK ; -99.000 ; -99.000       ;
-; PHI2  ; -9.292  ; -92.804       ;
-; RCLK  ; -8.365  ; -253.063      ;
-; nCRAS ; -0.490  ; -0.577        ;
-+-------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; DRCLK ; -16.306 ; -16.306       ;
-; ARCLK ; -16.272 ; -16.272       ;
-; RCLK  ; -0.874  ; -0.874        ;
-; PHI2  ; -0.396  ; -0.396        ;
-; nCRAS ; -0.125  ; -0.125        ;
-+-------+---------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+---------------------------------+
-; Minimum Pulse Width Summary     ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -29.500 ; -59.000       ;
-; DRCLK ; -29.500 ; -59.000       ;
-; PHI2  ; -2.289  ; -2.289        ;
-; RCLK  ; -2.289  ; -2.289        ;
-; nCCAS ; -2.289  ; -2.289        ;
-; nCRAS ; -2.289  ; -2.289        ;
-+-------+---------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -22.728 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 1.000        ; -1.715     ; 2.013      ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -22.714 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -2.165     ; 1.549      ;
-; -22.694 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -2.165     ; 1.529      ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2'                                                                                             ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -9.292 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.459      ;
-; -9.121 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.288      ;
-; -8.996 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.163      ;
-; -8.949 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.116      ;
-; -8.949 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.116      ;
-; -8.949 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.116      ;
-; -8.949 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.116      ;
-; -8.857 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.024      ;
-; -8.778 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.945      ;
-; -8.778 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.945      ;
-; -8.778 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.945      ;
-; -8.778 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.945      ;
-; -8.653 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.820      ;
-; -8.653 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.820      ;
-; -8.653 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.820      ;
-; -8.653 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.820      ;
-; -8.594 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.761      ;
-; -8.514 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.681      ;
-; -8.514 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.681      ;
-; -8.514 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.681      ;
-; -8.514 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.681      ;
-; -8.300 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.467      ;
-; -8.289 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.456      ;
-; -8.251 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
-; -8.251 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
-; -8.251 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
-; -8.251 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
-; -8.118 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.285      ;
-; -8.084 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.251      ;
-; -8.043 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.210      ;
-; -7.993 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.160      ;
-; -7.957 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.124      ;
-; -7.957 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.124      ;
-; -7.957 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.124      ;
-; -7.957 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.124      ;
-; -7.872 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.039      ;
-; -7.854 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.021      ;
-; -7.799 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.966      ;
-; -7.747 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.914      ;
-; -7.741 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.908      ;
-; -7.741 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.908      ;
-; -7.741 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.908      ;
-; -7.741 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.908      ;
-; -7.608 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.775      ;
-; -7.591 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.758      ;
-; -7.456 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.623      ;
-; -7.456 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.623      ;
-; -7.456 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.623      ;
-; -7.456 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.623      ;
-; -7.345 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.512      ;
-; -7.297 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.464      ;
-; -7.205 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.372      ;
-; -7.081 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.248      ;
-; -7.051 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.218      ;
-; -7.034 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.201      ;
-; -6.909 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.076      ;
-; -6.870 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.037      ;
-; -6.870 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.037      ;
-; -6.835 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.002      ;
-; -6.796 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.963      ;
-; -6.770 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.937      ;
-; -6.745 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.912      ;
-; -6.699 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.866      ;
-; -6.699 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.866      ;
-; -6.574 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.741      ;
-; -6.574 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.741      ;
-; -6.574 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.741      ;
-; -6.550 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.717      ;
-; -6.507 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.674      ;
-; -6.449 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.616      ;
-; -6.435 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.602      ;
-; -6.435 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.602      ;
-; -6.310 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.477      ;
-; -6.213 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.380      ;
-; -6.172 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.339      ;
-; -6.172 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.339      ;
-; -6.047 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.214      ;
-; -5.997 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.164      ;
-; -5.878 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.045      ;
-; -5.878 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.045      ;
-; -5.753 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.920      ;
-; -5.712 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.879      ;
-; -5.662 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.829      ;
-; -5.662 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.829      ;
-; -5.537 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.704      ;
-; -5.377 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.544      ;
-; -5.377 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.544      ;
-; -5.252 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.419      ;
-; -5.004 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 5.671      ;
-; -4.046 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.713      ;
-; -4.046 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.713      ;
-; -4.046 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.713      ;
-; -4.046 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.713      ;
-; -4.040 ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.707      ;
-; -4.001 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.668      ;
-; -3.752 ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.419      ;
-; -3.694 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 3.861      ;
-; -3.585 ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.252      ;
-; -2.929 ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.596      ;
-; -2.917 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.584      ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK'                                                                                                                                                                            ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -8.365 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 5.334      ;
-; -8.365 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 5.334      ;
-; -7.591 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 5.180      ;
-; -7.130 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.719      ;
-; -7.061 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.650      ;
-; -7.017 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 3.986      ;
-; -6.760 ; FS[5]                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.427      ;
-; -6.760 ; FS[5]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.427      ;
-; -6.691 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.280      ;
-; -6.669 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.258      ;
-; -6.664 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 3.633      ;
-; -6.612 ; FS[16]                                                                                      ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.279      ;
-; -6.612 ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.279      ;
-; -6.588 ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.255      ;
-; -6.574 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.163      ;
-; -6.549 ; FS[7]                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.216      ;
-; -6.549 ; FS[7]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.216      ;
-; -6.526 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 4.115      ;
-; -6.502 ; FS[17]                                                                                      ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.169      ;
-; -6.502 ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.169      ;
-; -6.501 ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.168      ;
-; -6.482 ; S[1]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.149      ;
-; -6.401 ; FS[5]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.068      ;
-; -6.399 ; FS[4]                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.066      ;
-; -6.399 ; FS[4]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.066      ;
-; -6.395 ; InitReady                                                                                   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.062      ;
-; -6.380 ; FS[5]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.047      ;
-; -6.328 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 3.297      ;
-; -6.258 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 3.847      ;
-; -6.256 ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.923      ;
-; -6.253 ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.920      ;
-; -6.232 ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.899      ;
-; -6.198 ; FS[6]                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.865      ;
-; -6.198 ; FS[6]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.865      ;
-; -6.193 ; FS[7]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.860      ;
-; -6.190 ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.857      ;
-; -6.169 ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.836      ;
-; -6.146 ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.813      ;
-; -6.143 ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.810      ;
-; -6.122 ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.789      ;
-; -6.070 ; UFMInitDone                                                                                 ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.737      ;
-; -6.070 ; UFMInitDone                                                                                 ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.737      ;
-; -6.044 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 3.633      ;
-; -6.040 ; FS[4]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.707      ;
-; -6.032 ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.699      ;
-; -6.028 ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.695      ;
-; -6.022 ; FS[16]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.689      ;
-; -6.019 ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.686      ;
-; -5.996 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.578     ; 3.585      ;
-; -5.959 ; FS[7]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.626      ;
-; -5.958 ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.625      ;
-; -5.954 ; FS[5]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.621      ;
-; -5.949 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.198     ; 2.918      ;
-; -5.942 ; UFMReqErase                                                                                 ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.609      ;
-; -5.915 ; FS[16]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.582      ;
-; -5.912 ; FS[17]                                                                                      ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.579      ;
-; -5.852 ; S[0]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.519      ;
-; -5.852 ; FS[7]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.519      ;
-; -5.839 ; FS[6]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.506      ;
-; -5.835 ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.502      ;
-; -5.818 ; FS[6]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.485      ;
-; -5.805 ; FS[17]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.472      ;
-; -5.739 ; FS[5]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.406      ;
-; -5.733 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 1.000        ; 2.165      ; 8.565      ;
-; -5.720 ; FS[5]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.387      ;
-; -5.714 ; UFMInitDone                                                                                 ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.381      ;
-; -5.711 ; FS[5]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.378      ;
-; -5.711 ; UFMInitDone                                                                                 ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.378      ;
-; -5.690 ; UFMInitDone                                                                                 ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.357      ;
-; -5.688 ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.355      ;
-; -5.666 ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.333      ;
-; -5.656 ; FS[12]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.323      ;
-; -5.596 ; FS[6]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.263      ;
-; -5.579 ; FS[4]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.246      ;
-; -5.563 ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.230      ;
-; -5.549 ; RASr2                                                                                       ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.216      ;
-; -5.503 ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.170      ;
-; -5.500 ; FS[7]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.167      ;
-; -5.487 ; RCKE~reg0                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.154      ;
-; -5.480 ; UFMInitDone                                                                                 ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.147      ;
-; -5.479 ; FS[6]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.146      ;
-; -5.459 ; FS[10]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.126      ;
-; -5.453 ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.120      ;
-; -5.425 ; UFMReqErase                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.092      ;
-; -5.420 ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.087      ;
-; -5.397 ; IS[2]                                                                                       ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.064      ;
-; -5.373 ; UFMInitDone                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.040      ;
-; -5.363 ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.030      ;
-; -5.350 ; FS[4]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.017      ;
-; -5.345 ; FS[14]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.012      ;
-; -5.345 ; FS[4]                                                                                       ; UFMD        ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.012      ;
-; -5.333 ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.000      ;
-; -5.312 ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.979      ;
-; -5.312 ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.979      ;
-; -5.290 ; FS[13]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.957      ;
-; -5.267 ; FS[3]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.934      ;
-; -5.230 ; PHI2r2                                                                                      ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.897      ;
-; -5.230 ; PHI2r2                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.897      ;
-; -5.208 ; IS[0]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.875      ;
-; -5.206 ; IS[3]                                                                                       ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.873      ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Setup: 'nCRAS'                                                                                         ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.490 ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 3.235      ;
-; -0.087 ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.832      ;
-; 0.071  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.500        ; 5.926      ; 6.022      ;
-; 0.079  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.666      ;
-; 0.080  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.665      ;
-; 0.081  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.664      ;
-; 0.082  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.663      ;
-; 0.084  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.661      ;
-; 0.091  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.654      ;
-; 0.095  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.650      ;
-; 0.099  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.646      ;
-; 0.104  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.641      ;
-; 0.105  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 0.500        ; 2.578      ; 2.640      ;
-; 0.571  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 1.000        ; 5.926      ; 6.022      ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.306 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.165     ; 1.529      ;
-; -16.286 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -2.165     ; 1.549      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.272 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -1.715     ; 2.013      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK'                                                                                             ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.874 ; ARCLK       ; ARCLK       ; ARCLK        ; RCLK        ; 0.000        ; 3.348      ; 3.071      ;
-; -0.374 ; ARCLK       ; ARCLK       ; ARCLK        ; RCLK        ; -0.500       ; 3.348      ; 3.071      ;
-; 1.192  ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 3.348      ; 4.761      ;
-; 1.264  ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 3.348      ; 4.833      ;
-; 1.344  ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 3.348      ; 4.913      ;
-; 1.400  ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.621      ;
-; 1.642  ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.863      ;
-; 1.670  ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.891      ;
-; 1.692  ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -0.500       ; 3.348      ; 4.761      ;
-; 1.695  ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.916      ;
-; 1.703  ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.924      ;
-; 1.706  ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.927      ;
-; 1.764  ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -0.500       ; 3.348      ; 4.833      ;
-; 1.844  ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -0.500       ; 3.348      ; 4.913      ;
-; 1.899  ; DRShift     ; DRShift     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.120      ;
-; 1.948  ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.169      ;
-; 1.959  ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.180      ;
-; 1.976  ; RASr2       ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.197      ;
-; 1.983  ; RASr2       ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.204      ;
-; 2.108  ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.329      ;
-; 2.117  ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117  ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.125  ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.346      ;
-; 2.126  ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.135  ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.356      ;
-; 2.135  ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.356      ;
-; 2.137  ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.358      ;
-; 2.141  ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.362      ;
-; 2.153  ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.374      ;
-; 2.212  ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.433      ;
-; 2.221  ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.442      ;
-; 2.221  ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.442      ;
-; 2.230  ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.230  ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.230  ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.231  ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231  ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231  ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231  ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.233  ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.454      ;
-; 2.292  ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.513      ;
-; 2.332  ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.553      ;
-; 2.363  ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.584      ;
-; 2.380  ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.601      ;
-; 2.407  ; CASr2       ; CASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.628      ;
-; 2.522  ; ARShift     ; ARShift     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.743      ;
-; 2.530  ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.751      ;
-; 2.542  ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.763      ;
-; 2.577  ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.798      ;
-; 2.582  ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.803      ;
-; 2.593  ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.814      ;
-; 2.615  ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.836      ;
-; 2.622  ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.843      ;
-; 2.837  ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.058      ;
-; 2.885  ; CASr3       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.106      ;
-; 2.912  ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.133      ;
-; 2.913  ; PHI2r3      ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.134      ;
-; 2.936  ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.157      ;
-; 2.940  ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
-; 2.949  ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.949  ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.957  ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.178      ;
-; 2.967  ; FS[1]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.188      ;
-; 2.969  ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.190      ;
-; 3.028  ; S[1]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.249      ;
-; 3.051  ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.272      ;
-; 3.060  ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.281      ;
-; 3.060  ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.281      ;
-; 3.066  ; IS[0]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.287      ;
-; 3.068  ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.289      ;
-; 3.078  ; FS[1]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.299      ;
-; 3.109  ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.330      ;
-; 3.130  ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.351      ;
-; 3.159  ; S[0]        ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.380      ;
-; 3.161  ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.382      ;
-; 3.161  ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.382      ;
-; 3.162  ; IS[2]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.383      ;
-; 3.170  ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.170  ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.170  ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.171  ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.392      ;
-; 3.171  ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.392      ;
-; 3.171  ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.392      ;
-; 3.179  ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.184  ; CASr        ; CASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.405      ;
-; 3.241  ; RASr        ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.462      ;
-; 3.277  ; UFMD        ; UFMD        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.498      ;
-; 3.281  ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
-; 3.281  ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
-; 3.282  ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.503      ;
-; 3.282  ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.503      ;
-; 3.289  ; IS[1]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.510      ;
-; 3.289  ; FS[16]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.510      ;
-; 3.290  ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
-; 3.296  ; UFMD        ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.517      ;
-; 3.306  ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.527      ;
-; 3.324  ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.545      ;
-; 3.328  ; IS[1]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.549      ;
-; 3.381  ; S[0]        ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.602      ;
-; 3.383  ; FS[17]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.604      ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Hold: 'PHI2'                                                                                              ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -0.396 ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.198      ; 3.023      ;
-; 0.072  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -0.500       ; 3.198      ; 2.991      ;
-; 0.129  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.198      ; 3.548      ;
-; 1.927  ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.148      ;
-; 2.681  ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.902      ;
-; 3.162  ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.383      ;
-; 3.363  ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.584      ;
-; 3.375  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.596      ;
-; 3.825  ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.546      ;
-; 4.031  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.252      ;
-; 4.110  ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.831      ;
-; 4.140  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.861      ;
-; 4.198  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.419      ;
-; 4.265  ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.986      ;
-; 4.326  ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.047      ;
-; 4.447  ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.668      ;
-; 4.486  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.707      ;
-; 4.492  ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.713      ;
-; 4.492  ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.713      ;
-; 4.492  ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.713      ;
-; 4.492  ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.713      ;
-; 4.550  ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.271      ;
-; 4.620  ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.341      ;
-; 4.766  ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.487      ;
-; 4.883  ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.604      ;
-; 5.022  ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.743      ;
-; 5.060  ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.781      ;
-; 5.064  ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.785      ;
-; 5.147  ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.868      ;
-; 5.318  ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.039      ;
-; 5.323  ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.044      ;
-; 5.349  ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.070      ;
-; 5.450  ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.671      ;
-; 5.462  ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.183      ;
-; 5.519  ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.240      ;
-; 5.565  ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.286      ;
-; 5.587  ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.308      ;
-; 5.758  ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.479      ;
-; 5.804  ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.525      ;
-; 5.859  ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.580      ;
-; 6.020  ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.741      ;
-; 6.122  ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.843      ;
-; 6.158  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.879      ;
-; 6.261  ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.982      ;
-; 6.314  ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.035      ;
-; 6.386  ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.107      ;
-; 6.443  ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.164      ;
-; 6.557  ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.278      ;
-; 6.577  ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.298      ;
-; 6.659  ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.380      ;
-; 6.716  ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.437      ;
-; 6.841  ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.562      ;
-; 6.953  ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.674      ;
-; 7.012  ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.733      ;
-; 7.216  ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.937      ;
-; 7.242  ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.963      ;
-; 7.355  ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.076      ;
-; 7.480  ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.201      ;
-; 7.527  ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.248      ;
-; 7.651  ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.372      ;
-; 7.743  ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.464      ;
-; 7.902  ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.623      ;
-; 7.902  ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.623      ;
-; 7.902  ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.623      ;
-; 7.902  ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.623      ;
-; 8.037  ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.758      ;
-; 8.187  ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.908      ;
-; 8.187  ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.908      ;
-; 8.187  ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.908      ;
-; 8.187  ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.908      ;
-; 8.245  ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.966      ;
-; 8.300  ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.021      ;
-; 8.403  ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.124      ;
-; 8.403  ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.124      ;
-; 8.403  ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.124      ;
-; 8.403  ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.124      ;
-; 8.439  ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.160      ;
-; 8.530  ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.251      ;
-; 8.564  ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.285      ;
-; 8.697  ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.418      ;
-; 8.697  ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.418      ;
-; 8.697  ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.418      ;
-; 8.697  ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.418      ;
-; 8.735  ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.456      ;
-; 8.746  ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.467      ;
-; 8.960  ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.681      ;
-; 8.960  ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.681      ;
-; 8.960  ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.681      ;
-; 8.960  ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.681      ;
-; 9.040  ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.761      ;
-; 9.099  ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.820      ;
-; 9.099  ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.820      ;
-; 9.099  ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.820      ;
-; 9.099  ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.820      ;
-; 9.224  ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.945      ;
-; 9.224  ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.945      ;
-; 9.224  ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.945      ;
-; 9.224  ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.945      ;
-; 9.303  ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.024      ;
-; 9.395  ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.116      ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS'                                                                                          ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.125 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 5.926      ; 6.022      ;
-; 0.341  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.640      ;
-; 0.342  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.641      ;
-; 0.347  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.646      ;
-; 0.351  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.650      ;
-; 0.355  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.654      ;
-; 0.362  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.661      ;
-; 0.364  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.663      ;
-; 0.365  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.664      ;
-; 0.366  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.665      ;
-; 0.367  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.666      ;
-; 0.375  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -0.500       ; 5.926      ; 6.022      ;
-; 0.533  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 2.832      ;
-; 0.936  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.578      ; 3.235      ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'ARCLK'                                                                                                                                                              ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk                                           ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|arclk                                           ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'DRCLK'                                                                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                      ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk                               ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_1br_component|maxii_ufm_block1|drclk                               ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'PHI2'                                                                       ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target           ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; PHI2  ; Rise       ; PHI2             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; RA11             ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'RCLK'                                                                  ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; RCLK  ; Rise       ; RCLK        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARShift     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARShift     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRDIn       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRDIn       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRShift     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRShift     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[10]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[10]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[11]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[11]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[12]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[12]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[13]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[13]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[14]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[14]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[15]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[15]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[16]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[16]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[17]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[17]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[4]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[4]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[5]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[5]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[6]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[6]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[7]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[7]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[8]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[8]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[9]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[9]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; InitReady   ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; InitReady   ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RA10        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RA10        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; Ready       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; Ready       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMD        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMD        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMErase    ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMErase    ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; n8MEGEN     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; n8MEGEN     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; nRCAS~reg0  ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCCAS'                                                                   ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCCAS ; Rise       ; nCCAS         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; nCCAS|combout ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; nCCAS|combout ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCRAS'                                                                     ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target          ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCRAS ; Rise       ; nCRAS           ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; CBR             ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; CBR             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; FWEr            ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; FWEr            ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; nCRAS|combout   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; nCRAS|combout   ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Times                                                             ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Din[*]    ; PHI2       ; 0.839  ; 0.839  ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 0.100  ; 0.100  ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 0.099  ; 0.099  ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 0.187  ; 0.187  ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 0.377  ; 0.377  ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 0.181  ; 0.181  ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 0.431  ; 0.431  ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 0.839  ; 0.839  ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -0.141 ; -0.141 ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 7.176  ; 7.176  ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 6.507  ; 6.507  ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 5.653  ; 5.653  ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 6.225  ; 6.225  ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 6.476  ; 6.476  ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 5.332  ; 5.332  ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 7.176  ; 7.176  ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 5.239  ; 5.239  ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 5.246  ; 5.246  ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; 7.271  ; 7.271  ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; 4.152  ; 4.152  ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; 4.051  ; 4.051  ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; 6.688  ; 6.688  ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; 7.271  ; 7.271  ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; 7.040  ; 7.040  ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; 5.984  ; 5.984  ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; 4.702  ; 4.702  ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; 4.845  ; 4.845  ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; 5.436  ; 5.436  ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; 1.898  ; 1.898  ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; 1.746  ; 1.746  ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; 1.818  ; 1.818  ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; 0.343  ; 0.343  ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; -0.572 ; -0.572 ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; -0.490 ; -0.490 ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; -0.295 ; -0.295 ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; -0.561 ; -0.561 ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; 0.097  ; 0.097  ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; 0.343  ; 0.343  ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; -0.478 ; -0.478 ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; -0.222 ; -0.222 ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; 1.871  ; 1.871  ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; 1.871  ; 1.871  ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; 1.618  ; 1.618  ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; 0.521  ; 0.521  ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; -0.639 ; -0.639 ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; 0.450  ; 0.450  ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; -0.345 ; -0.345 ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; 0.521  ; 0.521  ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; -0.391 ; -0.391 ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; -0.178 ; -0.178 ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; -0.439 ; -0.439 ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; -1.067 ; -1.067 ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; -0.425 ; -0.425 ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; -0.474 ; -0.474 ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; 0.429  ; 0.429  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; 2.878  ; 2.878  ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Hold Times                                                              ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Din[*]    ; PHI2       ; 0.943  ; 0.943  ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 0.454  ; 0.454  ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 0.455  ; 0.455  ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 0.367  ; 0.367  ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 0.177  ; 0.177  ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 0.373  ; 0.373  ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 0.123  ; 0.123  ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 0.943  ; 0.943  ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 0.695  ; 0.695  ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 0.303  ; 0.303  ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; -0.378 ; -0.378 ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 0.138  ; 0.138  ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; -0.365 ; -0.365 ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; -0.419 ; -0.419 ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 0.303  ; 0.303  ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; -1.686 ; -1.686 ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; -1.080 ; -1.080 ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -1.052 ; -1.052 ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; 0.837  ; 0.837  ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; 0.837  ; 0.837  ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; -0.027 ; -0.027 ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; -2.640 ; -2.640 ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; -3.223 ; -3.223 ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; -2.992 ; -2.992 ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; -1.936 ; -1.936 ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; -0.564 ; -0.564 ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; -0.704 ; -0.704 ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; -0.462 ; -0.462 ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; -1.344 ; -1.344 ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; -1.192 ; -1.192 ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; -1.264 ; -1.264 ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; 1.126  ; 1.126  ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; 1.126  ; 1.126  ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; 1.044  ; 1.044  ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; 0.849  ; 0.849  ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; 1.115  ; 1.115  ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; 0.457  ; 0.457  ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; 0.211  ; 0.211  ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; 1.032  ; 1.032  ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; 0.776  ; 0.776  ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; -1.064 ; -1.064 ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; -1.317 ; -1.317 ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; -1.064 ; -1.064 ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; 1.621  ; 1.621  ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; 1.193  ; 1.193  ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; 0.104  ; 0.104  ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; 0.899  ; 0.899  ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; 0.033  ; 0.033  ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; 0.945  ; 0.945  ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; 0.732  ; 0.732  ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; 0.993  ; 0.993  ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; 1.621  ; 1.621  ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; 0.979  ; 0.979  ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; 1.028  ; 1.028  ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; 0.125  ; 0.125  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; -2.324 ; -2.324 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Clock to Output Times                                                   ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 11.943 ; 11.943 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 11.943 ; 11.943 ; Rise       ; PHI2            ;
-; RA[*]     ; RCLK       ; 12.421 ; 12.421 ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 12.101 ; 12.101 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 11.881 ; 11.881 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 12.068 ; 12.068 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 12.421 ; 12.421 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 12.287 ; 12.287 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 12.220 ; 12.220 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 12.186 ; 12.186 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 11.890 ; 11.890 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 12.150 ; 12.150 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 12.269 ; 12.269 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 8.927  ; 8.927  ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 8.786  ; 8.786  ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 12.174 ; 12.174 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 12.206 ; 12.206 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 8.622  ; 8.622  ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 19.685 ; 19.685 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 19.685 ; 19.685 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 18.806 ; 18.806 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 17.621 ; 17.621 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 19.528 ; 19.528 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 18.795 ; 18.795 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 18.802 ; 18.802 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 18.954 ; 18.954 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 18.801 ; 18.801 ; Fall       ; nCCAS           ;
-; RA[*]     ; nCRAS      ; 14.657 ; 14.657 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 13.694 ; 13.694 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 13.338 ; 13.338 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 13.700 ; 13.700 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 13.894 ; 13.894 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 13.348 ; 13.348 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 13.282 ; 13.282 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 13.721 ; 13.721 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 13.003 ; 13.003 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 14.657 ; 14.657 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 13.207 ; 13.207 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 10.738 ; 10.738 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 10.096 ; 10.096 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 10.738 ; 10.738 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Minimum Clock to Output Times                                           ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 11.943 ; 11.943 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 11.943 ; 11.943 ; Rise       ; PHI2            ;
-; RA[*]     ; RCLK       ; 8.927  ; 8.927  ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 12.101 ; 12.101 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 11.881 ; 11.881 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 12.068 ; 12.068 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 12.421 ; 12.421 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 12.287 ; 12.287 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 12.220 ; 12.220 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 12.186 ; 12.186 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 11.890 ; 11.890 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 12.150 ; 12.150 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 12.269 ; 12.269 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 8.927  ; 8.927  ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 8.786  ; 8.786  ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 12.174 ; 12.174 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 12.206 ; 12.206 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 8.622  ; 8.622  ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 17.621 ; 17.621 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 19.685 ; 19.685 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 18.806 ; 18.806 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 17.621 ; 17.621 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 19.528 ; 19.528 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 18.795 ; 18.795 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 18.802 ; 18.802 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 18.954 ; 18.954 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 18.801 ; 18.801 ; Fall       ; nCCAS           ;
-; RA[*]     ; nCRAS      ; 13.003 ; 13.003 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 13.694 ; 13.694 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 13.338 ; 13.338 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 13.700 ; 13.700 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 13.894 ; 13.894 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 13.348 ; 13.348 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 13.282 ; 13.282 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 13.721 ; 13.721 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 13.003 ; 13.003 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 14.657 ; 14.657 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 13.207 ; 13.207 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 10.096 ; 10.096 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 10.096 ; 10.096 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 10.738 ; 10.738 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+------------------------------------------------------+
-; Propagation Delay                                    ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 10.124 ;    ;    ; 10.124 ;
-; MAin[1]    ; RA[1]       ; 9.891  ;    ;    ; 9.891  ;
-; MAin[2]    ; RA[2]       ; 8.276  ;    ;    ; 8.276  ;
-; MAin[3]    ; RA[3]       ; 10.704 ;    ;    ; 10.704 ;
-; MAin[4]    ; RA[4]       ; 8.824  ;    ;    ; 8.824  ;
-; MAin[5]    ; RA[5]       ; 8.367  ;    ;    ; 8.367  ;
-; MAin[6]    ; RA[6]       ; 10.195 ;    ;    ; 10.195 ;
-; MAin[7]    ; RA[7]       ; 9.820  ;    ;    ; 9.820  ;
-; MAin[8]    ; RA[8]       ; 9.678  ;    ;    ; 9.678  ;
-; MAin[9]    ; RA[9]       ; 8.912  ;    ;    ; 8.912  ;
-; MAin[9]    ; RDQMH       ; 8.830  ;    ;    ; 8.830  ;
-; MAin[9]    ; RDQML       ; 8.862  ;    ;    ; 8.862  ;
-; RD[0]      ; Dout[0]     ; 6.188  ;    ;    ; 6.188  ;
-; RD[1]      ; Dout[1]     ; 6.690  ;    ;    ; 6.690  ;
-; RD[2]      ; Dout[2]     ; 6.254  ;    ;    ; 6.254  ;
-; RD[3]      ; Dout[3]     ; 6.845  ;    ;    ; 6.845  ;
-; RD[4]      ; Dout[4]     ; 6.775  ;    ;    ; 6.775  ;
-; RD[5]      ; Dout[5]     ; 6.952  ;    ;    ; 6.952  ;
-; RD[6]      ; Dout[6]     ; 6.194  ;    ;    ; 6.194  ;
-; RD[7]      ; Dout[7]     ; 6.725  ;    ;    ; 6.725  ;
-; nFWE       ; RD[0]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[1]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[2]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[3]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[4]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[5]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[6]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[7]       ; 17.178 ;    ;    ; 17.178 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+------------------------------------------------------+
-; Minimum Propagation Delay                            ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 10.124 ;    ;    ; 10.124 ;
-; MAin[1]    ; RA[1]       ; 9.891  ;    ;    ; 9.891  ;
-; MAin[2]    ; RA[2]       ; 8.276  ;    ;    ; 8.276  ;
-; MAin[3]    ; RA[3]       ; 10.704 ;    ;    ; 10.704 ;
-; MAin[4]    ; RA[4]       ; 8.824  ;    ;    ; 8.824  ;
-; MAin[5]    ; RA[5]       ; 8.367  ;    ;    ; 8.367  ;
-; MAin[6]    ; RA[6]       ; 10.195 ;    ;    ; 10.195 ;
-; MAin[7]    ; RA[7]       ; 9.820  ;    ;    ; 9.820  ;
-; MAin[8]    ; RA[8]       ; 9.678  ;    ;    ; 9.678  ;
-; MAin[9]    ; RA[9]       ; 8.912  ;    ;    ; 8.912  ;
-; MAin[9]    ; RDQMH       ; 8.830  ;    ;    ; 8.830  ;
-; MAin[9]    ; RDQML       ; 8.862  ;    ;    ; 8.862  ;
-; RD[0]      ; Dout[0]     ; 6.188  ;    ;    ; 6.188  ;
-; RD[1]      ; Dout[1]     ; 6.690  ;    ;    ; 6.690  ;
-; RD[2]      ; Dout[2]     ; 6.254  ;    ;    ; 6.254  ;
-; RD[3]      ; Dout[3]     ; 6.845  ;    ;    ; 6.845  ;
-; RD[4]      ; Dout[4]     ; 6.775  ;    ;    ; 6.775  ;
-; RD[5]      ; Dout[5]     ; 6.952  ;    ;    ; 6.952  ;
-; RD[6]      ; Dout[6]     ; 6.194  ;    ;    ; 6.194  ;
-; RD[7]      ; Dout[7]     ; 6.725  ;    ;    ; 6.725  ;
-; nFWE       ; RD[0]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[1]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[2]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[3]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[4]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[5]       ; 16.032 ;    ;    ; 16.032 ;
-; nFWE       ; RD[6]       ; 17.178 ;    ;    ; 17.178 ;
-; nFWE       ; RD[7]       ; 17.178 ;    ;    ; 17.178 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+-----------------------------------------------------------------------+
-; Output Enable Times                                                   ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Minimum Output Enable Times                                           ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Output Disable Times                                                          ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Minimum Output Disable Times                                                  ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.198    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 14.344    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; ARCLK      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; DRCLK      ; RCLK     ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 619      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; ARCLK      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; DRCLK      ; RCLK     ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 619      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 30    ; 30   ;
-; Unconstrained Input Port Paths  ; 231   ; 231  ;
-; Unconstrained Output Ports      ; 37    ; 37   ;
-; Unconstrained Output Port Paths ; 75    ; 75   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Thu Jul 23 02:20:57 2020
-Info: Command: quartus_sta RAM4GS -c RAM4GS
-Info: qsta_default_script.tcl version: #1
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (306004): Started post-fitting delay annotation
-Info (306005): Delay annotation completed successfully
-Info (332104): Reading SDC File: 'constraints.sdc'
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
-    Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
-    Info (332105): create_clock -period 1.000 -name RCLK RCLK
-    Info (332105): create_clock -period 1.000 -name nCRAS nCRAS
-    Info (332105): create_clock -period 1.000 -name PHI2 PHI2
-    Info (332105): create_clock -period 1.000 -name nCCAS nCCAS
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -99.000
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -99.000       -99.000 ARCLK 
-    Info (332119):   -99.000       -99.000 DRCLK 
-    Info (332119):    -9.292       -92.804 PHI2 
-    Info (332119):    -8.365      -253.063 RCLK 
-    Info (332119):    -0.490        -0.577 nCRAS 
-Info (332146): Worst-case hold slack is -16.306
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -16.306       -16.306 DRCLK 
-    Info (332119):   -16.272       -16.272 ARCLK 
-    Info (332119):    -0.874        -0.874 RCLK 
-    Info (332119):    -0.396        -0.396 PHI2 
-    Info (332119):    -0.125        -0.125 nCRAS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -29.500
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -29.500       -59.000 ARCLK 
-    Info (332119):   -29.500       -59.000 DRCLK 
-    Info (332119):    -2.289        -2.289 PHI2 
-    Info (332119):    -2.289        -2.289 RCLK 
-    Info (332119):    -2.289        -2.289 nCCAS 
-    Info (332119):    -2.289        -2.289 nCRAS 
-Info (332001): The selected device family is not supported by the report_metastability command.
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 288 megabytes
-    Info: Processing ended: Thu Jul 23 02:21:02 2020
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:04
-
-
diff --git a/CPLD/MAXII/output_files/UFM.qip b/CPLD/MAXII/output_files/UFM.qip
deleted file mode 100755
index e69de29..0000000
diff --git a/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt b/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt
deleted file mode 100755
index e714d49..0000000
--- a/CPLD/MAXII/output_files/greybox_tmp/cbx_args.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-ERASE_TIME=500000000
-INTENDED_DEVICE_FAMILY="MAX II"
-LPM_FILE=RAM4GS.mif
-LPM_HINT=UNUSED
-LPM_TYPE=altufm_none
-OSC_FREQUENCY=180000
-PORT_ARCLKENA=PORT_UNUSED
-PORT_DRCLKENA=PORT_UNUSED
-PROGRAM_TIME=1600000
-WIDTH_UFM_ADDRESS=9
-DEVICE_FAMILY="MAX II"
-CBX_AUTO_BLACKBOX=ALL
-arclk
-ardin
-arshft
-busy
-drclk
-drdin
-drdout
-drshft
-erase
-osc
-oscena
-program
-rtpbusy